M25P128-VME6TGB - MICRON TECHNOLOGY

March 2010 Rev 6 1/47

M25P128

128-Mbit, low-voltage, serial flash memory

with 54-MHz SPI bus interface

Features

128-Mbit flash memory

2.7 to 3.6 V single supply voltage

SPI bus compatible serial interface

54 MHz clock rate (maximum) for 65 nm

devices

VPP = 9 V for fast program/erase mode

(optional)

Page program (up to 256 Bytes):

– in 0.5 ms (typical) for 65 nm device s

– in 0.4 ms (typical with VPP = 9 V) for 65 nm

devices

Sector erase (2 Mbit)

Bulk erase (128 Mbit)

Electronic signature

– JEDEC standard two-byte signature

(2018h)

More than 10,000 erase/program cycles per

sector

More than 20-year data retention

RoHS compliant packages

VDFPN8 (ME)

8 x 6 mm (MLP8)

SO16 (MF)

300 mils width

www.numonyx.com

Contents M25P128
2/47   
Contents
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1 Serial data output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  8
2 Serial data input (D)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  8
3 Serial clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  8
4 Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  8
5 Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  8
6 Write protect/enhanced program supply voltage (W/VPP)  . . . . . . . . . . . . .  9
7 VCC supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  9
8 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  9
SPI modes  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Operating features   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1 Page programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  12
2 Sector erase and bulk erase  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  12
3 Polling during a write, program or erase cycle . . . . . . . . . . . . . . . . . . . . .  12
4 Fast program/erase mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  12
5 Active power and standby power modes  . . . . . . . . . . . . . . . . . . . . . . . . .  13
6 Status register   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  13
7 Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  13
8 Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  14
Memory organization  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Instructions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . 19
1 Write enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  20
2 Write disable (WRDI)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  20
3 Read identification (RDID)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  21
4 Read status register (RDSR)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  22
4.1 WIP bit  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

M25P128 Contents
 3/47
4.2 WEL bit   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.3 BP2, BP1, BP0 bits  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.4 SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5 Write status register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  24
6 Read data bytes (READ)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  26
7 Read data bytes at higher speed (FAST_READ) . . . . . . . . . . . . . . . . . . .  27
8 Page program (PP)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  28
9 Sector erase (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  30
10 Bulk erase (BE)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  31
Power-up and power-down   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
DC and AC parameters  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Ordering information   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Revision history   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

List of tables M25P128
4/47   
List of tables
Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 2. Protected area sizes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 3. Memory organization  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 4. Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 5. Read identif ica tion  (RDID) da ta-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 6. Status register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 7. Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 8. Power-up timing and VWI threshold for 65 nm devices . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 9. Power-up timing and VWI threshold for 130 nm devices . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 10. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 11. Operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 12. AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 13. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 14. DC characteristics for 65 nm devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 15. AC characteristics for 65 nm devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 16. DC characteristics for 130 nm devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 17. AC characteristics for 130 nm devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 18. VDFPN8 (MLP8), 8-lead Very thin Dual Flat Package No lead, 8 × 6mm,
package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 19. SO16 wide – 16 lead Plastic Small Outline, 300 mils body width. . . . . . . . . . . . . . . . . . . . 44
Table 20. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 21. Document revision history  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

M25P128 List of figures
 5/47
List of figures
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. VDFPN connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. SO connections  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4. Bus master and memory devices on the SPI bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 5. SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 6. Hold condition activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 7. Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 8. Write enable (WREN) instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 9. Write disable (WRDI) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 10. Read identification (RDID) instruction sequence and data-out sequence  . . . . . . . . . . . . . 21
Figure 11. Read status register (RDSR) instruction sequence and data-out sequence  . . . . . . . . . . . 23
Figure 12. Write status register (WRSR) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 13. Read data bytes (READ) instruction sequence and data-out sequence  . . . . . . . . . . . . . . 26
Figure 14. Read data bytes at higher speed (FAST_READ) instruction and data-out sequence . . . . 27
Figure 15. Page program (PP) instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 16. Sector erase (SE) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 17. Bulk erase (BE) instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 18. Power-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 19. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 20. Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 21. Write protect setup and hold timing during WRSR when SRWD =1. . . . . . . . . . . . . . . . . . 41
Figure 22. Hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 23. Output timing  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 24. VPPH timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 25. VDFPN8 (MLP8), 8-lead Very thin Dual Flat Package No lead, 8x6mm, package outline. 43
Figure 26. SO16 wide – 16 lead Plastic Small Outline, 300 mils body width. . . . . . . . . . . . . . . . . . . . 44

Description M25P128

6/47

1 Description

The M25P128 is a 128-Mbit (16 Mbit × 8) serial flash memory, with ad vanced write

protection mechanisms and accessed by a high speed SPI-compatible bus, which allows

clock frequency operation up to 54 MHz(1).

The memory can be programmed 1 to 256 Bytes at a time, using the page program

instruction.

The memory is organized as 64 sectors, each containing 1024 pages. Each page is 256

bytes wide. Thus, the whole memory can be viewed as consisting of 65536 pages, or

16777216 bytes.

An enhanced fast program/erase mode is available to speed up operations in factory

environment. The device enters this mode whenever the VPPH voltage is applied to the write

protect/enhanced program supply voltage pin (W/VPP).

The whole memory can be erased using the bulk erase instruction, or a sector at a time,

using the sector erase instruction.

In order to meet environmental requirements, Numonyx of fers these devices in Lead-free

and RoHS compliant packages.

Note: Important: this datasheet details the functionality of the M25P128 devices, based on the

previous 130 nm MLC process or based on the current 65 nm SLC process, identified by the

process identification digit ‘A’ in the device marking and process letter "B" in the part

number. The new device is backward compatible with the old one.

Figure 1. Logic diagram

1. 54 MHz operation is available only for 65 nm process technology devices, which are identified by the process

identification digit ‘A’ in t he device marking and process letter "B" in the part number .

AI11313b

VCC

M25P128

HOLD

VSS

W/VPP

M25P128 Description

7/47

Figure 2. VDFPN connections

1. There is an exposed die paddle on the underside of the MLP8 package. This is pulled, internally, to VSS,

and must not be allowed to be connected to any other voltage or signal line o n the PCB.

2. See Package mechanical section for package dimensions, and how to identify pin-1.

Figure 3. SO connections

1. DU = Don’t use

2. See Package mechanical section for package dimensions, and how to identify pin-1.

Table 1. Signal names

Symbol Description Direction

C Serial Clock Input

D Serial Data Input Input

Q Serial Data Output Output

SChip Select Input

W/VPP Write Protect/Enhanced Program su pply voltage Input

HOLD Hold Input

VCC Supply voltage Supply

VSS Ground Ground

AI11314b

5DVSS C

HOLDQ

M25P128

W/VPP

AI11315b

DU DU

VCC

HOLD

DUDU

M25P128

QVSS

W/VPP

Signal description M25P128

8/47

2 Signal description

2.1 Serial data output (Q)

This output signal is u sed to transfer dat a serially out of the device . Data is shif ted out on the

falling edge of Serial Clock (C).

2.2 Serial data input (D)

This input signal is used to transfer data serially into th e device. It receives instructions,

addresses, and the data to be programmed. Values are latched on the rising edge of Serial

Clock (C).

2.3 Serial clock (C)

This input signal provides the timing of the serial interface. Instructions, addresses, or data

present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on

Serial Data Output (Q) changes after the falling edge of Serial Clock (C).

2.4 Chip Select (S)

When this input signal is High, the device is deselected and Serial Data Output (Q) is at high

impedance. Unless an intern al Program, Erase or Write Status Re gister cycle is in progress,

the device will be in the Standby Power mode. Driving Chip Select (S) Low selects the

device, placing it in the Active Power mode.

After Power-up, a falling edge on Chip Select (S) is required prior to the start of any

instruction.

2.5 Hold (HOLD)

The Hold (HOLD) signal is used to p ause any serial communica tions with the device without

deselecting the device.

During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data

Input (D) and Serial Clock (C) are Don’t Care.

To start the Hold condition, the device must be selected, with Chip Select (S) driven Low.

M25P128 Signal description

9/47

2.6 Write protect/enhanced program supply voltage (W/VPP)

W/VPP is both a control input and a power supply pi n. The two func tions are selected by the

voltage range applied to the pin .

If the W/VPP input is kept in a low voltage range (0V to VCC) the pin is seen as a control

input. This input signal is used to freeze the size of the area of memory that is protected

against program or erase instru ctions (as specified by the values in the BP2, BP1 and BP0

bits of the Status Register ).

If VPP is in the range of VPPH it acts as an additional power supply pin. In this case VPP must

be stable until the Program/Erase algorithm is completed.

2.7 VCC supply voltage

VCC is the supply voltage.

2.8 VSS ground

VSS is the reference for the VCC supply voltage.

SPI modes M25P128

10/47

3 SPI modes

These devices can be driven by a microcontroller with its SPI peripheral runn ing in either of

the two following modes:

CPOL=0, CPHA=0

CPOL=1, CPHA=1

For these two modes, input data is latched in on the rising edge of Serial Clock (C), and

output data is available from the falling edge of Serial Clock (C).

The dif ference b etween the two modes, as shown in Figure 5, is the clock polarity when the

bus master is in Stand-by mode and not transferring data:

C remains at 0 for (CPOL=0, CPHA=0)

C remains at 1 for (CPOL=1, CPHA=1)

Figure 4. Bus master and memory devices on the SPI bus

1. The Write Protect (W/VPP) and Hold (HOLD) signals should be driven, High or Low as appropriate.

2. These pull-up resistors, R, ensure that the memory devices are not selected if the Bus Master leaves the S line in the high-

impedance state. As the Bus Master may enter a state where all inputs/outputs are in high impedance at the same time

(e.g.: when the Bus Master is reset), the clock line (C) must be connected to an external pull-down resistor so that, when all

inputs/outputs become high impedance, S is pulled High while C is pulled Low (thus ensuring that S and C do not become

High at the same time, and so, that the tSHCH requirement is met).

AI12836

SPI bus master

SPI memory

device

SDO

SDI

SCK

CQD

SPI memory

device

CQD

SPI memory

device

CQD

CS3 CS2 CS1

SPI Interface with

(CPOL, CPHA) =

(0, 0) or (1, 1)

HOLD HOLD HOLD

R(2) R(2) R(2)

VCC VCC VCC

VSS VSS VSS

R(2)

W/VPP W/VPP W/VPP

M25P128 SPI modes

11/47

Figure 5. SPI modes supported

AI01438B

MSB

CPHA

CPOL

MSB

Operating features M25P128

12/47

4 Operating features

4.1 Page programming

To program one data byte, two instructions are required: Write Enable (WREN), which is

one byte, and a Page Program (PP) sequence, which consists of four bytes plus dat a. This

is followed by the internal Program cycle (of duration tPP).

To spread this overhead, the Page Program (PP) instruction allows up to 256 bytes to be

programmed at a time (changing bits from 1 to 0), provided that they lie in consecutive

addresses on the same page of memory.

For optimized timings, it is recommended to use the Page Program (PP) instruction to

program all consecutive targeted Bytes in a single sequence versus using several Page

Program (PP) sequences with each containing only a few Bytes (see Section 6.8: Page

program (PP), Table 15: AC characteristics for 65 nm devices, and Table 17: AC

characteristics for 130 nm devices).

4.2 Sector erase and bulk erase

The Page Program (PP) instru ction allows bits to be reset from 1 to 0. Before this can be

applied, the bytes of memory need to have been erased to all 1s (FFh). This can be

achieved either a sector at a tim e, using the Sector Erase (SE) instruction, or throughout the

entire memory, using the Bulk Eras e (BE) instr uc tion. T his starts an internal Erase cycle (of

duration tSE or tBE).

The Erase inst ru ctio n mus t be preceded by a Write Enable (WREN) ins tru ction.

4.3 Polling during a write, program or erase cycle

A further improvemen t in the time to Write Status Re giste r (WRSR) , Pr og ram (PP) or Era se

(SE or BE) can be achieved by not waiting for the worst case d elay (tW, tPP, tSE, or tBE). Th e

Write In Progress (WIP) bit is provided in the Status Register so that the application program

can monitor its value, polling it to est ablish when the previous Write cycle, Program cycle or

Erase cycle is complete.

4.4 Fast program/erase mode

The Fast Program/Erase mode is used to speed up programming/erasing. The device

enters the Fast Pr ogram/Erase mode du ring the Page Progr am, Sector Erase o r Bulk Erase

instruction whenever a voltage equal to VPPH is applied to the W/VPP pin.

The use of the Fast Program/Erase mode req uires specific operating conditions in addition

to the normal ones (VCC must be within the normal operating range):

the voltage ap plied to the W/VPP pin must be equal to VPPH (see Table 11)

ambient temperature, TA must be 25 °C ±10 °C,

the cumulated time during which W/VPP is at VPPH should be less than 80 hours

M25P128 Operating features

13/47

4.5 Active power and standby power modes

When Chip Select (S) is Low, the device is selected, and in the Active Power mode.

When Chip Select (S) is High, the device is deselected, but could remain in the Active

Power mode until all internal cycles have completed (Program, Erase, Write Status

drops to ICC1.

4.6 Status register

The Status Register contains a num ber o f status and contr ol b its that can be re ad or set (a s

appropriate) by specific instructions. See Section 6.4: Read status register (RDSR) for a

detailed description of the Status Register bits.

4.7 Protection modes

The environme nts where non -vo la tile memo ry de vice s ar e us ed can be very noisy. No SPI

device can operate correctly in the presence of excessive noise. To help combat this, the

M25P128 features the following data protectio n mechanisms:

Power On Reset and an internal timer (tPUW) can provide protection against

inadvertent changes while the power supply is out side the operating specification.

Program, Erase and Write S t atus Register instructions are checked that they consist of

a number of clock pulses that is a multiple of eight, before they are accepted for

execution.

All instructions that modify data must be preceded by a Write Enable (WREN)

instruction to set the Write Enable Latch (WEL) bit. This b it is retur ned to its reset state

by the following events:

–Power-up

– Write Disable (WRDI) instruction completion

– Write Status Register (WRSR) instruction completion

– Page Progra m (PP) instr uc tio n co mple tion

– Sector Erase (SE) instruction completion

– Bulk Erase (BE) instruction completion

The Block Protect (BP2, BP1, BP0) bits allow part of the memory to be configured as

read-only. This is the Software Protected Mode (SPM).

The Write Protect (W/VPP) signal allows the Block Protect (BP2, BP1, BP0) bits and

Status Register Write Disable (SRWD) bit to be protected. This is the Har dwar e

Protected Mode (HPM).

Operating features M25P128

14/47

4.8 Hold condition

The Hold (HOLD) signal is used to p ause any serial communica tions with the device without

resetting the clocking sequence. However, taking this signal Low does not terminate any

Write Status Register, Program or Erase cycle that is currently in progress.

To enter the Hold condition, the device must be selected, with Chip Select (S) Low.

The Hold condition starts on the falling edge of the Hold (HOLD) signal, provided that this

coincides with Serial Clock (C) being Low (as shown in Figure 6).

The Hold condition ends on the rising edge of the Hold (HOLD) signal, provided that this

coincides with Serial Clock (C) being Low.

If the falling edge does not coincide with Serial Clock (C) being Low, the Hold condition

starts after Serial Clock (C) next goes Low. Similarly, if the rising edge does not coincide

with Serial Clock (C) being Low, the Hold condition ends after Serial Clock (C) next goes

Low. (Th is is show n in Figure 6).

During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data

Input (D) and Serial Clock (C) are Don’t Care.

Normally, the device is kept selected, with Chip Select (S) driven Low , for the whol e duration

of the Hold condition. This is to ensure that the st ate of the internal logic remains unch anged

from the moment of entering the Hold condition.

If Chip Select (S) goes High while the device is in the Hold con dition, this has the effect of

resetting the internal logic of the device. To restart communication with the device, it is

necessary to drive Hold (HOLD) High, and then to drive Chip Select (S) Low. This prevents

the device from going back to the Hold condition.

Table 2. Protected area sizes

Status Register content Memory content

BP2 Bit BP1 Bit BP0 Bit Protected area Unprotected area

0 0 0 none All Sectors (Sectors 0 to 63)(1)

1. The device is ready to accept a Bulk Erase instruction if, and only if, all Block Protect (BP2, BP1, BP0) are 0.

0 0 1 Upper 64th (1 Sector, 2Mb) Sectors 0 to 62

0 1 0 Upper 32nd (2 Sectors, 4Mb) Sectors 0 to 61

0 1 1 Upper 16nd (4 Sectors, 8Mb) Sectors 0 to 59

1 0 0 Upper 8nd (8 Sectors, 16Mb) Sectors 0 to 55

1 0 1 Upper Quarter (16 Sectors, 32Mb) Lower 3 Quarters (Sectors 0 to 47)

1 1 0 Upper Half (32 Sectors, 64Mb) Lower Half (Sectors 0 to 31)

1 1 1 All sectors (64 Sectors, 128Mb) none

M25P128 Operating features

15/47

Figure 6. Hold condition activation

AI02029D

HOLD

Hold

Condition

(standard use)

Hold

Condition

(non-standard use)

Memory organization M25P128

16/47

5 Memory organization

The memory is organized as:

16777216 bytes (8 bits each)

64 sectors (2 Mbits, 262144 bytes each)

65536 pa ges (256 bytes each).

Each pag e can be individually programme d (bits are programme d from 1 to 0). The device is

Sector or Bulk Erasable (bits are erased from 0 to 1) but not Page Erasable.

Figure 7. Block diagram

AI11316b

HOLD

Control Logic High Voltage

Generator

I/O Shift Register

Address Register

and Counter 256 Byte

Data Buffer

256 Bytes (Page Size)

X Decoder

Y Decoder

Size of the

read-only

memory area

Status

00000h

FFFFFFh

000FFh

W/VPP

M25P128 Memory organization

17/47

Table 3. Memory organization

Sector Address Range

63 FC0000h FFFFFFh

62 F80000h FBFFFFh

61 F40000h F7FFFFh

60 F00000h F3FFFFh

59 EC0000h EFFFFFh

58 E80000h EBFFFFh

57 E40000h E7FFFFh

56 E00000h E3FFFFh

55 DC0000h DFFFFFh

54 D80000h DBFFFFh

53 D40000h D7FFFFh

52 D00000h D3FFFFh

51 CC0000h CFFFFFh

50 C80000h CBFFFFh

49 C40000h C7FFFFh

48 C00000h C3FFFFh

47 BC0000h BFFFFFh

46 B80000h BBFFFFh

45 B40000h B7FFFFh

44 B00000h B3FFFFh

43 AC0000h AFFFFFh

42 A80000h ABFFFFh

41 A40000h A7FFFFh

40 A00000h A3FFFFh

39 9C0000h 9FFFFFh

38 980000h 9BFFFFh

37 940000h 97FFFFh

36 900000h 93FFFFh

35 8C0000h 8FFFFFh

34 880000h 8BFFFFh

33 840000h 87FFFFh

32 800000h 83FFFFh

31 7C0000h 7FFFFFh

30 780000h 7BFFFFh

29 740000h 77FFFFh

Memory organization M25P128

18/47

28 700000h 73FFFFh

27 6C0000h 6FFFFFh

26 680000h 6BFFFFh

25 640000h 67FFFFh

24 600000h 63FFFFh

23 5C0000h 5FFFFFh

22 580000h 5BFFFFh

21 540000h 57FFFFh

20 500000h 53FFFFh

19 4C0000h 4FFFFFh

18 480000h 4BFFFFh

17 440000h 47FFFFh

16 400000h 43FFFFh

15 3C0000h 3FFFFFh

14 380000h 3BFFFFh

13 340000h 37FFFFh

12 300000h 33FFFFh

11 2C0000h 2FFFFFh

10 280000h 2BFFFFh

9 240000h 27FFFFh

8 200000h 23FFFFh

7 1C0000h 1FFFFFh

6 180000h 1BFFFFh

5 140000h 17FFFFh

4 100000h 13FFFFh

3 0C0000h 0FFFFFh

2 080000h 0BFFFFh

1 040000h 07FFFFh

0 000000h 03FFFFh

Table 3. Memory organization (continued)

Sector Address Range

M25P128 Instructions

19/47

6 Instructions

All instructions, addresses and data are shifted in and out of the device, most significant bit

first.

Serial Data In put (D) is sampled on the fir st rising ed ge of Seria l Clock (C) after Chip Select

(S) is driven Low. Then, the one-byte instruction code must be sh if ted in to the device, m ost

significant bit first, on Serial Data Input (D), each bit being latched on the rising edges of

Serial Clock (C).

The instruction set is listed in Table 4.

Every instruction sequence starts with a one-byte instruction code. Depending on the

instruction, this might be followed by address bytes, or by data bytes, or by both or none.

In the case of a Read Data Bytes (READ), Read Data Bytes at Higher Speed (Fast_Read),

Read Status Register (RDSR) or Read Identification (RDID) instruction, the shifted-in

instruction sequence is followed by a dat a-out sequence. Chip Sele ct (S) can be driven High

after any bit of the data-out sequence is being shifted out.

In the case of a Page Program (PP), Sector Erase (SE), Bulk Erase (BE), Write Status

driven High exactly at a byte boundary, otherwise the instruction is rejected, and is not

executed. That is, Chip Select (S) must driven High when the number of clock pulses after

Chip Select (S) being driven Low is an exact multiple of eight.

All attempts to access the memory array during a Write Status Register cycle, Program

cycle or Erase cycle are ignored, and the internal Write Status Register cycle, Program

cycle or Erase cycle continues unaffected.

Table 4. Instruction set

Instruction Description One-byte Instruction

Code Address

Bytes Dummy

Bytes Data

Bytes

WREN Write Enable 0000 0110 06h 0 0 0

WRDI Write Disable 0000 0100 04h 0 0 0

RDID Read Identification 1001 1111 9Fh 0 0 1 to 3

RDSR Read Status Register 0000 0101 05h 0 0 1 to ∞

WRSR Write Status Register 0000 0001 01h 0 0 1

READ Read Data Bytes 0000 0011 03h 3 0 1 to ∞

FAST_READ Read Data Bytes at Higher

Speed 0000 1011 0Bh 3 1 1 to ∞

PP Page Program 0000 0010 02h 3 0 1 to 256

SE Sector Erase 1101 1000 D8h 3 0 0

BE Bulk Erase 1100 0111 C7h 0 0 0

Instructions M25P128

20/47

6.1 Write enable (WREN)

The Write Enable (WREN) instruction (Figure 8) sets the Write Enable Latch (WEL) bit.

The Write Enable Latch (WEL) bit must be set prior to every Page Program (PP), Sector

Erase (SE), Bulk Erase (BE) and Write Status Register (WRSR) instruction.

The Write Enable (WREN) instruction i s entered by driving Chip Select (S) Low , sending the

instruction code, and then driving Chip Select (S) High.

Figure 8. Write enable (WREN) in st ruc t io n se q uen c e

6.2 Write disable (WRDI)

The Write Disable (WRDI) instruction (Figure 9) resets the Write Enable Latch (WEL) bit.

The Write Disable (WRDI) instruction is entered by driving Chip Select (S) Low, sending the

instruction code, and then driving Chip Select (S) High.

The Write Enable Latch (WEL) bit is reset under the following conditions:

Power-up

Write Disable (WRDI) instruction completion

Write Status Register (WRSR) instruction completion

Page Program (PP) instruction completion

Sector Erase (SE) instruction completion

Bulk Erase (BE) instruction completion

Figure 9. Write disable (WRDI) instruction sequence

AI02281E

21 34567

High Impedance

Instruction

AI03750D

21 34567

High Impedance

Instruction

M25P128 Instructions

21/47

6.3 Read identification (RDID)

The Read Identification (RDID) instruction allows the 8-bit manufacturer identification to be

read, followed by two bytes of device identification. The manufacturer identification is

assigned by JEDEC, and has the value 20h for Numonyx. The device identification is

assigned by the device manufacture r, and indicates the memory type in the first byte (20h),

and the memory ca pacity of the de vice in the second byte (18h ) .

Any Read Identification (RDID) instruction while an Erase or Program cycle is in progress, is

not decoded, and has no effect on the cycle that is in progress.

The device is first selected by driving Chip Select (S) Low. Then, the 8-bit instruction code

for the instruction is shifted in. This is followed by the 24-bit device identification, stored in

the memory, being shifted out on Serial Data Output (Q), each bit being shifted out during

the falling edge of Serial Clock (C).

The instruction sequence is shown in Figure 10.

The Read Identification (RDID) instr uction is terminated by driving Chip Select (S) High at

any time during data output.

When Chip Select (S) is driven High, the device is put in the Standby Power mode. Once in

the S tan dby Power mode, the device waits to be selected, so that it can receive , decode and

execute instructions.

Figure 10. Read identification (RDID) instruction sequence and data-out sequence

Table 5. Read identification (RDID) data-out sequence

Manufacturer Identification Device Identification

Memory Type Memory Capacity

20h 20h 18h

21 3456789101112131415

Instruction

AI06809b

Manufacturer Identification

High Impedance

MSB

15 1413 3210

Device Identification

MSB

16 17 18 28 29 30 31

Instructions M25P128

22/47

6.4 Read status register (RDSR)

The Read Status Register (RDSR) instruction allows the Status Register to be read. The

Status Register may be read at any time, even while a Program, Erase or Write Status

check the Write In Progress (WIP) bit before sending a new instruction to the device. It is

also possible to read th e Status Register continuo u sly, as show n in Figure 11.

The status and control bits of the Status Register are as follows:

6.4.1 WIP bit

The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status

0 no such cycle is in progress.

6.4.2 WEL bit

The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.

When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable

Latch is reset and no Write Status Register, Program or Erase instruction is accepted.

6.4.3 BP2, BP1, BP0 bits

The Block Protect (BP2, BP1, BP0) bits are non-volatile. They de fine th e size of the area to

be software protected against Program and Erase instructions. These bits are written with

the Write Status Register (WRSR) instruction. When one or more of the Block Pr otect (BP2,

BP1, BP0) bits is set to 1, the relevant memory area (as defined in Table 2) becomes

protected against Page Program (PP) and Sector Erase (SE) instructions. The Block Protect

(BP2, BP1, BP0) bits can be written provided that the Hardware Protected mode has not

been set. The Bulk Erase (BE) instruction is executed if, and only if, all Block Protect (BP2,

BP1, BP0) bits are 0.

6.4.4 SRWD bit

The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write

Protect (W/VPP) signal. The Status Register Write Disable (SRWD) bit and Write Protect

(W/VPP) signal allow the device to be put in the Hardwa re Protected mode (when the Status

this mode, the non-volatile bits of the Status Register (SRWD, BP2, BP1, BP0) become

Table 6. Status register format

b7 b0

SRWD 0 0 BP2 BP1 BP0 WEL WIP

Status Register Write Protect

Block Protect Bits

Write Enable Latch Bit

Write In Progress Bit

M25P128 Instructions

23/47

read-only bits and the Write Status Register (WRSR) instruction is no longer accepted for

execution.

Figure 11. Read status register (RDSR) instruction seque nce and data-out sequence

21 3456789101112131415

Instruction

AI02031E

Q76543210

Status Register Out

High Impedance

MSB

76543210

Status Register Out

MSB

Instructions M25P128

24/47

6.5 Write status register (WRSR)

The Write Status Register (WRSR) instruction allows new values to be written to the Status

have been executed. After the Write Enable (WREN) instruction has been decoded and

executed, the device sets the Write Enable Latch (WEL).

The Write Status Register (WRSR) instruction is entered by driving Chip Select (S) Low,

followed by the instruction code and the data byte on Serial Data Input (D).

The instruction sequence is shown in Figure 12.

The Write Status Register (WRSR) instruction has no effect on b6, b5, b1 and b0 of the

Status Register. b6 and b5 are always read as 0.

Chip Select (S) must be driven High after the eighth bi t of the dat a byte has been latched in.

If not, the Write S tatus Register (WRSR) instruction is not executed. As soon as Chip Select

(S) is driven High, the self-timed Write Status Register cycle (whose duration is tW) is

initiated. While the Write Status Register cycle is in progress, the Status Register may still

be read to check the value of the Write In Progress (WIP) bit. The Write In Prog re ss (W IP)

bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed.

When the cycle is completed, the Write Enable Latch (WEL) is reset.

The Write Status Register (WRSR) instruction allows the user to change the values of the

Block Protect (BP2, BP1, BP0) bits, to define the size of the area that is to be treated as

read-only, as defined in Table 2. The Write Status Register (WRSR) instruction also allows

the user to set or reset the St atus Register Write Disable (SRWD) bit in accordance with the

Write Protect (W/VPP) signal. The Status Register Write Disable (SRWD) bit and Write

Protect (W/VPP) signal allow the device to be put in the Hardware Protected Mode (HPM).

The Wr ite Status Register ( WRSR) instruction is not executed once the Hardware Protected

Mode (HPM) is entered.

The protection features of the de vice are summarized in Table 7

When the Status Register Write Disable (SR WD) bit of the Status Register is 0 (its initial

delivery state), it is possible to write to the Status Register provided that the Write Enable

Table 7. Protection modes

W/VPP

Signal SRWD

Bit Mode Write Protection of the

Status Register

Memory Content

Protected Area(1)

1. As defined by the values in the Block Protect (BP2, BP1, BP0) bits of the Status Register, as shown in

Table 2: Protected area sizes.

Unprotected Area(1)

Software

Protected

(SPM)

S tatus Register is Writable

(if the WREN instruction

has set the WEL bit)

The values in the SRWD,

BP2, BP1 and BP0 bits

can be changed

Protected against

Page Program,

Sector Erase and

Bulk Erase

Ready to accept

Page Program and

Sector Erase

instructions

Hardware

Protected

(HPM)

Status Register is

Hardware write protected

The values in the SRWD,

BP2, BP1 and BP0 bits

cannot be changed

Protected against

Page Program,

Sector Erase and

Bulk Erase

Ready to accept

Page Program and

Sector Erase

instructions

M25P128 Instructions

25/47

Latch (WEL) bit has previo usly been set by a Write Enable (WREN) instruction, regardless

of the whether Write Protect ( W/VPP) is driven High or Low.

When the Status Register Write Disable (SR WD) bit of the Status Register is set to 1, two

cases need to be considered, depending on the state of Write Protect (W/VPP):

If Write Protect (W/VPP) is driven High, it is possible to write to the Status Register

provided that the Write Enable Latch (WEL) bit has pr eviously been set by a Write

Enable (WREN) instruction.

If Write Protect (W/VPP) is driven Low, it is not possible to write to the Status Register

even if the Write Enable Latch (WEL) bit has previously been set by a Write Enable

(WREN) instruction. (Attempts to write to the Status Register are rejected, and are not

accepted for execution) . As a conse quence, all the data bytes in the mem ory a rea th at

are software protected (SPM) by the Block Protect (BP2, BP1, BP0) bits of the Status

Regardless of the order of the two events, the Hardware Protected Mode (H PM) can be

entered:

by setting the Status Register Write Disable (SRWD) bit after driving Write Protect

(W/VPP) Low

or by driving Write Protect (W/VPP) Low after setting the Status Register Write Disable

(SRWD) bit.

The only way to exit the Hardware Protected Mode (HPM) once entered is to pull Write

Protect (W/VPP) High.

If Write Protect (W/VPP) is per manently tied High, the Hardware Pr otected Mode (H PM) can

never be activat ed , an d on ly the Software Protected Mode (SPM), using the Block Protect

(BP2, BP1, BP0) bits of the Status Register, can be used.

Figure 12. Write status register (WRSR) instruction sequence

AI02282D

21 3456789101112131415

High Impedance

Instruction Status

765432 0

MSB

Instructions M25P128

26/47

6.6 Read data bytes (READ)

The device is first selected by driving Chip Select (S) Low. The instruction code for the Read

Data Bytes (READ) instruction is followed b y a 3- byte address (A23-A0), each bit being

latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that

address, is shifted out on Serial Data Output (Q), each bit being shifted out, at a maximum

frequency fR, during the falling edge of Serial Clock (C).

The instruction sequence is shown in Figure 13.

The first byte addressed can be at any location. The address is automatically incremented

to the next higher address after each byte of data is shifted out. The whole memory can,

therefore, be read with a single Read Data Bytes (READ) instruction. When the highest

address is reached, the address counter rolls over to 000000h, allowing the read sequence

to be continued indefinitely.

The Read Data Bytes (READ) instruction is terminated by driving Chip Select (S) High. Chip

Select (S) can be driven High at any time during dat a outp ut. Any Read Dat a Bytes (READ)

instruction, while an Erase, Program or Write cycle is in progress, is rejecte d without havi ng

any effects on the cycle that is in progress.

Figure 13. Read data bytes (READ) instruction sequence and data-out sequence

AI03748D

21 345678910 2829303132333435

2221 3210

36 37 38

76543 1 7

High Impedance Data Out 1

Instruction 24-Bit Address

MSB

Data Out 2

M25P128 Instructions

27/47

6.7 Read data bytes at higher speed (FAST_READ)

The device is first selected by driving Chip Select (S) Low. The instruction code for the Read

Data Bytes at Higher S peed (FAST_READ) instruction is followed by a 3-byte address (A23-

A0) and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (C).

Then the memory contents, at that address, is shifted out on Serial Data Output (Q), each

bit being shifted out, at a maximum frequency fC, during the falling edge of Serial Clock (C).

The instruction sequence is shown in Figure 14.

The first byte addressed can be at any location. The address is automatically incremented

to the next higher address after each byte of data is shifted out. The whole memory can,

therefore, be read wi th a single Read Data Bytes at Higher Speed (FAST_READ)

instruction. When the highest address is reached, the address counter rolls over to

000000h, allowing the read sequence to be continued indefinitely.

The Read Data Bytes at Higher Speed (FAST_REA D) instruction is terminated by driving

Chip Select (S) High. Chip Select (S) can be driven High at any time d uring dat a output. Any

Read Data Bytes at Higher Speed (FAST_READ) instruction, while an Erase, Program or

Write cycle is in progress, is rejected without having any effects on the cycle that is in

progress.

Figure 14. Read data bytes at higher speed (FAST_READ) instruction and data-out

sequence

AI04006

21 345678910 28293031

2221 3210

High Impedance

Instruction 24 BIT ADDRESS

32 33 34 36 37 38 39 40 41 42 43 44 45 46

765432 0

DATA OUT 1

Dummy Byte

MSB

76543210

DATA OUT 2

MSB MSB

765432 0

Instructions M25P128

28/47

6.8 Page program (PP)

The Page Program (PP) instruction allows bytes to be programmed in the memory

(changing bits from 1 to 0). Befo re it can be acce p ted , a Write Enable (WREN) instruction

must previously have been executed. After the Write Enable (WREN) instruction has been

decoded, the device sets the Write Enable Latch (WEL).

The Page Program (PP) instruction is entered by driving Chip Select (S) Low, followed by

the instruction code, th ree address bytes and at least one data byte on Serial Data Input (D) .

If the 8 least significant ad dr ess bits (A7-A0) are not all zero, all transm itt ed data that goes

beyond the end of the current page are programmed from the start address of the same

page (from the ad dress whose 8 least significant bits (A7-A0) are all zero). Chip Select (S)

must be driven Low for the entire duration of the sequence. The instruction sequence is

shown in Figure 15.

If more than 25 6 bytes are sent to the device, previo usly latched dat a are d iscarded and the

last 256 dat a bytes are guaranteed to be programmed correctly within the same page. If less

than 256 Data bytes are sent to device, they are correctly programmed at the requested

addresses without having any effects on the other bytes of the same page.

For optimized timings, it is recommended to use the Page Program (PP) instruction to

program all consecutive targeted Bytes in a single sequence versus using several Page

Program (PP) sequences with each containing only a few Bytes (see Table 15: AC

characteristics for 65 nm devices an d Table 17: AC characteristics for 130 nm devices).

Chip Select (S) must be driven High after the eighth bit of the last data byte has been

latched in, otherwise the Page Program (PP) instruction is not executed.

As soon as Chip Select (S) is driven High, the self-timed Page Program cycle (whose

duration is tPP) is initiated. While the Page Progr am cycle is in progress, the S tatus Register

may be read to check the value of the Write In Progress (WIP) bit. Th e Write In Progre ss

(WIP) bit is 1 during the self -t im e d Pa ge Prog ra m cycle, and is 0 when it is completed. At

some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is

reset.

A Page Program (PP) instruction applied to a page wh ich is protected by the Block Protect

(BP2, BP1, BP0) bits (see Table 2 and Table 3) is not executed.

M25P128 Instructions

29/47

Figure 15. Page program (PP) instruction sequence

AI04082B

4241 43 44 45 46 47 48 49 50 52 53 54 5540

21 345678910 2829303132333435

2221 3210

36 37 38

Instruction 24-Bit Address

765432 0

Data Byte 1

765432 0

Data Byte 2

765432 0

Data Byte 3 Data Byte 256

2079

2078

2077

2076

2075

2074

2073

765432 0

2072

MSB MSB

MSB MSB MSB

Instructions M25P128

30/47

6.9 Sector erase (SE)

The Sector Erase (SE) instruction sets to 1 (FFh) all bits inside the chosen sector. Before it

can be accepted, a Write Enable (WREN) instruction must previously have been executed.

After the Write Enable (WREN) instruction has been decoded, the device sets the Write

Enable Latch (WEL).

The Sector Erase (SE) instruction is entered by driving Chip Select (S) Low, followed by the

instruction code, and three address bytes on Serial Data Input (D). Any address inside the

Sector (see Table 3) is a valid address for the Sector Erase (SE) instruction. Chip Select (S)

must be driven Low for the entire duration of the sequence.

The instruction sequence is shown in Figure 16.

Chip Select (S) must be driven High after the eighth bit of the last address byte has been

latched in, otherwise the Sector Erase (SE) instruction is not executed. As soon as Chip

Select (S) is driven High, the self-timed Sector Erase cycle (whose duration is tSE) is

initiated. While the Sector Erase cycle is in progress, the Status Register may be read to

check the value of the Write In Progr ess (WIP) bit. The Write In Progress (WIP) bit is 1

during the self-timed Sector Erase cycle , and is 0 when it is completed. At some unspecified

time before the cycle is completed, the W rite Enable Latch (WEL) bit is reset.

A Sector Erase (SE) instruction applied to a page which is protected by the Block Protect

(BP2, BP1, BP0) bits (see Table 2 and Table 3) is not executed.

Figure 16. Sector erase (SE) instruction sequence

24 Bit Address

AI03751D

21 3456789 293031

Instruction

23 22 2 0

MSB

M25P128 Instructions

31/47

6.10 Bulk erase (BE)

The Bulk Erase (BE) instruction sets all bits to 1 (FFh). Before it can be accepted, a Write

Enable (WREN) instruction must previously have been executed. After the Write Enable

(WREN) instruction has been decoded, the device sets the Write Enab le Latch (WEL).

The Bulk Erase (BE) instruction is entered by driving Chip Select (S) Low, followed by the

instruction code on Serial Data Input (D). Chip Select (S) mu st be driven Low for the entire

duration of the sequence.

The instruction sequence is shown in Figure 17.

Chip Select (S) must be driven High after the eighth bit of the instruction code has been

latched in, otherwise the Bulk Erase instructio n is not executed. As soon as Chip Select (S)

is driven High, the self-timed Bulk Erase cycle (whose duration is tBE) is initiated. While the

Bulk Erase cycle is in progress, the Status Register may be read to check the value of the

Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Bulk

Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is

completed, the Write Enable Latch (W EL) bit is res et .

The Bulk Erase (BE) instruction is executed only if all Block Protect (BP2, BP1, BP0) bits

are 0. The Bulk Erase (BE) instruction is ignored if one, or more, sectors are protected.

Figure 17. Bulk erase (BE) instruction sequence

AI03752D

21 345670

Instruction

Power-up and power-down M25P128

32/47

7 Power-up and power-down

At Power-up and Power-do wn, the device must not be selecte d (that is Chip Select (S) must

follow the voltage applied on VCC) until VCC reaches the correct value:

VCC(min) at Power-up, and then for a further delay of tVSL

VSS at Power-down

Usually a simple pull-up resistor on Chip Select (S) can be used to ensure safe and proper

Power-up and Power-down.

To avoid data corruption and inadvertent write operations during Power -up, a Power On

Reset (POR) circuit is included. The logic inside the device is held reset while VCC is less

than the Power On Reset (POR) threshold voltage, VWI – all operations are disabled, and

the device does not respond to any instruction.

Moreover, the device ignores all Write Enable (WREN), Page Pro gram (PP), Sector Erase

(SE), Bulk Erase (BE) and W rite Status Register (WRSR) instructions until a time delay of

tPUW has elapsed after the moment that VCC rises above th e VWI threshold. However, the

correct operation of the de vice is not guaran teed if, by this time , VCC is still below VCC(min).

No Write Status Register, Program or Erase instructions should be sent until the later of:

tPUW after VCC passed the VWI threshold

tVSL after VCC passed the VCC(min) level

These values are sp ec ified in Table 8.

If the delay, tVSL, has elapsed, after VCC has risen above VCC(min), the device can be

selected for READ instructions even if the tPUW delay is not yet fully elapsed.

At Power-up, the device is in the following state:

The device is in the Standby Power mode

The Write Enable Latch (WEL) bit is reset.

Normal precautions must be taken for supply rail decoupling, to stabilize the VCC supply.

Each device in a system should have the VCC rail decoupled by a suitable cap acitor close to

the package pins (generally, this capacitor is of the order of 0.1µF).

At Power-down, when VCC drops from the operating voltage, to below the Power On Reset

(POR) threshold voltage, VWI, all operations are disabled and the device does not respond

to any instruction. (The designer needs to be aware that if a Power-down occurs while a

Write, Program or Erase cycle is in progress, some data corruption can result.)

Power up se quencing for Fa st program/er ase mode: V CC should attain VCCMIN before VPPH

is applied.

M25P128 Initial delivery state

33/47

Figure 18. Power-up timing

8 Initial delivery state

The device is delivered with the memory array erased: all bits are set to 1 (each byte

contains FFh). The Status Register contains 00h (all Status Register bits are 0).

Table 8. Power-up timing and VWI threshold for 65 nm devices(1)

1. 65 nm technology devices are identified by the process identification digit ‘A’ in the device marking and

process letter "B" in the part number.

Symbol Parameter Min. Max. Unit

tVSL(2)

2. These parameters are characterized only.

VCC(min) to S Low 200 µs

tPUW(2) Time delay to Write instruction 400 µs

VWI Wri t e Inhibit Voltage 1.5 2.5 V

Table 9. Power-up timing and VWI threshold for 130 nm devices

Symbol Parameter Min. Max. Unit

tVSL(1)

1. These parameters are characterized only.

VCC(min) to S Low 60 µs

tPUW(2) Time delay to Write instruction 1 10 ms

VWI Write Inhibit Voltage 1.5 2.5 V

VCC

AI04009C

VCC(min)

VWI

Reset State

of the

Device

Chip Selection Not Allowed

Program, Erase and Write Commands are Rejected by the Device

tVSL

tPUW

time

Read Access allowed Device fully

accessible

VCC(max)

Maximum rating M25P128

34/47

9 Maximum rating

Stressing the device out side the ratings listed in Table 10 may cause permanent damage to

the device. These are stress ratings only, and operation of the device at th ese, or an y other

conditions outside those indicated in the operating sections of this specification, is not

implied. Exposure to absolute maximum rating conditions for extended periods may affe ct

device reliability.

Table 10. Absolute maximum ratings

Symbol Parameter Min. Max. Unit

TSTG Storage Temperature –65 150 °C

VIO Input and output voltage (with respect to Ground) –0.5 VCC + 0.6 V

VCC Supply voltage –0.2 4.0 V

VPP Fast Program/Erase voltage –0.2 10.0 V

VESD Electrostatic Discharge Voltage (Human Body Model) (1)

1. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω)

–2000 2000 V

M25P128 DC and AC parameters

35/47

10 DC and AC parameters

This section summarizes the operating and measurement conditions, and the DC and AC

characteristics of the device. The parameters in the DC and AC Characteristic tables that

follow are derived from tests performed under the measurement conditions summarized in

the relevant tables. Designers should check that the operating conditions in their circuit

match the measurement conditions when relying on the quoted parameters.

1. Output Hi-Z is defined as the point where data out is no longer driven.

Figure 19. AC measurement I/O waveform

1. Sampled only, not 100% tested, at TA=25 °C and a frequency of 20 MHz.

Table 11. Operating conditions

Symbol Parameter Min. Typ. Max. Unit

VCC Supply Voltage 2.7 3.6 V

VPPH Supply V oltage on W/VPP pin for Fast

Program/Erase mo de 8.5 9.5 V

TAAmbient Oper ating Temperature –40 85 °C

TAVPP Ambient Operating Temperature for Fast

Program/Erase mo de 15 25 35 °C

Table 12. AC measurement conditions

Symbol Parameter Min. Max. Unit

CLLoad Capacitance 30 pF

Input Rise and Fall Times 5 ns

Input Pulse Voltages 0.2VCC to 0.8VCC V

Input T iming Reference Voltages 0.3VCC to 0.7VCC V

Output Timing Reference Voltages VCC / 2 V

Table 13. Capacitance

Symbol Parameter Test Condition Min. Max. Unit

COUT Output Capacitance (Q) VOUT = 0V 8 pF

CIN Input Capacitance (oth er pins) VIN = 0V 6 p F

AI07455

0.8VCC

0.2VCC

0.7VCC

0.3VCC

Input and Output

Timing Reference Levels

Input Levels

0.5VCC

DC and AC parameters M25P128

36/47

Table 14. DC characteristics for 65 nm devices(1)

1. 65 nm process technology devices are identified by the process identification digit ‘A’ in the device marking

and process letter "B" in the part number.

Symbol Parameter Te st condition

(in addition to those in Table 11)Min. Max. Unit

ILI Input Leakage Current ± 2 µA

ILO Output Leakage Current ± 2 µ A

ICC1 Standby Current S = VCC, VIN = VSS or VCC 100 µA

ICC3 Operating Current (READ)

C=0.1V

CC / 0.9.VCC at 54 MHz,

Q = open 6mA

C=0.1V

CC / 0.9.VCC at 33 MHz,

Q = open 4mA

ICC4 Operating Current (PP) S = VCC 20 mA

ICC5 Operating Current

(WRSR) S = VCC 20 mA

ICC6 Operating Current (SE) S = VCC 20 mA

ICC7 Operating Current (BE) S = VCC 20 mA

ICCPP(2)

2. Characterized only.

Operating current for Fast

Program/Erase mode S = VCC, VPP = VPPH 20 mA

IPP(2) VPP Operating current in

Fast Program/Erase mode S = VCC, VPP = VPPH 20 mA

VIL Input Low Voltage – 0.5 0.3 VCC V

VIH Input High V oltage 0.7 VCC VCC+0.4 V

VOL Output Low Voltage IOL = 1.6 mA 0.4 V

VOH Output High Voltage IOH = –100 μAV

CC–0.2 V

Table 15. AC characteristics for 65 nm devices(1)

Test conditions specified in Table 11 and Table 12

Symbol Alt. Parameter Min. Typ. Max. Unit

fCfC

Clock frequency for the following

instructions: F AST_READ, PP, SE, BE,

WREN, WRDI, RDID, RDSR, WRSR D.C. 54 MHz

fRClock frequency for READ instructions D.C. 33 MHz

tCH(2) tCLH Clock High Time 9 ns

tCL(2) tCLL Clock Low Time 9 ns

tCLCH(3) Clock Rise Time(4) (peak to peak) 0.1 V/ns

tCHCL(3) Clock Fall Time(3) (peak to peak) 0.1 V/ns

tSLCH tCSS S Active Setup Time (relative to C) 4 ns

tCHSL S Not Active Hold Time (relative to C) 4 ns

M25P128 DC and AC parameters

37/47

tDVCH tDSU Data In Setup Time 2 ns

tCHDX tDH Data In Hold Time 3 ns

tCHSH S Active Hold Time (relative to C) 4 ns

tSHCH S Not Active Setu p Time (relative to C) 4 ns

tSHSL tCSH S Deselect Time 50 ns

tSHQZ(2) tDIS Output Disable Time 8 ns

tCLQV tVClock Low to Output Valid 8 ns

tCLQX tHO Output Hold Time 1 ns

tHLCH HOLD Setup Time (relative to C) 4 ns

tCHHH HOLD Hold Time (relative to C) 4 ns

tHHCH HOLD Setup Time (relative to C) 4 ns

tCHHL HOLD Hold Time (relative to C) 4 ns

tHHQX(3) tLZ HOLD to Output Low-Z 8 ns

tHLQZ(3) tHZ HOLD to Output High-Z 8 ns

tWHSL(5) W rite Protect Setup Time 20 ns

tSHWL (5) Write Protect Hold Ti me 100 ns

tVPPHSL(3)

(6) Enhanced Program Supply Vol tage

High to Chip Select Low 200 ns

tWWrite Status Register Cycle Time 1.3 15 s

tPP(7)

Page Program Cycle Time (256 Bytes) 0.5

5ms

Page Program Cycle Time (n Bytes) int(n/8) x

0.015(8)

Page Program Cycle Time (VPP =

VPPH) (256 Bytes) 0.4(3)

tSE Sector Erase Cycle Time 1.6 3 s

tSE Sector Erase Cycle Time (VPP = VPPH)1.63s

tBE Bulk Erase Cycle Time 130 250 s

tBE Bulk Erase Cycle Time (VPP = VPPH)120250s

1. 65 nm process technology devices are identified by the process identification digit ‘A’ in the device marking

and process letter "B" in the part number.

2. tCH and tCL must be greater than or equal to 1/fC (max).

3. Value is guaranteed by characterization, not 100% tested in production.

4. Expressed as a slew-rate.

5. Only applicable as a constraint for WRSR instruction when SRWD is set to 1.

6. VPPH should be kept at a valid level until the program or erase operation has completed and its result

(success or failure) is known.

Table 15. AC characteristics for 65 nm devices(1) (continued)

Test conditions specified in Table 11 and Table 12

Symbol Alt. Parameter Min. Typ. Max. Unit

DC and AC parameters M25P128

38/47

7. When using the Page Program (PP) instruction to program consecutive Bytes, optimized timings are

obtained with one sequence including all the Bytes versus several sequences of only a few Bytes. If only a

single byte is programmed, the estimated programming time is close to the time needed to program a full

page of 256 Bytes. Therefore, it is highly recommended to use the Page Program (PP) instruction with a

sequence of 256 consecutive Bytes. (1 ≤ n ≤ 256)

8. int(A) corresponds to the upper integer part of A. For example int(12/8) = 2, int(32/8) = 4, int(15.3) = 16.

Table 16. DC characteristics for 130 nm devices

Symbol Parameter Test conditio n

(in addition to those in

Table 11)Min. Max. Unit

ILI Input Leakage Current ± 2 µA

ILO Output Leakage Current ± 2 µA

ICC1 Standby Current S = VCC, VIN = VSS or VCC 100 µA

ICC3 Operating Current (READ)

C=0.1V

CC / 0.9.VCC at

50MHz,

Q = open 8mA

C=0.1V

CC / 0.9.VCC at

20MHz,

Q = open 4mA

ICC4 Operating Current (PP) S = VCC 20 mA

ICC5 Operating Current (WRSR) S = VCC 20 mA

ICC6 Operating Current (SE) S = VCC 20 mA

ICC7 Operating Current (BE) S = VCC 20 mA

ICCPP(1)

1. Characterized only.

Operating current for Fast

Program/Erase mode S = VCC, VPP = VPPH 20 mA

IPP(2) VPP Operating current in

Fast Program/Erase mode S = VCC, VPP = VPPH 20 mA

VIL Input Low Voltage – 0.5 0.3VCC V

VIH Input High Voltage 0.7VCC VCC+0.2 V

VOL Output Low Voltage IOL = 1.6mA 0.4 V

VOH Output High Voltage IOH = –100μAV

CC–0.2 V

M25P128 DC and AC parameters

39/47

Table 17. AC characteristics for 130 nm devices

Test conditions specified in Table 11 and Table 12

Symbol Alt. Parameter Min. Typ. Max. Unit

fCfC

Clock frequency for the following instructions:

FAST_READ, PP, SE, BE, WREN, WRDI,

RDID, RDSR, WRSR D.C. 50 MHz

fRClock frequency for READ instructions D.C. 20 MHz

tCH(1) tCLH Clock High Time 9 ns

tCL(1) tCLL Clock Low Time 9 ns

tCLCH(2) Clock Rise Time(3) (peak to peak) 0.1 V/ns

tCHCL(2) Clock Fall Time(3) (peak to peak) 0.1 V/ns

tSLCH tCSS S Active Setup Time (relative to C) 5 ns

tCHSL S Not Active Hold Time (relative to C) 5 ns

tDVCH tDSU Data In Setup Time 2 ns

tCHDX tDH Data In Hold Time 5 ns

tCHSH S Active Hold Time (relative to C) 5 ns

tSHCH S Not Active Setup Time (relative to C) 5 ns

tSHSL tCSH S Deselect Time 100 ns

tSHQZ(2) tDIS Output Disable Time 8 n s

tCLQV tVClock Low to Output Valid 8 ns

tCLQX tHO Output Hold Time 0 ns

tHLCH HOLD Setup Time (relative to C) 5 ns

tCHHH HOLD Hold Time (relative to C) 5 ns

tHHCH HOLD Setup Time (relative to C) 5 ns

tCHHL HOLD Hold Time (relative to C) 5 ns

tHHQX(2) tLZ HOLD to Output Low-Z 8 ns

tHLQZ(2) tHZ HOLD to Output High-Z 8 ns

tWHSL(4) Write Protect Setup Time 20 ns

tSHWL (4) Write Protect Hold Time 100 ns

tVPPHSL(2)(5) Enhanced Program Supply Voltage High to

Chip Select Low 200 ns

tWWrite Status Register Cycle Time 5 15 ms

tPP(6)

Page Program Cycle Time (256 Bytes) 2.5

7ms

Page Program Cycle Time (n Bytes) 2.5

Page Program Cycle Time (VPP = VPPH) (256

Bytes) 1.2(2)

tSE Sector Erase Cycle T ime 2 6s

Sector Erase Cycle T ime (VPP = VPPH)1.6

(2)

DC and AC parameters M25P128

40/47

Figure 20. Serial input timing

tBE Bulk Erase Cycle Time 105 250 s

Bulk Erase Cycle Time (VPP = VPPH)56

(2)

1. tCH and tCL must be greater than or equal to 1/fC (max).

2. Value is guaranteed by characterization, not 100% tested in production.

3. Expressed as a slew-rate.

4. Only applicable as a constraint for WRSR instruction when SRWD is set to 1.

5. VPPH should be kept at a valid level until the program or erase operation has completed and its result

(success or failure) is known.

6. When using the Page Program (PP) instruction to program consecutive Bytes, optimized timings are

obtained with one sequence including all the Bytes versus several sequences of only a few Bytes. If only a

single byte is programmed, the estimated programming time is close to the time needed to program a full

page of 256 Bytes. Therefore, it is highly recommended to use the Page Program (PP) instruction with a

sequence of 256 consecutive Bytes. (1 ≤ n ≤ 256)

Table 17. AC characteristics for 130 nm devices (continued)

Test conditions specified in Table 11 and Table 12

Symbol Alt. Parameter Min. Typ. Max. Unit

AI01447C

MSB IN

tDVCH

High Impedance

LSB IN

tSLCH

tCHDX

tCHCL

tCLCH

tSHCH

tSHSL

tCHSHtCHSL

M25P128 DC and AC parameters

41/47

Figure 21. Write protect setup and hold timing during WRSR when SRWD =1

Figure 22. Hold timing

High Impedance

tWHSL tSHWL

AI07439

W/VPP

AI02032

HOLD

tCHHL

tHLCH

tHHCH

tCHHH

tHHQXtHLQZ

DC and AC parameters M25P128

42/47

Figure 23. Output timing

Figure 24. VPPH timing

AI01449e

LSB OUT

DADDR.LSB IN

tSHQZ

tCH

tCL

tQLQH

tQHQL

tCLQX

tCLQV

tCLQX

tCLQV

W/VPP

VPPH

PP, SE, BE

ai12092

tVPPHSL

End of PP, SE or BE

(identified by WPI polling)

M25P128 Package mechanical

43/47

11 Package mechanical

Figure 25. VDFPN8 (MLP8) , 8-lead Very thin Dual Flat Package No lead, 8x6mm,

package outline

1. Drawing is not to scale.

2. The circle in the top view of the package indicates the position of pin 1.

Table 18. VDFPN8 (MLP8), 8-lead Very thin Dual Flat Package No lead, 8 × 6mm,

package mechanical data

Symbol millimeters inches

Typ. Min. Max. Typ. Min. Max.

A 0.85 1.00 0.0335 0.0394

A1 0.00 0.05 0.0000 0.0020

b 0.40 0.35 0.48 0.0157 0.0138 0.0189

D 8.00 0.3150

D2 5.16 (1)

1. D2 Max should not exceed (D – K – 2 × L).

0.2031

ddd 0.05 0.0020

E 6.00 0.2362

E2 4.80 0.1890

e1.27– –0.0500– –

K 0.20 0.0079

L 0.50 0.45 0.60 0.0197 0.0177 0.0236

L1 0.15 0.0059

N8 8

VDFPN-02

A1 ddd

Package mechanical M25P128

44/47

Figure 26. SO16 wide – 16 lead Plastic Small Outline, 300 mils body width

1. Drawing is not to scale.

Table 19. SO16 wide – 16 lead Plastic Small Outline, 300 mils body width

Symbol millimeters inches

Typ Min Max Typ Min Max

A 2.35 2.65 0.093 0.104

A1 0.10 0.30 0.004 0.012

B 0.33 0.51 0.013 0.020

C 0.23 0.32 0.009 0.013

D 10.10 10.50 0.398 0.413

E 7.40 7.60 0.291 0.299

e 1.27 – – 0.050 – –

H 10.00 10.65 0.394 0.419

h 0.25 0.75 0.010 0.030

L 0.40 1.27 0.016 0.050

θ0° 8° 0° 8°

ddd 0.10 0.004

SO-H

LA1

ddd

h x 45˚

M25P128 Ordering information

45/47

12 Ordering information

For a list of available options (speed, package, etc.) or for further information on any aspect

of this device, please co ntact your nearest Numonyx sales office.

The category of second-level interconnect is marked on the package and on the inner box

label, in compliance with JEDEC Standard JESD97. The maximum ratings related to

soldering conditions are also marked on th e inner box label.

Table 20. Ordering information scheme

Example: M25P128 – V MF 6 T P B

Device Type

M25P = Serial flash memory for code storage

Device function

128 = 128 Mbit (16 Mbit × 8)

Operating voltage

V = VCC = 2.7 to 3.6 V

Package

MF = SO16 (300 mil width)

ME = VDFPN8 8 x 6 mm (MLP8)

Device grade

6 = Industrial temperature range, –40 to 85 °C.

Device tested with standard test flow

Option

blank = Standard packing

T = Tape and reel packing

Plating technology

P or G = RoHS compliant

Process Technology

Blank = 130nm MLC

B = 65 nm SLC

Revision history M25P128
46/47   
13 Revision history
         
Ta b le  21. Do cu me n t re vision hist ory
Date Revision Changes
02-May-2005 0.1 First issue.
09-Jun-2005 0.2 Table 2: Protected area sizes updated. 
Memory capacity modified in Section 6.3: Read identification (RDID).
28-Aug-2005 0.3
Updated tPP values in Table 17: AC characteristics for 130 nm 
devices and tVSL value in Table 8: Power-up timing and VWI 
threshold for 65 nm devices. Modified information in Section 4.1: 
Page programming and Section 6.8: Page program (PP).
20-Jan-2006 1
Document status promoted from Targ et specification to Preliminar y 
data.
Packages are ECOPACK® compliant. Blank option removed under 
Plating technology in Table 20. Read Electronic Signature (RES) 
instruction removed. ICC1 p arameter updated in Table 14: DC 
characteristics for 65 nm devices.
17-Oct-2006 2
Document status promoted from Preliminary Data to full Datasheet.
Write Protect pin (W) changed to Write protect/enhanced program 
supply voltage (W/VPP). Section 4.4: Fast program/erase mode and 
Figure 24: VPPH timi ng added. Power-up specified for Fast 
Program/Erase mode in Power-up and power-down section.
Figure 4: Bus master and memory devices on the SPI bus modified 
and Note 2 added.
Note 1 added below Table 18: VDFPN8 (MLP8), 8-lead Very thin 
Dual Flat Package No lead, 8 × 6mm,  package mechanical data. 
VIO max modified in Table 10: Absolute maximum ratings.
10-Dec-2007 3 Applied Numonyx branding.
26-Nov-2009 4
Removed references to multilevel cell technology and ECOPACK® 
packages.
Added: Table 14: DC characteristics for 65 nm devices and Table 15: 
AC characteristics for 65 nm devices, and references to 65 nm 
process technology throughout the document
Modified D2 value in Table 18: VDFPN8 (MLP8), 8-lead Very thin 
Dual Flat Package No lead, 8 × 6mm,  package mechanical data.
17-Dec-2009 5 Added “Process Technology” to Ordering Information table.
1-Feb-2010 6
Added sector erase cycle times to Table 15.: AC characteristics for 
65 nm devices.
Changed Icc3 test conditions in Table 14.: DC characteristics for 
65 nm devices as follows: 50 MHz to 54 MHz and 20 MHz to 33 MHz.

M25P128

47/47

Please Read Carefully:

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR

IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT

AS PROVIDED IN NUMONYX'S TER M S AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY

WHATSOEVER, AND NUMONYX DIS CLAIMS ANY EXPRESS OR IMPLI ED WARRANTY, RELATING TO SALE AND/OR USE OF

NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE,

MERCHANTABILITY, OR I NFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.

Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility

applications.

Numonyx may make changes to specifications and prod uct descriptions at any time, without notice.

Numonyx, B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the

presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied,

by estoppel or otherwise, to any such patents, trademark s, copyrights , or other intellectual property rights.

Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Numonyx reserves

these for future definition and shall have no responsi b ility whatsoever for conflicts or incompatibilities arising from future changes to them.

Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of doc uments which have an order number and are referenced in this document, or other Numonyx literature may be obtained by

visiting Numonyx's website at http://www.numonyx.com.

Numonyx StrataFlash is a trademark or registered trademark o f Numonyx or its sub sidiaries in the United States and other countries.

*Other names and brands may be claimed as the property of others.