General Description
The MAX9317/MAX9317A/MAX9317B/MAX9317C low-
skew, dual 1-to-5 differential drivers are designed for
clock and data distribution. The differential input is
reproduced at five LVDS outputs with a low output-to-
output skew of 5ps.
The MAX9317/MAX9317A are designed for low-voltage
operation from a 2.375V to 2.625V power supply for use
in 2.5V systems. The MAX9317B/MAX9317C operate
from a 3.0V to 3.6V power supply for use in 3.3V sys-
tems. The MAX9317A/MAX9317C feature 50Ωinput ter-
mination resistors to reduce component count.
The MAX9317 family is available in 32-pin 7mm ✕7mm
TQFP and space-saving 5mm ✕5mm QFN packages
and operate across the extended temperature range of
-40°C to +85°C. The MAX9317A is pin compatible with
ON Semiconductor’s MC100EP210S.
Applications
Precision Clock Distribution
Low-Jitter Data Repeaters
Data and Clock Drivers and Buffers
Central-Office Backplane Clock Distribution
DSLAM Backplanes
Base Stations
ATE
Features
♦Guaranteed 1.0GHz Operating Frequency
♦145ps (max) Part-to-Part Skew
♦5ps Output-to-Output Skew
♦330ps Propagation Delay from CLK_ to Q_
♦2.375V to 2.625V Operation (MAX9317/MAX9317A)
♦3.0V to 3.6V Operation (MAX9317B/MAX9317C)
♦ESD Protection: ±2kV (Human Body Model)
♦Internal 50ΩInput Termination Resistors
(MAX9317A/MAX9317C)
MAX9317/MAX9317A/MAX9317B/MAX9317C
Dual 1:5 Differential Clock Drivers with LVPECL
Inputs and LVDS Outputs
________________________________________________________________ Maxim Integrated Products 1
Ordering Information
MAX9317
MAX9317A
MAX9317B
MAX9317C
31 QA0
30 QA0
29 QA1
28 QA1
24 QA3
23 QA3
22 QA4
21 QA4
20 QB0
19 QB0
18 QB1
17 QB1
27 QA2
26 QA2
10
11
QB4
QB4
12
13
QB3
QB3
14
15
QB2
QB2
2
3
4
6
7
5
1, 8
9, 16
25, 32
VCC
VTA
CLKA
CLKA
CLKB
VTB
GND
CLKB
RIN
50Ω
RIN
50Ω
RIN
50Ω
RIN
50Ω
MAX9317A/MAX9317C ONLY.
19-2543; Rev 0; 7/02
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
PA RT
T EM P R AN G E
PIN-
PA CK A G E
N O M IN A L
SU PPL Y
VO LT A G E
( V)
MAX9317ETJ*
-40°C to +85°C 32 Thin QFN
2.5
MAX9317ECJ
-40°C to +85°C
32 TQFP 2.5
MAX9317AETJ*
-40°C to +85°C 32 Thin QFN
2.5
MAX9317AECJ
-40°C to +85°C
32 TQFP 2.5
MAX9317BETJ*
-40°C to +85°C 32 Thin QFN
3.3
MAX9317BECJ
-40°C to +85°C
32 TQFP 3.3
MAX9317CETJ*
-40°C to +85°C 32 Thin QFN
3.3
MAX9317CECJ
-40°C to +85°C
32 TQFP 3.3
Pin Configurations appear at end of data sheet. *Future product—contact factory for availability.
Functional Diagram
MAX9317/MAX9317A/MAX9317B/MAX9317C
Dual 1:5 Differential Clock Drivers with LVPECL
Inputs and LVDS Outputs
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS
(VCC = 2.375V to 2.625V (MAX9317/MAX9317A), VCC = 3.0V to 3.6V (MAX9317B/MAX9317C), all outputs loaded 100Ω±1%
between Q_ and Q_, unless otherwise noted. Typical values are at VCC = 2.5V (MAX9317/MAX9317A), VCC = 3.3V
(MAX9317B/MAX9317C), VIHD = VCC - 1.0V, VILD = VCC - 1.5V, unless otherwise noted.) (Notes 1, 2, and 3)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCC to GND...........................................................-0.3V to +4.1V
Input Pins to GND.......................................-0.3V to (VCC + 0.3V)
Differential Input Voltage .............VCC or 3.0V, whichever is less
Continuous Output Current .................................................28mA
Surge Output Current..........................................................50mA
Continuous Power Dissipation (TA= +70°C)
32-Pin, 7mm ✕7mm TQFP
(derate 20.7mW/°C above +70°C).................................1.65W
32-Pin 5mm ✕5mm QFN
(derate 21.3mW/°C above +70°C)...................................1.7W
Junction-to-Ambient Thermal Resistance in Still Air
32-Pin, 7mm ✕7mm TQFP......................................+48.4°C/W
32-Pin, 5mm ✕5mm QFN ..........................................+47°C/W
Junction-to-Case Thermal Resistance
32-Pin, 7mm ✕7mm TQFP.........................................+12°C/W
32-Pin, 5mm ✕5mm QFN ............................................+2°C/W
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
ESD Protection
Human Body Model (CLK_, CLK_, Q_, Q_, VT_) .............±2kV
Soldering Temperature (10s) ...........................................+300°C
-40°C +25°C +85°C
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX MIN TYP MAX MIN TYP MAX
UNITS
INPUTS (CLK_, CLK_)
Differential Input
High Voltage VIHD Figure 1
1.2 VCC 1.2 VCC 1.2 VCC
V
Differential Input
Low Voltage VILD Figure 1
0
VCC
- 0.1 0
VCC
- 0.1 0
VCC
- 0.1
V
MAX9317/
MAX9317A
0.1 VCC 0.1 VCC 0.1 VCC
Differential Input
Voltage VID VIHD -
VILD
MAX9317B/
MAX9317C
0.1 3.0 0.1 3.0 0.1 3.0
V
Input Current IIH, IIL
CLK_, or CLK_ =
VIHD or VILD,
MAX9317/MAX9317B
-60 +60 -60 +60 -60 +60
µA
Input Termination
Resistance RIN MAX9317A/MAX9317C,
Figure 2 (Note 4)
43 50 57 43 50 57 43 50 57
Ω
OUTPUTS (Q_, Q_)
Output High
Voltage VOH Figure 1
1.6 1.6 1.6
V
Output Low
Voltage VOL Figure 1
0.9 0.9 0.9
V
MAX9317/MAX9317A/MAX9317B/MAX9317C
Dual 1:5 Differential Clock Drivers with LVPECL
Inputs and LVDS Outputs
_______________________________________________________________________________________ 3
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC = 2.375V to 2.625V (MAX9317/MAX9317A), VCC = 3.0V to 3.6V (MAX9317B/MAX9317C), all outputs loaded 100Ω±1%
between Q_ and Q_, unless otherwise noted. Typical values are at VCC = 2.5V (MAX9317/MAX9317A), VCC = 3.3V
(MAX9317B/MAX9317C), VIHD = VCC - 1.0V, VILD = VCC - 1.5V, unless otherwise noted.) (Notes 1, 2, and 3)
-40°C +25°C +85°C
PARAMETER
CONDITIONS
MIN TYP MAX MIN TYP MAX MIN TYP MAX
UNITS
Differential
Output Voltage VOD Figure 1
250 350 450 250 350 450 250 350 450
mV
Change in VOD
Between
Complementary
Output States
∆VOD
750 650 650
mV
Output Offset
Voltage VOS
1.125 1.25 1.375 1.125 1.25 1.375 1.125 1.25 1.375
V
Change in VOS
Between
Complementary
Output States
∆VOS
25 25 25
mV
Q_ shorted to Q_
12 12 12
Output Short-
Circuit Current IOSC Q_ or Q_ shorted to
GND
28 28 28
mA
POWER SUPPLY
MAX9317/9317A
69 107 75 107 80 107
Power-Supply
Current (Note 5) ICC MAX9317B/9317C
75 107 81 107 86 107
mA
AC ELECTRICAL CHARACTERISTICS
(VCC = 2.375V to 2.625V (MAX9317/MAX9317A) or VCC = 3.0V to 3.6V (MAX9317B/MAX9317C), all outputs loaded with 100Ω±1%,
between Q_ and Q_, fIN ≤1.0GHz, input transition time = 125ps (20% to 80%), VIHD - VILD = 0.15V to VCC, unless otherwise noted.
Typical values are at VCC = 2.5V (MAX9317/MAX9317A), VCC = 3.3V (MAX9317B/MAX9317C), fIN = 1.0GHz, VIHD = VCC - 1.0V,
VILD = VCC - 1.5V, unless otherwise noted.) (Notes 1 and 4)
-40°C +25°C +85°C
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX MIN TYP MAX MIN TYP MAX
UNITS
Propagation
Delay CLK_,
CLK_ to Q_, Q_
tPHL
tPLH Figure 1
250 310 600 250 330 600 250 335 600
ps
Output-to-Output
Skew tSKEW1 (Note 6)
955 545 425
ps
Part-to-Part Skew
tSKEW2 (Note 7)
145 145 145
ps
Added Random
Jitter tRJ fIN = 1.0GHz, clock
pattern (Note 8)
0.8 2.0 0.8 2.0 0.8 2.0
ps(RMS)
Added
Deterministic Jitter
tDJ fIN = 1.0GHz, 223 - 1
PRBS pattern (Note 8)
80 105 80 105 80 105
ps(P-P)
Operating
Frequency fMAX VOD ≥ 250mV
1.0 1.0 1.0
GHz
MAX9317/MAX9317A/MAX9317B/MAX9317C
Dual 1:5 Differential Clock Drivers with LVPECL
Inputs and LVDS Outputs
4 _______________________________________________________________________________________
SUPPLY CURRENT vs. TEMPERATURE
MAX9317 toc01
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
603510-15
70
75
80
85
90
65
-40 85
INPUTS OPEN, OUTPUTS TERMINATED
WITH 100Ω DIFFERENTIAL
OUTPUT AMPLITUDE (VOH - VOL)
vs. CLK_ FREQUENCY
MAX9317 toc02
CLK_ FREQUENCY (GHz)
OUTPUT AMPLITUDE (mV)
1.51.00.5
100
200
300
400
0
0 2.0
OUTPUT RISE/FALL TIME
vs. TEMPERATURE
MAX9317 toc03
TEMPERATURE (°C)
OUTPUT RISE/FALL TIME (ps)
603510-15
190
200
210
220
230
180
-40 85
FALL TIME
RISE TIME
CLK-TO-Q PROPAGATION DELAY
vs. TEMPERATURE
MAX9317 toc04
TEMPERATURE (°C)
CLK-TO-Q PROPAGATION DELAY (ps)
603510-15
315
320
325
330
335
340
310
-40 85
tPLH
tPHL
CLK-TO-Q PROPAGATION DELAY vs. HIGH
VOLTAGE OF DIFFERENTIAL INPUT (VIHD)
MAX9317 toc05
HIGH VOLTAGE OF DIFFERENTIAL INPUT (V)
CLK-TO-Q PROPAGATION DELAY (ps)
2.42.11.81.5
322.5
323.0
323.5
324.0
322.0
1.2
tPLH
tPHL
Typical Operating Characteristics
(MAX9317, VCC = 2.5V, all outputs loaded with 100Ω±1%, between Q_ and Q_, fIN = 1.0GHz, input transition time = 125ps (20% to
80%), VIHD = VCC - 1.0V, VILD = VCC - 1.5V, unless otherwise noted.)
Note 1: Measurements are made with the device in thermal equilibrium.
Note 2: Current into a pin is defined as positive. Current out of a pin is defined as negative.
Note 3: DC parameters are production tested at +25°C. DC limits are guaranteed by design and characterization over the full oper-
ating temperature range.
Note 4: Guaranteed by design and characterization, and are not production tested. Limits are set to ±6 sigma.
Note 5: All outputs loaded with 100Ωdifferential, all inputs biased differential high or low except VT_.
Note 6: Measured between outputs of the same device at the signal crossing points for a same-edge transition.
Note 7: Measured between outputs on different devices for identical transitions and VCC levels.
Note 8: Device jitter added to the input signal.
AC ELECTRICAL CHARACTERISTICS (continued)
(VCC = 2.375V to 2.625V (MAX9317/MAX9317A) or VCC = 3.0V to 3.6V (MAX9317B/MAX9317C), all outputs loaded with 100Ω±1%,
between Q_ and Q_, fIN ≤1.0GHz, input transition time = 125ps (20% to 80%), VIHD - VILD = 0.15V to VCC, unless otherwise noted.
Typical values are at VCC = 2.5V (MAX9317/MAX9317A), VCC = 3.3V (MAX9317B/MAX9317C), fIN = 1.0GHz, VIHD = VCC - 1.0V,
VILD = VCC - 1.5V, unless otherwise noted.) (Notes 1 and 4)
-40°C +25°C +85°C
PARAMETER
CONDITIONS
MIN TYP MAX MIN TYP MAX MIN TYP MAX
UNITS
Differential
Output Rise/Fall
Time
tR/tF20% to 80%, Figure 1
140 200 300 140 205 300 140 205 300
ps
MAX9317/MAX9317A/MAX9317B/MAX9317C
Dual 1:5 Differential Clock Drivers with LVPECL
Inputs and LVDS Outputs
_______________________________________________________________________________________ 5
Pin Description
NAME
PIN MAX9317
MAX9317B
MAX9317A
MAX9317C
FUNCTION
1, 8 GND GND Ground
N.C. —No Connection. Connect this pin to ground or leave floating.
2—VTA
CLKA Input Termination Voltage. This pin is connected to CLKA and CLKA through 50Ω
termination resistors. Connect this pin to VCC - 2V for an LVPECL input signal on CLKA or
leave floating for an LVDS input signal.
3 CLKA CLKA Noninverting Differential Clock Input A
4CLKA CLKA Inverting Differential Clock Input A
N.C. —No Connection. Connect this pin to ground or leave floating.
5—VTB
CLKB Input Termination Voltage. This pin is connected to CLKB and CLKB through 50Ω
termination resistors. Connect this pin to VCC - 2V for an LVPECL input signal on CLKB or
leave floating for an LVDS input signal.
6 CLKB CLKB Noninverting Differential Clock Input B
7CLKB CLKB Inverting Differential Clock Input B
9, 16,
25, 32
VCC VCC
Positive Supply Voltage. Bypass each VCC pin to ground with 0.1µF and 0.01µF ceramic
capacitors. Place the capacitors as close to the device as possible with the 0.01µF
capacitor closest to the device.
10 QB4 QB4 CLKB Inverting Differential Output 4. Terminate with 100Ω to QB4.
11 QB4 QB4 CLKB Noninverting Differential Output 4. Terminate with 100Ω to QB4.
12 QB3 QB3 CLKB Inverting Differential Output 3. Terminate with 100Ω to QB3.
13 QB3 QB3 CLKB Noninverting Differential Output 3. Terminate with 100Ω to QB3.
14 QB2 QB2 CLKB Inverting Differential Output 2. Terminate with 100Ω to QB2.
15 QB2 QB2 CLKB Noninverting Differential Output 2. Terminate with 100Ω to QB2.
17 QB1 QB1 CLKB Inverting Differential Output 1. Terminate with 100Ω to QB1.
18 QB1 QB1 CLKB Noninverting Differential Output 1. Terminate with 100Ω to QB1.
19 QB0 QB0 CLKB Inverting Differential Output 0. Terminate with 100Ω to QB0.
20 QB0 QB0 CLKB Noninverting Differential Output 0. Terminate with 100Ω to QB0.
21 QA4 QA4 CLKA Inverting Differential Output 4. Terminate with 100Ω to QA4.
22 QA4 QA4 CLKA Noninverting Differential Output 4. Terminate with 100Ω to QA4.
23 QA3 QA3 CLKA Inverting Differential Output 3. Terminate with 100Ω to QA3.
24 QA3 QA3 CLKA Noninverting Differential Output 3. Terminate with 100Ω to QA3.
26 QA2 QA2 CLKA Inverting Differential Output 2. Terminate with 100Ω to QA2.
27 QA2 QA2 CLKA Noninverting Differential Output 2. Terminate with 100Ω to QA2.
28 QA1 QA1 CLKA Inverting Differential Output 1. Terminate with 100Ω to QA1.
29 QA1 QA1 CLKA Noninverting Differential Output 1. Terminate with 100Ω to QA1.
30 QA0 QA0 CLKA Inverting Differential Output 0. Terminate with 100Ω to QA0.
31 QA0 QA0 CLKA Noninverting Differential Output 0. Terminate with 100Ω to QA0.
—EP EP Exposed Pad. QFN package only. Internally connected to ground.
MAX9317/MAX9317A/MAX9317B/MAX9317C
Detailed Description
The MAX9317 family of low-skew, 1-to-5 dual differen-
tial drivers are designed for clock or data distribution.
Two independent 1-to-5 splitters accept a differential
input signal and reproduce it on five separate differen-
tial LVDS outputs. The output drivers are guaranteed to
operate at frequencies up to 1.0GHz with the LVDS out-
put levels conforming to the EIA/TIA-644 standard.
The MAX9317/MAX9317A operate from a 2.375V to
2.625V power supply for use in 2.5V systems. The
MAX9317B/MAX9317C operate from a 3.0V to 3.6V
supply for 3.3V systems.
Differential LVPECL and LVDS Input
The MAX9317 family has two input differential pairs:
CLKA and CLKA, and CLKB and CLKB. Each differen-
tial input pair can be configured or terminated indepen-
dently. The inputs are designed to be driven by either
LVPECL or LVDS signals with a maximum differential
voltage of VCC or 3.0V, whichever is less.
The MAX9317A/MAX9317C reduce external component
count by having the input 50Ωtermination resistors on
chip. Configure the MAX9317A/MAX9317C to receive
LVPECL signals by connecting VT_ to VCC - 2V (Figure
2(a)). Leaving the VT_ input floating configures the
Dual 1:5 Differential Clock Drivers with LVPECL
Inputs and LVDS Outputs
6 _______________________________________________________________________________________
CLK
CLK
Q_ - Q_
20%
80%
0V
(DIFFERENTIAL)
DIFFERENTIAL
OUTPUT
WAVEFORM
20%
80%
Q_
Q_
VIHD
VILD
VOH
VOL
VIHD - VILD
VOD
tPLH tPHL
tF
tR
Figure 1. MAX9317 Timing Diagram
MAX9317A
MAX9317C
LVPECL
DRIVER
RIN
50Ω
RIN
50Ω
VCC -
2.0V
CLK_
VT_
CLK_
(a) MAX9317A/MAX9317C CONFIGURED FOR LVPECL INPUT SIGNALS.
MAX9317A
MAX9317C
LVDS
DRIVER
RIN
50Ω
RIN
50Ω
VT_
CLK_
CLK_
(b) MAX9317A/MAX9317C CONFIGURED FOR LVDS INPUT SIGNALS.
Figure 2. MAX9317A/MAX9317C Input Terminations
respective input with a differential 100Ωtermination to
receive LVDS signals (Figure 2(b)).
The MAX9317/MAX9317B accept LVPECL if the inputs
are externally terminated with 50Ωresistors from CLKA
and CLKA or CLKB and CLKB to VCC - 2V. Alternatively,
if the inputs are differentially terminated with 100Ω, they
accept an LVDS input signal.
The LVDS input signal must adhere to the specifications
given in the Electrical Characteristics table. Note that the
signal must be at least 1.2V to be a valid logic HIGH.
Applications Information
Output Termination
Terminate the outputs with 100Ωacross each differen-
tial pair (Q_ to Q_). Ensure that output currents do not
exceed the current limits as specified in the Absolute
Maximum Ratings table. Under all operating conditions,
observe the device’s total thermal limits.
Power-Supply Bypassing
Bypass each VCC pin to ground with high-frequency sur-
face-mount ceramic 0.1µF and 0.01µF capacitors in par-
allel and as close to the device as possible, with the
0.01µF capacitor closest to the device. Use multiple par-
allel vias to minimize parasitic inductance and reduce
power-supply bounce with high-current transients.
Circuit Board Traces
Circuit board trace layout is very important to maintain
the signal integrity of high-speed differential signals. Use
50Ωtraces for CLK_, CLK_, Q_, and Q_. Maintaining
integrity is accomplished in part by reducing signal
reflections and skew, and increasing common-mode
noise immunity by keeping the differential traces close
together.
Signal reflections are caused by discontinuities in the
50Ωcharacteristic impedance of the traces. Avoid dis-
continuities by maintaining the distance between differ-
ential traces, and not using sharp corners or vias.
Maintaining distance between the traces also increases
common-mode noise immunity. Reducing signal skew
is accomplished by matching the electrical length of
the differential traces.
Chip Information
TRANSISTOR COUNT: 1119
PROCESS: Bipolar
MAX9317/MAX9317A/MAX9317B/MAX9317C
Dual 1:5 Differential Clock Drivers with LVPECL
Inputs and LVDS Outputs
_______________________________________________________________________________________ 7
MAX9317
MAX9317A
MAX9317B
MAX9317C
TQFP (7mm x 7mm)
TOP VIEW TOP VIEW
32 28
293031 25
26
27
QA2
VCC
VCC
10 13 15
14 1611 12
9
VCC
VCC
QB4
17
18
19
20
21
22
23
24
2
3
4
5
6
7
8GND
CLKA
N.C. (VTA)
N.C. (VTB)
1GND
CLKA
CLKB
CLKB
QB4
QB3
QB3
QB2
QB2
QB1
QB1
QB0
QB0
QA4
QA4
QA3
QA3
QA2
QA1
QA1
QA0
QA0
MAX9317
MAX9317A
MAX9317B
MAX9317C
QFN-EP**
32 28
293031 25
26
27
QA2
VCC
VCC
10 13 15
14 1611 12
9
VCC
VCC
QB4
17
18
19
20
21
22
23
24
2
3
4
5
6
7
8GND
CLKA
N.C. (VTA)
N.C. (VTB)
1GND
CLKA
CLKB
CLKB
QB4
QB3
QB3
QB2
QB2
QB1
QB1
QB0
QB0
QA4
QA4
QA3
QA3
QA2
QA1
QA1
QA0
QA0
**EXPOSED PADDLE
**EXPOSED PADDLE AND CORNER PINS ARE CONNECTED TO V
EE
.( ) MAX9317A/MAX9317C.
Pin Configurations
MAX9317/MAX9317A/MAX9317B/MAX9317C
Dual 1:5 Differential Clock Drivers with LVPECL
Inputs and LVDS Outputs
8 _______________________________________________________________________________________
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
QFN THIN 5x5x0.8 .EPS
D2
(ND-1) X e
e
D
C
PIN # 1
I.D.
(NE-1) X e
E/2
E
0.08 C
0.10 C
A
A1 A3
DETAIL A
0.15 C B
0.15 C A
DOCUMENT CONTROL NO.
21-0140
PACKAGE OUTLINE
16, 20, 28, 32L, QFN THIN, 5x5x0.8 mm
PROPRIETARY INFORMATION
APPROVAL
TITLE:
C
REV.
2
1
E2/2
E2
0.10 M C A B
PIN # 1 I.D.
b
0.35x45
L
D/2 D2/2
L
C
L
C
e e
L
CC
L
k
k
L
L
MAX9317/MAX9317A/MAX9317B/MAX9317C
Dual 1:5 Differential Clock Drivers with LVPECL
Inputs and LVDS Outputs
_______________________________________________________________________________________ 9
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
2
2
21-0140
REV.DOCUMENT CONTROL NO.APPROVAL
PROPRIETARY INFORMATION
TITLE:
COMMON DIMENSIONS EXPOSED PAD VARIATIONS
1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.
3. N IS THE TOTAL NUMBER OF TERMINALS.
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1
SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE
ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE.
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm
FROM TERMINAL TIP.
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.
7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.
8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
9. DRAWING CONFORMS TO JEDEC MO220.
NOTES:
10. WARPAGE SHALL NOT EXCEED 0.10 mm.
C
PACKAGE OUTLINE
16, 20, 28, 32L, QFN THIN, 5x5x0.8 mm
MAX9317/MAX9317A/MAX9317B/MAX9317C
Dual 1:5 Differential Clock Drivers with LVPECL
Inputs and LVDS Outputs
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
10 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
32L/48L,TQFP.EPS
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)