IR2184(4)(S)
Typical Connection
HALF-BRIDGE DRIVER
Features
•Floating channel designed for bootstrap operation
Fully operational to +600V
Tolerant to negative transient voltage
dV/dt immune
•Gate drive supply range from 10 to 20V
•Under voltage lockout for both channels
•3.3V and 5V input logic compatible
•Matched propagation delay for both channels
•Logic and power ground +/- 5V offset.
•Lower di/dt gate driver for better noise immunity
•Output source/sink current capability 1.4A/1.8A
Description
IR21844
IR2184
www.irf.com 1
Data Sheet No. PD60174-D
VCC VB
VS
HO
LOCOM
IN
SD
SD
IN
up to 600V
TO
LOAD
VCC
IN
up to 600V
TO
LOAD
VCC VB
VS
HO
LO
COM
IN
DT
VSS
SD
VCC
SD
VSS RDT
(Refer to Lead Assignments f or correct
configuration). This/These diagram(s) show
electrical connections only . Please refer to
our Application Notes and DesignTips for
proper circuit board lay out.
Packages
14-Lead PDIP
IR21844
8-Lead SOIC
IR2184S
14-Lead SOIC
IR21844S
8-Lead PDIP
IR2184
The IR2184(4)(S) are high voltage,
high speed power MOSFET and IGBT
drivers with dependent high and low
side ref erenced output channels. Pro-
prietary HVIC and latch immune
CMOS technologies enable rugge-
dized monolithic construction. The
logic input is compatible with standard
CMOS or LSTTL output, down to 3.3V
logic. The output drivers feature a high
pulse current buffer stage designed for
minimum driver cross-conduction. The floating channel can be used to drive an N-channel power MOSFET or
IGBT in the high side configuration which operates up to 600 volts.
Part Input
logic
Cross-
conduction
prevention
logic
Dead-Time Ground Pins Ton/Toff
2181 COM
21814 HIN/LIN no none VSS/COM 180/220 ns
2183 Internal 500ns COM
21834 HIN/LIN yes Program 0.4 ~ 5 us VSS/COM 180/220 ns
2184 Internal 500ns COM
21844 IN/SD yes Program 0.4 ~ 5 us VSS/COM 680/270 ns
IR2181/IR2183/IR2184 Feature Comparison
IR2184(4) (S)
2www.irf.com
Symbol Definition Min. Max. Units
VBHigh side floating absolute voltage -0.3 625
VSHigh side floating supply offset voltage VB - 25 VB + 0.3
VHO High side floating output voltage VS - 0.3 VB + 0.3
VCC Low side and logic fixed supply voltage -0.3 25
VLO Low side output voltage -0.3 VCC + 0.3
DT Programmable dead-time pin voltage (IR21844 only) VSS - 0.3 VCC + 0.3
VIN Logic input voltage (IN & SD) VSS - 0.3 VSS + 10
VSS Logic ground (IR21844 only) VCC - 25 VCC + 0.3
dVS/dt Allowable offset supply voltage transient — 50 V/ns
PDPackage power dissipation @ TA ≤ +25°C (8-lead P DIP) — 1.0
(8-lead SOIC) — 0.625
(14-lead PDIP) — 1. 6
(14-lead SOIC) — 1.0
RthJA Thermal resistance, junction to ambient (8-lead PDIP) — 125
(8-lead SOIC) — 200
(14-lead PDIP) — 75
(14-lead SOIC) — 120
TJJunction temperature — 150
TSStorage temperature -50 150
TLLead temperature (soldering, 10 seconds) — 300
V
°C
°C/W
W
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits be y ond which damage to the de vice ma y occur . All voltage parameters
are absolute voltages ref erenced to COM. The thermal resistance and power dissipation ratings are measured under board
mounted and still air conditions.
Recommended Operating Conditions
The input/output logic timing diagram is shown in figure 1. For proper operation the device should be used within the
recommended conditions. The VS and VSS offset rating are tested with all supplies biased at 15V differential.
Note 1: Logic operational for VS of -5 to +600V. Logic state held for V S of -5V to -V BS. (Please refer to the Design Tip
DT97-3 for more details).
Note 2: IN and SD are internally clamped with a 5.2V zener diode.
VB High side floating supply absolute voltage VS + 10 VS + 20
VSHigh side floating supply offset voltage Note 1 600
VHO High side floating output voltage VSVB
VCC Low side and logic fixed supply voltage 10 20
VLO Low side output voltage 0 VCC
VIN Logic input voltage (IN & SD) VSS VSS + 5
DT Programmable dead-time pin voltage (IR21844 only) VSS VCC
VSS Logic ground (IR21844 only) -5 5
TAAmbient temperature -40 125 °C
V
Symbol Definition Min. Max. Units
IR2184(4) (S)
www.irf.com 3
Dynamic Electrical Characteristics
VBIAS (VCC, VBS) = 15V, V SS = COM, CL = 1000 pF, TA = 25°C, DT = VSS unless otherwise specified.
Symbol Definition Min. Typ. Max. Units Test Conditions
ton Turn-on propagation delay — 680 900 VS = 0V
toff Turn-off propagation delay — 270 400 VS = 0V or 600V
tsd Shut-down propagation delay — 180 270
MTon Delay matching, HS & LS tur n-on — 0 90
MToff Delay matching, HS & LS tur n-off — 0 40
trTurn-on rise time — 40 60 VS = 0V
tfTurn-off fall time — 20 35 VS = 0V
DT Deadtime: LO turn-off to HO turn-on(DTLO-HO) & 280 400 520 RDT= 0
HO tur n-off to LO turn-on (DTHO-LO) 456µse c RDT = 200k
MDT Deadtime matching = DTLO - HO - DTHO-LO — 0 50 RDT=0
— 0 600 RDT = 200k
nsec
nsec
Static Electrical Characteristics
VBIAS (VCC, VBS) = 15V, VSS = COM, DT= VSS and TA = 25°C unless otherwise specified. The VIL, VIH and IIN
para m e t e r s are referenced to V SS /COM and are applicable to the respective input leads: IN and SD. The VO, IO and Ron
parameters are referenced to COM and are applicab le to the respective output leads: HO and LO.
Symbol Definition Min. Typ. Max. Units Test Conditions
VIH Logic “1” input voltage for HO & logic “0” for LO 2.7 — — VCC = 10V to 20V
VIL Logic “0” input voltage for HO & logic “1” for LO — — 0.8 VCC = 10V to 20V
VSD,TH+ SD input positive going threshold 2.7 —— V
CC = 10V to 20V
VSD,TH- SD input negative going threshold ——
0.8 VCC = 10V to 20V
VOH High level output voltage, V BIAS - VO— — 1.2 IO = 0A
VOL Low level output voltage, VO— — 0.1 IO = 0A
ILK Offset supply leakage current — — 50 VB = VS = 600V
IQBS Quiescent VBS supply current 20 60 15 0 VIN = 0V or 5V
IQCC Quiescent VCC supply current 0.4 1.0 1.6 mA VIN = 0V or 5V
IIN+ Logic “1” input bias current — 5 20 IN = 5V, SD = 0V
IIN- Logic “0” input bias current — 1 2 IN = 0V, SD = 5V
VCCUV+ VCC and VBS supply undervoltage positive going 8.0 8.9 9.8
VBSUV+ threshold
VCCUV- VCC and VBS dupply undervoltage negative going 7.4 8.2 9.0
VBSUV- threshold
VCCUVH Hysteresis 0.3 0.7 —
VBSUVH
IO+ Output high short circuit pulsed vurrent 1.4 1.9 — VO = 0V,
PW ≤ 10 µs
IO- Output low shor t circuit pulsed current 1.8 2.3 — VO = 15V,
PW ≤ 10 µs
V
µA
µA
V
A
IR2184(4) (S)
4www.irf.com
Functional Block Diagrams
2184
SD
UV
DETECT
DELAY
IN VS
HO
VB
PULSE
FILTER
HV
LEVEL
SHIFTER
R
R
S
Q
UV
DETECT
PULSE
GENERATOR
VSS/COM
LEVEL
SHIFT
VSS/COM
LEVEL
SHIFT
+5V
DEADTIME
COM
LO
VCC
21844
SD
UV
DETECT
DELAY
IN
DT
VSS
VS
HO
VB
PULSE
FILTER
HV
LEVEL
SHIFTER
R
R
S
Q
UV
DETECT
PULSE
GENERATOR
VSS/COM
LEVEL
SHIFT
VSS/COM
LEVEL
SHIFT
+5V
DEADTIME
COM
LO
VCC
IR2184(4) (S)
www.irf.com 5
14-Lead PDIP 14-Lead SOIC
IR21844 IR21844S
Lead Assignments
8-Lead PDIP 8-Lead SOIC
Lead Definitions
Symbol Description
IN Logic input for high and low side gate driver outputs (HO and LO), in phase with HO (referenced to COM
for IR2184 and VSS for IR21844)
SD Logic input for shutdown (referenced to COM for IR2184 and VSS for IR21844)
DT Programmable dead-time lead, referenced to VSS. (IR21844 only)
VSS Logic Ground (21844 only)
VBHigh side floating supply
HO High side gate drive output
VSHigh side floating supply return
VCC Low side and logic fixed supply
LO Low side gate drive output
COM Low side return
IR2184 IR2184S
1
2
3
4
8
7
6
5
IN
SD
COM
LO
VB
HO
VS
VCC
1
2
3
4
8
7
6
5
IN
SD
COM
LO
VB
HO
VS
VCC
1
2
3
4
5
6
7
14
13
12
11
10
9
8
IN
SD
VSS
DT
COM
LO
VCC
VB
HO
VS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
IN
SD
VSS
DT
COM
LO
VCC
VB
HO
VS
IR2184(4) (S)
6www.irf.com
01-6014
01-3003 01 (MS-001AB)
8-Lead PDIP
01-6027
01-0021 11 (MS-012AA)
8-Lead SOIC
87
5
65
D B
E
A
e
6X
H
0.25 [.010] A
6
4312
4. OUTLINE CO NFORMS TO JEDEC OUTLINE MS-012AA.
NOTES:
1. DIMENSIONING & TOLERANCING PER ASME Y 14.5M-1994.
2. CONTROLLING DIMENSION: MILLIMETER
3. DIMENS IONS ARE SHOWN IN M ILLIM ETERS [INCHES].
7
K x 45 °
8X L 8X c
y
FOOTPRINT
8X 0. 72 [.028]
6.46 [.255]
3X 1. 27 [.050] 8X 1.78 [ .070]
5 DIMENSION DO ES NOT INCLUDE MOLD PROTRUSIONS.
6 DIMENSION DO ES NOT INCLUDE MOLD PROTRUSIONS.
MO LD PROTRUSIONS NOT TO EXCEED 0.25 [.010].
7 DIMENSION IS THE LENGTH OF LEAD FOR SOLDERING TO
A SUBSTRATE.
MO LD PROTRUSIONS NOT TO EXCEED 0.15 [.006].
0.25 [.010] C A B
e1 A
A1
8X b
C
0.10 [.004]
e1
D
E
y
b
A
A1
H
K
L
.189
.1497
0°
.013
.050 BASIC
.0532
.0040
.2284
.0099
.016
.1968
.1574
8°
.020
.0688
.0098
.2440
.0196
.050
4.80
3.80
0.33
1.35
0.10
5.80
0.25
0.40
0°
1.27 BASIC
5.00
4.00
0.51
1.75
0.25
6.20
0.50
1.27
MIN MAX MILLIMETERSINCHES MIN MAX
DIM
8°
e
c .0075 .0098 0.19 0.25
.025 BASIC 0 .635 BASIC
IR2184(4) (S)
www.irf.com 7
01-6019
01-3063 00 (MS-012AB)
14-Lead SOIC (narro w body)
01-6010
01-3002 03 (MS-001AC)
14-Lead PDIP
IR2184(4) (S)
8www.irf.com
Figure 1. Input/Output Timing Diagram Figure 2. Switching Time Waveform Definitions
SD
IN
HO
LO
IN(HO)
tr
ton tf
toff
LO
HO
50% 50%
90% 90%
10% 10%
IN(LO)
Figure 5. Delay Matching Waveform Definitions
HO
50% 50%
10%
LO
90%
MT
HOLO
MT
IN(LO)
IN(HO)
Figure 3. Shutdown Waveform Definitions
SD
tsd
HO
LO
50%
90%
Figure 4. Deadtime Waveform Definitions
IN
HO
50% 50%
90%
10%
LO 90%
10%
DTLO-HO
DTLO-HO
MDT= - DTHO-LO
DTHO-LO
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105
Data and specifications subject to change without notice. 7/24/2001
