Datasheet
www.renesas.com
S5D9 Microcontroller Datasheet
Renesas Synergy™ Platform
Synergy Microcontrollers
S5 Series
Nov 2016Rev.1.00
All information contained in these materials, including products and product specifications,
represents information on the product at the time of publication and is subject to change by
Renesas Electronics Corp. without notic e. Please review the latest information published by
Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
website (http://www.renesas.com).
Cover
Notice
1. Descriptions of circuits, software and oth e r rel a ted inf or mation in this document are provided only to illustrate the
operation of semiconductor products and application examples. You are fully responsible for the incorp orat ion of
these circuits, software, and information in the design of your equipm ent. Renesas Electron ics assumes no
responsibility for any losses incurred by you or third parties arising from the use of these circuits, softw a re, or
information.
2. Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas
Electronics does not warrant that such information is error free. Renesas Electronics assumes no liability whatsoever
for any damages incurred by you resulting from errors in or omissi ons from the information included herein.
3. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or othe r intellectual
property rights of third parties by or arising from the use of Renesas Electronics products or technical information
described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights
or other intellectual property ri ghts of Renesas Electronics or others.
4. Yo u should not alt er, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole
or in part. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from
such alteration, modificat ion, copy or otherwise misappropriation of Renesas Electronics product.
5. Renesas Electronics products are classified according to the following two quality grades: "Standard" and "High
Quality". The recommended applications for each Renesas Electronics product depends on the product's quality
grade, as indicated below.
"Standard": Computers; office equipment; comm unications equipment; te st and measurement equipment; audio and
visual equipment; home electronic appliances; machine tools; personal electronic equipment; and
industrial robots etc.
"High Quality": Transportation equi pmen t (automobiles, trains, ships, etc.); traffic control systems; anti-disaster
systems; anti-crime systems; and safety equipment etc.
Renesas Electronics products are neither intended nor authorized for use in products or systems that may pose a direct
threat to human life or bodily injury (arti fici al life support devices or systems, surgical implantations etc.), or may
cause serious property damages (nuclear reactor control systems, military equipment etc.). You must check the
quality grade of each Renesas Electronics product before using it in a particular application. You may not use any
Renesas Electronics product for any application fo r which it is not intended. Renesas El ectronics shall not be in any
way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics
product for which the product is not intended by Re nesas Electronics.
6. Yo u should use the Renesas Electronics products described in this document with in the range specified by Renesas
Electronics, especially with respect to the maximum rating, operating supply voltage range, movement power voltage
range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no
liability for malfunction s or damag e s ari s ing out of the use of Renesas Electronics products beyond such specified
ranges.
7. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor
products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain
use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to
implement safety measures to guard them against the possibility of ph ysical inj ury, and injury or damag e caused by
fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software
including but not limited to redundancy, fire control and malfunction prevention, appropriate treatmen t for aging
degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very
difficult, please evaluate the safety of the final products or systems manufactured by you.
8. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental
compatibility of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all
applicable laws and regulations that regulate the in clusion or use of contro lled substances, including wit hout
limitation, the EU RoHS Directive. Renesas Electronics assumes no liabilit y for damages or losses occurring as a
result of your noncompliance with applicable laws and regulations.
9. Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose
manufacture, use, or sale is prohibited under any applicab le domestic or foreign laws or regulations. You should not
use Renesas Electronics products or technology describe d in th is document for any purpose relatin g to mi litary
applications or use by the military, including but not limited to the development of weapons of mass destru ction.
When exporting the Renesas Electronics products or technology described in this document, you should comply with
the applicable export control laws and regulations and follow the procedures required by such laws and regulations.
10.It is the responsibility of the buyer or distributor of Renesas Electronics products, who distributes, disposes of, or
otherwise places the product with a third party, to notify such third party in advance of the contents and conditions set
forth in this document, Renesas Electronics assu mes no responsibility for any losses incurred by you or third parties
as a result of unauthorized use of Renesas Electronics products.
1 1. This document may not be reproduced or duplicated in any form, in whole or in part, without prior written consent of
Renesas Electronics.
12.Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in
this document or Renesas Electronics pro duct s, or if you hav e any other inquiries.
(Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its
majority-owned subsidiaries.
(Note 2) "Renesas Electronics product(s)" means any product develo ped or manufactured by or for Renesas Electronics.
(2012.4)
General Precautions
1. Precaution against Electrostatic Discharge (ESD)
A strong electrical field, when exposed to a CMOS device, can cause destruction of the gate oxide and ultimately
degrade the device operation. Steps must be taken to stop the generation of static electricity as much as possible, and
quickly dissipate it when it occurs. Environmenta l control must be adequate. When it is dry, a humidifier should be
used. This is recommended to avoid using insulators that can easily build up static electricity. Semiconductor devices
must be stored and tran sp orted in an anti-static container, static shielding bag or conductive material. All test and
measurement tools including work benches and floors must be grounded. The operator must also be grounded using a
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions must be taken for
printed circuit boards with mounted semiconductor devices.
2. Processing at power-on
The state of the product is undefined at the time when power is supplied. The states of internal circuits in the LSI are
indeterminate and the states of register settings and pins are undefined at the time when power is supplied. In a
finished product where the reset signal is applied to the external reset pin , th e states of pins are not guaranteed from
the time when power is supplied until the reset process is completed. In a similar way, the states of pins in a product
that is reset by an on-chip power-on reset function are not guaranteed from the time when power is supplied until the
power reaches the level at which resetting is specified.
3. Input of signal during power-off state
Do not input signals or an I/O pull-up power supply while the device is powered off. The current injection that results
from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes
in the device at this time may cause degradation of internal elements. Follow the guideline for input signal during
power-off state as described in your product do cumentation.
4. Han d l ing of unuse d pins
Handle unused pins in accordance with the directions given under handling of unused pins in the manual. The input
pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit
state, extra electromagnetic noise is induced in the vicinity of the LSI, an associated shoot-through current flows
internally, and malfunctions occur du e to the false recognition of the pin state as an input signal become possible.
5. Clock signals
After applying a reset, only release the reset line after the operating clock signal becomes stable. When switching the
clock signal during program execution, wa it unt il the target clock signal is stabilized. When the clock signal is
generated with an external resonator or from an external oscillator during a reset, ensure that the reset line is only
released after full stabilization of the clock signal. Additionally, when switching to a clock signal produced with an
external resonator or by an external oscillator while program execution is in progress, wait until the target clock
signal is stable.
6. Voltage application waveform at input pin
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device
stays in the area between VIL (Max.) and VIH (Min.) due to noise, for example, the device may malfunction. Take
care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition
period when the input level passes through the area between VIL (Max.) and VIH (Min.).
7. Prohibition of access to reserved addresses
Access to reserved addresses is prohibited. The reserved addresses are provided for possible future expansion of
functions. Do not access these addresses as the correct operation of the LSI is not guaranteed.
8. Diff erences between products
Before changing from one product to another , for example to a product with a different part number, confirm that the
change will not lead to problems. The characteristics of a microprocessing unit or microcontroller unit products in the
same group but having a different part number might differ in terms of internal memory capacity, layout pattern, and
other factors, which can affect the ranges of electrical characteristics, such as characteristic values, operating
margins, immunity to noise, and amount of radiated noise. When changing to a product with a dif ferent part number,
implement a system-evaluation test for the given product.
R01DS0303EU0100 Rev.1.00 Page 4 of 115
Nov 3, 2016
■ ARM Cortex-M4 Core with Floating Point Unit (FPU)
ARMv7E-M architecture with DSP instruction set
Maximum operating frequ e ncy: 120 MHz
Support for 4-GB address space
On-chip debugging system: JTAG, SWD, and ETM
Boundary scan and ARM Memory Protection Unit (MPU)
■ Memory
Up to 2-MB code flash memory (40 MHz zero wait states)
64-KB data flash memory (up to 100,000 erase/write cycles)
Up to 640-KB SRAM
Flash Cache (FCACHE)
Memory Protection Units (MPU)
Memory Mirror Function (MMF)
128-bit unique ID
■ Connectivity
Ethernet MAC Controller (ETHERC)
Ethernet DMA Controller (EDMAC)
Ethernet PTP Controller (EPTPC)
USB 2.0 High-Speed Module (USBHS)
- On-chip transceiver
- USB battery charge version 1.2 supported
USB 2.0 Full-Speed Module (USBFS)
- On-chip transceiver
Serial Communications Interface (SCI) with FIFO × 10
Serial Peripheral Interface (SPI) × 2
I2C Bus Interface (IIC) × 3
CAN module (CAN) × 2
Serial Sound Interface Enhanced (SSIE) × 2
SD/MMC Host Interfa ce (SDHI) × 2
Quad Serial Peripheral Interface (QSPI)
IrDA interface
Sampling Rate Converter (SRC)
External address space
- 8- or 16-bit bus space is selectable per area
- SDRAM support
■ Analog
12-Bit A/D Converter (ADC12) with 3 sample-and-ho ld circuits
each × 2
12-Bit D/A Converter (DAC12) × 2
High-Speed Analog Comparator (ACMPHS) × 6
Programmable Gain Amplifier (PGA) × 6
Temperature sensor (TSN)
■ Timers
General PWM Timer 32-Bit Enhanced High Resolution
(GPT32EH) × 4
General PWM Timer 32-Bit Enhanced (GPT32E) × 4
General PWM Timer 32-Bit (GPT32) × 6
Asynchronous Genera l-Pu rp ose Tim er (AGT) × 2
Watchdog Timer (WDT)
■ Safety
ECC in SRAM
SRAM parity error check
Flash area protection
ADC self-diagnosis function
Clock Frequency Accuracy Measurement Circuit (CAC)
Cyclic Redundancy Check (CRC) calculator
Data Operation Circuit (DOC)
Port Output Enable for GPT (POEG)
Independent Watchdog Timer (IWDT)
GPIO readback level detection
Register write protection
Main oscillator stop detection
Illegal memory access
■ System and Power Management
Low-power modes
Realtime Clock (RTC) with calendar and VBATT support
Event Link Controller (ELC)
DMA Controller (DMAC) × 8
Data Transfer Controller (DTC)
Key interrupt function (KINT)
Power-on reset
Low Voltage Detection (LVD) with voltage settings
■ Security and Encryption
AES128/192/256
3DES/ARC4
SHA1/SHA224/SHA256
GHASH
RSA/DSA
True Random Number Gen erato r (T RNG)
■ Human Machine Interface (HMI)
Graphics LCD Controller (GLCDC)
JPEG Codec
2D Drawing Engine (DRW)
Capacitive Touch Sensing Unit (CTSU)
Parallel Data Capture Unit (PDC)
■ Multiple Clock Sources
Main clock oscillator (MOSC) (8 to 24 MHz)
Sub-clock oscillator (SOSC) (32.768 kHz)
High-speed on-chip oscillator (HOCO) (16/18/20 MHz)
Middle-speed on-chip oscillator (MOCO) (8 MHz)
Low-speed on-chip oscillator (LOCO) (32.768 kHz)
Independent Watchdog Timer OCO (15 kHz)
Clock trim function for HOCO/MOCO/LOCO
Clock out support
■ General-Purpose I/O Ports
Up to 133 input/output pins
- Up to 9 CMOS input
- Up to 124 CMOS input/output
- Up to 21 5-V tolerant input/output
- Up to 18 high current (20 mA)
■ Operating Voltage
VCC: 2.7 to 3.6 V
■ Operating Temperature and Packages
Ta = –40°C to +85°C
- 176-pin BGA (13 mm × 13 mm, 0.8 mm pitch)
- 145-pin LGA (7 mm × 7 mm, 0.5 mm pitch)
Ta = –40°C to +105°C
- 176-pin LQFP (24 mm × 24 mm, 0. 5 mm pitch)
- 144-pin LQFP (20 mm × 20 mm, 0. 5 mm pitch)
- 100-pin LQFP (14 mm × 14 mm, 0. 5 mm pitch)
S5D9 MCU (High-integration MCU)
32-bit ARM® Cortex®-M4 microcontroller
Leading performance 120-MHz ARM Cortex-M4 microcontroller, up to 2-MB code flash memory, 640-KB SRAM,
Graphics LCD Controller, 2D Drawing Engine, Capacitive Touch Sensing Unit, Ethernet MAC Controller with IEEE 1588
PTP, USB 2.0 High-Speed, USB 2.0 Full-Speed, SDHI, Quad SPI, security and safety features, and advanced analog.
Features
R01DS0303EU0100 Rev.1.00 Page 5 of 115
Nov 3, 2016
S5D9 1. Overview
1. Overview
The S5D9 MCU integrates multiple series of software- and pi n-compatible ARM®-based 32-bit MCUs that share the
same set of Renesas peripherals to facilitate design scalability and efficient platform-based product development.
The MCU provides a high-performance ARM Cortex®-M4 core running up to 120 MHz with the fo llowing features:
Up to 2-MB code flash memory
640-KB SRAM
Graphics LCD Controller (GLCDC)
2D Drawing Engine (DRW)
Capacitive Touch Sensing Unit (CTSU)
Ethernet MAC Controller (ETHERC) with IEEE 1588 PTP, USBFS, USBHS, SD/MMC Host Interface
Quad Serial Peripheral Interface (QSPI)
Security and safety features
Analog peripherals.
1.1 Function Outline
Table 1.1 ARM core
Feature Functional description
ARM Cortex-M4 Maximum operating frequency: up to 120 MHz
ARM Cortex-M4 core:
- Revision: r0p1-01rel0
- ARMv7E-M architecture profile
- Single precision floating point unit compliant with the ANSI/IEEE Std 754-2008
ARM Memory Protection Unit (MPU):
- ARMv7 Protected Memory System Architecture
- 8 protect regions
SysTick timer:
- Driven by LOCO clock
Table 1.2 Memory
Feature Functional description
Code flash memory Maximum 2 MB of code flash memory. See section 55, Flash Memory in User's Manual.
Data flash memory 64 KB of data flash memory. See section 55, Flash Memory in User's Manual.
Memory Mirror Function (MMF) The MMF can be configured to mirror the wanted application image load address in code flash
memory to the application image link address in the 23-bit unused memory space (memory
mirror space addresses). Your application code is developed and linked to run from this MMF
destination address. The application code does not need to know the load location where it is
stored in code flash memory. See section 5, Memory Mirror Function (MMF) in User's Manual.
SRAM On-chip high-speed SRAM providing either parity-bit or Error Correction Code (ECC). The first
32 KB of SRAM0 is subject to ECC. Parity check is performed for other areas. See section 53,
SRAM in User's Manual.
Standby SRAM On-chip SRAM that can retain data in Deep Software Standby mode. See section 54, Standby
SRAM in User's Manual.
Table 1.3 System (1 of 3)
Feature Functional description
Operating modes Two operating modes:
- Single-chip mode
- SCI or USB boot mode.
See section 3, Operating Modes in User's Manual.
R01DS0303EU0100 Rev.1.00 Page 6 of 115
Nov 3, 2016
S5D9 1. Overview
Resets 14 resets:
RES pin reset
Power-on reset
Voltage monitor reset 0
Voltage monitor reset 1
Voltage monitor reset 2
Independent Watchdog Timer reset
Watchdog Timer reset
Deep Software Standby reset
SRAM parity error reset
SRAM ECC error reset
Bus master MPU error reset
Bus slave MPU error reset
Stack pointer error reset
Software reset.
See section 6, Resets in User's Manual.
Low Voltage Detection (LVD) The Low Voltage Detection (LVD) function monitors the voltage level input to the VCC pin, and
the detection level can be selected in the software program. See section 8, Low Voltage
Detection (LVD) in User's Manual.
Clocks Main clock oscillator (MOSC)
Sub-clock oscillator (SOSC)
High-speed on-chip oscillator (HOCO)
Middle-speed on-chip oscillator (MOCO)
Low-speed on-chip oscillator (LOCO)
PLL frequency synthesizer
Independent Watchdog Timer (WDT) on-chip oscillator
Clock out support.
See section 9, Clock Generation Circuit in User's Manual.
Clock Frequency Accuracy
Measurement Circuit (CAC)
The CAC checks the system clock frequency with a reference clock signal by counting the
number of pulses of the system clock to be measured. The reference clock can be provided
externally through a CACREF pin or internally from various on-chip oscillators.
Event signals can be generated when the clock does not match or measurement ends. This
feature is particularly useful in implementing a fail-safe mechanism for home and industrial
automation applications.
See section 10, Clock Frequency Accuracy Measurement Circuit (CAC) in User's Manual.
Interrupt Controller Unit (ICU) The ICU controls which event signals are linked to the NVIC/DTC module and DMAC module.
The ICU also controls NMI interrupts. See section 14, Interrupt Controller Unit (ICU) in User's
Manual.
Key interrupt function (KINT) A key interrupt can be generated by setting the Key Return Mode register (KRM) and inputting
a rising or falling edge to the key interrupt input pins. See section 21, Key Interrupt Function
(KINT) in User's Manual.
Low-power modes Power consumption can be reduced in multiple ways, including by setting clock dividers,
controlling EBCLK output, controlling SDCLK output, stopping modules, selecting power
control mode in normal operation, and transitioning to low-power modes. See section 11, Low-
Power Modes in User's Manual.
Battery backup function A battery backup function is provided for partial powering by a battery. The battery-powered
area includes the RTC, SOSC, backup memory, and switch between VCC and VBATT. See
section 12, Battery Backup Function in User's Manual.
Register write protection The register write protection function protects important registers from being overwritten
because of software errors. See section 13, Register Write Protection in User's Manual.
Memory Protection Unit (MPU) Four MPUs and a CPU stack pointer monitor function are provided for memory protection. See
section 16, Memory Protection Unit (MPU) in User's Manual.
Watchdog Timer (WDT) The WDT is a 14-bit down-counter. It can be used to reset the MCU when the counter
underflows because the system has run out of control and is unable to refresh the WDT. In
addition, a non-maskable interrupt or interrupt can be generated by an underflow.
A refresh-permitted period can be set to refresh the counter and be used as the condition for
detecting when the system runs out of control. See section 27, Watchdog Timer (WDT) in
User's Manual.
Table 1.3 System (2 of 3)
Feature Functional description
R01DS0303EU0100 Rev.1.00 Page 7 of 115
Nov 3, 2016
S5D9 1. Overview
Independent Watchdog Timer (IWDT) The IWDT consists of a 14-bit down-counter that must be serviced periodically to prevent
counter underflow. The IWDT provides functionality to reset the MCU or to generate a non-
maskable interrupt or interrupt for a timer underflow. Because the timer operates with an
independent, dedicated clock source, it is particularly useful in returning the MCU to a known
state as a fail safe mechanism when the system runs out of control. The IWDT can be
triggered automatically on a reset, underflow, or refresh error, or by a refresh of the count value
in the registers. See section 28, Independent Watchdog Timer (IWDT) in User's Manual.
Table 1.4 Event link
Feature Functional description
Event Link Controller (ELC) The ELC uses the interrupt requests generated by various peripheral modules as event
signals to connect them to different modules, enabling direct interaction between the modules
without CPU intervention. See section 19, Event Link Controller (ELC) in User's Manual.
Table 1.5 Direct memory access
Feature Functional description
Data Transfer Controller (DTC) A DTC module is provided for transferring data when activated by an interrupt request. See
section 18, Data Transfer Controller (DTC) in User's Manual.
DMA Controller (DMAC) An 8-channel DMAC module is provided for transferring data without the CPU. When a DMA
transfer request is generated, the DMAC transfers data stored at the transfer source address
to the transfer destination address. See section 17, DMA Controller (DMAC) in User's Manual.
Table 1.6 External bus interfa ce
Feature Functional description
External buses CS area (EXBIU): Connected to the external devices (external memory interface)
SDRAM area (EXBIU): Connected to the SDRAM (external memory interface)
QSPI area (EXBIUT2): Connected to the QSPI (external device interface).
Table 1.7 Timers
Feature Functional description
General PWM Timer (GPT) The GPT is a 32-bit timer with 14 channels. PWM waveforms can be generated by controlling
the up-counter, down-counter, or up- and down-counter. In addition, PWM waveforms can be
generated for controlling brushless DC motors. The GPT can also be used as a general-
purpose timer. See section 23, General PWM Timer (GPT) in User's Manual.
Port Output Enable for GPT (POEG) Use the Port Output Enable for GPT (POEG) function to place the General PWM Timer (GPT)
output pins in the output disable state. See section 22, Port Output Enable for GPT (POEG) in
User's Manual.
Asynchronous General-Purpose
Timer (AGT)
The AGT is a 16-bit timer that can be used for pulse output, external pulse width or period
measurement, and counting of external events.
This 16-bit timer consists of a reload register and a down-counter. The reload register and the
down-counter are allocated to the same address, and can be accessed with the AGT register.
See section 25, Asynchronous General-Purpose Timer (AGT) in User's Manual.
Realtime Clock (RTC) The RTC has two counting modes, calendar count mode and binary count mode, that are
controlled by the register settings.
For calendar count mode, the RTC has a 100-year calendar from 2000 to 2099 and
automatically adjusts dates for leap years.
For binary count mode, the RTC counts seconds and retains the information as a serial value.
Binary count mode can be used for calendars other than the Gregorian (Western) calendar.
See section 26, Realtime Clock (RTC) in User's Manual.
Table 1.3 System (3 of 3)
Feature Functional description
R01DS0303EU0100 Rev.1.00 Page 8 of 115
Nov 3, 2016
S5D9 1. Overview
Table 1.8 Communication int erfa c es (1 of 2)
Feature Functional description
Serial Communications Interface
(SCI)
The SCI is configurable to five asynchronous and synchronous serial interfaces:
Asynchronous interfaces (UART and Asynchronous Communications Interface Adapter
(ACIA))
8-bit clock synchronous interface
Simple IIC (master-only)
Simple SPI
Smart card interface.
The smart card interface complies with the ISO/IEC 7816-3 standard for electronic signals and
transmission protocol.
Each SCI has FIFO buffers to enable continuous and full-duplex communication, and the data
transfer speed can be configured independently using an on-chip baud rate generator. See
section 34, Serial Communications Interface (SCI) in User's Manual.
IrDA Interface (IrDA) The IrDA interface sends and receives IrDA data communication waveforms in cooperation
with the SCI1 based on the IrDA (Infrared Data Association) standard 1.0. See section 35,
IrDA Interface in User's Manual.
I2C Bus Interface (IIC) The three-channel IIC conforms with and provides a subset of the NXP I2C bus (Inter-
Integrated Circuit bus) interface functions. See section 36, I2C Bus Interface (IIC) in User's
Manual.
Serial Peripheral Interface (SPI) Two independent SPI channels are capable of high-speed, full-duplex synchronous serial
communications with multiple processors and peripheral devices. See section 38, Serial
Peripheral Interface (SPI) in User's Manual.
Serial Sound Interface Enhanced
(SSIE)
The Serial Sound Interface Enhanced (SSIE) peripheral provides functionality to interface with
digital audio devices for transmitting I2S 2ch, 4ch, 6ch, 8ch, WS Continue/Monaural/TDM
audio data over a serial bus. The SSIE supports an audio clock frequency of up to 50 MHz,
and can be operated as a slave or master receiver, transmitter, or transceiver to suit various
applications. The SSIE includes 32-stage FIFO buffers in the receiver and transmitter, and
supports interrupts and DMA-driven data reception and transmission. See section 41, Serial
Sound Interface Enhanced (SSIE) in User's Manual.
Quad Serial Peripheral Interface
(QSPI)
The QSPI is a memory controller for connecting a serial ROM (nonvolatile memory such as a
serial flash memory, serial EEPROM, or serial FeRAM) that has an SPI-compatible interface.
See section 39, Quad Serial Peripheral Interface (QSPI) in User's Manual.
CAN module (CAN) The CAN module provides functionality to receive and transmit data using a message-based
protocol between multiple slaves and masters in electromagnetically-noisy applications.
The CAN module complies with the ISO 11898-1 (CAN 2.0A/CAN 2.0B) standard and supports
up to 32 mailboxes, which can be configured for transmission or reception in normal mailbox
and FIFO modes. Both standard (11-bit) and extended (29-bit) messaging formats are
supported. See section 37, Controller Area Network (CAN) Module in User's Manual.
USB 2.0 Full-Speed Module (USBFS) Full-Speed USB controller that can operate as a host controller or device controller. The
module supports full-speed and low-speed (host controller only) transfer as defined in
Universal Serial Bus Specification 2.0. The module has an internal USB transceiver and
supports all of the transfer types defined in Universal Serial Bus Specification 2.0.
The USB has buffer memory for data transfer, providing a maximum of 10 pipes. Pipes 1 to 9
can be assigned any endpoint number based on the peripheral devices used for
communication or based on your system. See section 32, USB 2.0 Full-Speed Module
(USBFS) in User's Manual.
USB 2.0 High-Speed Module
(USBHS)
High-Speed USB controller that can operate as a host controller or a device controller. As a
host controller, the USBHS supports high-speed transfer, full-speed transfer, and low-speed
transfer as defined in Universal Serial Bus Specification 2.0. As a device controller, the USBHS
supports high-speed transfer and full-speed transfer as defined in Universal Serial Bus
Specification 2.0. The USBHS has an internal USB transceiver and supports all of the transfer
types defined in Universal Serial Bus Specification 2.0.
The USBHS has FIFO buffers for data transfer, providing a maximum of 10 pipes. Any
endpoint number can be assigned to pipes 1 to 9, based on the peripheral devices or your
system for communication. See section 33, USB 2.0 High-Speed Module (USBHS) in User's
Manual.
R01DS0303EU0100 Rev.1.00 Page 9 of 115
Nov 3, 2016
S5D9 1. Overview
Ethernet MAC with IEEE 1588 PTP
(ETHERC)
One-channel Ethernet MAC Controller (ETHERC) compliant with the Ethernet/IEEE802.3
Media Access Control (MAC) layer protocol. An ETHERC channel provides one channel of the
MAC layer interface, connecting the MCU to the physical layer LSI (PHY-LSI) that allows
transmission and reception of frames compliant with the Ethernet and IEEE802.3 standards.
The ETHERC is connected to the Ethernet DMA Controller (EDMAC) so data can be
transferred without using the CPU.
To handle timing and synchronization between devices, an on-chip Precision Time Protocol
(PTP) module for the Ethernet PTP Controller (EPTPC) applies the PTP defined in the IEEE
1588-2008 version 2.0 standard.
The EPTPC is composed of:
Synchronization Frame Processing unit (SYNFP0)
A Statistical Time Correction Algorithm unit (STCA).
Use the EPTPC in combination with the on-chip Ethernet MAC Controller (ETHERC) and the
DMA Controller for the PTP Ethernet Controller (PTPEDMAC). See section 29, Ethernet MAC
Controller (ETHERC) in User's Manual.
SD/MMC Host Interface (SDHI) The SDHI and MultiMediaCard (MMC) interface module provides the functionality required to
connect a variety of external memory cards to the MCU. The SDHI supports both 1- and 4-bit
buses for connecting memory cards that support SD, SDHC, and SDXC formats. When
developing host devices that are compliant with the SD Specifications, you must comply with
the SD Host/Ancillary Product License Agreement (SD HALA).
The MMC interface supports 1-, 4-, and 8-bit MMC buses that provide eMMC 4.51 (JEDEC
Standard JESD 84-B451) device access. This interface also provides backward compatibility
and supports high-speed SDR transfer modes. See section 43, SD/MMC Host Interface
(SDHI) in User's Manual.
Table 1.9 Analog
Feature Functional description
12-Bit A/D Converter (ADC12) Up to two successive approximation 12-Bit A/D Converters are provided. In unit 0, up to 13
analog input channels are selectable. In unit 1, up to 11 analog input channels, the
temperature sensor output, and an internal reference voltage are selectable for conversion.
The A/D conversion accuracy is selectable from 12-, 10-, and 8-bit conversion, making it
possible to optimize the tradeoff between speed and resolution in generating a digital value.
See section 47, 12-Bit A/D Converter (ADC12) in User's Manual.
12-Bit D/A Converter (DAC12) The DAC12 D/A converts data and includes an output amplifier. See section 48, 12-Bit D/A
Converter (DAC12) in User's Manual.
Temperature sensor (TSN) The on-chip temperature sensor can determine and monitor the die temperature for reliable
operation of the device. The sensor outputs a voltage directly proportional to the die
temperature, and the relationship between the die temperature and the output voltage is linear.
The output voltage is provided to the ADC12 for conversion and can also be used by the end
application. See section 49, Temperature Sensor (TSN) in User's Manual.
High-Speed Analog Comparator
(ACMPHS)
Analog comparators can be used to compare a test voltage with a reference voltage and to
provide a digital output based on the conversion result.
Both the test and reference voltages can be provided to the comparator from internal sources
such as the DAC12 output and internal reference voltage, and an external source with or
without an internal PGA.
Such flexibility is useful in applications that require go/no-go comparisons to be performed
between analog signals without necessarily requiring A/D conversion. See section 50, High-
Speed Analog Comparator (ACMPHS) in User's Manual.
Table 1.10 Human machine interfaces
Feature Functional description
Capacitive Touch Sensing Unit
(CTSU)
The CTSU measures the electrostatic capacitance of the touch sensor. Changes in the
electrostatic capacitance are determined by the software, which enables the CTSU to detect
whether a finger is in contact with the touch sensor. The electrode surface of the touch sensor
is usually enclosed with an electrical conductor so that fingers do not come into direct contact
with the electrodes. See section 51, Capacitive Touch Sensing Unit (CTSU) in User's Manual.
Table 1.8 Communication int erfa c es (2 of 2)
Feature Functional description
R01DS0303EU0100 Rev.1.00 Page 10 of 115
Nov 3, 2016
S5D9 1. Overview
Table 1.11 Graphics
Feature Functional description
Graphics LCD Controller (GLCDC) The GLCDC provides multiple functions and supports various data formats and panels. Key
GLCDC features include:
GPX bus master function for accessing graphics data
Superimposition of three planes (single color background plane, graphic 1 plane, and
graphic 2 plane)
Support for many types of 32- or 16-bit per pixel graphics data and 8-, 4-, or 1-bit LUT data
format
Digital interface signal output supporting a video image size of WVGA or greater.
See section 58, Graphics LCD Controller (GLCDC) in User's Manual.
2D Drawing Engine (DRW) The 2D Drawing Engine (DRW) provides flexible functions that can support almost any object
geometry rather than being bound to only a few specific geometries such as lines, triangles, or
circles. The edges of every object can be independently blurred or antialiased.
Rasterization is executed at one pixel per clock on the bounding box of the object from left to
right and top to bottom. The DRW can also raster from bottom to top to optimize the
performance in certain cases. In addition, optimization methods are available to avoid
rasterization of many empty pixels of the bounding box.
The distances to the edges of the object are calculated by a set of edge equations for every
pixel of the bounding box. These edge equations can be combined to describe the entire
object.
If a pixel is inside the object, it is selected for rendering. If it is outside, it is discarded. If it is on
the edge, an alpha value can be chosen proportional to the distance of the pixel to the nearest
edge for antialiasing.
Every pixel that is selected for rendering can be textured. The resulting aRGB quadruple can
be modified by a general raster operation approach independently for each of the four
channels. The aRGB quadruples can then be blended with one of the multiple blend modes of
the DRW.
The DRW provides two inputs (texture read and framebuffer read), and one output
(framebuffer write).
The internal color format is always aRGB (8888). The color formats from the inputs are
converted to the internal format on read and a conversion back is made on write.
See section 56, 2D Drawing Engine (DRW) in User's Manual.
JPEG Codec (JPEG) The JPEG Codec (JPEG) incorporates a JPEG codec that conforms to the JPEG baseline
compression and decompression standard. This provides high-speed compression of image
data and high-speed decoding of JPEG data. See section 57, JPEG Codec (JPEG) in User's
Manual.
Parallel Data Capture Unit (PDC) One PDC unit is provided for communicating with external I/O devices, including image
sensors, and transferring parallel data such as an image output from the external I/O device
through the DTC or DMAC to the on-chip SRAM and external address spaces (the CS and
SDRAM areas). See section 44, Parallel Data Capture Unit (PDC) in User's Manual.
Table 1.12 Data proce s sing
Feature Functional description
Cyclic Redundancy Check (CRC)
calculator
The CRC calculator generates CRC codes to detect errors in the data. The bit order of CRC
calculation results can be switched for LSB-first or MSB-first communication. Additionally,
various CRC-generating polynomials are available. The snoop function allows monitoring
reads from and writes to specific addresses. This function is useful in applications that require
CRC code to be generated automatically in certain events, such as monitoring writes to the
serial transmit buffer and reads from the serial receive buffer. See section 40, Cyclic
Redundancy Check (CRC) Calculator in User's Manual.
Data Operation Circuit (DOC) The DOC compares, adds, and subtracts 16-bit data. See section 52, Data Operation Circuit
(DOC) in User's Manual.
Sampling Rate Converter (SRC) The SRC converts the sampling rate of data produced by various audio decoders, such as the
WMA, MP3, and AAC. Both 16-bit stereo and monaural data are supported.
See section 42, Sampling Rate Converter (SRC) in User's Manual.
R01DS0303EU0100 Rev.1.00 Page 11 of 115
Nov 3, 2016
S5D9 1. Overview
1.2 Block Diagram
Figure 1.1 shows the block diagram of the MCU superset. Some individual devices within the group have a subset of the
features.
Table 1.13 Security
Feature Functional description
Secure Crypto Engine 7 (SCE7) Security algorithms:
- Symmetric algorithms: AES, 3DES, and ARC4
- Asymmetric algorithms: RSA and DSA.
Other support features:
- TRNG (True Random Number Generator)
- Hash-value generation: SHA1, SHA224, SHA256, GHASH
- 128-bit unique ID.
R01DS0303EU0100 Rev.1.00 Page 12 of 115
Nov 3, 2016
S5D9 1. Overview
Figure 1.1 Block diagram
Memory
2 MB code flash
64 KB data flash
640 KB SRAM
DMA
DMAC × 8
System
Mode control
Power control
Register write
protection
MOSC/SOSC
Clocks
(H/M/L) OCO
PLL/USBPLL
Battery backup
GPT32EH x 4
GPT32E x 4
GPT32 x 6
Timers
AGT × 2
RTC
CTSU
ARM Cortex-M4
DSP FPU
MPU
NVIC
System timer
Test and DBG interface
DTC
WDT/IWDT
CAC
POR/LVD
Reset
Human machine interfaces
GLCDC
Graphics
DRW
JPEG Codec
PDC
ELC
Event link
SCE7
Security
Analog
CRC
Data processing
DOC
SRC
Communication interfaces
QSPI USBHS
IIC × 3 SDHI × 2 ETHERC
with IEEE 1588
SPI × 2 CAN × 2
SSIE × 2 USBFS
SCI × 10
IrDA × 1
TSN
DAC12 ACMPHS × 6
ADC12 with
PGA × 2
8 KB Standby
SRAM
Bus
MPU
CSC
External
SDRAM
KINT
ICU
R01DS0303EU0100 Rev.1.00 Page 13 of 115
Nov 3, 2016
S5D9 1. Overview
1.3 Part Numbering
Figure 1.2 Part numbering scheme
Table 1.14 List of Products
Part Number Orderable Part Number Package Code
flash Data
flash SRAM Operating
Temperature
R7FS5D97E2A01CBG R7FS5D97E2A01CBG#AC0 PLBG0176GE-A 2 MB 64 KB 640 KB -40 to +85°C
R7FS5D97E3A01CFC R7FS5D97E3A01CFC#AA0 PLQP0176KB-A -40 to +105°C
R7FS5D97E2A01CLK R7FS5D97E2A01CLK#AC0 PTLG0145KA-A -40 to +85°C
R7FS5D97E3A01CFB R7FS5D97E3A01CFB#AA0 PLQP0144KA-B -40 to +105°C
R7FS5D97E3A01CFP R7FS5D97E3A01CFP#AA0 PLQP0100KB-B -40 to +105°C
R7FS5D97C2A01CBG R7FS5D97C2A01CBG#AC0 PLBG0176GE-A 1 MB -40 to +85°C
R7FS5D97C3A01CFC R7FS5D97C3A01CFC#AA0 PLQP0176KB-A -40 to +105°C
R7FS5D97C2A01CLK R7FS5D97C2A01CLK#AC0 PTLG0145KA-A -40 to +85°C
R7FS5D97C3A01CFB R7FS5D97C3A01CFB#AA0 PLQP0144KA-B -40 to +105°C
R7FS5D97C3A01CFP R7FS5D97C3A01CFP#AA0 PLQP0100KB-B -40 to +105°C
R 7 F S 5 D 9 7
Package type
BG: BGA 176 pins
FC: LQFP 176 pins
FB: LQFP 144 pins
FP: LQFP 100 pins
LK: LGA 145 pins
Quality ID
Software ID
Operating temperature
2: -40°C to 85°C
3: -40°C to 105°C
Code flash memory size
C: 1 MB
E: 2 MB
Feature set
7: Superset
Group name
9: S5D9
Core
D: ARM Cortex-M4, 120 MHz
Series name
5: High integration
Renesas Synergy family
Flash memory
Renesas microcontroller unit
Renesas
E 2 A 0 1 C B G # A C 0
Packaging, Terminal material (Pb-free)
#AA: Tray/Sn (Tin) only
#AC: Tray/others
Production identification code
R01DS0303EU0100 Rev.1.00 Page 14 of 115
Nov 3, 2016
S5D9 1. Overview
1.4 Function Comparison
Table 1.15 Functional comparison (Graphics)
Function
Part numbers
R7FS5D97E2XXXCBG/
R7FS5D97C2XXXCBG R7FS5D97E3XXXCFC/
R7FS5D97C3XXXCFC R7FS5D97E2XXXCLK/
R7FS5D97C2XXXCLK R7FS5D97E3XXXCFB/
R7FS5D97C3XXXCFB R7FS5D97E3XXXCFP/
R7FS5D97C3XXXCFP
Pin count 176 176 145 144 100
Package BGA LQFP LGA LQFP LQFP
Code flash memory 2/1 MB
Data flash memory 64 KB
SRAM 640 KB
Parity 608 KB
ECC 32 KB
Standby SRAM 8 KB
System CPU clock 120 MHz
Backup
registers
512 B
ICU Yes
KINT 8
Event link ELC Yes
DMA DTC Yes
DMAC 8
BUS External bus 16-bit bus 8-bit bus
SDRAM Yes No
Timers GPT32EH 4 4 4 4 4
GPT32E44444
GPT32 6 6 6 6 5
AGT 2 2 2 2 2
RTC Yes
WDT/IWDT Yes
Communication SCI 10
IIC 3 2
SPI 2
SSIE 2 1
QSPI 1
SDHI 2
CAN 2
USBFS Yes
USBHS Yes No
ETHERC 1
Analog ADC12 24 22 19
DAC12 2
ACMPHS 6
TSN Yes
HMI CTSU 13 18 12
Graphics GLCDC RGB888
DRW Yes
JPEG Yes
PDC Yes
Data processing CRC Yes
DOC Yes
SRC Yes
Security SCE7
R01DS0303EU0100 Rev.1.00 Page 15 of 115
Nov 3, 2016
S5D9 1. Overview
1.5 Pin Functions
Table 1.16 Pin functions (1 of 5)
Function Signal I/O Description
Power supply VCC Input Digital voltage supply pin. This is used as the digital power supply for the
respective modules and internal voltage regulator, and used to monitor the
voltage of the POR/LVD. Connect to the system power supply. Connect to
VSS through a 0.1-μF smoothing capacitor close to each VCC pin.
VCL0 - Connect to VSS through a 0.1-μF smoothing capacitor close to each VCL
pin. Stabilize the internal power supply.
VCL -
VSS Input Ground pin. Connect to the system power supply (0 V).
VBATT Input Backup power pin.
Clock XTAL Output Pins for a crystal resonator. An external clock signal can be input through the
EXTAL pin.
EXTAL Input
XCIN Input Input/output pins for the sub-clock oscillator. Connect a crystal resonator
between XCOUT and XCIN.
XCOUT Output
EBCLK Output Outputs the external bus clock for external devices.
SDCLK Output Outputs the SDRAM-dedicated clock.
CLKOUT Output Clock output pin.
Operating mode
control
MD Input Pin for setting the operating mode. The signal level on this pin must not be
changed during operation mode transition on release from the reset state.
System control RES Input Reset signal input pin. The MCU enters the reset state when this signal goes
low.
CAC CACREF Input Measurement reference clock input pin.
Interrupt NMI Input Non-maskable interrupt request pin.
IRQ0 to IRQ15 Input Maskable interrupt request pins.
KINT KR00 to KR07 Input A key interrupt can be generated by inputting a falling edge to the key
interrupt input pins.
On-chip emulator TMS I/O On-chip emulator or boundary scan pins.
TDI Input
TCK Input
TDO Output
TCLK Output This pin outputs the clock for synchronization with the trace data.
TDATA0 to TDATA3 Output Trace data output.
SWDIO I/O Serial wire debug data input/output pin.
SWCLK Input Serial wire clock pin.
SWO Output Serial wire trace output pin.
External bus
interface
RD Output Strobe signal indicating that reading from the external bus interface space is
in progress, active low.
WR Output Strobe signal indicating that writing to the external bus interface space is in
progress, in 1-write strobe mode, active low.
WR0 to WR1 Output Strobe signals indicating that either group of data bus pins (D07 to D00 or
D15 to D08) is valid in writing to the external bus interface space, in byte
strobe mode, active low.
BC0 to BC1 Output Strobe signals indicating that either group of data bus pins (D07 to D00 or
D15 to D08) is valid in access to the external bus interface space, in 1-write
strobe mode, active low.
ALE Output Address latch signal when address/data multiplexed bus is selected.
WAIT Input Input pin for wait request signals in access to the external space, active low.
CS0 to CS7 Output Select signals for CS areas, active low.
A00 to A23 Output Address bus.
D00 to D15 I/O Data bus.
A00/D00 to A15/D15 I/O Address/data multiplexed bus.
R01DS0303EU0100 Rev.1.00 Page 16 of 115
Nov 3, 2016
S5D9 1. Overview
SDRAM interface CKE Output SDRAM clock enable signal.
SDCS Output SDRAM chip select signal, active low.
RAS Output SDRAM low address strobe signal, active low.
CAS Output SDRAM column address strobe signal, active low.
WE Output SDRAM write enable signal, active low.
DQM0 Output SDRAM I/O data mask enable signal for DQ07 to DQ00.
DQM1 Output SDRAM I/O data mask enable signal for DQ15 to DQ08.
A00 to A15 Output Address bus.
DQ00 to DQ15 I/O Data bus.
GPT GTETRGA,
GTETRGB,
GTETRGC,
GTETRGD
Input External trigger input pins.
GTIOC0A to
GTIOC13A,
GTIOC0B to
GTIOC13B
I/O Input capture, output compare, or PWM output pins.
GTIU Input Hall sensor input pin U.
GTIV Input Hall sensor input pin V.
GTIW Input Hall sensor input pin W.
GTOUUP Output Three-phase PWM output for BLDC motor control (positive U phase).
GTOULO Output Three-phase PWM output for BLDC motor control (negative U phase).
GTOVUP Output Three-phase PWM output for BLDC motor control (positive V phase).
GTOVLO Output Three-phase PWM output for BLDC motor control (negative V phase).
GTOWUP Output Three-phase PWM output for BLDC motor control (positive W phase).
GTOWLO Output Three-phase PWM output for BLDC motor control (negative W phase).
AGT AGTEE0, AGTEE1 Input External event input enable signals.
AGTIO0, AGTIO1 I/O External event input and pulse output pins.
AGTO0, AGTO1 Output Pulse output pins.
AGTOA0, AGTOA1 Output Output compare match A output pins.
AGTOB0, AGTOB1 Output Output compare match B output pins.
RTC RTCOUT Output Output pin for 1-Hz or 64-Hz clock.
RTCIC0 to RTCIC2 Input Time capture event input pins.
SCI SCK0 to SCK9 I/O Input/output pins for the clock (clock synchronous mode).
RXD0 to RXD9 Input Input pins for received data (asynchronous mode/clock synchronous mode).
TXD0 to TXD9 Output Output pins for transmitted data (asynchronous mode/clock synchronous
mode).
CTS0_RTS0 to
CTS9_RTS9
I/O Input/output pins for controlling the start of transmission and reception
(asynchronous mode/clock synchronous mode), active low.
SCL0 to SCL9 I/O Input/output pins for the I2C clock (simple IIC mode).
SDA0 to SDA9 I/O Input/output pins for the I2C data (simple IIC mode).
SCK0 to SCK9 I/O Input/output pins for the clock (simple SPI mode).
MISO0 to MISO9 I/O Input/output pins for slave transmission of data (simple SPI mode).
MOSI0 to MOSI9 I/O Input/output pins for master transmission of data (simple SPI mode).
SS0 to SS9 Input Chip-select input pins (simple SPI mode), active low.
IIC SCL0 to SCL2 I/O Input/output pins for the clock.
SDA0 to SDA2 I/O Input/output pins for data.
SSIE SSIBCK0 I/O SSIE serial bit clock pins.
SSIBCK1
SSILRCK0/SSIFS0 I/O LR clock/frame synchronization pins.
SSILRCK1/SSIFS1
SSITXD0 Output Serial data output pins.
SSIRXD0 Input Serial data input pins.
SSIDATA1 I/O Serial data input/output pins.
AUDIO_CLK Input External clock pin for audio (input oversampling clock).
Table 1.16 Pin functions (2 of 5)
Function Signal I/O Description
R01DS0303EU0100 Rev.1.00 Page 17 of 115
Nov 3, 2016
S5D9 1. Overview
SPI RSPCKA, RSPCKB I/O Clock input/output pin.
MOSIA, MOSIB I/O Input or output pins for data output from the master.
MISOA, MISOB I/O Input or output pins for data output from the slave.
SSLA0, SSLB0 I/O Input or output pin for slave selection.
SSLA1 to SSLA3,
SSLB1 to SSLB3
Output Output pins for slave selection.
QSPI QSPCLK Output QSPI clock output pin.
QSSL Output QSPI slave output pin.
QIO0 to QIO3 I/O Data0 to Data3.
CAN CRX0, CRX1 Input Receive data.
CTX0, CTX1 Output Transmit data.
USBFS VCC_USB Input Power supply pins.
VSS_USB Input Ground pins.
USB_DP I/O D+ I/O pin of the USB on-chip transceiver. Connect this pin to the D+ pin of
the USB bus.
USB_DM I/O D- I/O pin of the USB on-chip transceiver. Connect this pin to the D- pin of
the USB bus.
USB_VBUS Input USB cable connection monitor pin. Connect this pin to VBUS of the USB
bus. The VBUS pin status (connected or disconnected) can be detected
when the USB module is operating as a function controller.
USB_EXICEN Output Low-power control signal for external power supply (OTG) chip.
USB_VBUSEN Output VBUS (5 V) supply enable signal for external power supply chip.
USB_OVRCURA,
USB_OVRCURB
Input Connect the external overcurrent detection signals to these pins. Connect
the VBUS comparator signals to these pins when the OTG power supply
chip is connected.
USB_ID Input Connect the MicroAB connector ID input signal to this pin during operation in
OTG mode.
USBHS VCC_USBHS Input Power supply pin.
VSS1_USBHS Input Ground pin.
VSS2_USBHS Input Ground pin.
AVCC_USBHS Input Analog power supply pin for the USBHS.
AVSS_USBHS Input Analog ground pin for the USBHS. Must be shorted to the PVSS_USBHS
pin.
PVSS_USBHS Input PLL circuit ground pin for the USBHS. Must be shorted to the AVSS_USBHS
pin.
USBHS_RREF I/O USBHS reference current source pin. Connect this pin to the AVSS_USBHS
pin through a 2.2-kΩ resistor (1%).
USBHS_DP I/O USB bus D+ data pin.
USBHS_DM I/O USB bus D- data pin.
USBHS_EXICEN Output Connect this pin to the OTG power supply IC.
USBHS_ID Input Connect this pin to the OTG power supply IC.
USBHS_VBUSEN Output VBUS power enable signal for USB.
USBHS_OVRCURA,
USBHS_OVRCURB
Input Overcurrent pin for USB.
USBHS_VBUS Input USB cable connection monitor input pin.
Table 1.16 Pin functions (3 of 5)
Function Signal I/O Description
R01DS0303EU0100 Rev.1.00 Page 18 of 115
Nov 3, 2016
S5D9 1. Overview
ETHERC REF50CK0 Input 50-MHz reference clock. This pin inputs reference signal for
transmission/reception timing in RMII mode.
RMII0_CRS_DV Input Indicates carrier detection signals and valid receive data on RMII0_RXD1
and RMII0_RXD0 in RMII mode.
RMII0_TXD0,
RMII0_TXD1
Output 2-bit transmit data in RMII mode.
RMII0_RXD0,
RMII0_RXD1
Input 2-bit receive data in RMII mode.
RMII0_TXD_EN Output Output pin for data transmit enable signal in RMII mode.
RMII0_RX_ER Input Indicates an error occurred during reception of data in RMII mode.
ET0_CRS Input Carrier detection/data reception enable signal.
ET0_RX_DV Input Indicates valid receive data on ET0_ERXD3 to ET0_ERXD0.
ET0_EXOUT Output General-purpose external output pin.
ET0_LINKSTA Input Input link status from the PHY-LSI.
ET0_ETXD0 to
ET0_ETXD3
Output 4 bits of MII transmit data.
ET0_ERXD0 to
ET0_ERXD3
Input 4 bits of MII receive data.
ET0_TX_EN Output Transmit enable signal. Functions as signal indicating that transmit data is
ready on ET_ETXD3 to ET_ETXD0.
ET0_TX_ER Output Transmit error pin. Functions as signal notifying the PHY_LSI of an error
during transmission.
ET0_RX_ER Input Receive error pin. Functions as signal to recognize an error during
reception.
ET0_TX_CLK Input Transmit clock pin. This pin inputs reference signal for output timing from
ET0_TX_EN, ET0_ETXD3 to ET0_ETXD0, and ET0_TX_ER.
ET0_RX_CLK Input Receive clock pin. This pin inputs reference signal for input timing to
ET0_RX_DV, ET0_ERXD3 to ET0_ERXD0, and ET0_RX_ER.
ET0_COL Input Input collision detection signal.
ET0_WOL Output Receive Magic packets.
ET0_MDC Output Output reference clock signal for information transfer through ET0_MDIO.
ET0_MDIO I/O Input or output bidirectional signal for exchange of management data with
PHY-LSI.
SDHI SD0CLK, SD1CLK Output SD clock output pins.
SD0CMD, SD1CMD I/O Command output pin and response input signal pins.
SD0DAT0 to
SD0DAT7,
SD1DAT0 to
SD1DAT7
I/O SD and MMC data bus pins.
SD0CD, SD1CD Input SD card detection pins.
SD0WP, SD1WP Input SD write-protect signals.
Analog power
supply
AVCC0 Input Analog voltage supply pin. This is used as the analog power supply for the
respective modules. Supply this pin with the same voltage as the VCC pin.
AVSS0 Input Analog ground pin. This is used as the analog ground for the respective
modules. Supply this pin with the same voltage as the VSS pin.
VREFH0 Input Analog reference voltage supply pin for the ADC12 (unit 0). Connect this pin
to VCC when not using the ADC12 (unit 0) and sample-and-hold circuit for
AN000 to AN002.
VREFL0 Input Analog reference ground pin for the ADC12. Connect this pin to VSS when
not using the ADC12 (unit 0) and sample-and-hold circuit for AN000 to
AN002.
VREFH Input Analog reference voltage supply pin for the ADC12 (unit 1) and D/A
Converter. Connect this pin to VCC when not using the ADC12 (unit 1),
sample-and-hold circuit for AN100 to AN102, and D/A Converter.
VREFL Input Analog reference ground pin for the ADC12 and D/A Converter. Connect this
pin to VSS when not using the ADC12 (unit 1), sample-and-hold circuit for
AN100 to AN102, and D/A Converter.
Table 1.16 Pin functions (4 of 5)
Function Signal I/O Description
R01DS0303EU0100 Rev.1.00 Page 19 of 115
Nov 3, 2016
S5D9 1. Overview
ADC12 AN000 to AN007,
AN016 to AN020
Input Input pins for the analog signals to be processed by the ADC12.
AN100 to AN103,
AN105 to AN107,
AN116 to AN119
Input
ADTRG0 Input Input pins for the external trigger signals that start the A/D conversion.
ADTRG1 Input
PGAVSS000/PGAVS
S100
Input Differential input pins.
DAC12 DA0, DA1 Output Output pins for the analog signals processed by the D/A converter.
ACMPHS VCOUT Output Comparator output pin.
IVREF0 to IVREF3 Input Reference voltage input pins for comparator.
IVCMP0 to IVCMP2 Input Analog voltage input pins for comparator.
CTSU TS00 to TS17 Input Capacitive touch detection pins (touch pins).
TSCAP - Secondary power supply pin for the touch driver.
I/O ports P000 to P007 Input General-purpose input pins.
P008 to P010,
P014, P015
I/O General-purpose input/output pins.
P100 to P115 I/O General-purpose input/output pins.
P200 Input General-purpose input pin.
P201 to P214 I/O General-purpose input/output pins.
P300 to P315 I/O General-purpose input/output pins.
P400 to P415 I/O General-purpose input/output pins.
P500 to P508,
P511 to P513
I/O General-purpose input/output pins.
P600 to P615 I/O General-purpose input/output pins.
P700 to P713 I/O General-purpose input/output pins.
P800 to P806 I/O General-purpose input/output pins.
P900, P901,
P905 to P908
I/O General-purpose input/output pins.
PA00, PA01,
PA08 to PA10
I/O General-purpose input/output pins.
PB00, PB01 I/O General-purpose input/output pins.
GLCDC LCD_DATA23 to
LCD_DATA00
Output Data output pins for panel.
LCD_TCON3 to
LCD_TCON0
Output Output pins for panel timing adjustment.
LCD_CLK Output Panel clock output pin.
LCD_EXTCLK Input Panel clock source input pin.
PDC PIXCLK Input Image transfer clock pin.
VSYNC Input Vertical synchronization signal pin.
HSYNC Input Horizontal synchronization signal pin.
PIXD0 to PIXD7 Input 8-bit image data pins.
PCKO Output Output pin for dot clock.
Table 1.16 Pin functions (5 of 5)
Function Signal I/O Description
R01DS0303EU0100 Rev.1.00 Page 20 of 115
Nov 3, 2016
S5D9 1. Overview
1.6 Pin Assignments
Figure 1.3 to Figure 1.7 show the pin assignments.
Figure 1.3 Pin assignment for 176-pin BGA (top view)
P201/MD
N P RK L MG H JD E FA B C
N P RK L MG H JD E FA B C
P401
P512
P805
P000
P002
P005
VREFH0
VREFH
P014
P508
P506
P502
P500
P803
P801
P405
P402
P511
P806
P004
P008
VREFL0
VREFL
P015
P505
P504
P501
P804
P802
P100
P700
P406
P400
P513
P001
P006
AVSS0
AVCC0
VSS
P507
P503
VCC
P800
P101
P103
P703
P701
P404
P403
VCC
VSS
P009
P010
VCC
P007
P003
VSS
P102
P104
P106
P707
P706
P704
P702
VSS
P105
P107
P600
VCL0
VBATT
PB01
P705
VCC
P603
P601
P602
XCIN
XCOUT
VSS
PB00
P607
P604
P605
P606
P212
/EXTAL
P213
/XTAL
AVCC_
USBHS
VCC
PA00
VSS
PA01
VCL
PVSS_
USBHS
AVSS_
USBHS
USBHS_
RREF
VSS2_
USBHS
PA09
VCC
PA10
PA08
USBHS_
DM
USBHS_
DP
VCC_
USBHS
VSS1_
USBHS
P613
P610
P614
P615
P708
P415
P413
P205
VSS
VCC
P611
P612
P414
P412
P408
P206
P203
VSS
VCC
P908
P907
P311
VCC
P111
P110/TDI
P608
P609
P411
P410
VSS_
USB
P207
P314
P901
RES
P200
P312
P307
VSS
P300/TCK
/SWCLK
P108/TMS
SWDIO
P114
P115
P409
USB_DM
VCC_
USB
P202
P315
P211
P209
P905
P309
P305
P304
P302
P112
P113
P407
USB_DP
P204
P313
P900
P214
P210
P208
P906
P310
P308
P306
P303
P301
P109/TDO
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
R7FS5D9XX2XXXCBG
R01DS0303EU0100 Rev.1.00 Page 21 of 115
Nov 3, 2016
S5D9 1. Overview
Figure 1.4 Pin assignment for 176-pin LQFP (top view)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
P802
P803
P804
VCC
VSS
P500
P501
P502
P503
P504
P505
P506
P508
VCC
VSS
P015
P014
VREFL
VREFH
AVCC0
AVSS0
VREFL0
VREFH0
P010
P008
P006
P004
P002
P000
VCC
P805
P511
P801
P507
P512
VSS_USB
P100
P102
P103
P104
P105
P106
P107
VSS
VCC
P600
P601
P602
P603
P605
P606
P607
PA00
PA01
VCL
VSS
VCC
PA10
PA09
PA08
P615
P613
P612
P609
P608
VCC
P114
P112
P108/TMS/SWDIO
P101
P604
P109/TDO
P400
P402
P403
P404
P405
P406
P700
P701
P702
P703
P704
P705
P706
PB00
PB01
VBATT
VCL0
XCIN
XCOUT
VSS
P213/XTAL
VCC
USBHS_RREF
USBHS_DM
VSS1_USBHS
P708
P414
P412
P410
P409
P407
P212/EXTAL
P401
P707
PVSS_USBHS
P800
AVCC_USBHS
AVSS_USBHS
VSS2_USBHS
USBHS_DP
VCC_USBHS
P415
P413
P411
P408
USB_DM
USB_DP
VCC_USB
P207
P206
P205
P204
P203
P202
P313
P314
P315
P900
P901
VSS
VCC
P214
P210
P209
P312
P310
P309
P308
P307
P306
P305
P304
VSS
VCC
P211
P208
RES
P201/MD
P200
P908
P907
P906
P905
P311
P303
P302
P301
P300/TCK/SWCLK
P614
P611
P610
VSS
P115
P113
P110/TDI
P111
P009
P007
P005
P003
P001
VSS
P513
P806
R7FS5D9XX3XXXCFC
R01DS0303EU0100 Rev.1.00 Page 22 of 115
Nov 3, 2016
S5D9 1. Overview
Figure 1.5 Pin assignment for 145-pin LGA (top view)
P400
VCC
VSS
P001
P008
VREFH0
VREFH
P014
VCC
P508
VCC
P801
P100
P402
P511
P512
P002
P009
VREFL0
VREFL
P015
VSS
P501
VSS
P101
P102
P405
P404
P401
P000
P006
AVSS0
AVCC0
P506
P504
P502
P104
P800
P103
P702
P701
P403
P003
P004
P005
P007
P505
P503
P500
P106
VCC
VSS
VCL0
VBATT
P703
P406
P105
P107
P601
P602
XCIN
XCOUT
P704
P700
P600
P603
P605
VCL
P212
/EXTAL
P213
/XTAL
P705
P713
P604
P614
VSS
VCC
VCC
VSS
P712
P709
P608
P610
P612
P613
P711
P710
P415
P413
P114
P115
P609
P611
P708
P414
P411
P408
VSS
VCC
P310
P305
P303
P109/TDO
P112
VCC
VSS
P412
P410
P207
P204
P202
P200
RES
P312
P308
P304
P301
P111
P113
P409
USB_DP
VSS_
USB
P206
P313
P211
P209
P201/MD
P311
P306
VCC
P300/TCK
/SWCLK
P110/TDI
P407
USB_DM
VCC_
USB
P205
P203
P214
P210
P208
P309
P307
VSS
P302
P108/TMS
/SWDIO
R7FS5D9XX2XXXCLK
13
12
11
10
9
8
7
6
5
4
3
2
1
13
12
11
10
9
8
7
6
5
4
3
2
1
N K L MG H JD E FA B C
N K L MG H JD E FA B C
NC
R01DS0303EU0100 Rev.1.00 Page 23 of 115
Nov 3, 2016
S5D9 1. Overview
Figure 1.6 Pin assignment for 144-pin LQFP (top view)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
VCC
VSS
P500
P501
P502
P503
P504
P505
P506
P508
VCC
VSS
P014
VREFL
VREFH
AVCC0
AVSS0
VREFL0
VREFH0
P009
P008
P007
P006
P005
P004
P003
P002
P001
P000
VSS
VCC
P511
P801
P015
P512
P300/TCK/SWCLK
P302
P303
VCC
VSS
P304
P305
P306
P307
P308
P309
P310
P311
P200
P201/MD
RES
P208
P209
P210
P211
P214
VCC
VSS
P313
P202
P203
P204
P205
P206
P207
VCC_USB
USB_DP
VSS_USB
P301
P312
USB_DM
P100
P102
P103
P104
P105
P106
P107
VSS
VCC
P600
P601
P602
P603
P605
VCL
VSS
VCC
P614
P613
P612
P611
P610
P609
P608
VSS
VCC
P115
P114
P113
P112
P111
P110/TDI
P108/TMS/SWDIO
P101
P604
P109/TDO
P400
P402
P403
P404
P405
P406
P700
P701
P702
P703
P704
P705
VBATT
XCIN
XCOUT
VSS
P213/XTAL
P212/EXTAL
VCC
P713
P712
P711
P710
P708
P415
P414
P413
P412
P411
P410
P409
P407
P401
VCL0
P408
P709
P800
R7F5D9XX3XXXCFB
R01DS0303EU0100 Rev.1.00 Page 24 of 115
Nov 3, 2016
S5D9 1. Overview
Figure 1.7 Pin assignment for 100-pin LQFP (top view)
R7FS5D9XX3XXXCFP
R01DS0303EU0100 Rev.1.00 Page 25 of 115
Nov 3, 2016
S5D9 1. Overview
1.7 Pin Lists
Pin number
Power, System,
Clock, Debug,
CAC
Interrupt
I/O port
Extbus Timers Communication interfaces Analog HMI
BGA176
LQFP176
LGA145
LQFP144
LQFP100
External bus
SDRAM
AGT
GPT
GPT
RTC
USBFS,
CAN
SCI0,2,4,6,8
(30 MHz)
SCI1,3,5,7,9
(30 MHz)
IIC
SPI, QSPI
SSIE
ETHERC (MII)
(25 MHz)
ETHERC (RMII)
(50 MHz)
USBHS
SDHI
ADC12
DAC12,
ACMPHS
CTSU
GLCDC, PDC
N13 1 N13 1 1 - IRQ0 P400 - - AGTIO1 - GTIOC
6A
- - SCK4 SCK7 SCL0
_A
-AUDIO
_CLK
ET0_W
OL
ET0_
WOL
--ADTRG
1
---
R152L1122- IRQ5-
DS
P401 - - - GTETRGA GTIOC
6B
- CTX0 CTS4_
RTS4/
SS4
TXD7/
MOSI7
/SDA7
SDA0
_A
--ET0_M
DC
ET0_M
DC
--- - - -
P14 3 M13 3 3 CACREF IRQ4-
DS
P402 - - AGTIO0/
AGTIO1
--RTC
IC0
CRX0 - RXD7/
MISO7
/SCL7
-- AUDIO
_CLK
ET0_M
DIO
ET0_M
DIO
--- - - VSYNC
M124K1144- - P403- - AGTIO0/
AGTIO1
-GTIOC
3A
RTC
IC1
-- CTS7_
RTS7/
SS7
-- SSIBC
K0_A
ET0_LI
NKSTA
ET0_LI
NKST
A
-SD1
DAT7
_B
---PIXD7
M13 5 L12 5 5 - - P404 - - - - GTIOC
3B
RTC
IC2
-- - -- SSILR
CK0/S
SIFS0_
A
ET0_EX
OUT
ET0_E
XOUT
-SD1
DAT6
_B
---PIXD6
P15 6 L13 6 6 - - P405 - - - - GTIOC
1A
-- - - - - SSITX
D0_A
ET0_TX
_EN
RMII0_
TXD_E
N_B
-SD1
DAT5
_B
---PIXD5
N147J1077- - P406- - - - GTIOC
1B
- - - - - SSLB3
_C
SSIRX
D0_A
ET0_RX
_ER
RMII0_
TXD1_
B
-SD1
DAT4
_B
---PIXD4
N15 8 H10 8 - - - P700 - - - - GTIOC
5A
-- - - - MISOB
_C
-ET0_ET
XD1
RMII0_
TXD0_
B
-SD1
DAT3
_B
---PIXD3
M14 9 K12 9 - - - P701 - - - - GTIOC
5B
-- - - - MOSIB
_C
-ET0_ET
XD0
REF50
CK0_B
-SD1
DAT2
_B
---PIXD2
L12 10 K13 10 - - - P702 - - - - GTIOC
6A
-- - - - RSPC
KB_C
-ET0_ER
XD1
RMII0_
RXD0_
B
-SD1
DAT1
_B
---PIXD1
M15 11 J11 11 - - - P70 3 - - - - G TIOC
6B
- - - - - SSLB0
_C
-ET0_ER
XD0
RMII0_
RXD1_
B
-SD1
DAT0
_B
- VCOUT - PIXD0
L13 12 H11 12 - - - P704 - - AGTO0 - - - CTX0 - - - SSLB1
_C
-ET0_RX
_CLK
RMII0_
RX_E
R_B
-SD1
CLK_
B
---HSYNC
K12 13 G11 13 - - - P705 - - AGTIO0 - - - CRX0 - - - SSLB2
_C
-ET0_C
RS
RMII0_
CRS_
DV_B
-SD1
CMD
_B
---PIXCLK
L14 14 - - - - IRQ7 P706 - - - - - - - - RXD3/
MISO3
/SCL3
-- - - - USB
HS_
OVR
CUR
B
SD1
CD_
B
----
L1515- --- IRQ8P707- - - - - - - - TXD3/
MOSI3
/SDA3
-- - - - USB
HS_
OVR
CUR
A
SD1
WP_
B
----
J12 16 - - - - - PB00 - - - - - - - - SCK3 - - - - - USB
HS_
VBU
SEN
-- - - -
K13 17 - - - - - PB01 - - - - - - - - CTS3_
RTS3/
SS3
-- - - - USB
HS_
VBU
S
-- - - -
K14 18 J12 14 8 VBATT - - - - - - - - - - - - - - - - - - - - - -
K15 19 J13 15 9 VCL0 - - - - - - - - - - - - - - - - - - - - - -
J15 20 H13 16 10 XCIN - - - - - - - - - - - - - - - - - - - - - -
J14 21 H12 17 11 XCOUT - - - - - - - - - - - - - - - - - - - - - -
J13 22 F12 18 12 VSS - - - - - - - - - - - - - - - - - - - - - -
H14 23 G12 19 13 XTAL IRQ2 P213 - - - GTETRGC GTIOC
0A
-- - TXD1/
MOSI1
/SDA1
-- - - - --ADTRG
1
---
H15 24 G13 20 14 EXTAL IRQ3 P212 - - AGTEE1 GTETRGD GTIOC
0B
-- - RXD1/
MISO1
/SCL1
-- - - - --- - - -
H12 25 F13 21 15 VCC - - - - - - - - - - - - - - - - - - - - - -
H13 26 - - - AVCC_U
SBHS
----- - - ------- - ---- - - -
G1327- --USBHS_
RREF
----- - - ------- - ---- - - -
G14 28 - - - AVSS_U
SBHS
----- - - ------- - ---- - - -
G1529- --PVSS_U
SBHS
----- - - ------- - ---- - - -
G1230- --VSS2_U
SBHS
----- - - ------- - ---- - - -
F1531- --- - - - - - - - - - - - - - - - - USB
HS_
DM
-- - - -
F1432- --- - - - - - - - - - - - - - - - - USB
HS_
DP
-- - - -
F1233- --VSS1_U
SBHS
----- - - ------- - ---- - - -
F13 34 - - - VCC_US
BHS
----- - - ------- - ---- - - -
E1535- --- - P708- - - - - - - - - - - - - - - - - - - -
R01DS0303EU0100 Rev.1.00 Page 26 of 115
Nov 3, 2016
S5D9 1. Overview
- - G10 22 - - - P713 - - AGTOA0 - GTIOC
2A
-- - - - - - - - - - - - TS17-
- - F11 23 - - - P712 - - AGTOB0 - GTIOC
2B
-- - - - - - - - - - - - TS16-
- - E13 24 - - - P711 - - AGTEE0 - - - - - CTS1_
RTS1/
SS1
-- - ET0_TX
_CLK
---- - TS15-
- - E12 25 - - - P710 - - - - - - - - SCK1 - - - ET0_TX
_ER
---- - TS14-
- - F10 26 - - IRQ10 P709 - - - - - - - - TXD1/
MOSI1
/SDA1
-- - ET0_ET
XD2
---- - TS13-
- - D13 27 16 CACREF IRQ11 P708 - - - - - - - - RXD1/
MISO1
/SCL1
- SSLA3
_B
AUDIO
_CLK
ET0_ET
XD3
---- - TS12PCKO
E14 36 E11 28 17 - IRQ8 P415 - - - - GTIOC
0A
-USB_
VBUS
EN
- - - SSLA2
_B
-ET0_TX
_EN
RMII0_
TXD_E
N_A
-SD0
CD_
A
--TS11PIXD5
D15 37 D12 29 18 - IRQ9 P414 - - - - GTIOC
0B
- - - - - SSLA1
_B
-ET0_RX
_ER
RMII0_
TXD1_
A
-SD0
WP_
A
--TS10PIXD4
E13 38 E10 30 19 - - P413 - - - GTOUUP - - - CTS0_
RTS0/
SS0
--SSLA0
_B
-ET0_ET
XD1
RMII0_
TXD0_
A
-SD0
CLK_
A
--TS09PIXD3
D14 39 C13 31 20 - - P412 - - AGTEE1 GTOULO - - - SCK0 - - RSPC
KA_B
-ET0_ET
XD0
REF50
CK0_A
-SD0
CMD
_A
--TS08PIX02
C15 40 D11 32 21 - IRQ4 P411 - - AGTOA1 GTOVUP GTIOC
9A
-- TXD0/
MOSI0
/SDA0
CTS3_
RTS3/
SS3
-MOSIA
_B
-ET0_ER
XD1
RMII0_
RXD0_
A
-SD0
DAT0
_A
--TS07PIX01
C14 41 C12 33 22 - IRQ5 P410 - - AGTOB1 GTOVLO GTIOC
9B
- - RXD0/
MISO0
/SCL0
SCK3 - MISOA
_B
-ET0_ER
XD0
RMII0_
RXD1_
A
-SD0
DAT1
_A
--TS06PIXD0
B15 42 B13 34 23 - IRQ6 P409 - - - GTOWUP GTIOC
10A
-USB_
EXIC
EN
-TXD3/
MOSI3
/SDA3
-- - ET0_RX
_CLK
RMII0_
RX_E
R_A
USB
HS_
EXIC
EN
-- - TS05HSYNC
D13 43 D10 35 24 - IRQ7 P408 - - - GTOWLO GTIOC
10B
-USB_
ID
-RXD3/
MISO3
/SCL3
SCL0
_B
--ET0_C
RS
RMII0_
CRS_
DV_A
USB
HS_I
D
-- - TS04PIXCLK
A15 44 A13 36 25 - - P407 - - AGTIO0 - - RTC
OUT
USB_
VBUS
CTS4_
RTS4/
SS4
-SDA0
_B
SSLB3
_A
-ET0_EX
OUT
ET0_E
XOUT
--ADTRG
0
-TS03-
C13 45 B11 37 26 VSS_US
B
----- - - ------- - ---- - - -
B14 46 A12 38 27 - - - - - - - - - USB_
DM
----- - ---- - --
A14 47 B12 39 28 - - - - - - - - - USB_
DP
----- - ---- - --
B13 48 A11 40 29 VCC_US
B
----- - - ------- - ---- - - -
C12 49 C11 41 30 - - P207 A17 - - - - - - - - - SSLB2
_A/QS
SL
- - - - - - - TS02 LCD_DATA
23_B
D12 50 B10 42 31 - IRQ0-
DS
P206 WAIT - - GTIU - - USB_
VBUS
EN
RXD4/
MISO4
/SCL4
-SDA1
_A
SSLB1
_A
SSIDA
TA1_A
ET0_LI
NKSTA
ET0_LI
NKST
A
-SD0
DAT2
_A
--TS01-
E12 51 A10 43 32 CLKOUT IRQ1-
DS
P205 A16 - AGTO1 GTIV GTIOC
4A
-USB_
OVR
CUR
A-DS
TXD4/
MOSI4
/SDA4
CTS9_
RTS9/
SS9
SCL1
_A
SSLB0
_A
SSILR
CK1/S
SIFS1_
A
ET0_W
OL
ET0_
WOL
-SD0
DAT3
_A
--TSCA
P
-
A13 52 C10 44 - CACREF - P204 A18 - AGTIO1 GTIW GTIOC
4B
-USB_
OVR
CUR
B-DS
SCK4 SCK9 SCL0
_B
RSPC
KB_A
SSIBC
K1_A
ET0_RX
_DV
--SD0
DAT4
_A
--TS00-
D11 53 A9 45 - - IRQ2-
DS
P203 A19 - - - GTIOC
5A
- CTX0 CTS2_
RTS2/
SS2
TXD9/
MOSI9
/SDA9
-MOSIB
_A
-ET0_C
OL
--SD0
DAT5
_A
--TSCA
P
-
B12 54 C9 46 - - IRQ3-
DS
P202 WR1/
BC1
-- - GTIOC
5B
- CRX0 SCK2 RXD9/
MISO9
/SCL9
-MISOB
_A
ET0_ER
XD2
--SD0
DAT6
_A
- - - LCD_TCO
N3_B
A12 55 B9 47 - - - P313 A20 - - - - - - - - - - - ET0_ER
XD3
--SD0
DAT7
_A
- - - LCD_TCO
N2_B
C11 56 - - - - - P314 A21 - - - - - - - - - - - - - - - ADTRG
0
- - LCD_TCO
N1_B
B11 57 - - - - - P315 A22 - - - - - - RXD4 - - - - - - - - - - - LCD_TCO
N0_B
A11 58 - - - - - P900 A23 - - - - - - TXD4 - - - - - - - - - - - LCD_CLK_
B
C10 59 - - - - - P901 - - AGTIO1 - - - - SCK4 - - - - - - - - - - - LCD_DATA
15_B
D10 60 D9 48 - VSS - - - - - - - - - - - - - - - - - - - - - -
D9 61 D8 49 - VCC - - - - - - - - - - - - - - - - - - - - - -
A10 62 A8 50 33 TRCLK - P214 - - - GTIU - - - - - - QSPC
LK
-ET0_M
DC
ET0_M
DC
-SD0
CLK_
B
- - - LCD_DATA
22_B
B10 63 B8 51 34 TRDATA
0
- P211 - - - GTIV - - - - - - QIO0 - ET0_M
DIO
ET0_M
DIO
-SD0
CMD
_B
- - - LCD_DATA
21_B
A9 64 A7 52 35 TRDATA
1
- P210 - - - GTIW - - - - - - QIO1 - ET0_W
OL
ET0_
WOL
-SD0
CD_
B
- - - LCD_DATA
20_B
B9 65 B7 53 36 TRDATA
2
- P209 - - - GTOVUP - - - - - - QIO2 - ET0_EX
OUT
ET0_E
XOUT
-SD0
WP_
B
- - - LCD_DATA
19_B
Pin number
Power, System,
Clock, Debug,
CAC
Interrupt
I/O port
Extbus Timers Communication interfaces Analog HMI
BGA176
LQFP176
LGA145
LQFP144
LQFP100
External bus
SDRAM
AGT
GPT
GPT
RTC
USBFS,
CAN
SCI0,2,4,6,8
(30 MHz)
SCI1,3,5,7,9
(30 MHz)
IIC
SPI, QSPI
SSIE
ETHERC (MII)
(25 MHz)
ETHERC (RMII)
(50 MHz)
USBHS
SDHI
ADC12
DAC12,
ACMPHS
CTSU
GLCDC, PDC
R01DS0303EU0100 Rev.1.00 Page 27 of 115
Nov 3, 2016
S5D9 1. Overview
A8 66 A6 54 37 TRDATA
3
- P208 - - - GTOVLO - - - - - - QIO3 - ET0_LI
NKSTA
ET0_LI
NKST
A
-SD0
DAT0
_B
- - - LCD_DATA
18_B
C9 67 C7 55 38 RES - - - - - - - - - - - - - - - - - - - - - -
B8 68 B6 56 39 MD - P201 - - - - - - - - - - - - - - - - - - - -
C8 69 C8 57 40 - NMI P200 - - - - - - - - - - - - - - - - - - - -
D8 70 - - - - - P908 CS7 - - - GTIOC
2A
- - - - - - - - - - - - - - LCD_DATA
14_B
D7 71 - - - - - P907 CS6 - - - GTIOC
2B
- - - - - - - - - - - - - - LCD_DATA
13_B
A7 72 - - - - - P906 CS5 - - - GTIOC
3A
- - - - - - - - - - - - - - LCD_DATA
12_B
B7 73 - - - - - P905 CS4 - - - GTIOC
3B
- - - - - - - - - - - - - - LCD_DATA
11_B
C7 74 C6 58 - - - P312 CS3 CAS AGTOA1 - - - - - CTS3_
RTS3/
SS3
-- - - - --- - - -
D6 75 B5 59 - - - P311 CS2 RAS AGTOB1 - - - - - SCK3 - - - - - - - - - - LCD_DATA
23_A
A6 76 D7 60 - - - P310 A15 A15 AGTEE1 - - - - - TXD3 - QIO3 - - - - - - - - LCD_DATA
22_A
B6 77 A5 61 - - - P309 A14 A14 - - - - - - RXD3 - QIO2 - - - - - - - - LCD_DATA
21_A
A5 78 C5 62 - - - P308 A13 A13 - - - - - - - - QIO1 - - - - - - - - LCD_DATA
20_A
C6 79 A4 63 41 - - P307 A12 A12 - GTOUUP - - - CTS6 - - QIO0 - - - - - - - - LCD_DATA
19_A
A4 80 B4 64 42 - - P306 A11 A11 - GTOULO - - - SCK6 - - QSSL - - - - - - - - LCD_DATA
18_A
B5 81 D6 65 43 - IRQ8 P305 A10 A10 - GTOWUP - - - TXD6/
MOSI6
/SDA6
--QSPC
LK
- - - - - - - - LCD_DATA
17_A
B4 82 C4 66 44 - IRQ9 P304 A09 A09 - GTOWLO GTIOC
7A
- - RXD6/
MISO6
/SCL6
- - - - - - - - - - - LCD_DATA
16_A
C5 83 A3 67 45 VSS - - - - - - - - - - - - - - - - - - - - - -
D5 84 B3 68 46 VCC - - - - - - - - - - - - - - - - - - - - - -
A3 85 D5 69 47 - - P303 A08 A08 - - GTIOC
7B
- - - - - - - - - - - - - - LCD_DATA
15_A
B3 86 A2 70 48 - IRQ5 P302 A07 A07 - GTOUUP GTIOC
4A
-- TXD2/
MOSI2
/SDA2
--SSLB3
_B
- - - - - - - - LCD_DATA
14_A
A2 87 C3 71 49 - IRQ6 P301 A06 A06 AGTIO0 GTOULO GTIOC
4B
- - RXD2/
MISO2
/SCL2
CTS9_
RTS9/
SS9
- SSLB2
_B
- - - - - - - - LCD_DATA
13_A
C4 88 B2 72 50 TCK/SW
CLK
- P300 - - - GTOUUP GTIOC
0A_A
- - - - - SSLB1
_B
-- ---- - --
C3 89 A1 73 51 TMS/SW
DIO
- P108 - - - GTOULO GTIOC
0B_A
-- - CTS9_
RTS9/
SS9
- SSLB0
_B
-- ---- - --
A1 90 D4 74 52 CLKOUT
/TDO/S
WO
- P109 - - - GTOVUP GTIOC
1A_A
-CTX1- TXD9/
MOSI9
/SDA9
-MOSIB
_B
-- ---- - --
D3 91 B1 75 53 TDI IRQ3 P110 - - - GTOVLO GTIOC
1B_A
- CRX1 CTS2_
RTS2/
SS2
RXD9/
MISO9
/SCL9
-MISOB
_B
-- ---- VCOUT--
D4 92 C2 76 54 - IRQ4 P111 A05 A05 - - GTIOC
3A_A
- - SCK2 SCK9 - RSPC
KB_B
- - - - - - - - LCD_DATA
12_A
B2 93 D3 77 55 - - P112 A04 A04 - - GTIOC
3B_A
-- TXD2/
MOSI2
/SDA2
SCK1 - SSLB0
_B
SSIBC
K0_B
- - - - - - - LCD_DATA
11_A
B1 94 C1 78 56 - - P113 A03 A03 - - GTIOC
2A
- - RXD2/
MISO2
/SCL2
--- SSILR
CK0/S
SIFS0_
B
- - - - - - - LCD_DATA
10_A
C2 95 E4 79 57 - - P114 A02 A02 - - GTIOC
2B
-- - - - - SSIRX
D0_B
- - - - - - - LCD_DATA
09_A
C1 96 E3 80 58 - - P115 A01 A01 - - GTIOC
4A
-- - - - - SSITX
D0_B
- - - - - - - LCD_DATA
08_A
E3 97 D2 81 - VCC - - - - - - - - - - - - - - - - - - - - - -
E4 98 D1 82 - VSS - - - - - - - - - - - - - - - - - - - - - -
D2 99 F4 83 59 - - P608 A00/
BC0
A00/D
QM1
-- GTIOC
4B
- - - - - - - - - - - - - - LCD_DATA
07_A
D1 100 E2 84 60 - - P609 CS1 CKE - - GTIOC
5A
- CTX1 - - - - - - - - - - - - LCD_DATA
06_A
F3 101 F3 85 61 - - P610 CS0 WE - - GTIOC
5B
- CRX1 - - - - - - - - - - - - LCD_DATA
05_A
E2 102 E1 86 - CLKOUT
/CACRE
F
- P611 - SDCS - - - - - - CTS7_
RTS7/
SS7
-- - - - --- - - -
E1 103 F2 87 - - - P612 D08[
A08/
D08]
DQ08- - ----SCK7---- ---- - --
F4 104 F1 88 - - - P613 D09[
A09/
D09]
DQ09 - - - - - - TXD7 - - - - - - - - - - -
F2 105 G3 89 - - - P614 D10[
A10/
D10]
DQ10 - - - - - - RXD7 - - - - - - - - - - -
F1 106 - - - - - P615 - - - - - - - - - - - - - - - - - - - LCD_DATA
10_B
G1 107 - - - - - PA08 - - - - - - - - - - - - - - - - - - - LCD_DATA
09_B
Pin number
Power, System,
Clock, Debug,
CAC
Interrupt
I/O port
Extbus Timers Communication interfaces Analog HMI
BGA176
LQFP176
LGA145
LQFP144
LQFP100
External bus
SDRAM
AGT
GPT
GPT
RTC
USBFS,
CAN
SCI0,2,4,6,8
(30 MHz)
SCI1,3,5,7,9
(30 MHz)
IIC
SPI, QSPI
SSIE
ETHERC (MII)
(25 MHz)
ETHERC (RMII)
(50 MHz)
USBHS
SDHI
ADC12
DAC12,
ACMPHS
CTSU
GLCDC, PDC
R01DS0303EU0100 Rev.1.00 Page 28 of 115
Nov 3, 2016
S5D9 1. Overview
G4 108 - - - - - PA09 - - - - - - - - - - - - - - - - - - - LCD_DATA
08_B
G2 109 - - - - - PA10 - - - - - - - - - - - - - - - - - - - LCD_DATA
07_B
G3 110 G1 90 62 VCC - - - - - - - - - - - - - - - - - - - - - -
H3 111 G2 9 1 63 VSS - - - - - - - - - - - - - - - - - - - - - -
H1 112 H1 92 64 VCL - - - - - - - - - - - - - - - - - - - - - -
H2 113 - - - - - PA01 - - - - - - - SCK8 - - - - - - - - - - - LCD_DATA
06_B
H4 114 - - - - - PA00 - - - - - - - TXD8 - - - - - - - - - - - LCD_DATA
05_B
J4 115 - - - - - P607 - - - - - - - RXD8 - - - - - - - - - - - LCD_DATA
04_B
J1116- --- - P606- - - - - RTC
OUT
-CTS8_
RTS8/
SS8
- - - - - - - - - - - LCD_DATA
03_B
J2 117 H2 93 - - - P605 D11[
A11/
D11]
DQ11 - - GTIOC
8A
-- - - - - - - - - - - - - -
J3 118 G4 94 - - - P604 D12[
A12/
D12]
DQ12 - - GTIOC
8B
-- - - - - - - - - - - - - -
K3 119 H3 95 - - - P603 D13[
A13/
D13]
DQ13 - - GTIOC
7A
-- - CTS9_
RTS9/
SS9
-- - - - --- - - -
K1 120 J1 96 65 - - P602 EBC
LK
SDCL
K
-- GTIOC
7B
- - - TXD9 - - - - - - - - - - LCD_DATA
04_A
K2 121 J2 97 66 - - P601 WR/
WR0
DQM0 - - GTIOC
6A
- - - RXD9 - - - - - - - - - - LCD_DATA
03_A
L1 122 H4 98 67 CLKOUT
/CACRE
F
-P600RD-- - GTIOC
6B
- - - SCK9 - - - - - - - - - - LCD_DATA
02_A
K4 123 K2 99 - VCC - - - - - - - - - - - - - - - - - - - - - -
L4 124 K1 100 - VSS - - - - - - - - - - - - - - - - - - - - - -
L2 125 J3 101 68 - KR07 P107 D07[
A07/
D07]
DQ07 AGTOA0 - GTIOC
8A
-- CTS8_
RTS8/
SS8
- - - - - - - - - - - LCD_DATA
01_A
M1 126 K3 102 69 - KR06 P106 D06[
A06/
D06]
DQ06 AGTOB0 - GTIOC
8B
- - SCK8 - - SSLA3
_A
- - - - - - - - LCD_DATA
00_A
L3 127 J4 103 70 - IRQ0/
KR05
P105 D05[
A05/
D05]
DQ05 - GTETRGA GTIOC
1A
-- TXD8/
MOSI8
/SDA8
--SSLA2
_A
- - - - - - - - LCD_TCO
N3_A
M2 128 L3 104 71 - IRQ1/
KR04
P104 D04[
A04/
D04]
DQ04 - GTETRGB GTIOC
1B
- - RXD8/
MISO8
/SCL8
--SSLA1
_A
- - - - - - - - LCD_TCO
N2_A
N1 129 L1 105 72 - KR03 P103 D03[
A03/
D03]
DQ03 - GTOWUP GTIOC
2A_A
- CTX0 CTS0_
RTS0/
SS0
--SSLA0
_A
- - - - - - - - LCD_TCO
N1_A
M3 130 M1 106 73 - KR02 P102 D02[
A02/
D02]
DQ02 AGTO0 GTOWLO GTIOC
2B_A
- CRX0 SCK0 - - RSPC
KA_A
-- ---ADTRG
0
- - LCD_TCO
N0_A
N2 131 M2 107 74 - IRQ1/
KR01
P101 D01[
A01/
D01]
DQ01 AGTEE0 GTETRGB GTIOC
5A
-- TXD0/
MOSI0
/SDA0
CTS1_
RTS1/
SS1
SDA1
_B
MOSIA
_A
- - - - - - - - LCD_CLK_
A
P1 132 N1 108 75 - IRQ2/
KR00
P100 D00[
A00/
D00]
DQ00 AGTIO0 GTETRGA GTIOC
5B
- - RXD0/
MISO0
/SCL0
SCK1 SCL1
_B
MISOA
_A
- - - - - - - - LCD_EXT
CLK_A
N3 133 L2 109 - - - P800 D14[
A14/
D14]
DQ14 - - - - - - - - - - - - - - - - - -
R1 134 N2 110 - - - P801 D15[
A15/
D15]
DQ15 - - - - - - - - - - - - - SD1
DAT4
_A
----
P2 135 - - - - - P802 - - - - - - - - - - - - - - - SD1
DAT5
_A
- - - LCD_DATA
02_B
R2 136 - - - - - P803 - - - - - - - - - - - - - - - SD1
DAT6
_A
- - - LCD_DATA
01_B
P3 137 - - - - P804 - - - - - - - - - - - - - - - SD1
DAT7
_A
- - - LCD_DATA
00_B
N4 138 N3 111 - VCC - - - - - - - - - - - - - - - - - - - - - -
M4 139 M3 112 - VSS - - - - - - - - - - - - - - - - - - - - - -
R3 140 K4 113 76 - - P500 - - AGTOA0 GTIU GTIOC
11A
-USB_
VBUS
EN
---QSPC
LK
-- --SD1
CLK_
A
AN016 IVREF0 - -
P4 141 M4 114 77 - IRQ11 P501 - - AGTOB0 GTIV GTIOC
11B
-USB_
OVR
CUR
A
-TXD5/
MOSI5
/SDA5
-QSSL- - - -SD1
CMD
_A
AN116 IVREF1 - -
R4 142 L4 115 78 - IRQ12 P502 - - - GTIW GTIOC
12A
-USB_
OVR
CUR
B
-RXD5/
MISO5
/SCL5
-QIO0- - - -SD1
DAT0
_A
AN017 IVCMP0 - -
N5 143 K5 116 79 - - P503 - - - GTETRGC GTIOC
12B
-USB_
EXIC
EN
CTS6_
RTS6/
SS6
SCK5 - QIO1 - - - - SD1
DAT1
_A
AN117 - - -
P5 144 L5 117 80 - - P504 ALE - - GTETRGD GTIOC
13A
-USB_
ID
SCK6 CTS5_
RTS5/
SS5
-QIO2- - - -SD1
DAT2
_A
AN018 - - -
P6 145 K6 118 - - IRQ14 P505 - - - - GTIOC
13B
- - RXD6/
MISO6
/SCL6
- - QIO3 - - - - SD1
DAT3
_A
AN118 - - -
Pin number
Power, System,
Clock, Debug,
CAC
Interrupt
I/O port
Extbus Timers Communication interfaces Analog HMI
BGA176
LQFP176
LGA145
LQFP144
LQFP100
External bus
SDRAM
AGT
GPT
GPT
RTC
USBFS,
CAN
SCI0,2,4,6,8
(30 MHz)
SCI1,3,5,7,9
(30 MHz)
IIC
SPI, QSPI
SSIE
ETHERC (MII)
(25 MHz)
ETHERC (RMII)
(50 MHz)
USBHS
SDHI
ADC12
DAC12,
ACMPHS
CTSU
GLCDC, PDC
R01DS0303EU0100 Rev.1.00 Page 29 of 115
Nov 3, 2016
S5D9 1. Overview
Note: Some pin names have the added suffix of _A, _B, and _C. When assigning the GPT, IIC, SPI, SSIE, ETHERC (RMII), SDHI,
and GLCDC functionality, select the functional pins with the same suffix.
R5 146 L6 119 - - IRQ15 P506 - - - - - - - TXD6/
MOSI6
/SDA6
--- - - - -SD1
CD_
A
AN019 - - -
N6 147 - - - - - P507 - - - - - - - - CTS5_
RTS5/
SS5
-- - - - -SD1
WP_
A
AN119 - - -
R6 148 N4 120 81 - - P508 - - - - - - - SCK6 SCK5 - - - - - - - AN020 - - -
M7 149 N5 121 82 VCC - - - - - - - - - - - - - - - - - - - - - -
N7 150 M5 122 83 VSS - - - - - - - - - - - - - - - - - - - - - -
P7 151 M6 123 84 - IRQ13 P015 - - - - - - - - - - - - - - - - AN006/
AN106
DA1/
IVCMP1
--
R7 152 N6 124 85 - - P014 - - - - - - - - - - - - - - - - AN005/
AN105
DA0/
IVREF3
--
P8 153 M7 125 86 VREFL - - - - - - - - - - - - - - - - - - - - - -
R8 154 N7 126 87 VREFH - - - - - - - - - - - - - - - - - - - - - -
N8 155 L7 127 88 AVCC0 - - - - - - - - - - - - - - - - - - - - - -
N9 156 L8 128 89 AVSS0 - - - - - - - - - - - - - - - - - - - - - -
P9 157 M8 129 90 VREFL0 - - - - - - - - - - - - - - - - - - - - - -
R9 158 N8 130 91 VREFH0 - - - - - - - - - - - - - - - - - - - - - -
M8 159 - - - - IRQ14
-DS
P010 - - - - - - - - - - - - - - - - AN103 - - -
M9 160 M9 131 - - IRQ13
-DS
P009 - - - - - - - - - - - - - - - - AN004 - - -
P10 161 N9 132 92 - IRQ12
-DS
P008 - - - - - - - - - - - - - - - - AN003 - - -
M6 162 K7 133 93 - - P007 - - - - - - - - - - - - - - - - PGAVS
S100/A
N107
---
N10 163 L9 134 94 - IRQ11-
DS
P006 - - - - - - - - - - - - - - - - AN102 IVCMP2 - -
R10 164 K8 135 95 - IRQ10
-DS
P005 - - - - - - - - - - - - - - - - AN101 IVCMP2 - -
P11 165 K9 136 96 - IRQ9-
DS
P004 - - - - - - - - - - - - - - - - AN100 IVCMP2 - -
M5 166 K10 137 97 - - P003 - - - - - - - - - - - - - - - - PGAVS
S000/A
N007
---
R11 167 M10 138 98 - IRQ8-
DS
P002 - - - - - - - - - - - - - - - - AN002 IVCMP2 - -
N11 168 N10 139 99 - IRQ7-
DS
P001 - - - - - - - - - - - - - - - - AN001 IVCMP2 - -
R12 169 L10 140 100 - IRQ6-
DS
P000 - - - - - - - - - - - - - - - - AN000 IVCMP2 - -
M10 170 N11 141 - VSS - - - - - - - - - - - - - - - - - - - - - -
M11 171 N12 142 - VCC - - - - - - - - - - - - - - - - - - - - - -
P12 172 - - - - - P806 - - - - - - - - - - - - - - - - - - - LCD_EXT
CLK_B
R13 173 - - - - - P805 - - - - - - - - TXD5 - - - - - - - - - - LCD_DATA
17_B
N12 174 - - - - - P513 - - - - - - - - RXD5 - - - - - - - - - - LCD_DATA
16_B
R14 175 M11 143 - - IRQ14 P512 - - - - GTIOC
0A
-CTX1TXD4/
MOSI4
/SDA4
- SCL2 - - - - - - - - - VSYNC
P13 176 M12 144 - - IRQ15 P511 - - - - GTIOC
0B
- CRX1 RXD4/
MISO4
/SCL4
-SDA2- - - - --- - - PCKO
Pin number
Power, System,
Clock, Debug,
CAC
Interrupt
I/O port
Extbus Timers Communication interfaces Analog HMI
BGA176
LQFP176
LGA145
LQFP144
LQFP100
External bus
SDRAM
AGT
GPT
GPT
RTC
USBFS,
CAN
SCI0,2,4,6,8
(30 MHz)
SCI1,3,5,7,9
(30 MHz)
IIC
SPI, QSPI
SSIE
ETHERC (MII)
(25 MHz)
ETHERC (RMII)
(50 MHz)
USBHS
SDHI
ADC12
DAC12,
ACMPHS
CTSU
GLCDC, PDC
R01DS0303EU0100 Rev.1.00 Page 30 of 115
Nov 3, 2016
S5D9 2. Electrical Characteristics
2. Electrical Characteristics
Unless otherwise specified, the electrical characteristics of the MCU are defined under the following conditions:
VCC = AVCC0 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 ≤ VREFH0/VREFH ≤ AVCC0, VCC_USBHS =
AVCC_USBHS = 3.0 to 3.6 V, VSS = AVSS0 = VREFL0/VREFL = VSS_USB = VSS1_USBHS = VSS2_USBHS =
PVSS_USBHS = AVSS_USBHS = 0 V, Ta = Topr
Figure 2.1 shows the timing conditions.
Figure 2.1 Input or output timing measurement conditions
The measurement conditions of timing specification in each peripherals are recommended for the best peripheral
operation, however make sure to adjust driving abilities of each pins to meet your conditions.
2.1 Absolute Maximum Ratings
Caution: Permanent damage to the MCU might result if absolute maximum ratings are exceeded.
Note 1. Ports P205, P206, P400, P401, P407 to P415, P511, P512, P708 to P713, and PB01 are 5V-tolerant.
Note 2. Connect AVCC0 and VCC_USB to VCC.
Note 3. See section 2.2.1, Tj/Ta Definition.
Note 4. Contact a Renesas Electronics sales office for information on derating operation when Ta = +85°C to +105°C. Derating is the
systematic reduction of load for improved reliability.
Note 5. The upper limit of operating temperature is 85°C or 105°C, depending on the product. For details, see section 1.3, Part
Numbering.
Table 2.1 Absolute maximum ratings
Item Symbol Value Unit
Power supply voltage VCC, VCC_USB *2–0.3 to +4.0 V
VBATT power supply voltage VBATT –0.3 to +4.0 V
Input voltage (except for 5V-tolerant ports*1)V
in –0.3 to VCC + 0.3 V
Input voltage (5V-tolerant ports*1)V
in –0.3 to + VCC + 4.0 (max 5.8) V
Reference power supply voltage VREFH/VREFH0 –0.3 to VCC + 0.3 V
Analog power supply voltage AVCC0 *2–0.3 to +4.0 V
USBHS power supply voltage VCC_USBHS –0.3 to +4.0 V
USBHS analog power supply voltage AVCC_USBHS –0.3 to +4.0 V
Analog input voltage VAN –0.3 to AVCC0 + 0.3 V
Operating temperature*3,*4,*5Topr –40 to +85
–40 to +105
°C
Storage temperature Tstg –55 to +125 °C
For example P100
C
VOH = VCC × 0.7, VOL = VCC × 0.3
VIH = VCC × 0.7, VIL = VCC × 0.3
Load capacitance C = 30pF
R01DS0303EU0100 Rev.1.00 Page 31 of 115
Nov 3, 2016
S5D9 2. Electrical Characteristics
Note 1. Connect AVCC0 to VCC. When neither the A/D converter nor the D/A converter nor the comparator is in use, do not leave the
AVCC0, VREFH/VREFH0, AVSS0, and VREFL/VREFL0 pins open. Connect the AVCC0 and VREFH/VREFH0 pins to VCC,
and the AVSS0 and VREFL/VREFL0 pins to VSS, respectively.
2.2 DC Characteristics
2.2.1 Tj/Ta Definition
Note: Make sure that Tj = Ta + θja × total power consumption (W), where total power consumption = (VCC – VOH) × ΣIOH + VOL ×
ΣIOL + ICCmax × VCC.
Note 1. The upper limit of operating temperature is 85°C or 105°C, depending on the product. For details, see section 1.3, Part
Numbering. If the part number shows the operation temperature to 85°C, then Tj max is 105°C, otherwise, 125°C.
Table 2.2 Recommended operating conditions
Item Symbol Value Min Typ Max Unit
Power supply voltages VCC When USB/SDRAM is not used 2.7 - 3.6 V
When USB/SDRAM is used 3.0 - 3.6 V
VSS -0-V
USB power supply voltages VCC_USB,
VCC_USBHS
-VCC-V
VSS_USB,
AVSS_USBHS,
PVSS_USBHS,
VSS1_USBHS,
VSS2_USBHS
-0-V
VBATT power supply voltage VBATT 1.8 - 3.6 V
Analog power supply voltages AVCC0*1-VCC-V
AVSS0 - 0 - V
Table 2.3 DC characteristics
Conditions: Products with operating temperature (Ta) –40 to +105°C
Item Symbol Typ Max Unit Test conditions
Permissible junction temperature Tj- 125 °C High-speed mode
Low-speed mode
Subosc-speed mode
105*1
R01DS0303EU0100 Rev.1.00 Page 32 of 115
Nov 3, 2016
S5D9 2. Electrical Characteristics
2.2.2 I/O VIH, VIL
Note 1. SCL0_B (P204), SCL1_B, SDA1_B (total 3 pins).
Note 2. SCL0_A, SDA0_A, SCL0_B (P408), SDA0_B, SCL1_A, SDA1_A, SCL2, SDA2 (total 8 pins).
Note 3. RES and peripheral function pins associated with P205, P206, P400, P401, P407 to P415, P511, P512, P708 to P713, PB01
(total 23 pins).
Table 2.4 I/O VIH, VIL
Item Symbol Min Typ Max Unit
Input voltage
(except for
Schmitt trigger
input pins)
Peripheral
function
pin
EXTAL(external clock input), WAIT, SPI (except
RSPCK)
VIH VCC × 0.8 - - V
VIL - - VCC × 0.2
D00 to D15,
DQ00 to DQ15
VIH VCC × 0.7 - -
VIL - - VCC × 0.3
ETHERC VIH 2.3 - -
VIL - - VCC × 0.2
IIC (SMBus)*1VIH 2.1 - -
VIL --0.8
IIC (SMBus)*2VIH 2.1 - VCC + 3.6
(max 5.8)
VIL --0.8
Schmitt trigger
input voltage
IIC (except for SMBus)*1VIH VCC × 0.7 - -
VIL - - VCC × 0.3
VTVCC × 0.05 - -
IIC (except for SMBus)*2VIH VCC × 0.7 - VCC + 3.6
(max 5.8)
VIL - - VCC × 0.3
VTVCC × 0.05 - -
5V-tolerant ports*3, *7VIH VCC × 0.8 - VCC + 3.6
(max 5.8)
VIL - - VCC × 0.2
VTVCC × 0.05 - -
RTCIC0,
RTCIC1,
RTCIC2
When using the
Battery Backup
Function
When VBATT
power supply is
selected
VIH VBATT × 0.8 - VBATT + 0.3
VIL --V
BATT × 0.2
VTVBATT × 0.05 - -
When VCC
power supply is
selected
VIH VCC × 0.8 - Higher
voltage either
VCC + 0.3 V
or
VBATT + 0.3 V
VIL - - VCC × 0.2
VTVCC × 0.05 - -
When not using the Battery Backup
Function
VIH VCC × 0.8 - VCC + 0.3
VIL - - VCC × 0.2
VTVCC × 0.05 - -
Other input pins*4VIH VCC × 0.8 - -
VIL - - VCC × 0.2
VTVCC × 0.05 - -
Ports 5V-tolerant ports*5, *7VIH VCC × 0.8 - VCC + 3.6
(max 5.8)
VIL - - VCC × 0.2
Other input pins*6VIH VCC × 0.8 - -
VIL - - VCC × 0.2
R01DS0303EU0100 Rev.1.00 Page 33 of 115
Nov 3, 2016
S5D9 2. Electrical Characteristics
Note 4. All input pins except for the peripheral function pins already described in the table.
Note 5. P205, P206, P400, P401, P407 to P415, P511, P512, P708 to P713, PB01 (total 22 pins).
Note 6. All input pins except for the ports already described in the table.
Note 7. When VCC is less than 2.7 V, the input voltage of 5V-tolerant ports should be less than 3.6 V, otherwise breakdown may occur
because 5V-tolerant ports are electrically controlled so as not to violate the break down voltage.
2.2.3 I/O IOH, IOL
Caution: To protect the reliability of the MCU, the output current values should not exceed the values in this
table. The average output current indicates the average value of current measured during 100 μs.
Note 1. This is the value when low driving ability is selected in the port drive capability bit in the PmnPFS register. The selected driving
ability is retained in Deep Software Standby mode.
Note 2. This is the value when middle driving ability is selected in the port drive capability bit in the PmnPFS register. The selected
driving ability is retained in Deep Software Standby mode.
Note 3. This is the value when high driving ability is selected in the port drive capability bit in the PmnPFS register. The selected driving
ability is retained in Deep Software Standby mode.
Table 2.5 I/O IOH, IOL
Item Symbol Min Typ Max Unit
Permissible output current
(average value per pin)
Ports P008 to P010, P201 - IOH - -- –2.0 mA
IOL --2.0mA
Ports P014, P015 - IOH - - –4.0 mA
IOL --4.0mA
Ports P205, P206, P407 to P415,
P602, P708 to P713, PB01 (total
19 pins)
Low drive*1IOH - - –2.0 mA
IOL --2.0mA
Middle drive*2IOH - - –4.0 mA
IOL --4.0mA
High drive*3IOH - - –20 mA
IOL --20mA
Other output pins*4Low drive*1IOH - - –2.0 mA
IOL --2.0mA
Middle drive*2IOH - - –4.0 mA
IOL --4.0mA
High drive*3IOH - - –16 mA
IOL --16mA
Permissible output current
(max value per pin)
Ports P008 to P010, P201 - IOH - - –4.0 mA
IOL --4.0mA
Ports P014, P015 - IOH - - –8.0 mA
IOL --8.0mA
Ports P205, P206, P407 to P415,
P602, P708 to P713, PB01
(total 19 pins)
Low drive*1IOH - - –4.0 mA
IOL --4.0mA
Middle drive*2IOH - - –8.0 mA
IOL --8.0mA
High drive*3IOH - - –40 mA
IOL --40mA
Other output pins*4Low drive*1IOH - - –4.0 mA
IOL --4.0mA
Middle drive*2IOH - - –8.0 mA
IOL --8.0mA
High drive*3IOH - - –32 mA
IOL --32mA
Permissible output current
(max value total pins)
Maximum of all output pins IOH (max) - - –80 mA
IOL (max) --80mA
R01DS0303EU0100 Rev.1.00 Page 34 of 115
Nov 3, 2016
S5D9 2. Electrical Characteristics
Note 4. Except for P000 to P007, P200, which are input ports.
2.2.4 I/O VOH, VOL, and Other Characteristics
Note 1. SCL0_A, SDA0_A (total 2 pins).
Note 2. This is the value when high driving ability is selected in the port drive capability bit in the PmnPFS register.
The selected driving ability is retained in Deep Software Standby mode.
Table 2.6 I/O VOH, VOL, and other characteristics
Item Symbol Min Typ Max Unit Test conditions
Output voltage IIC VOL --0.4VI
OL = 3.0 mA
VOL --0.6 I
OL = 6.0 mA
IIC*1VOL --0.4 I
OL = 15.0 mA
(ICFER.FMPE = 1)
VOL -0.4- I
OL = 20.0 mA
(ICFER.FMPE = 1)
ETHERC VOH VCC – 0.5 - - IOH = –1.0 mA
VOL --0.4 I
OL = 1.0 mA
Ports P205, P206, P407 to P415,
P602, P708 to P713, PB01 (total 19
pins)*2
VOH VCC – 1.0 - - IOH = –20 mA
VCC = 3.3 V
VOL --1.0 I
OL = 20 mA
VCC = 3.3 V
Other output pins VOH VCC – 0.5 - - IOH = –1.0 mA
VOL --0.5 I
OL = 1.0 mA
Input leakage current RES |Iin|- -5.0AV
in = 0 V
Vin = 5.5 V
Ports P000 to P002, P004 to P006,
P200
--1.0 V
in = 0 V
Vin = VCC
Ports P003, P007 Before
initialization
--45.0 V
in = 0 V
Vin = VCC
After
initialization
--1.0 V
in = 0 V
Vin = VCC
Three-state leakage
current (off state)
5V-tolerant ports |ITSI|- -5.0AV
in = 0 V
Vin = 5.5 V
Other ports (except for ports P000
to P007, P200)
--1.0 V
in = 0 V
Vin = VCC
Input pull-up MOS current Ports P0 to PB (except for ports
P000 to P007)
Ip–300 - –10 A VCC = 2.7 to 3.6 V
Vin = 0 V
Input capacitance USB_DP, USB_DM, and ports
P003, P007, P014, P015, P400,
P401, P511, P512
Cin - - 16 pF Vbias = 0V
Vamp = 20mV
f = 1 MHz
Ta = 25°C
Other input pins - - 8
R01DS0303EU0100 Rev.1.00 Page 35 of 115
Nov 3, 2016
S5D9 2. Electrical Characteristics
2.2.5 Operating and Standby Current
Table 2.7 Operating and standby current (1 of 2)
Item Symbol Min Typ Max Unit Test conditions
Supply
current*1
High-speed mode
Maximum*2ICC*3--137*2mA ICLK = 120 MHz
PCLKA = 120 MHz*7
PCLKB = 60 MHz
PCLKC = 60 MHz
PCLKD = 120 MHz
FCLK = 60 MHz
BCLK = 120 MHz
CoreMark®*5-21-
Normal mode All peripheral clocks enabled,
while (1) code executing from
flash*4
-34-
All peripheral clocks disabled,
while (1) code executing from
flash*5, *6
-14-
Sleep mode*5, *6-1246
Increase during BGO
operation
Data flash P/E - 6 -
Code flash P/E - 8 -
Low-speed mode*5-2.4- ICLK = 1 MHz
Subosc-speed mode*5- 2 - ICLK = 32.768 kHz
Software Standby mode - 1.8 28 -
Deep Software Standby mode
Power supplied to Standby SRAM and USB resume
detecting unit
-30113A-
Power not supplied to
SRAM or USB resume
detecting unit
Power-on reset circuit low-
power function disabled
-1340 -
Power-on reset circuit low-
power function enabled
-6.334 -
Increase when the RTC
and AGT are operating
When the low-speed on-chip
oscillator (LOCO) is in use
-5- -
When a crystal oscillator for
low clock loads is in use
-1.0- -
When a crystal oscillator for
standard clock loads is in use
-1.5- -
RTC operating while VCC is off (with
the battery backup function, only the
RTC and sub-clock oscillator
operate)
When a crystal
oscillator for low clock
loads is in use
-0.9- V
BATT = 1.8 V,
VCC = 0 V
-1.3- V
BATT = 3.3 V,
VCC = 0 V
When a crystal
oscillator for standard
clock loads is in use
-1.1- V
BATT = 1.8 V,
VCC = 0 V
-1.8- V
BATT = 3.3 V,
VCC = 0 V
Analog
power
supply
current
During 12-bit A/D conversion AICC -0.81.1mA-
During 12-bit A/D conversion with S/H amp - 2.3 3.3 mA -
PGA (1ch) - 1 3 mA -
ACMPHS (1unit) - 100 150 µA AVCC 2.7 V
Temperature sensor - 0.1 0.2 mA -
During D/A conversion (per unit) Without AMP output - 0.1 0.2 mA -
With AMP output - 0.6 1.1 mA -
Waiting for A/D, D/A conversion (all units) - 0.9 1.6 mA -
ADC12, DAC12 in standby modes (all units)*8-28µA-
Reference
power
supply
current
(VREFH0)
During 12-bit A/D conversion (unit 0) AIREFH0 - 70 120 A-
Waiting for 12-bit A/D conversion (unit 0) - 0.07 0.5 A-
ADC12 in standby modes (unit 0) - 0.07 0.5 µA -
Reference
power
supply
current
(VREFH)
During 12-bit A/D conversion (unit 1) AIREFH - 70 120 µA -
During D/A conversion
(per unit)
Without AMP output - 0.1 0.4 mA -
With AMP ouput - 0.1 0.4 mA -
Waiting for 12-bit A/D (unit 1), D/A (all units) conversion - 0.07 0.8 µA -
ADC12 unit 1 in standby modes - 0.07 0.8 µA -
R01DS0303EU0100 Rev.1.00 Page 36 of 115
Nov 3, 2016
S5D9 2. Electrical Characteristics
Note 1. Supply current values are with all output pins unloaded and all input pull-up MOS transistors in the off state.
Note 2. Measured with clocks supplied to the peripheral functions. This does not include the BGO operation.
Note 3. ICC depends on f (ICLK) as follows. (ICLK:PCLKA:PCLKB:PCLKC:PCLKD:BCK:EBCLK = 2:2:1:1:2:1:1)
ICC Max. = 0.84 × f + 37 (max. operation in High-speed mode)
ICC Typ. = 0.09 × f + 3.7 (normal operation in High-speed mode)
ICC Typ. = 0.6 × f + 1.8 (Low-speed mode 1)
ICC Max. = 0.08 × f + 37 (Sleep mode).
Note 4. This does not include the BGO operation.
Note 5. Supply of the clock signal to peripherals is stopped in this state. This does not include the BGO operation.
Note 6. FCLK, BCLK, PCLKA, PCLKB, PCLKC, and PCLKD are set to divided by 64 (3.75 MHz).
Note 7. When using ETHERC, GLCDC, DRW, and JPEG, PCLKA frequency is such that PCLKA = ICLK.
Note 8. When the MCU is in Software Standby mode or the MSTPCRD.MSTPD16 (ADC120 module stop bit) and
MSTPCRD.MSTPD15 (ADC121 module stop bit) are in the module stop state.
USB
operating
current
Low speed USB ICCUSBLS - 3.5 6.5 mA VCC_USB
USBHS - 10.5 13.5 mA VCC_USBHS =
AVCC_USBHS
(PHYSET.HSEB = 0)
USBHS - 2.8 3.6 mA VCC_USBHS =
AVCC_USBHS
(PHYSET.HSEB = 1)
Full speed USB ICCUSBFS - 4.0 10.0 mA VCC_USB
USBHS - 14 22 mA VCC_USBHS =
AVCC_USBHS
(PHYSET.HSEB = 0)
USBHS - 6.5 13.0 mA VCC_USBHS =
AVCC_USBHS
(PHYSET.HSEB = 1)
High speed USBHS ICCUSBHS - 50 65 mA VCC_USBHS =
AVCC_USBHS
Standby mode (direct power down) USBHS ICCUSBSBY -0.54.5A VCC_USBHS =
AVCC_USBHS
Table 2.7 Operating and standby current (2 of 2)
Item Symbol Min Typ Max Unit Test conditions
R01DS0303EU0100 Rev.1.00 Page 37 of 115
Nov 3, 2016
S5D9 2. Electrical Characteristics
2.2.6 VCC Rise and Fall Gradient and Ripple Frequency
Note 1. At boot mode, the reset from voltage monitor 0 is disabled regardless of the value of OFS1.LVDAS bit.
Note 2. This applies when VBATT is used.
Figure 2.2 Ripple waveform
2.3 AC Characteristics
2.3.1 Frequency
Table 2.8 Rise and fall gradient characteristics
Item Symbol Min Typ Max Unit Test conditions
VCC rising gradient Voltage monitor 0 reset disabled at startup SrVCC 0.0084 - 20 ms/V -
Voltage monitor 0 reset enabled at startup 0.0084 - - -
SCI/USB boot mode*10.0084 - 20 -
VCC falling gradient*2SfVCC 0.0084 - - ms/V -
Table 2.9 Rise and fall gradient and ripple frequency characteristics
The ripple voltage must meet the allowable ripple frequency fr(VCC) within the range between the VCC upper limit (3.6 V) and lower limit
(2.7 V). When the VCC change exceeds VCC ±10%, the allowable voltage change rising and falling gradient dt/dVCC must be met.
Item Symbol Min Typ Max Unit Test conditions
Allowable ripple frequency fr (VCC) --10kHzFigure 2.2
Vr (VCC) VCC × 0.2
--1MHzFigure 2.2
Vr (VCC) VCC × 0.08
--10MHzFigure 2.2
Vr (VCC) VCC × 0.06
Allowable voltage change rising
and falling gradient
dt/dVCC 1.0 - - ms/V When VCC change exceeds VCC ±10%
Table 2.10 Operation frequency value in high-speed mode
Item Symbol Min Typ Max Unit
Operation frequency System clock (ICLK*2) f - - 120 MHz
Peripheral module clock (PCLKA)*2- - 120
Peripheral module clock (PCLKB)*2--60
Peripheral module clock (PCLKC)*2-*3-60
Peripheral module clock (PCLKD)*2- - 120
Flash interface clock (FCLK)*2-*1-60
External bus clock (BCLK)*2- - 120
EBCLK pin output - - 60
SDCLK pin output VCC 3.0 V - - 120
Vr(VCC)
VCC
1/fr(VCC)
R01DS0303EU0100 Rev.1.00 Page 38 of 115
Nov 3, 2016
S5D9 2. Electrical Characteristics
Note 1. FCLK must run at a frequency of at least 4 MHz when programming or erasing the flash memory.
Note 2. See section 9, Clock Generation Circuit in User's Manual for the relationship between the ICLK, PCLKA, PCLKB, PCLKC,
PCLKD, FCLK, and BCLK frequencies.
Note 3. When the ADC12 is used, the PCLKC frequency must be at least 1 MHz.
Note 1. Programming or erasing the flash memory is disabled in low-speed mode.
Note 2. See section 9, Clock Generation Circuit in User's Manual for the relationship between the ICLK, PCLKA, PCLKB, PCLKC,
PCLKD, FCLK, and BCLK frequencies.
Note 3. When the ADC12 is used, the PCLKC frequency must be set to at least 1 MHz.
Note 1. Programming or erasing the flash memory is disable in Subosc-speed mode.
Note 2. See section 9, Clock Generation Circuit in User's Manual for the relationship between the ICLK, PCLKA, PCLKB, PCLKC,
PCLKD, FCLK, and BCLK frequencies.
Note 3. The ADC12 cannot be used.
2.3.2 Clock Timing
Table 2.11 Operation frequency value in low-speed mode
Item Symbol Min Typ Max Unit
Operation frequency System clock (ICLK)*2f--1MHz
Peripheral module clock (PCLKA)*2--1
Peripheral module clock (PCLKB)*2--1
Peripheral module clock (PCLKC)*2,*3-*3-1
Peripheral module clock (PCLKD)*2--1
Flash interface clock (FCLK)*1, *2--1
External bus clock (BCLK) - - 1
EBCLK pin output - - 1
Table 2.12 Operation frequency value in Subosc-speed mode
Item Symbol Min Typ Max Unit
Operation frequency System clock (ICLK)*2f 27.8 - 37.7 kHz
Peripheral module clock (PCLKA)*2- - 37.7
Peripheral module clock (PCLKB)*2- - 37.7
Peripheral module clock (PCLKC)*2,*3- - 37.7
Peripheral module clock (PCLKD)*2- - 37.7
Flash interface clock (FCLK)*1, *227.8 - 37.7
External bus clock (BCLK)*2- - 37.7
EBCLK pin output - - 37.7
Table 2.13 Clock timing except for sub-clock oscillator (1 of 2)
Item Symbol Min Typ Max Unit Test conditions
EBCLK pin output cycle time tBcyc 16.6 - - ns Figure 2.3
EBCLK pin output high pulse width tCH 3.3 - - ns
EBCLK pin output low pulse width tCL 3.3 - - ns
EBCLK pin output rise time tCr --5.0ns
EBCLK pin output fall time tCf --5.0ns
SDCLK pin output cycle time tSDcyc 8.33 - - ns
SDCLK pin output high pulse width tCH 1.0 - - ns
SDCLK pin output low pulse width tCL 1.0 - - ns
SDCLK pin output rise time tCr --3.0ns
SDCLK pin output fall time tCf --3.0ns
R01DS0303EU0100 Rev.1.00 Page 39 of 115
Nov 3, 2016
S5D9 2. Electrical Characteristics
Note 1. When setting up the main clock oscillator, ask the oscillator manufacturer for an oscillation evaluation and use the results as the
recommended oscillation stabilization time. Set the MOSCWTCR register to a value equal to or greater than the recommended
value.
After changing the setting in the MOSCCR.MOSTP bit to start main clock operation, read the OSCSF.MOSCSF flag to confirm
that it is 1, and then start using the main clock oscillator.
Note 2. This is the time from release from reset state until the HOCO oscillation frequency (fHOCO) reaches the range for guaranteed
operation.
Note: When setting up the sub-clock oscillator, ask the oscillator manufacturer for an oscillation evaluation and use the results as the
recommended oscillation stabilization time.
After changing the setting in the SOSCCR.SOSTP bit to start sub-clock operation, only start using the sub-clock oscillator after
the sub-clock oscillation stabilization time elapses with an adequate margin. Two times the value shown is recommended.
EXTAL external clock input cycle time tEXcyc 41.66 - - ns Figure 2.4
EXTAL external clock input high pulse width tEXH 15.83 - - ns
EXTAL external clock input low pulse width tEXL 15.83 - - ns
EXTAL external clock rise time tEXr --5.0ns
EXTAL external clock fall time tEXf --5.0ns
Main clock oscillator frequency fMAIN 8-24MHz-
Main clock oscillation stabilization wait time
(crystal) *1
tMAINOSCWT ---*
1ms Figure 2.5
LOCO clock oscillation frequency fLOCO 27.8528 32.768 37.6832 kHz -
LOCO clock oscillation stabilization wait time tLOCOWT - - 60.4 sFigure 2.6
ILOCO clock oscillation frequency fILOCO 12.75 15 17.25 kHz -
MOCO clock oscillation frequency FMOCO 6.8 8 9.2 MHz -
MOCO clock oscillation stabilization wait time tMOCOWT - - 15.0 s-
HOCO clock oscillator
oscillation frequency
Without FLL*2fHOCO16 15.78 16 16.22 MHz –20 Ta 105°C
fHOCO18 17.75 18 18.25
fHOCO20 19.72 20 20.28
fHOCO16 15.71 16 16.29 –40 Ta –20°C
fHOCO18 17.68 18 18.32
fHOCO20 19.64 20 20.36
With FLL fHOCO16 15.955 16 16.045 –40 Ta –105°C
Sub-clock
frequency accuracy
is ±50 ppm.
fHOCO18 17.949 18 18.051
fHOCO20 19.944 20 20.056
HOCO clock oscillation stabilization wait time tHOCOWT - - 64.7 s-
FLL stabilization wait time tFLLWT --1.8ms-
PLL clock frequency fPLL 120 - 240 MHz -
PLL clock oscillation stabilization wait time tPLLWT - - 174.9 sFigure 2.7
Table 2.14 Clock timing for the sub-clock oscillator
Item Symbol Min Typ Max Unit Test conditions
Sub-clock frequency fSUB - 32.768 - kHz -
Sub-clock oscillation stabilization wait time tSUBOSCWT ---*
Note: s-
Table 2.13 Clock timing except for sub-clock oscillator (2 of 2)
Item Symbol Min Typ Max Unit Test conditions
R01DS0303EU0100 Rev.1.00 Page 40 of 115
Nov 3, 2016
S5D9 2. Electrical Characteristics
Figure 2.3 EBCLK and SDCLK output timing
Figure 2.4 EXTAL external clock input timing
Figure 2.5 Main clock oscillation start timing
Figure 2.6 LOCO clock oscillation start timing
tCf
tCH
tBcyc, tSDcyc
tCr
tCL
EBCLK pin output, SDCLK pin output
tEXH
tEXcyc
EXTAL external clock input VCC × 0.5
tEXL
tEXr tEXf
Main clock oscillator output
MOSCCR.MOSTP
Main clock
tMAINOSCWT
LOCO clock
LOCOCR.LCSTP
tLOCOWT
On-chip oscillator output
R01DS0303EU0100 Rev.1.00 Page 41 of 115
Nov 3, 2016
S5D9 2. Electrical Characteristics
Figure 2.7 PLL clock oscillation start timing
Note: Only operate the PLL is operated after main clock oscillation has stabilized.
Figure 2.8 Sub-clock oscillation start timing
2.3.3 Reset Timing
Table 2.15 Reset timing
Item Symbol Min Typ Max Unit
Test
conditions
RES pulse width Power-on tRESWP 1- - msFigure 2.9
Deep Software Standby mode tRESWD 0.6 - - ms Figure 2.10
Software Standby mode, Subosc-speed
mode
tRESWS 0.3 - - ms
All other tRESW 200 - - s
Wait time after RES cancellation tRESWT -2933sFigure 2.9
Wait time after internal reset cancellation
(IWDT reset, WDT reset, software reset, SRAM parity error
reset, SRAM ECC error reset, bus master MPU error reset, bus
slave MPU error reset, stack pointer error reset)
tRESW2 - 320 408 s-
PLLCR.PLLSTP
OSCSF.PLLSF
PLL clock
tPLLWT
PLL circuit output
Sub-clock oscillator output
SOSCCR.SOSTP
tSUBOSC
Sub-clock
R01DS0303EU0100 Rev.1.00 Page 42 of 115
Nov 3, 2016
S5D9 2. Electrical Characteristics
Figure 2.9 Power-on reset timing
Figure 2.10 Reset input timing
2.3.4 Wakeup Timing
Table 2.16 Timing of recovery from low-power modes
Item Symbol Min Typ Max Unit
Test
conditions
Recovery time
from Software
Standby mode*1
Crystal
resonator
connected
to main
clock
oscillator
System clock source is main
clock oscillator*2
tSBYMC - 2.4*9 2.8*9ms Figure 2.11
The division
ratio of all
oscillators is
1.
System clock source is PLL
with main clock oscillator*3
tSBYPC - 2.7*9 3.2*9ms
External
clock input
to main
clock
oscillator
System clock source is main
clock oscillator*4
tSBYEX - 230*9 280*9s
System clock source is PLL
with main clock oscillator*5
tSBYPE - 570*9 700*9s
System clock source is sub-clock
oscillator*8
tSBYSC -1.2*
91.3*9ms
System clock source is LOCO*8tSBYLO -1.2*
91.4*9ms
System clock source is HOCO clock
oscillator*6
tSBYHO - 240*9, *10 310
*9, *10
µs
System clock source is MOCO clock
oscillator*7
tSBYMO - 220*9300*9µs
Recovery time from Deep Software Standby mode tDSBY - 0.65 1.0 ms Figure 2.12
Wait time after cancellation of Deep Software Standby mode tDSBYWT 34 - 35 tcyc
Recovery time
from Software
Standby mode to
Snooze mode
High-speed mode when system clock
source is HOCO (20 MHz)
tSNZ - 35*9, *10 71
*9, *10
sFigure 2.13
High-speed mode when system clock
source is MOCO (8 MHz)
tSNZ -11*
914*9 s
VCC
RES
Internal reset signal
(low is valid)
tRESWP
tRESWT
RES
Internal reset signal
(low is valid)
tRESWD, tRESWS, tRESW
tRESWT
R01DS0303EU0100 Rev.1.00 Page 43 of 115
Nov 3, 2016
S5D9 2. Electrical Characteristics
Note 1. The recovery time is determined by the system clock source. When multiple oscillators are active, the recovery time can be
determined with the following equation:
Total recovery time = recovery time for an oscillator as the system clock source + the longest oscillation stabilization time of any
oscillators requiring longer stabilization times than the system clock source + 2 LOCO cycles (when LOCO is operating) + 3
SOSC cycles (when Subosc is oscillating and MSTPC0 = 0 (CAC module stop)).
Note 2. When the frequency of the crystal is 24 MHz (Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 05h). For
other settings (MOSCWTCR is set to Xh), the recovery time can be determined with the following equation:
tSBYMC (MOSCWTCR = Xh) = tSBYMC (MOSCWTCR = 05h) + (tMAINOSCWT (MOSCWTCR = Xh) - tMAINOSCWT (MOSCWTCR =
05h))
Note 3. When the frequency of PLL is 240 MHz (Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 05h). For other
settings (MOSCWTCR is set to Xh), the recovery time can be determined with the following equation:
tSBYMC (MOSCWTCR = Xh) = tSBYMC (MOSCWTCR = 05h) + (tMAINOSCWT (MOSCWTCR = Xh) - tMAINOSCWT (MOSCWTCR =
05h))
Note 4. When the frequency of the external clock is 24 MHz (Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 00h).
For other settings (MOSCWTCR is set to Xh), the recovery time can be determined with the following equation:
tSBYMC (MOSCWTCR = Xh) = tSBYMC (MOSCWTCR = 00h) + (tMAINOSCWT (MOSCWTCR = Xh) - tMAINOSCWT (MOSCWTCR =
00h))
Note 5. When the frequency of PLL is 240 MHz (Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 00h). For other
settings (MOSCWTCR is set to Xh), the recovery time can be determined with the following equation:
tSBYMC (MOSCWTCR = Xh) = tSBYMC (MOSCWTCR = 00h) + (tMAINOSCWT (MOSCWTCR = Xh) - tMAINOSCWT (MOSCWTCR =
00h))
Note 6. The HOCO frequency is 20 MHz.
Note 7. The MOCO frequency is 8 MHz.
Note 8. In Subosc-speed mode, the sub-clock oscillator or LOCO continues oscillating in Software Standby mode.
Note 9. When the SNZCR.RXDREQEN bit is set to 0, the following time is added as the power supply recovery time:
STCONR.STCON[1:0] = 00b:16 µs (typical), 34 µs (maximum)
STCONR.STCON[1:0] = 11b:16 µs (typical), 104 µs (maximum).
Note 10. When the SNZCR.RXDREQEN bit is set to 0, 16 s (typical) or 18 s (maximum) is added as the HOCO wait time.
R01DS0303EU0100 Rev.1.00 Page 44 of 115
Nov 3, 2016
S5D9 2. Electrical Characteristics
Figure 2.11 Software Standby mode cancellation timing
Oscillator
(system clock)
ICLK
IRQ
Software Standby mode
tSBYMC, tSBYEX, tSBYPC, tSBYPE,
tSBYPH, tSBYSC, tSBYHO, tSBYLO
Oscillator
(not the system clock)
tSBYOSCWT tSBYSEQ
Oscillator
(system clock)
ICLK
IRQ
Software Standby mode
tSBYMC, tSBYEX, tSBYPC, tSBYPE,
tSBYPH, tSBYSC, tSBYHO, tSBYLO
tSBYOSCWT
tSBYOSCWT
When stabilization of the system clock oscillator is slower
tSBYSEQ
Oscillator
(not the system clock)
When stabilization of an oscillator other than the system clock is slower
R01DS0303EU0100 Rev.1.00 Page 45 of 115
Nov 3, 2016
S5D9 2. Electrical Characteristics
Figure 2.12 Deep Software Standby mode cancellation timing
Figure 2.13 Recovery timing from Software Standby mode to Snooze mode
2.3.5 NMI and IRQ Noise Filter
Note: 200 ns minimum in Software Standby mode.
Note 1. tPcyc indicates the PCLKB cycle.
Table 2.17 NMI and IRQ noise filter
Item Symbol Min Typ Max Unit Test conditions
NMI pulse width tNMIW 200 - - ns NMI digital filter disabled tPcyc × 2 200 ns
tPcyc × 2*1-- t
Pcyc × 2 > 200 ns
200 - - NMI digital filter enabled tNMICK × 3 200 ns
tNMICK × 3.5*2-- t
NMICK × 3 > 200 ns
IRQ pulse width tIRQW 200 - - ns IRQ digital filter disabled tPcyc × 2 200 ns
tPcyc × 2*1-- t
Pcyc × 2 > 200 ns
200 - - IRQ digital filter enabled tIRQCK × 3 200 ns
tIRQCK × 3.5*3-- t
IRQCK × 3 > 200 ns
Oscillator
IRQ
Internal reset
(low is valid)
Reset exception handling start
Deep Software Standby mode
Deep Software Standby
reset
(low is valid)
tDSBY
tDSBYWT
tSNZ
IRQ
ICLK(to DTC, SRAM)*1
PCLK
ICLK(except DTC, SRAM)
Oscillator
Software Standby mode Snooze mode
Note 1. When SNZCR.SNZDTCEN is set to 1, ICLK is supplied to DTC and SRAM.
R01DS0303EU0100 Rev.1.00 Page 46 of 115
Nov 3, 2016
S5D9 2. Electrical Characteristics
Note 2. tNMICK indicates the cycle of the NMI digital filter sampling clock.
Note 3. tIRQCK indicates the cycle of the IRQi digital filter sampling clock.
Figure 2.14 NMI interrupt input timing
Figure 2.15 IRQ interrupt input timing
2.3.6 Bus Timing
Table 2.18 Bus timing (1 of 2)
Condition 1: When using the CS area controller (CSC).
BCLK = 8 to 120 MHz, EBCLK = 8 to 60 MHz
VCC = AVCC0 = VCC_USB = VBATT = 2.7 to 3.6 V, VREFH/VREFH0 = 2.7 V to AVCC0,
VCC_USBHS = AVCC_USBHS = 3.0 to 3.6 V
Output load conditions: VOH = VCC × 0.5, VOL = VCC × 0.5, C = 30 pF
EBCLK: High drive output is selected in the port drive capability bit in the PmnPFS register.
Others: Middle drive output is selected in the port drive capability bit in the PmnPFS register.
Condition 2: When using the SDRAM area controller (SDRAMC).
BCLK = SDCLK = 8 to 120 MHz
VCC = AVCC0 = VCC_USB = VBATT = 3.0 to 3.6 V, VREFH/VREFH0 = 3.0 V to AVCC0,
VCC_USBHS = AVCC_USBHS = 3.0 to 3.6 V
Output load conditions: VOH = VCC × 0.5, VOL = VCC × 0.5, C = 15 pF
High drive output is selected in the port drive capability bit in the PmnPFS register.
Condition 3: When using the SDRAM area controller (SDRAMC) and CS area controller (CSC) simultaneously.
BCLK = SDCLK = 8 to 60 MHz
VCC = AVCC0 = VCC_USB = VBATT = 3.0 to 3.6 V, VREFH/VREFH0 = 3.0 V to AVCC0,
VCC_USBHS = AVCC_USBHS = 3.0 to 3.6 V
Output load conditions: VOH = VCC × 0.5, VOL = VCC × 0.5, C = 15 pF
High drive output is selected in the port drive capability bit in the PmnPFS register.
Item Symbol Min Max Unit Test conditions
Address delay tAD - 12.5 ns Figure 2.18 to
Figure 2.21
Byte control delay tBCD - 12.5 ns
CS delay tCSD - 12.5 ns
ALE delay time tALED - 12.5 ns
RD delay tRSD - 12.5 ns
Read data setup time tRDS 12.5 - ns
Read data hold time tRDH 0- ns
WR/WRn delay tWRD - 12.5 ns
Write data delay tWDD - 12.5 ns
Write data hold time tWDH 0- ns
WAIT setup time tWTS 12.5 - ns Figure 2.22
WAIT hold time tWTH 0- ns
tNMIW
NMI
tIRQW
IRQ
R01DS0303EU0100 Rev.1.00 Page 47 of 115
Nov 3, 2016
S5D9 2. Electrical Characteristics
Address delay 2 (SDRAM) tAD2 0.8 6.8 ns Figure 2.23 to
Figure 2.29
CS delay 2 (SDRAM) tCSD2 0.8 6.8 ns
DQM delay (SDRAM) tDQMD 0.8 6.8 ns
CKE delay (SDRAM) tCKED 0.8 6.8 ns
Read data setup time 2 (SDRAM) tRDS2 2.9 - ns
Read data hold time 2 (SDRAM) tRDH2 1.5 - ns
Write data delay 2 (SDRAM) tWDD2 - 6.8 ns
Write data hold time 2 (SDRAM) tWDH2 0.8 - ns
WE delay (SDRAM) tWED 0.8 6.8 ns
RAS delay (SDRAM) tRASD 0.8 6.8 ns
CAS delay (SDRAM) tCASD 0.8 6.8 ns
Table 2.18 Bus timing (2 of 2)
Condition 1: When using the CS area controller (CSC).
BCLK = 8 to 120 MHz, EBCLK = 8 to 60 MHz
VCC = AVCC0 = VCC_USB = VBATT = 2.7 to 3.6 V, VREFH/VREFH0 = 2.7 V to AVCC0,
VCC_USBHS = AVCC_USBHS = 3.0 to 3.6 V
Output load conditions: VOH = VCC × 0.5, VOL = VCC × 0.5, C = 30 pF
EBCLK: High drive output is selected in the port drive capability bit in the PmnPFS register.
Others: Middle drive output is selected in the port drive capability bit in the PmnPFS register.
Condition 2: When using the SDRAM area controller (SDRAMC).
BCLK = SDCLK = 8 to 120 MHz
VCC = AVCC0 = VCC_USB = VBATT = 3.0 to 3.6 V, VREFH/VREFH0 = 3.0 V to AVCC0,
VCC_USBHS = AVCC_USBHS = 3.0 to 3.6 V
Output load conditions: VOH = VCC × 0.5, VOL = VCC × 0.5, C = 15 pF
High drive output is selected in the port drive capability bit in the PmnPFS register.
Condition 3: When using the SDRAM area controller (SDRAMC) and CS area controller (CSC) simultaneously.
BCLK = SDCLK = 8 to 60 MHz
VCC = AVCC0 = VCC_USB = VBATT = 3.0 to 3.6 V, VREFH/VREFH0 = 3.0 V to AVCC0,
VCC_USBHS = AVCC_USBHS = 3.0 to 3.6 V
Output load conditions: VOH = VCC × 0.5, VOL = VCC × 0.5, C = 15 pF
High drive output is selected in the port drive capability bit in the PmnPFS register.
Item Symbol Min Max Unit Test conditions
R01DS0303EU0100 Rev.1.00 Page 48 of 115
Nov 3, 2016
S5D9 2. Electrical Characteristics
Figure 2.16 Address/data multiplexed bus read access timing
Figure 2.17 Address/data multiplexed bus write access timing
Address bus/
data bus
Data read
(RD)
tAD
EBCLK
Address bus
Address latch
(ALE)
Chip select
(CSn)
tALED
TW1 TW2 Tn1
tAD tAD
tRDS
Tn2
tRSD tRSD
TW3 TW4 TW5 Tend
Ta1 Ta1 Tan
Address cycle Data cycle
tRDH
tALED
tCSD tCSD
Address bus/
data bus
Data write
(WRm)
tAD
EBCLK
Address bus
Address latch
(ALE)
Chip select
(CSn)
tALED
TW1 TW2 Tn1
tAD tAD
Tn2
tWRD tWRD
TW3 TW4 TW5 Tend
Ta1 Ta1 Tan
Address cycle Data cycle
tALED
tCSD tCSD
tWDD tWDH
Tn3
R01DS0303EU0100 Rev.1.00 Page 49 of 115
Nov 3, 2016
S5D9 2. Electrical Characteristics
Figure 2.18 External bus timing for normal read cycle with bus clock synchronized
A23 to A01
CS7 to CS0
tAD
EBCLK
A23 to A00
D15 to D00 (read)
Byte strobe mode
1-write strobe mode
BC1, BC0
Common to both byte strobe mode
and 1-write strobe mode
tBCD
tCSD tCSD
RD (read)
tRSD tRSD
tAD
tRDH
tRDS
tAD
tAD
tBCD
TW1 TW2 Tend Tn1 Tn2
RDON:1
CSRWAIT: 2
CSROFF: 2
CSON: 0
R01DS0303EU0100 Rev.1.00 Page 50 of 115
Nov 3, 2016
S5D9 2. Electrical Characteristics
Figure 2.19 External bus timing for normal write cycle with bus clock synchronized
Note 1. Always specify WDON and WDOFF as at least one EBCLK cycle.
A23 to A01
CS7 to CS0
tAD
EBCLK
A23 to A00
Byte strobe mode
1-write strobe mode
BC1, BC0
Common to both byte strobe mode
and 1-write strobe mode
tBCD
tCSD tCSD
tAD
tAD
tAD
tBCD
D15 to D00 (write)
WR1, WR0, WR (write)
tWRD tWRD
tWDH
tWDD
TW1 TW2 Tend Tn1 Tn2
WRON: 1
WDON: 1*1
CSWWAIT: 2
WDOFF: 1*1
CSON:0
CSWOFF: 2
R01DS0303EU0100 Rev.1.00 Page 51 of 115
Nov 3, 2016
S5D9 2. Electrical Characteristics
Figure 2.20 External bus timing for page read cycle with bus clock synchronized
Figure 2.21 External bus timing for page write cycle with bus clock synchronized
A23 to A01
CS7 to CS0
tAD
EBCLK
A23 to A00
D15 to D00 (Read)
Byte strobe mode
1-write strobe mode
BC1, BC0
Common to both byte strobe mode
and 1-write strobe mode
tBCD
tCSD tCSD
RD (Read)
tRSD tRSD
tRDH
tRDS
tAD
tBCD
TW1 TW2 Tend Tpw1 Tpw2
tAD tAD
tRSD tRSD
tRDH
tRDS
tRSD tRSD
tRDH
tRDS
Tend Tpw1 Tpw2 Tend Tn1 Tn2
tAD tAD tAD tAD
RDON:1
CSRWAIT:2
CSROFF:2
tRSD tRSD
tRDH
tRDS
tAD
tAD
CSPRWAIT:2
Tpw1 Tpw2 Tend
RDON:1
CSPRWAIT:2
RDON:1
CSPRWAIT:2
RDON:1
CSON:0
Note 1. Always specify WDON and WDOFF as at least one EBCLK cycle.
A23 to A01
CS7 to CS0
tAD
EBCLK
A23 to A00
Byte strobe mode
1-write strobe mode
BC1, BC0
Common to both byte strobe mode
and 1-write strobe mode
tBCD
tCSD tCSD
tAD
tBCD
TW1
D15 to D00 (write)
WR1, WR0, WR (write)
tWRD tWRD
tWDH
tWDD
TW2 Tend Tpw1 Tpw2
tAD tAD
tWRD tWRD
tWDH
tWDD
tWRD tWRD
tWDH
tWDD
Tdw1 Tend Tpw1 Tpw2 Tend Tn1 Tn2
Tdw1
tAD tAD tAD tAD
WRON:1
WDON:1*1
CSWWAIT:2 CSPWWAIT:2
WDOFF:1*1
CSPWWAIT:2
WDOFF:1*1WDOFF:1*1
CSON:0
WRON:1
WDON:1*1
WRON:1
WDON:1*1
CSWOFF:2
R01DS0303EU0100 Rev.1.00 Page 52 of 115
Nov 3, 2016
S5D9 2. Electrical Characteristics
Figure 2.22 External bus timing for external wait control
tWTS tWTH tWTS tWTH
CSRWAIT:3
CSWWAIT:3
EBCLK
A23 to A00
CS7 to CS0
RD (read)
WR (write)
WAIT
TW1 TW2 (Tend)T
end
TW3 Tn1 Tn2
External wait
R01DS0303EU0100 Rev.1.00 Page 53 of 115
Nov 3, 2016
S5D9 2. Electrical Characteristics
Figure 2.23 SDRAM single read timing
Note 1. Address pins are for output of the precharge-select command (Precharge-sel) for the SDRAM.
tAD2
SDCLK
A15 to A00
SDCS
AP*1
DQMn
DQ15 to DQ00
RAS
CAS
WE
CKE
tDQMD
(High)
Row
address Column address
SDRAM command ACT RD PRA
tAD2
tCSD2
tRASD
tAD2
tAD2
tCSD2
tRASD
tAD2
tAD2
tCSD2
tRASD
tAD2
tAD2
tCSD2
tRASD
tWED tWED
tCSD2 tCSD2
tCASD tCASD
tRDS2 tRDH2
PRA
command
R01DS0303EU0100 Rev.1.00 Page 54 of 115
Nov 3, 2016
S5D9 2. Electrical Characteristics
Figure 2.24 SDRAM single write timing
Note 1. Address pins are for output of the precharge-select command (Precharge-sel) for the SDRAM.
tAD2
SDCLK
A15 to A00
SDCS
AP*1
DQMn
DQ15 to DQ00
RAS
CAS
WE
CKE
tDQMD
(High)
Row
address Column address
SDRAM command ACT WR PRA
tAD2
tCSD2
tRASD
tWED
tCASD
tWDD2
tAD2
tAD2
tCSD2
tRASD
tAD2
tAD2
tCSD2
tRASD
tAD2
tAD2
tCSD2
tRASD
tCSD2 tCSD2
tCASD
tWED tWED tWED
tWDH2
PRA
command
R01DS0303EU0100 Rev.1.00 Page 55 of 115
Nov 3, 2016
S5D9 2. Electrical Characteristics
Figure 2.25 SDRAM multiple read timing
Note 1. Address pins are for output of the precharge-select command (Precharge-sel) for the SDRAM.
SDCLK
ACT RD RD RD RD PRA
A15 to A00
tAD2 tAD2 tAD2 tAD2 tAD2 tAD2 tAD2 tAD2
AP*1
SDCS
RAS
CAS
WE
CKE
DQMn
DQ15 to DQ00
C1 C2 C3
Row
address
C0
(column address)
tAD2 tAD2 tAD2 tAD2 tAD2
tCSD2 tCSD2 tCSD2 tCSD2 tCSD2
tRASD tRASD tRASD tRASD tRASD
tCASD tCASD tCASD
tWED tWED
(High)
tDQMD tDQMD
tRDS2 tRDH2 tRDS2 tRDH2
PRA
command
R01DS0303EU0100 Rev.1.00 Page 56 of 115
Nov 3, 2016
S5D9 2. Electrical Characteristics
Figure 2.26 SDRAM multiple write timing
Note 1. Address pins are for output of the precharge-select command (Precharge-sel) for the SDRAM.
ACT WR PRAWR WR WR
SDCLK
A15 to A00
AP*1
SDCS
RAS
CAS
WE
CKE
DQMn
DQ15 to DQ00
tAD2 tAD2 tAD2 tAD2 tAD2 tAD2 tAD2 tAD2
tAD2 tAD2 tAD2 tAD2 tAD2
tCSD2 tCSD2 tCSD2 tCSD2 tCSD2
tRASD tRASD tRASD tRASD tRASD
tCASD tCASD tCASD
tWED tWED
(High)
tDQMD tDQMD
tWDD2 tWDH2 tWDD2 tWDH2
C1 C2 C3
Row
address
C0
(column address)
PRA
command
R01DS0303EU0100 Rev.1.00 Page 57 of 115
Nov 3, 2016
S5D9 2. Electrical Characteristics
Figure 2.27 SDRAM multiple read line stride timing
Note 1. Address pins are for output of the precharge-select command (Precharge-sel) for the SDRAM.
R1
A15 to A00
SDCLK
SDCS
AP*1
DQMn
DQ15 to DQ00
RAS
CAS
WE
CKE
SDRAM command ACT RD RDRDRDPRA ACT RD RDRDRDPRA
tCASD
tRASD
tCSD2
tAD2
tAD2
tAD2
tAD2
tAD2
tAD2
tAD2
tAD2
tAD2
tAD2
tAD2
tAD2
tAD2 tAD2
tAD2 tAD2 tAD2 tAD2 tAD2 tAD2 tAD2 tAD2
tCSD2 tCSD2 tCSD2 tCSD2 tCSD2 tCSD2 tCSD2
tRASD tRASD tRASD tRASD tRASD
tCASD tCASD
tRASD tRASD
tCASD
tDQMD
tRDS2 tRDH2 tRDS2 tRDH2 tRDS2 tRDH2 tRDS2 tRDH2
(High)
Row
address C0
(column address 0) C1 C2 C3 C4 C5 C6 C7
PRA
command PRA
command
tWED tWED tWED tWED
R01DS0303EU0100 Rev.1.00 Page 58 of 115
Nov 3, 2016
S5D9 2. Electrical Characteristics
Figure 2.28 SDRAM mode register set timing
Note 1. Address pins are for output of the precharge-select command (Precharge-sel) for the SDRAM.
A15 to A00
SDCLK
SDCS
AP*1
DQMn
DQ15 to DQ00
RAS
CAS
WE
CKE
SDRAM command
(Hi-Z)
(High)
tCASD
tRASD
tCSD2
tAD2
MRS
tAD2
tAD2
tAD2
tCASD
tRASD
tCSD2
tWED tWED
R01DS0303EU0100 Rev.1.00 Page 59 of 115
Nov 3, 2016
S5D9 2. Electrical Characteristics
Figure 2.29 SDRAM self-refresh timing
2.3.7 I/O Ports, POEG, GPT32, AGT, KINT, and ADC12 Trigger Timing
Table 2.19 I/O ports, POEG, GPT32, AGT, KINT, and ADC12 trigger timing (1 of 2)
GPT32 Conditions:
High drive output is selected in the port drive capability bit in the PmnPFS register.
AGT Conditions:
Middle drive output is selected in the port drive capability bit in the PmnPFS register.
Item Symbol Min Max Unit
Test
conditions
I/O ports Input data pulse width tPRW 1.5 - tPcyc Figure 2.30
POEG POEG input trigger pulse width tPOEW 3- t
Pcyc Figure 2.31
Note 1. Address pins are for output of the precharge-select command (Precharge-sel) for the SDRAM.
A15 to A00
(RFS)
SDCLK
SDCS
AP*1
DQMn
DQ15 to DQ00
RAS
CAS
WE
CKE
(Hi-Z)
tCKED
(High)
tCASD
tCASD
tCASD
tRASD tRASD tRASD
tCSD2
tCSD2
tCSD2
tAD2
tAD2
(RFA)Ts (RFX) (RFA)
tAD2
tAD2
tCSD2 tCSD2
tCSD2
tCSD2
tRASD tRASD tRASD tRASD
tCASD tCASD tCASD tCASD
tCKED
SDRAM command
tDQMD tDQMD
R01DS0303EU0100 Rev.1.00 Page 60 of 115
Nov 3, 2016
S5D9 2. Electrical Characteristics
Note 1. tPcyc: PCLKB cycle, tPDcyc: PCLKD cycle.
Note 2. This skew applies when the same driver I/O is used. If the I/O of the middle and high drivers is mixed, operation is not
guaranteed.
Note 3. The load is 30 pF.
Note 4. Constraints on AGTIO input: tPcyc × 2 (tPcyc: PCLKB cycle) < tACYC.
Figure 2.30 I/O ports input timing
Figure 2.31 POEG input trigger timing
GPT32 Input capture pulse width Single edge tGTICW 1.5 - tPDcyc Figure 2.32
Dual edge 2.5 -
GTIOCxY output skew
(x = 0 to 7, Y= A or B)
Middle drive buffer tGTISK*2-4nsFigure 2.33
High drive buffer - 4
GTIOCxY output skew
(x = 8 to 13, Y = A or B)
Middle drive buffer - 4
High drive buffer - 4
GTIOCxY output skew
(x = 0 to 13, Y = A or B)
Middle drive buffer - 6
High drive buffer - 6
OPS output skew
GTOUUP, GTOULO, GTOVUP,
GTOVLO, GTOWUP, GTOWLO
tGTOSK
-5nsFigure 2.34
GPT(PWM
Delay
Generation
Circuit)
GTIOCxY_Z output skew
(x = 0 to 3, Y = A or B, Z = A)
tHRSK*3-2.0nsFigure 2.35
AGT AGTIO, AGTEE input cycle tACYC*4100 - ns Figure 2.36
AGTIO, AGTEE input high width, low width tACKWH,
tACKWL
40 - ns
AGTIO, AGTO, AGTOA, AGTOB output cycle tACYC2 62.5 - ns
ADC12 ADC12 trigger input pulse width tTRGW 1.5 - tPcyc Figure 2.37
KINT Key interrupt input low width tKR 250 - ns Figure 2.38
Table 2.19 I/O ports, POEG, GPT32, AGT, KINT, and ADC12 trigger timing (2 of 2)
GPT32 Conditions:
High drive output is selected in the port drive capability bit in the PmnPFS register.
AGT Conditions:
Middle drive output is selected in the port drive capability bit in the PmnPFS register.
Item Symbol Min Max Unit
Test
conditions
Port
tPRW
POEG input trigger
tPOEW
R01DS0303EU0100 Rev.1.00 Page 61 of 115
Nov 3, 2016
S5D9 2. Electrical Characteristics
Figure 2.32 GPT32 input capture timing
Figure 2.33 GPT32 output delay skew
Figure 2.34 GPT32 output delay skew for OPS
Figure 2.35 GPT32 (PWM Delay Generation Circuit) output delay skew
Input capture
tGTICW
GPT32 output
PCLKD
tGTISK
Output delay
GPT32 output
PCLKD
tGTOSK
Output delay
GPT32 output
(PWM delay
generation circuit)
PCLKD
tHRSK
Output delay
R01DS0303EU0100 Rev.1.00 Page 62 of 115
Nov 3, 2016
S5D9 2. Electrical Characteristics
Figure 2.36 AGT input/output timing
Figure 2.37 ADC12 trigger input timing
Figure 2.38 Key interrupt input timing
2.3.8 PWM Delay Generation Circuit Timing
Note 1. This value normalizes the differences between lines in 1-LSB resolution.
2.3.9 CAC Timing
Table 2.20 PWM Delay Generation Circuit timing
Item Min Typ Max Unit Test conditions
Operation frequency 80 - 120 MHz -
Resolution - 260 - ps PCLKD = 120 MHz
DNL*1- ±2.0 - LSB -
Table 2.21 CAC timing
Item Symbol Min Typ Max Unit
Test
conditions
CAC CACREF input pulse width tPBcyc tcac*2tCACREF 4.5 × tcac + 3 × tPBcyc --ns-
tPBcyc > tcac*25 × tcac + 6.5 × tPBcyc --ns
tACYC2
AGTIO, AGTEE
(input)
tACYC
tACKWL tACKWH
AGTIO, AGTO,
AGTOA, AGTOB
(output)
ADTRG0,
ADTRG1
tTRGW
KR00 to KR07
tKR
R01DS0303EU0100 Rev.1.00 Page 63 of 115
Nov 3, 2016
S5D9 2. Electrical Characteristics
Note 1. tPBcyc: PCLKB cycle.
Note 2. tcac: CAC count clock source cycle.
2.3.10 SCI Timing
Note 1. tPcyc: PCLKA cycle.
Figure 2.39 SCK clock input/output timing
Table 2.22 SCI timing (1)
Conditions: High drive output is selected in the port drive capability bit in the PmnPFS register for the following pins: SCK0 to SCK9.
For other pins, middle drive output is selected in the port drive capability bit in the PmnPFS register.
Item Symbol Min Max Unit*1
Test
conditions
SCI Input clock cycle Asynchronous tScyc 4 - tPcyc Figure 2.39
Clock
synchronous
6-
Input clock pulse width tSCKW 0.4 0.6 tScyc
Input clock rise time tSCKr -5ns
Input clock fall time tSCKf -5ns
Output clock cycle Asynchronous tScyc 6-t
Pcyc
Clock
synchronous
4-
Output clock pulse width tSCKW 0.4 0.6 tScyc
Output clock rise time tSCKr -5ns
Output clock fall time tSCKf -5ns
Transmit data delay Clock
synchronous
tTXD -25nsFigure 2.40
Receive data setup time Clock
synchronous
tRXS 15 - ns
Receive data hold time Clock
synchronous
tRXH 5-ns
tSCKW tSCKr tSCKf
tScyc
SCKn
(n = 0 to 9)
R01DS0303EU0100 Rev.1.00 Page 64 of 115
Nov 3, 2016
S5D9 2. Electrical Characteristics
Figure 2.40 SCI input/output timing in clock synchronous mode
Table 2.23 SCI timing (2)
Conditions: High drive output is selected in the port drive capability bit in the PmnPFS register for the following pins: SCK0 to SCK9.
For other pins, middle drive output is selected in the port drive capability bit in the PmnPFS register.
Item Symbol Min Max Unit
Test
conditions
Simple
SPI
SCK clock cycle output
(master)
tSPcyc 4 (PCLKA 60 MHz)
8 (PCLKA > 60 MHz)
65536 tPcyc Figure 2.41
SCK clock cycle input (slave) - 6 (PCLKA 60 MHz)
12 (PCLKA > 60 MHz)
65536
SCK clock high pulse width tSPCKWH 0.4 0.6 tSPcyc
SCK clock low pulse width tSPCKWL 0.4 0.6 tSPcyc
SCK clock rise and fall time tSPCKr, tSPCKf -20ns
Data input setup time tSU 33.3 - ns Figure 2.42 to
Figure 2.45
Data input hold time tH33.3 - ns
SS input setup time tLEAD 1- t
SPcyc
SS input hold time tLAG 1- t
SPcyc
Data output delay tOD - 33.3 ns
Data output hold time tOH –10 - ns
Data rise and fall time tDr, tDf - 16.6 ns
SS input rise and fall time tSSLr, tSSLf - 16.6 ns
Slave access time tSA - 4 (PCLKA 60 MHz)
8 (PCLKA > 60 MHz)
tPcyc Figure 2.45
Slave output release time tREL - 5 (PCLKA 60 MHz)
10 (PCLKA > 60 MHz)
tPcyc
tTXD
tRXS tRXH
TxDn
RxDn
SCKn
n = 0 to 9
R01DS0303EU0100 Rev.1.00 Page 65 of 115
Nov 3, 2016
S5D9 2. Electrical Characteristics
Figure 2.41 SCI simple SPI mode clock timing
Figure 2.42 SCI simple SPI mode timing for master when CKPH = 1
Figure 2.43 SCI simple SPI mode timing for master when CKPH = 0
tSPCKWH
VOH VOH
VOL VOL
VOH VOH
tSPCKWL
tSPCKr tSPCKf
VOL
tSPcyc
tSPCKWH
VIH VIH
VIL VIL
VIH VIH
tSPCKWL
tSPCKr tSPCKf
VIL
tSPcyc
VOH = 0.7 × VCC, VOL = 0.3 × VCC, VIH = 0.7 × VCC, VIL = 0.3 × VCC
(n = 0 to 9)
SCKn
master select
output
SCKn
slave select input
tDr, tDf
tSU tH
tOH tOD
MSB IN DATA LSB IN MSB IN
MSB OUT DATA LSB OUT IDLE MSB OUT
SCKn
CKPOL = 0
output
SCKn
CKPOL = 1
output
MISOn
input
MOSIn
output
(n = 0 to 9)
tSU tH
tOH tOD
MSB IN DATA LSB IN MSB IN
MSB OUT DATA LSB OUT IDLE MSB OUT
SCKn
CKPOL = 1
output
SCKn
CKPOL = 0
output
MISOn
input
MOSIn
output
(n = 0 to 9)
tDr, tDf
R01DS0303EU0100 Rev.1.00 Page 66 of 115
Nov 3, 2016
S5D9 2. Electrical Characteristics
Figure 2.44 SCI simple SPI mode timing for slave when CKPH = 1
Figure 2.45 SCI simple SPI mode timing for slave when CKPH = 0
Table 2.24 SCI timing (3) (1 of 2)
Conditions: Middle drive output is selected in the port drive capability bit in the PmnPFS register.
Item Symbol Min Max Unit Test conditions
Simple IIC
(Standard mode)
SDA input rise time tSr - 1000 ns Figure 2.46
SDA input fall time tSf - 300 ns
SDA input spike pulse removal time tSP 04 × t
IICcyc ns
Data input setup time tSDAS 250 - ns
Data input hold time tSDAH 0- ns
SCL, SDA capacitive load Cb*1- 400 pF
tDr, tDf
tSU tH
tLEAD
tTD
tLAG
tSA
MSB IN DATA LSB IN MSB IN
MSB OUT DATA LSB OUT MSB IN MSB OUT
tOH tOD tREL
SSn
input
SCKn
CKPOL = 0
input
SCKn
CKPOL = 1
input
MISOn
output
MOSIn
input
(n = 0 to 9)
tDr, tDf
tSA tOH
tLEAD
tTD
tLAG
tH
LSB OUT
(Last data) DATA MSB OUT
MSB IN DATA LSB IN MSB IN
LSB OUT
tSU
tOD tREL
MSB OUT
SSn
input
SCKn
CKPOL = 1
input
SCKn
CKPOL = 0
input
MISOn
output
MOSIn
input
(n = 0 to 9)
R01DS0303EU0100 Rev.1.00 Page 67 of 115
Nov 3, 2016
S5D9 2. Electrical Characteristics
Note: tIICcyc: IIC internal reference clock (IIC) cycle, tPcyc: PCLKA cycle.
Note 1. Cb indicates the total capacity of the bus line.
Figure 2.46 SCI simple IIC mode timing
Simple IIC
(Fast mode)
SDA input rise time tSr - 300 ns Figure 2.46
SDA input fall time tSf - 300 ns
SDA input spike pulse removal time tSP 04 × t
IICcyc ns
Data input setup time tSDAS 100 - ns
Data input hold time tSDAH 0- ns
SCL, SDA capacitive load Cb*1- 400 pF
Table 2.24 SCI timing (3) (2 of 2)
Conditions: Middle drive output is selected in the port drive capability bit in the PmnPFS register.
Item Symbol Min Max Unit Test conditions
SDAn
SCLn
VIH
VIL
P*1S*1
tSf
tSr
tSDAH tSDAS
tSP
P*1
Test conditions:
VIH = VCC × 0.7, VIL = VCC × 0.3
VOL = 0.6 V, IOL = 6 mA
Sr*1
Note 1. S, P, and Sr indicate the following:
S: Start condition
P: Stop condition
Sr: Restart condition
(n = 0 to 9)
R01DS0303EU0100 Rev.1.00 Page 68 of 115
Nov 3, 2016
S5D9 2. Electrical Characteristics
2.3.11 SPI Timing
Note 1. tPcyc: PCLKA cycle.
Table 2.25 SPI timing
Conditions:
For RSPCKA and RSPCKB pins, high drive output is selected with the port drive capability bit in the PmnPFS register.
For other pins, middle drive output is selected in the port drive capability bit in the PmnPFS register.
Item Symbol Min Max Unit*1Test conditions*2
SPI RSPCK clock cycle Master tSPcyc 2 (PCLKA 60 MHz)
4 (PCLKA > 60 MHz)
4096 tPcyc Figure 2.47
C = 30 pF
Slave 4 4096
RSPCK clock high
pulse width
Master tSPCKWH (tSPcyc – tSPCKR –
tSPCKF) / 2 – 3
-ns
Slave 2 × tPcyc -
RSPCK clock low pulse
width
Master tSPCKWL (tSPcyc – tSPCKR –
tSPCKF) / 2 – 3
-ns
Slave 2 × tPcyc -
RSPCK clock rise and
fall time
Master tSPCKr,
tSPCKf
-5ns
Slave - 1 µs
Data input setup time Master tSU 4-nsFigure 2.48 to
Figure 2.53
C = 30 pF
Slave 5 -
Data input hold time Master
(PCLKA division ratio
set to 1/2)
tHF 0-ns
Master
(PCLKA division ratio
set to a value other
than 1/2)
tHtPcyc -
Slave tH20 -
SSL setup time Master tLEAD N × tSPcyc - 10*3N ×
tSPcyc +
100*3
ns
Slave 6 x tPcyc -ns
SSL hold time Master tLAG N × tSPcyc - 10 *4N ×
tSPcyc +
100*4
ns
Slave 6 x tPcyc -ns
Data output delay Master tOD -6.3ns
Slave - 20
Data output hold time Master tOH 0-ns
Slave 0 -
Successive
transmission delay
Master tTD tSPcyc + 2 × tPcyc 8 ×
tSPcyc +
2 × tPcyc
ns
Slave 6 × tPcyc
MOSI and MISO rise
and fall time
Output tDr, tDf -5ns
Input - 1 s
SSL rise and fall time Output tSSLr,
tSSLf
-5ns
Input - 1 s
Slave access time tSA -2 x t
Pcyc
+ 28
ns Figure 2.52 and
Figure 2.53
C = 30PF
Slave output release time tREL -2 x t
Pcyc
+ 28
R01DS0303EU0100 Rev.1.00 Page 69 of 115
Nov 3, 2016
S5D9 2. Electrical Characteristics
Note 2. Must use pins that have a letter (“_A”, “_B”) to indicate group membership appended to their name as groups. For the SPI
interface, the AC portion of the electrical characteristics is measured for each group.
Note 3. N is set to an integer from 1 to 8 by the SPCKD register.
Note 4. N is set to an integer from 1 to 8 by the SSLND register.
Figure 2.47 SPI clock timing
Figure 2.48 SPI timing for master when CPHA = 0
RSPCKA
master select
output
RSPCKA
slave select input
tSPCKWH
VOH VOH
VOL VOL
VOH VOH
tSPCKWL
tSPCKr tSPCKf
VOL
tSPcyc
tSPCKWH
VIH VIH
VIL VIL
VIH VIH
tSPCKWL
tSPCKr tSPCKf
VIL
tSPcyc
VOH = 0.7 × VCC, VOL = 0.3 × VCC, VIH = 0.7 × VCC, VIL = 0.3 × VCC
SPI
tDr, tDf
tSU tH
tLEAD
tTD
tLAG
tSSLr, tSSLf
tOH tOD
MSB IN DATA LSB IN MSB IN
MSB OUT DATA LSB OUT IDLE MSB OUT
SSLA0 to
SSLA3
output
RSPCKA
CPOL = 0
output
RSPCKA
CPOL = 1
output
MISOA
input
MOSIA
output
SPI
R01DS0303EU0100 Rev.1.00 Page 70 of 115
Nov 3, 2016
S5D9 2. Electrical Characteristics
Figure 2.49 SPI timing for master when CPHA = 0 and the bit rate is set to PCLKA/2
Figure 2.50 SPI timing for master when CPHA = 1
SSLA0 to
SSLA3
output
RSPCKA
CPOL = 0
output
RSPCKA
CPOL = 1
output
MISOA
input
MOSIA
output
LSB IN
tDr, tDf
tSU tHF
tLEAD
tTD
tLAG
tSSLr, tSSLf
tOH tOD
MSB IN
MSB OUT DATA LSB OUT IDLE MSB OUT
MSB IN DATA
tHF
SPI
tSU tH
tLEAD
tTD
tLAG
tSSLr, tSSLf
tOH tOD
MSB IN DATA LSB IN MSB IN
MSB OUT DATA LSB OUT IDLE MSB OUT
SSLA0 to
SSLA3
output
RSPCKA
CPOL = 0
output
RSPCKA
CPOL = 1
output
MISOA
input
MOSIA
output
SPI
tDr, tDf
R01DS0303EU0100 Rev.1.00 Page 71 of 115
Nov 3, 2016
S5D9 2. Electrical Characteristics
Figure 2.51 RSPI timing for master when CPHA = 1 and the bit rate is set to PCLKA/2
Figure 2.52 SPI timing for slave when CPHA = 0
tSU tHF
tLEAD
tTD
tLAG
tSSLr, tSSLf
tOH tOD
MSB IN DATA LSB IN MSB IN
MSB OUT DATA LSB OUT IDLE MSB OUT
SSLA0 to
SSLA3
output
RSPCKA
CPOL = 0
output
RSPCKA
CPOL = 1
output
MISOA
input
MOSIA
output
SPI
tDr, tDf
tH
tDr, tDf
tSU tH
tLEAD
tTD
tLAG
tSA
MSB IN DATA LSB IN MSB IN
MSB OUT DATA LSB OUT MSB IN MSB OUT
tOH tOD tREL
SSLA0
input
RSPCKA
CPOL = 0
input
RSPCKA
CPOL = 1
input
MISOA
output
MOSIA
input
SPI
R01DS0303EU0100 Rev.1.00 Page 72 of 115
Nov 3, 2016
S5D9 2. Electrical Characteristics
Figure 2.53 SPI timing for slave when CPHA = 1
2.3.12 QSPI Timing
Note 1. tPcyc: PCLKA cycle.
Note 2. N is set to 0 or 1 in SFMSLD.
Note 3. N is set to 0 or 1 in SFMSHD.
Figure 2.54 QSPI clock timing
Table 2.26 QSPI timing
Conditions: High drive output is selected in the port drive capability bit in the PmnPFS register.
Item Symbol Min Max Unit*1Test conditions
QSPI QSPCK clock cycle tQScyc 248t
Pcyc Figure 2.54
QSPCK clock high pulse width tQSWH tQScyc × 0.4 - ns
QSPCK clock low pulse width tQSWL tQScyc × 0.4 - ns
Data input setup time tSu 8- nsFigure 2.55
Data input hold time tIH 0- ns
QSSL setup time tLEAD (N+0.5) x
tQscyc - 5 *2
(N+0.5) x
tQscyc +100 *2
ns
QSSL hold time tLAG (N+0.5) x
tQscyc - 5 *3
(N+0.5) x
tQscyc +100 *3
ns
Data output delay tOD -4ns
Data output hold time tOH –3.3 - ns
Successive transmission delay tTD 116t
QScyc
SSLA0
input
RSPCKA
CPOL = 0
input
RSPCKA
CPOL = 1
input
MISOA
output
MOSIA
input
tDr, tDf
tSA tOH
tLEAD
tTD
tLAG
tH
LSB OUT
(Last data) DATA MSB OUT
MSB IN DATA LSB IN MSB IN
LSB OUT
tSU
tOD tREL
MSB OUT
SPI
tQScyc
QSPCLK output
tQSWH tQSWL
R01DS0303EU0100 Rev.1.00 Page 73 of 115
Nov 3, 2016
S5D9 2. Electrical Characteristics
Figure 2.55 Transmit and receive timing
2.3.13 IIC Timing
Table 2.27 IIC timing (1) (1 of 2)
(1) Conditions: Middle drive output is selected in the port drive capability bit in the PmnPFS register for the following pins: SDA0_B,
SCL0_B, SDA1_A, SCL1_A, SDA1_B, SCL1_B.
(2) The following pins do not require setting: SCL0_A, SDA0_A, SCL2, SDA2.
(3) Use pins that have a letter appended to their names, for instance “_A” or “_B”, to indicate group membership. For the IIC interface, the
AC portion of the electrical characteristics is measured for each group.
Item Symbol Min*1Max Unit
Test
conditions*3
IIC
(Standard mode,
SMBus)
ICFER.FMPE = 0
SCL input cycle time tSCL 6 (12) × tIICcyc + 1300 - ns Figure 2.56
SCL input high pulse width tSCLH 3 (6) × tIICcyc + 300 - ns
SCL input low pulse width tSCLL 3 (6) × tIICcyc + 300 - ns
SCL, SDA input rise time tSr - 1000 ns
SCL, SDA input fall time tSf - 300 ns
SCL, SDA input spike pulse removal
time
tSP 0 1 (4) × tIICcyc ns
SDA input bus free time when
wakeup function is disabled
tBUF 3 (6) × tIICcyc + 300 - ns
SDA input bus free time when
wakeup function is enabled
tBUF 3 (6) × tIICcyc + 4 × tPcyc
+ 300
-ns
START condition input hold time
when wakeup function is disabled
tSTAH tIICcyc + 300 - ns
START condition input hold time
when wakeup function is enabled
tSTAH 1 (5) × tIICcyc + tPcyc +
300
-ns
Repeated START condition input
setup time
tSTAS 1000 - ns
STOP condition input setup time tSTOS 1000 - ns
Data input setup time tSDAS tIICcyc + 50 - ns
Data input hold time tSDAH 0-ns
SCL, SDA capacitive load Cb- 400 pF
tSU tH
tLEAD
tTD
tLAG
tOH tOD
MSB IN DATA LSB IN
MSB OUT DATA LSB OUT IDLE
QSSL
output
QSPCLK
output
QIO0-3
input
QIO0-3
output
R01DS0303EU0100 Rev.1.00 Page 74 of 115
Nov 3, 2016
S5D9 2. Electrical Characteristics
Note: tIICcyc: IIC internal reference clock (IIC) cycle, tPcyc: PCLKB cycle.
Note 1. Values in parentheses apply when ICMR3.NF[1:0] is set to 11b while the digital filter is enabled with ICFER.NFE set to 1.
Note 2. Only supported for SCL0_A, SDA0_A, SCL2, and SDA2.
Note 3. Must use pins that have a letter (“_A”, “_B”) to indicate group membership appended to their name as groups. For the IIC
interface, the AC portion of the electrical characteristics is measured for each group.
IIC
(Fast mode)
SCL input cycle time tSCL 6 (12) × tIICcyc + 600 - ns Figure 2.56
SCL input high pulse width tSCLH 3 (6) × tIICcyc + 300 - ns
SCL input low pulse width tSCLL 3 (6) × tIICcyc + 300 - ns
SCL, SDA input rise time tSr 20 × (external pullup
voltage/5.5V)*2
300 ns
SCL, SDA input fall time tSf 20 × (external pullup
voltage/5.5V)*2
300 ns
SCL, SDA input spike pulse removal
time
tSP 0 1 (4) × tIICcyc ns
SDA input bus free time when
wakeup function is disabled
tBUF 3 (6) × tIICcyc + 300 - ns
SDA input bus free time when
wakeup function is enabled
tBUF 3 (6) × tIICcyc + 4 × tPcyc
+ 300
-ns
START condition input hold time
when wakeup function is disabled
tSTAH tIICcyc + 300 - ns
START condition input hold time
when wakeup function is enabled
tSTAH 1 (5) × tIICcyc + tPcyc +
300
-ns
Repeated START condition input
setup time
tSTAS 300 - ns
STOP condition input setup time tSTOS 300 - ns
Data input setup time tSDAS tIICcyc + 50 - ns
Data input hold time tSDAH 0-ns
SCL, SDA capacitive load Cb- 400 pF
Table 2.27 IIC timing (1) (2 of 2)
(1) Conditions: Middle drive output is selected in the port drive capability bit in the PmnPFS register for the following pins: SDA0_B,
SCL0_B, SDA1_A, SCL1_A, SDA1_B, SCL1_B.
(2) The following pins do not require setting: SCL0_A, SDA0_A, SCL2, SDA2.
(3) Use pins that have a letter appended to their names, for instance “_A” or “_B”, to indicate group membership. For the IIC interface, the
AC portion of the electrical characteristics is measured for each group.
Item Symbol Min*1Max Unit
Test
conditions*3
R01DS0303EU0100 Rev.1.00 Page 75 of 115
Nov 3, 2016
S5D9 2. Electrical Characteristics
Note: tIICcyc: IIC internal reference clock (IIC) cycle, tPcyc: PCLKB cycle.
Note 1. Values in parentheses apply when ICMR3.NF[1:0] is set to 11b while the digital filter is enabled with ICFER.NFE set to 1.
Note 2. Cb indicates the total capacity of the bus line.
Figure 2.56 IIC bus interface input/output timing
Table 2.28 IIC timing (2)
Setting of the SCL0_A, SDA0_A pins is not required with the port drive capability bit in the PmnPFS register.
Item Symbol Min*1,*2Max Unit
Test
conditions
IIC
(Fast-mode+)
ICFER.FMPE = 1
SCL input cycle time tSCL 6 (12) × tIICcyc + 240 - ns Figure 2.56
SCL input high pulse width tSCLH 3 (6) × tIICcyc + 120 - ns
SCL input low pulse width tSCLL 3 (6) × tIICcyc + 120 - ns
SCL, SDA input rise time tSr - 120 ns
SCL, SDA input fall time tSf - 120 ns
SCL, SDA input spike pulse removal
time
tSP 0 1 (4) × tIICcyc ns
SDA input bus free time when
wakeup function is disabled
tBUF 3 (6) × tIICcyc + 120 - ns
SDA input bus free time when
wakeup function is enabled
tBUF 3 (6) × tIICcyc + 4 × tPcyc
+ 120
-ns
Start condition input hold time when
wakeup function is disabled
tSTAH tIICcyc + 120 - ns
START condition input hold time
when wakeup function is enabled
tSTAH 1 (5) × tIICcyc + tPcyc +
120
-ns
Restart condition input setup time tSTAS 120 - ns
Stop condition input setup time tSTOS 120 - ns
Data input setup time tSDAS tIICcyc + 30 - ns
Data input hold time tSDAH 0-ns
SCL, SDA capacitive load Cb- 550 pF
SDA0 to SDA2
SCL0 to SCL2
VIH
VIL
tSTAH
tSCLH
tSCLL
P*1S*1
tSf tSr
tSCL tSDAH
tSDAS
tSTAS tSP tSTOS
P*1
tBUF
Test conditions:
VIH = VCC × 0.7, VIL = VCC × 0.3
VOL = 0.6 V, IOL = 6 mA (ICFER.FMPE = 0)
VOL = 0.4 V, IOL = 15 mA (ICFER.FMPE = 1)
Sr*1
Note 1. S, P, and Sr indicate the following:
S: Start condition
P: Stop condition
Sr: Restart condition
R01DS0303EU0100 Rev.1.00 Page 76 of 115
Nov 3, 2016
S5D9 2. Electrical Characteristics
2.3.14 SSIE Timing
Note 1. For slave-mode transmission, SSIE has a path, through which the signal input from the SSILRCK/SSIFS pin is used to
generate transmit data, and the transmit data is logically output to the SSITXD0 or SSIDATA1 pin.
Figure 2.57 SSIE clock input/output timing
Table 2.29 SSIE timing
(1) High drive output is selected with the port drive capability bit in the PmnPFS register.
(2) Use pins that have a letter appended to their names, for instance “_A” or “_B” to indicate group membership. For the SSIE interface,
the AC portion of the electrical characteristics is measured for each group.
Item Symbol
Target specification
Unit CommentsMin. Max.
SSIBCK Cycle Master tO80 - ns Figure 2.57
Slave tI80 - ns
High level/ low level Master tHC/tLC 0.35 - tO
Slave 0.35 - tI
Rising time/falling time Master tRC/tFC -0.15t
O / tI
Slave - 0.15 tO / tI
SSILRCK/SSIFS,
SSITXD0, SSIRXD0,
SSIDATA1
Input set up time Master tSR 12 - ns Figure 2.59,
Figure 2.60
Slave 12 - ns
Input hold time Master tHR 8- ns
Slave 15 - ns
Output delay time Master tDTR -10 5 ns
Slave 0 20 ns Figure 2.59,
Figure 2.60
Output delay time from
SSILRCK/SSIFS
change
Slave tDTRW -20nsFigure 2.61*1
GTIOC1A,
AUDIO_CLK
Cycle tEXcyc 20 - ns Figure 2.58
High level/ low level tEXL/
tEXH
0.4 0.6 tEXcyc
SSIBCKn
tHC
tO, tI
tLC
tRC tFC
R01DS0303EU0100 Rev.1.00 Page 77 of 115
Nov 3, 2016
S5D9 2. Electrical Characteristics
Figure 2.58 Clock input timing
Figure 2.59 SSIE data transmit and receive timing when SSICR.BCKP = 0
GTIOC1A,
AUDIO_CLK
(input)
tEXH tEXL
tEXr
tEXcyc
tEXf
1/2 VCC
tSR tHTR
tDTR
SSIBCKn
(Input or Output)
SSILRCKn/SSIFSn (input),
SSIRXD0,
SSIDATA1 (input)
SSILRCKn/SSIFSn (output),
SSITXD0,
SSIDATA1 (output)
R01DS0303EU0100 Rev.1.00 Page 78 of 115
Nov 3, 2016
S5D9 2. Electrical Characteristics
Figure 2.60 SSIE data transmit and receive timing when SSICR.BCKP = 1
Figure 2.61 SSIE data output delay after SSILRCKn/SSIFSn change
2.3.15 SD/MMC Host Interface Timing
Note 1. Must use pins that have a letter (“_A”, “_B”) to indicate group membership appended to their name as groups. For
Table 2.30 SD/MMC Host Interface signal timing
Conditions: High drive output is selected in the port drive capability bit in the PmnPFS register.
Clock duty ratio is 50%.
Item Symbol Min Max Unit Test conditions*1
SDCLK clock cycle TSDCYC 20 - ns Figure 2.62
SDCLK clock high pulse width TSDWH 6.5 - ns
SDCLK clock low pulse width TSDWL 6.5 - ns
SDCLK clock rise time TSDLH -3ns
SDCLK clock fall time TSDHL -3ns
SDCMD/SDDAT output data delay TSDODLY –6 5 ns
SDCMD/SDDAT input data setup TSDIS 4- ns
SDCMD/SDDAT input data hold TSDIH 2- ns
tSR tHTR
tDTR
SSIBCKn
(Input or Output)
SSILRCKn/SSIFSn (input),
SSIRXD0,
SSIDATA1 (input)
SSILRCKn/SSIFSn (output),
SSITXD0,
SSIDATA1 (output)
tDTRW
SSILRCKn/SSIFSn (input)
SSITXD0,
SSIDATA1 (output)
MSB bit output delay after SSILRCKn/SSIFSn change for slave
transmitter when DEL = 1, SDTA = 0 or DEL = 1, SDTA = 1, SWL[2:0] = DWL[2:0] in SSICR.
R01DS0303EU0100 Rev.1.00 Page 79 of 115
Nov 3, 2016
S5D9 2. Electrical Characteristics
the SD/MMC Host interface, the AC portion of the electrical characteristics is measured for each group.
Figure 2.62 SD/MMC Host Interface signal timing
2.3.16 ETHERC Timing
Note 1. RMII_TXD_EN, RMII_TXD1, RMII_TXD0.
Note 2. RMII_CRS_DV, RMII_RXD1, RMII_RXD0, RMII_RX_ER.
Table 2.31 ETHERC timing
Conditions: ETHERC (RMII): Middle drive output is selected in the port drive capability bit in the PmnPFS register for the following pins:
ET0_MDC, ET0_MDIO.
For other pins, high drive output is selected in the port drive capability bit in the PmnPFS register.
ETHERC (MII): Middle drive output is selected in the port drive capability bit in the PmnPFS register.
Item Symbol Min Max Unit
Test
conditions*3
ETHERC
(RMII)
REF50CK cycle time Tck 20 - ns Figure 2.63 to
Figure 2.66
REF50CK frequency, typical 50 MHz - - 50 + 100 ppm MHz
REF50CK duty - 35 65 %
REF50CK rise/fall time Tckr/ckf 0.5 3.5 ns
RMII_xxxx*1 output delay Tco 2.5 12.0 ns
RMII_xxxx*2 setup time Tsu 3- ns
RMII_xxxx*2 hold time Thd 1- ns
RMII_xxxx*1, *2 rise/fall time Tr/Tf0.5 4 ns
ET_WOL output delay tWOLd 1 23.5 ns Figure 2.67
ETHERC
(MII)
ET_TX_CLK cycle time tTc y c 40 - ns -
ET_TX_EN output delay tTENd 120nsFigure 2.68
ET_ETXD0 to ET_ETXD3 output delay tMTDd 120ns
ET_CRS setup time tCRSs 10 - ns
ET_CRS hold time tCRSh 10 - ns
ET_COL setup time tCOLs 10 - ns Figure 2.69
ET_COL hold time tCOLh 10 - ns
ET_RX_CLK cycle time tTRcyc 40 - ns -
ET_RX_DV setup time tRDVs 10 - ns Figure 2.70
ET_RX_DV hold time tRDVh 10 - ns
ET_ERXD0 to ET_ERXD3 setup time tMRDs 10 - ns
ET_ERXD0 to ET_ERXD3 hold time tMRDh 10 - ns
ET_RX_ER setup time tRERs 10 - ns Figure 2.71
ET_RX_ER hold time tRESh 10 - ns
ET_WOL output delay tWOLd 1 23.5 ns Figure 2.72
SDCLK
(output)
SDCMD/SDDAT
(input)
SDCMD/SDDAT
(output)
TSDODLY(max)
TSDIS TSDIH
TSDLH
TSDHL
TSDCYC
TSDWH
TSDWL
TSDODLY(min)
R01DS0303EU0100 Rev.1.00 Page 80 of 115
Nov 3, 2016
S5D9 2. Electrical Characteristics
Note 3. The following pins, must use pins that have a letter (“_A”, “_B”) to indicate group membership appended to their name as
groups. For the ETHERC (RMII) Host interface, the AC portion of the electrical characteristics is measured for each group.
REF50CK0_A, REF50CF0_B, RMII0_xxxx_A, RMII0_xxxx_B
Figure 2.63 REF50CK and RMII signal timing
Figure 2.64 RMII transmission timing
Figure 2.65 RMII reception timing in normal operation
Note 1. RMII_TXD_EN, RMII_TXD1, RMII_TXD0, RMII_CRS_DV, RMII_RXD1, RMII_RXD0,
RMII_RX_ER
Change in
signal level Signal
ThdTsuTco
TfTr
Tckr
Tckf
Tck
Signal
90%
50%
10%
90%
50%
REF50CK
RMII_xxxx*1
10%
Change
in signal
level
Change
in signal
level
Preamble SFD DATA CRC
TCO
TCO
TCK
REF50CK
RMII_TXD_EN
RMII_TXD1,
RMII_TXD0
Preamble DATA CRC
SFD
Tsu
Tsu
Thd
Thd
L
REF50CK
RMII_CRS_DV
RMII_RXD1,
RMII_RXD0
RMII_RX_ER
R01DS0303EU0100 Rev.1.00 Page 81 of 115
Nov 3, 2016
S5D9 2. Electrical Characteristics
Figure 2.66 RMII reception timing when an error occurs
Figure 2.67 WOL output timing for RMII
Figure 2.68 MII transmission timing in normal operation
Preamble DATA
REF50CK
RMII_CRS_DV
RMII_RXD1,
RMII_RXD0 SFD xxxx
RMII_RX_ER
Tsu
Thd
tWOLd
REF50CK
ET_WOL
ET_TX_CLK
ET_TX_EN
ET_ETXD[3:0]
ET_TX_ER
ET_CRS
ET_COL
SFD DATA CRCPreamble
tTENd
tMTDd
tCRSs tCRSh
R01DS0303EU0100 Rev.1.00 Page 82 of 115
Nov 3, 2016
S5D9 2. Electrical Characteristics
Figure 2.69 MII transmission timing when a conflict occurs
Figure 2.70 MII reception timing in normal operation
Figure 2.71 MII reception timing when an error occurs
Figure 2.72 WOL output timing for MII
ET_TX_CLK
ET_TX_EN
ET_ETXD[3:0]
ET_TX_ER
ET_CRS
ET_COL
JAMPreamble
tCOLs tCOLh
Preamble DATA CRCSFD
tRDVs
tMRDs
tMRDh
tRDVh
ET_RX_CLK
ET_RX_DV
ET_ERXD[3:0]
ET_RX_ER
Preamble DATASFD
tRERs
ET_RX_CLK
ET_RX_DV
ET_ERXD[3:0]
ET_RX_ER
xxxx
tRERh
tWOLd
ET_RX_CLK
ET_WOL
R01DS0303EU0100 Rev.1.00 Page 83 of 115
Nov 3, 2016
S5D9 2. Electrical Characteristics
2.3.17 PDC Timing
Note 1. tPBcyc: PCLKB cycle.
Figure 2.73 PDC input clock timing
Figure 2.74 PDC output clock timing
Table 2.32 PDC timing
Conditions: Middle drive output is selected in the port drive capability bit in the PmnPFS register.
Output load conditions: VOH = VCC × 0.5, VOL = VCC × 0.5, C = 30 pF
Item Symbol Min Max Unit
Test
conditions
PDC PIXCLK input cycle time tPIXcyc 37 - ns Figure 2.73
PIXCLK input high pulse width tPIXH 10 - ns
PIXCLK input low pulse width tPIXL 10 - ns
PIXCLK rise time tPIXr -5ns
PIXCLK fall time tPIXf -5ns
PCKO output cycle time tPCKcyc 2 × tPBcyc -nsFigure 2.74
PCKO output high pulse width tPCKH (tPCKcyc – tPCKr – tPCKf)/2 – 3 - ns
PCKO output low pulse width tPCKL (tPCKcyc – tPCKr – tPCKf)/2 – 3 - ns
PCKO rise time tPCKr -5ns
PCKO fall time tPCKf -5ns
VSYNV/HSYNC input setup time tSYNCS 10 - ns Figure 2.75
VSYNV/HSYNC input hold time tSYNCH 5-ns
PIXD input setup time tPIXDS 10 - ns
PIXD input hold time tPIXDH 5-ns
tPIXcyc
tPIXH tPIXf
tPIXL
tPIXr
PIXCLK input
tPCKcyc
tPCKH tPCKf
tPCKL
tPCKr
PCKO pin output
R01DS0303EU0100 Rev.1.00 Page 84 of 115
Nov 3, 2016
S5D9 2. Electrical Characteristics
Figure 2.75 PDC AC timing
2.3.18 GLCDC Timing
Note 1. Parallel RGB888, 666,565: Maximum 54 MHz
Serial RGB888: Maximum 60 MHz (4x speed)
Note 2. Use pins that have a letter appended to their names, for instance, “_A” or “_B”, to indicate
Note 3. Pins of group “_A” and “_B” combinations are used.
Figure 2.76 LCD_EXTCLK clock input timing
Table 2.33 GLCDC timing
Conditions:
LCD_CLK: High drive output is selected in the port drive capability bit in the PmnPFS register.
LCD_DATA: Middle drive output is selected in the port drive capability bit in the PmnPFS register.
Item Symbol Min Typ Max Unit Test conditions
LCD_EXTCLK input clock frequency tEcyc - - 60*1MHz Figure 2.76
LCD_EXTCLK input clock low pulse width tWL 0.45 - 0.55 tEcyc
LCD_EXTCLK input clock high pulse width tWH 0.45 - 0.55
LCD_CLK output clock frequency tLcyc - - 60*1MHz Figure 2.77
LCD_CLK output clock low pulse width tLOL 0.4 - 0.6 tLcyc Figure 2.77
LCD_CLK output clock high pulse width tLOH 0.4 - 0.6 tLcyc Figure 2.77
LCD data output delay timing _A or _B combinations*2tDD –3.5 - 4 ns Figure 2.78
_A and _B combinations*3–5.0 - 5.5
PIXCLK
VSYNC
HSYNC
PIXD7 to PIXD0
tSYNCS
tSYNCS
tPIXDS tPIXDH
tSYNCH
tSYNCH
1/2 Vcc VIH VIH
VIL VIL
tDcyc, tEcyc
tWH tWL
LCD_EXTCLK
R01DS0303EU0100 Rev.1.00 Page 85 of 115
Nov 3, 2016
S5D9 2. Electrical Characteristics
Figure 2.77 LCD_CLK clock output timing
Figure 2.78 Display output timing
2.4 USB Characteristics
2.4.1 USBHS Timing
Table 2.34 USBHS low-speed characteristics for host only (USBHS_DP and USBHS_DM pin characteristics)
Conditions: USBHS_RREF = 2.2 k ± 1%, USBMCLK = 12/20/24 MHz, UCLK = 48 MHz
Item Symbol Min Typ Max Unit Test conditions
Input
characteristics
Input high voltage VIH 2.0 - - V - -
Input low voltage VIL --0.8V- -
Differential input sensitivity VDI 0.2 - - V | USBHS_DP -
USBHS_DM |
-
Differential common-mode
range
VCM 0.8 - 2.5 V - -
Output
characteristics
Output high voltage VOH 2.8 - 3.6 V IOH = –200 A-
Output low voltage VOL 0.0 - 0.3 V IOL= 2 mA -
Cross-over voltage VCRS 1.3 - 2.0 V - Figure 2.79,
Figure 2.80
Rise time tLR 75 - 300 ns -
Fall time tLF 75 - 300 ns -
Rise/fall time ratio tLR / tLF 80 - 125 % tLR / tLF -
Pull-up,
Pull-down
characteristics
USBHS_DP and USBHS_DM
pull-down resistors (Host)
Rpd 14.25 - 24.80 k-
tLcyc
tLOL tLOH
tLOF tLOR
LCD_CLK
LCD_CLK
tDD
tDD
LCD_DATA23 to
LCD_DATA00,
LCD_TCON3 to
LCD_TCON0
Output on
falling edge
Output on
rising edge
R01DS0303EU0100 Rev.1.00 Page 86 of 115
Nov 3, 2016
S5D9 2. Electrical Characteristics
Figure 2.79 USBHS_DP and USBHS_DM output timing in low-speed mode
Figure 2.80 Test circuit in low-speed mode
Table 2.35 USBHS full-speed characteristics (USBHS_DP and USBHS_DM pin characteristics)
Conditions: USBHS_RREF = 2.2 k ± 1%, USBMCLK = 12/20/24 MHz, UCLK = 48 MHz
Item Symbol Min Typ Max Unit Test conditions
Input
characteristics
Input high voltage VIH 2.0 - - V - -
Input low voltage VIL --0.8V- -
Differential input sensitivity VDI 0.2 - - V | USBHS_DP -
USBHS_DM |
-
Differential common-mode
range
VCM 0.8 - 2.5 V - -
Output
characteristics
Output high voltage VOH 2.8 - 3.6 V IOH = –200 A-
Output low voltage VOL 0.0 - 0.3 V IOL= 2 mA -
Cross-over voltage VCRS 1.3 - 2.0 V - Figure 2.81,
Figure 2.82
Rise time tLR 4 - 20 ns -
Fall time tLF 4 - 20 ns -
Rise/fall time ratio tLR / tLF 90 - 111.11 % tFR / tFF -
Output resistance ZDRV 40.5 - 49.5 Rs Not used
(PHYSET.REPSEL[1:0] = 01b
and PHYSET. HSEB = 0)
DC
characteristics
USBHS_DM pull-up resistor
(device)
Rpu 0.900 - 1.575 kDuring idle state
1.425 - 3.090 kDuring transmission and
reception
USBHS_DP/USBHS_DM
pull-down resistor (host)
Rpd 14.25 - 24.80 k-
USBHS_DP,
USBHS_DM
tf
tr
90%
10%10%
90%
VCRS
Observation
point
200 pF to
600 pF
USBHS_DP
USBHS_DM
200 pF to
600 pF
1.5 K
3.6 V
R01DS0303EU0100 Rev.1.00 Page 87 of 115
Nov 3, 2016
S5D9 2. Electrical Characteristics
Figure 2.81 USBHS_DP and USBHS_DM output timing in full-speed mode
Figure 2.82 Test circuit in full-speed mode
Figure 2.83 USBHS_DP and USBHS_DM squelch detect sensitivity in high-speed mode
Figure 2.84 USBHS_DP and USBHS_DM disconnect detect sensitivity in high-speed mode
Table 2.36 USBHS high-speed characteristics (USBHS_DP and USBHS_DM pin characteristics)
Conditions: USBHS_RREF = 2.2 k ± 1%, USBMCLK = 12/20/24 MHz
Item Symbol Min Typ Max Unit Test conditions
Input
characteristics
Squelch detect sensitivity VHSSQ 100 - 150 mV Figure 2.83
Disconnect detect sensitivity VHSDSC 525 - 625 mV Figure 2.84
Common-mode voltage VHSCM –50 - 500 mV -
Output
characteristics
Idle state VHSOI –10.0 - 10 mV -
Output high voltage VHSOH 360 - 440 mV
Output low voltage VHSOL –10.0 - 10 mV
Chirp J output voltage (difference) VCHIRPJ 700 - 1100 mV
Chirp K output voltage (difference) VCHIRPK –900 - –500 mV
AC
characteristics
Rise time tHSR 500 - - ps Figure 2.85
Fall time tHSF 500 - - ps
Output resistance ZHSDRV 40.5 - 49.5 -
USBHS_DP,
USBHS_DM
tFF
tFR
90%
10%10%
90%
VCRS
Observation
point
50 pF
50 pF
USBHS_DP
USBHS_DM
USBHS_DP,
USBHS_DM VHSSQ
USBHS_DP,
USBHS_DM
VHSDSC
R01DS0303EU0100 Rev.1.00 Page 88 of 115
Nov 3, 2016
S5D9 2. Electrical Characteristics
Figure 2.85 USBHS_DP and USBHS_DM output timing in high-speed mode
Figure 2.86 Test circuit in high-speed mode
2.4.2 USBFS Timing
Table 2.37 USBHS high-speed characteristics (USBHS_DP and USBHS_DM pin characteristics)
Conditions: USBHS_RREF = 2.2 k ± 1%, USBMCLK = 12/20/24 MHz
Item Symbol Min Max Unit Test conditions
Battery Charging
Specification
D+ sink current IDP_SINK 25 175 A-
D– sink current IDM_SINK 25 175 A-
DCD source current IDP_SRC 713A-
Data detection voltage VDAT_REF 0.25 0.4 V -
D+ source voltage VDP_SRC 0.5 0.7 V Output current = 250 A
D– source voltage VDM_SRC 0.5 0.7 V Output current = 250 A
Table 2.38 USBFS low-speed characteristics for host only (USB_DP and USB_DM pin characteristics) (1 of 2)
Conditions: VCC = AVCC0 = VCC_USB = VBATT = 3.0 to 3.6V, 2.7 VREFH0/VREFH AVCC0, VCC_USBHS = AVCC_USBHS = 3.0
to 3.6 V, UCLK = 48 MHz
Item Symbol Min Typ Max Unit Test conditions
Input
characteristics
Input high voltage VIH 2.0 - - V -
Input low voltage VIL --0.8V-
Differential input sensitivity VDI 0.2 - - V | USB_DP - USB_DM |
Differential common-mode
range
VCM 0.8 - 2.5 V -
Output
characteristics
Output high voltage VOH 2.8 - 3.6 V IOH = –200 A
Output low voltage VOL 0.0 - 0.3 V IOL= 2 mA
Cross-over voltage VCRS 1.3 - 2.0 V Figure 2.87
Rise time tLR 75 - 300 ns
Fall time tLF 75 - 300 ns
Rise/fall time ratio tLR / tLF 80 - 125 % tLR/ tLF
USBHS_DP,
USBHS_DM
tHSF
tHSR
90%
10%10%
90%
Observation
point
USBHS_DP
USBHS_DM
45
45
R01DS0303EU0100 Rev.1.00 Page 89 of 115
Nov 3, 2016
S5D9 2. Electrical Characteristics
Figure 2.87 USB_DP and USB_DM output timing in low-speed mode
Figure 2.88 Test circuit in low-speed mode
Pull-up and pull-
down
characteristics
USB_DP and USB_DM pull-
down resistance in host
controller mode
Rpd 14.25 - 24.80 k-
Table 2.39 USBFS full-speed characteristics (USB_DP and USB_DM pin characteristics)
Conditions: VCC = AVCC0 = VCC_USB = VBATT = 3.0 to 3.6 V, 2.7 VREFH0/VREFH AVCC0, VCC_USBHS = AVCC_USBHS = 3.0
to 3.6 V, UCLK = 48 MHz
Item Symbol Min Typ Max Unit Test conditions
Input
characteristics
Input high voltage VIH 2.0 - - V -
Input low voltage VIL --0.8V-
Differential input sensitivity VDI 0.2 - - V | USB_DP - USB_DM |
Differential common-mode
range
VCM 0.8 - 2.5 V -
Output
characteristics
Output high voltage VOH 2.8 - 3.6 V IOH = –200 A
Output low voltage VOL 0.0 - 0.3 V IOL= 2 mA
Cross-over voltage VCRS 1.3 - 2.0 V Figure 2.89
Rise time tLR 4 - 20 ns
Fall time tLF 4 - 20 ns
Rise/fall time ratio tLR / tLF 90 - 111.11 % tFR/ tFF
Output resistance ZDRV 28 - 44 USBFS: Rs = 27 included
Pull-up and pull-
down
characteristics
DM pull-up resistance in
device controller mode
Rpu 0.900 - 1.575 kDuring idle state
1.425 - 3.090 kDuring transmission and
reception
USB_DP and USB_DM pull-
down resistance in host
controller mode
Rpd 14.25 - 24.80 k-
Table 2.38 USBFS low-speed characteristics for host only (USB_DP and USB_DM pin characteristics) (2 of 2)
Conditions: VCC = AVCC0 = VCC_USB = VBATT = 3.0 to 3.6V, 2.7 VREFH0/VREFH AVCC0, VCC_USBHS = AVCC_USBHS = 3.0
to 3.6 V, UCLK = 48 MHz
Item Symbol Min Typ Max Unit Test conditions
USB_DP,
USB_DM
tLF
tLR
90%
10%10%
90%
VCRS
Observation
point
200 pF to
600 pF
USB_DP
USB_DM
200 pF to
600 pF
1.5 K
3.6 V
27
R01DS0303EU0100 Rev.1.00 Page 90 of 115
Nov 3, 2016
S5D9 2. Electrical Characteristics
Figure 2.89 USB_DP and USB_DM output timing in full-speed mode
Figure 2.90 Test circuit in full-speed mode
2.5 ADC12 Characteristics
[Normal-precision channel]
Table 2.40 A/D conversion characteristics for unit 0 (1 of 2)
Conditions: PCLKC = 1 to 60 MHz
Item Min Typ Max Unit Test conditions
Frequency 1 - 60 MHz -
Analog input capacitance - - 30 pF -
Quantization error - ±0.5 - LSB -
Resolution - - 12 Bits -
Channel-dedicated
sample-and-hold
circuits in use
(AN000 to AN002)
Conversion time*1
(operation at
PCLKC = 60 MHz)
Permissible signal
source impedance
Max. = 1 k
1.06
(0.4 + 0.25)*2
--sSampling of channel-
dedicated sample-and-hold
circuits in 24 states
Sampling in 15 states
Offset error - ±1.5 ±3.5 LSB AN000 to AN002 = 0.25 V
Full-scale error - ±1.5 ±3.5 LSB AN000 to AN002 =
VREFH0- 0.25 V
Absolute accuracy - ±2.5 ±5.5 LSB -
DNL differential nonlinearity error - ±1.0 ±2.0 LSB -
INL integral nonlinearity error - ±1.5 ±3.0 LSB -
Holding characteristics of sample-and hold
circuits
--20s-
Dynamic range 0.25 - VREFH
0 – 0.25
V-
Channel-dedicated
sample-and-hold
circuits not in use
(AN000 to AN002)
Conversion time*1
(operation at
PCLKC = 60 MHz)
Permissible signal
source impedance
Max. = 1 k
0.48 (0.267)*2--s Sampling in 16 states
Offset error - ±1.0 ±2.5 LSB -
Full-scale error - ±1.0 ±2.5 LSB -
Absolute accuracy - ±2.0 ±4.5 LSB -
DNL differential nonlinearity error - ±0.5 ±1.5 LSB -
INL integral nonlinearity error - ±1.0 ±2.5 LSB -
USB_DP,
USB_DM
tFF
tFR
90%
10%10%
90%
VCRS
Observation
point
50 pF
50 pF
USB_DP
USB_DM
27
R01DS0303EU0100 Rev.1.00 Page 91 of 115
Nov 3, 2016
S5D9 2. Electrical Characteristics
Note: These specification values apply when there is no access to the external bus during A/D conversion. If access occurs during
A/D conversion, values might not fall within the indicated ranges.
The use of pins AN000 to AN007 as digital outputs is not allowed when the 12-Bit A/D converter is used.
The characteristics apply when AVCC0, AVSS0, VREFH0/VREFH, VREFL0, VREFL, and 12-bit A/D converter input voltage is
stable.
Note 1. The conversion time includes the sampling and comparison times. The number of sampling states is indicated for the test
conditions.
Note 2. Values in parentheses indicate the sampling time.
High-precision
channels
(AN003 to AN007)
Conversion time*1
(operation at
PCLKC = 60 MHz)
Permissible signal
source impedance
Max. = 1 k
0.48 (0.267)*2--s Sampling in 16 states
Max. = 400 0.40 (0.183)*2--s Sampling in 11 states
VCC = AVCC0 = 3.0 to 3.6 V
3.0 V VREFH0 AVCC0
Offset error - ±1.0 ±2.5 LSB -
Full-scale error - ±1.0 ±2.5 LSB -
Absolute accuracy - ±2.0 ±4.5 LSB -
DNL differential nonlinearity error - ±0.5 ±1.5 LSB -
INL integral nonlinearity error - ±1.0 ±2.5 LSB -
Normal-precision
channels
(AN016 to AN020)
Conversion time*1
(Operation at
PCLKC = 60 MHz)
Permissible signal
source impedance
Max. = 1 k
0.88 (0.667)*2--s Sampling in 40 states
Offset error - ±1.0 ±5.5 LSB -
Full-scale error - ±1.0 ±5.5 LSB -
Absolute accuracy - ±2.0 ±7.5 LSB -
DNL differential nonlinearity error - ±0.5 ±4.5 LSB -
INL integral nonlinearity error - ±1.0 ±5.5 LSB -
Table 2.41 A/D conversion characteristics for unit 1 (1 of 2)
Conditions: PCLKC = 1 to 60 MHz
Item Min Typ Max Unit Test conditions
Frequency 1 - 60 MHz -
Analog input capacitance - - 30 pF -
Quantization error - ±0.5 - LSB -
Resolution - - 12 Bits -
Channel-dedicated
sample-and-hold
circuits in use
(AN100 to AN102)
Conversion time*1
(operation at
PCLKC = 60 MHz)
Permissible signal
source impedance
Max. = 1 k
1.06
(0.4 + 0.25)*2
--sSampling of channel-
dedicated sample-and-hold
circuits in 24 states
Sampling in 15 states
Offset error - ±1.5 ±3.5 LSB AN100 to AN102 = 0.25 V
Full-scale error - ±1.5 ±3.5 LSB AN100 to AN102 =
VREFH - 0.25 V
Absolute accuracy - ±2.5 ±5.5 LSB -
DNL differential nonlinearity error - ±1.0 ±2.0 LSB -
INL integral nonlinearity error - ±1.5 ±3.0 LSB -
Holding characteristics of sample-and hold
circuits
--20s-
Dynamic range 0.25 - VREFH -
0.25
V-
Table 2.40 A/D conversion characteristics for unit 0 (2 of 2)
Conditions: PCLKC = 1 to 60 MHz
Item Min Typ Max Unit Test conditions
R01DS0303EU0100 Rev.1.00 Page 92 of 115
Nov 3, 2016
S5D9 2. Electrical Characteristics
Note: These specification values apply when there is no access to the external bus during A/D conversion. If access occurs during
A/D conversion, values might not fall within the indicated ranges.
The use of pins AN100 to AN103, AN105 to AN107 as digital outputs is not allowed when the 12-Bit A/D converter is used.
The characteristics apply when AVCC0, AVSS0, VREFH0/VREFH, VREFL0, VREFL, and 12-bit A/D converter input voltage is
stable.
Note 1. The conversion time includes the sampling and comparison times. The number of sampling states is indicated for the test
conditions.
Note 2. Values in parentheses indicate the sampling time.
Channel-dedicated
sample-and-hold
circuits not in use
(AN100 to AN102)
Conversion time*1
(Operation at
PCLKC = 60 MHz)
Permissible signal
source impedance
Max. = 1 k
0.48
(0.267)*2
--s Sampling in 16 states
Offset error - ±1.0 ±2.5 LSB -
Full-scale error - ±1.0 ±2.5 LSB -
Absolute accuracy - ±2.0 ±4.5 LSB -
DNL differential nonlinearity error - ±0.5 ±1.5 LSB -
INL integral nonlinearity error - ±1.0 ±2.5 LSB -
High-precision
channels
(AN103, AN105 to
AN107)
Conversion time*1
(Operation at
PCLKC = 60 MHz)
Permissible signal
source impedance
Max. = 1 k
0.48
(0.267)*2
--s Sampling in 16 states
Max. = 400 0.40
(0.183)*2
--s Sampling in 11 states
VCC = AVCC0 = 3.0 to 3.6 V
3.0 V VREFH AVCC0
Offset error - ±1.0 ±2.5 LSB -
Full-scale error - ±1.0 ±2.5 LSB -
Absolute accuracy - ±2.0 ±4.5 LSB -
DNL differential nonlinearity error - ±0.5 ±1.5 LSB -
INL integral nonlinearity error - ±1.0 ±2.5 LSB -
Normal-precision
channels
(AN116 to AN119)
Conversion time*1
(Operation at
PCLKC = 60 MHz)
Permissible signal
source impedance
Max. = 1 k
0.88
(0.667)*2
--s Sampling in 40 states
Offset error - ±1.0 ±5.5 LSB -
Full-scale error - ±1.0 ±5.5 LSB -
Absolute accuracy - ±2.0 ±7.5 LSB -
DNL differential nonlinearity error - ±0.5 ±4.5 LSB -
INL integral nonlinearity error - ±1.0 ±5.5 LSB -
Table 2.42 A/D conversion characteristics for simultaneous using of channel-dedicated sample-and-hold
circuits in unit0 and unit1
Conditions: PCLKC = 30/60 MHz
Item Min Typ Max Test conditions
Channel-dedicated sample-and-hold circuits in use
with continious sampling function enabled
(AN000 to AN002)
Offset error -±1.5 ±5.0 PCLKC = 60 MHz
Sampling in 15 states
Full-scale error -±2.5 ±5.0
Absolute accuracy -±4.0 ±8.0
Channel-dedicated sample-and-hold circuits in use
with continious sampling function enabled
(AN100 to AN102)
Offset error -±1.5 ±5.0
Full-scale error -±2.5 ±5.0
Absolute accuracy -±4.0 ±8.0
Channel-dedicated sample-and-hold circuits in use
with continious sampling function enabled
(AN000 to AN002)
Offset error -±1.5 ±3.5 PCLKC = 30 MHz
Sampling in 7 states
Full-scale error -±1.5 ±3.5
Absolute accuracy -±3.0 ±5.5
Channel-dedicated sample-and-hold circuits in use
with continious sampling function enabled
(AN100 to AN102)
Offset error -±1.5 ±3.5
Full-scale error -±1.5 ±3.5
Absolute accuracy -±3.0 ±5.5
Table 2.41 A/D conversion characteristics for unit 1 (2 of 2)
Conditions: PCLKC = 1 to 60 MHz
Item Min Typ Max Unit Test conditions
R01DS0303EU0100 Rev.1.00 Page 93 of 115
Nov 3, 2016
S5D9 2. Electrical Characteristics
Note: When simultaneously using channel-dedicated sample-and-hold circuits in unit0 and unit1, setting the ADSHMSR.SHMD bit to
1 is recommended.
Figure 2.91 Illustration of ADC12 characteristic terms
Absolute accuracy
Absolute accuracy is the difference between output code based on the theoretical A/D conversion characteristics, and the
actual A/D conversion result. When measuring absolute accuracy, the voltage at the midpoint of the width of the analog
input voltage (1-LSB width), which can meet the expectation of outputting an equal code based on the theoretical A/D
conversion characteristics, is used as an analog input voltage. For example, if 12-bit resolution is used and the reference
voltage VREFH0 = 3.072 V, then 1-LSB width becomes 0.75 mV, and 0 mV, 0.75 mV, and 1.5 mV are used as the analog
input voltages. If the analog input voltage is 6 mV, an absolute accuracy of ±5 LSB means that the actual A/D conversion
result is in the range of 003h to 00Dh, though an output code of 008h can be expected from the theoretical A/D
conversion characteristics.
Integral nonlinearity error (INL)
Integral nonlinearity error is the maximum deviation between the ideal line when the measured offset and full-scale
errors are zeroed, and the actual output code.
Differential nonlinearity error (DNL)
Differential nonlinearity error is the difference between the 1-LSB width based on the ideal A/D conversion
characteristics and the width of the actual output code.
Table 2.43 A/D internal reference voltage characteristics
Item Min Typ Max Unit Test conditions
A/D internal reference voltage 1.13 1.18 1.23 V -
Sampling time 4.15 - - s-
Integral nonlinearity
error (INL)
Actual A/D conversion
characteristic
Ideal A/D conversion
characteristic
Analog input voltage
Offset error
Absolute accuracy
Differential nonlinearity error (DNL)
Full-scale error
FFFh
000h
0
Ideal line of actual A/D
conversion characteristic
1-LSB width for ideal A/D
conversion characteristic
Differential nonlinearity error (DNL)
1-LSB width for ideal A/D
conversion characteristic
VREFH0
(full-scale)
A/D converter
output code
R01DS0303EU0100 Rev.1.00 Page 94 of 115
Nov 3, 2016
S5D9 2. Electrical Characteristics
Offset error
Offset error is the difference between the transition point of the ideal first output code and the actual first output code.
Full-scale error
Full-scale error is the difference between the transition point of the ideal last output code and the actual last output code.
2.6 DAC12 Characteristics
2.7 TSN Characteristics
2.8 OSC Stop Detect Characteristics
Table 2.44 D/A conversion characteristics
Item Min Typ Max Unit Test conditions
Resolution - - 12 Bits -
Without output amplifier
Absolute accuracy - - ±24 LSB Resistive load 2 M
INL - ±2.0 ±8.0 LSB Resistive load 2 M
DNL - ±1.0 ±2.0 LSB -
Output impedance - 8.5 - k-
Conversion time - - 3.0 s Resistive load 2 M,
Capacitive load 20 pF
Output voltage range 0 - VREFH V -
With output amplifier
INL - ±2.0 ±4.0 LSB -
DNL - ±1.0 ±2.0 LSB -
Conversion time - - 4.0 s-
Resistive load 5 - - k-
Capacitive load - - 50 pF -
Output voltage range 0.2 - VREFH – 0.2 V -
Table 2.45 TSN characteristics
Item Symbol Min Typ Max Unit Test conditions
Relative accuracy - - ±1.0 - °C -
Temperature slope - - 4.0 - mV/°C -
Output voltage (at 25°C) - - 1.24 - V -
Temperature sensor start time tSTART --30s-
Sampling time - 4.15 - - s-
Table 2.46 Oscillation stop detection circuit characteristics
Item Symbol Min Typ Max Unit Test conditions
Detection time tdr --1msFigure 2.92
R01DS0303EU0100 Rev.1.00 Page 95 of 115
Nov 3, 2016
S5D9 2. Electrical Characteristics
Figure 2.92 Oscillation stop detection timing
2.9 POR and LVD Characteristics
Note 1. The minimum VCC down time indicates the time when VCC is below the minimum value of voltage detection levels VPOR,
Vdet1, and Vdet2 for POR and LVD.
Note 2. The low-power function is disabled and DEEPCUT[1:0] = 00b or 01b.
Note 3. The low-power function is enabled and DEEPCUT[1:0] = 11b.
Table 2.47 Power-on reset circuit and voltage detection circuit characteristics
Item Symbol Min Typ Max Unit Test conditions
Voltage detection
level
Power-on reset
(POR)
Module-stop function
disabled*2
VPOR 2.5 2.6 2.7 V Figure 2.93
Module-stop function
enabled*3
1.8 2.25 2.7
Voltage detection circuit (LVD0) Vdet0_1 2.84 2.94 3.04 Figure 2.94
Vdet0_2 2.77 2.87 2.97
Vdet0_3 2.70 2.80 2.90
Voltage detection circuit (LVD1) Vdet1_1 2.89 2.99 3.09 Figure 2.95
Vdet1_2 2.82 2.92 3.02
Vdet1_3 2.75 2.85 2.95
Voltage detection circuit (LVD2) Vdet2_1 2.89 2.99 3.09 Figure 2.96
Vdet2_2 2.82 2.92 3.02
Vdet2_3 2.75 2.85 2.95
Internal reset time Power-on reset time tPOR -4.5-msFigure 2.93
LVD0 reset time tLVD0 -0.51- Figure 2.94
LVD1 reset time tLVD1 -0.38- Figure 2.95
LVD2 reset time tLVD2 -0.38- Figure 2.96
Minimum VCC down time*1tVOFF 200 - - sFigure 2.93,
Figure 2.94
Response delay tdet - - 200 sFigure 2.93 to
Figure 2.96
LVD operation stabilization time (after LVD is enabled) td(E-A) --10sFigure 2.95,
Figure 2.96
Hysteresis width (LVD1 and LVD2) VLVH -70-mV
tdr
Main clock
OSTDSR.OSTDF
MOCO clock
ICLK
R01DS0303EU0100 Rev.1.00 Page 96 of 115
Nov 3, 2016
S5D9 2. Electrical Characteristics
Figure 2.93 Power-on reset timing
Figure 2.94 Voltage detection circuit timing (Vdet0)
Internal reset signal
(active-low)
VCC
tVOFF
tdet tPOR
tdet
tPOR
tdet
VPOR
tVOFF
tLVD0
tdet
Vdet0
VCC
Internal reset signal
(active-low)
tdet
R01DS0303EU0100 Rev.1.00 Page 97 of 115
Nov 3, 2016
S5D9 2. Electrical Characteristics
Figure 2.95 Voltage detection circuit timing (Vdet1)
Figure 2.96 Voltage detection circuit timing (Vdet2)
tVOFF
Vdet1
VCC
tdet
tdet
tLVD1
td(E-A)
LVCMPCR.LVD1E
LVD1
Comparator output
LVD1CR0.CMPE
LVD1SR.MON
Internal reset signal
(active-low)
When LVD1CR0.RN = 0
When LVD1CR0.RN = 1
VLVH
tLVD1
tVOFF
Vdet2
VCC
tdet
tdet
tLVD2
td(E-A)
VLVH
tLVD2
LVCMPCR.LVD2E
LVD2
Comparator output
LVD2CR0.CMPE
LVD2SR.MON
Internal reset signal
(active-low)
When LVD2CR0.RN = 0
When LVD2CR0.RN = 1
R01DS0303EU0100 Rev.1.00 Page 98 of 115
Nov 3, 2016
S5D9 2. Electrical Characteristics
2.10 VBATT Characteristics
Note: The VCC-off period for starting power supply switching indicates the period in which VCC is below the minimum
value of the voltage level for switching to battery backup (VDETBATT).
Figure 2.97 Battery backup function characteristics
2.11 CTSU Characteristics
2.12 ACMPHS Characteristics
Note 1. This value is the internal propagation delay.
Table 2.48 Battery backup function characteristics
Conditions: VCC = AVCC0 = VCC_USB = 2.7 to 3.6 V, 2.7 VREFH0/VREFH AVCC0, VBATT = 1.8 to 3.6 V
Item Symbol Min Typ Max Unit Test conditions
Voltage level for switching to battery backup VDETBATT 2.50 2.60 2.70 V Figure 2.97
Lower-limit VBATT voltage for power supply
switching caused by VCC voltage drop
VBATTSW 2.70 - - V
VCC-off period for starting power supply switching tVOFFBATT 200 - - s
Table 2.49 CTSU characteristics
Item Symbol Min Typ Max Unit Test conditions
External capacitance connected to TSCAP pin Ctscap 91011nF-
TS pin capacitive load Cbase --50pF-
Permissible output high current IoH - - -40 mA When the mutual
capacitance method
is applied
Table 2.50 ACMPHS characteristics
Item Symbol Min Typ Max Unit Test conditions
Reference voltage range VREF 0 - AVCC0 V -
Input voltage range VI 0 - AVCC0 V -
Output delay*1Td - 50 100 ns VI = VREF ± 100 mV
Internal reference voltage Vref 1.13 1.18 1.23 V -
VCC
tVOFFBATT
VDETBATT
VBATTSW
VBATT
VCC supplyVBATT supplyVCC supply
Backup power
area
R01DS0303EU0100 Rev.1.00 Page 99 of 115
Nov 3, 2016
S5D9 2. Electrical Characteristics
2.13 PGA Characteristics
Table 2.51 PGA characteristics in single mode
Item Symbol Min Typ Max Unit
PGAVSS input voltage range PGAVSS 0 - 0 V
AIN0 (G = 2.000) 0.050 × AVCC0 - 0.45 × AVCC0 V
AIN1 (G = 2.500) 0.047 × AVCC0 - 0.360 × AVCC0 V
AIN2 (G = 2.667) 0.046 × AVCC0 - 0.337 × AVCC0 V
AIN3 (G = 2.857) 0.046 × AVCC0 - 0.32 × AVCC0 V
AIN4 (G = 3.077) 0.045 × AVCC0 - 0.292 × AVCC0 V
AIN5 (G = 3.333) 0.044 × AVCC0 - 0.265 × AVCC0 V
AIN6 (G = 3.636) 0.042 × AVCC0 - 0.247 × AVCC0 V
AIN7 (G = 4.000) 0.040 × AVCC0 - 0.212 × AVCC0 V
AIN8 (G = 4.444) 0.036 × AVCC0 - 0.191 × AVCC0 V
AIN9 (G = 5.000) 0.033 × AVCC0 - 0.17 × AVCC0 V
AIN10 (G = 5.714) 0.031 × AVCC0 - 0.148 × AVCC0 V
AIN11 (G = 6.667) 0.029 × AVCC0 - 0.127 × AVCC0 V
AIN12 (G = 8.000) 0.027 × AVCC0 - 0.09 × AVCC0 V
AIN13 (G = 10.000) 0.025 × AVCC0 - 0.08 × AVCC0 V
AIN14 (G = 13.333) 0.023 × AVCC0 - 0.06 × AVCC0 V
Gain error Gerr0 (G = 2.000) –1.0 - 1.0 %
Gerr1 (G = 2.500) –1.0 - 1.0 %
Gerr2 (G = 2.667) –1.0 - 1.0 %
Gerr3 (G = 2.857) –1.0 - 1.0 %
Gerr4 (G = 3.077) –1.0 - 1.0 %
Gerr5 (G = 3.333) –1.5 - 1.5 %
Gerr6 (G = 3.636) –1.5 - 1.5 %
Gerr7 (G = 4.000) –1.5 - 1.5 %
Gerr8 (G = 4.444) –2.0 - 2.0 %
Gerr9 (G = 5.000) –2.0 - 2.0 %
Gerr10 (G = 5.714) –2.0 - 2.0 %
Gerr11 (G = 6.667) –2.0 - 2.0 %
Gerr12 (G = 8.000) –2.0 - 2.0 %
Gerr13 (G = 10.000) –2.0 - 2.0 %
Gerr14 (G = 13.333) –2.0 - 2.0 %
Offset error Voff –8 - 8 mV
Table 2.52 PGA characteristics in differential mode (1 of 2)
Item Symbol Min Typ Max Unit
PGAVSS input voltage range PGAVSS –0.5 - 0.3 V
Differential input
voltage range
G = 1.500 AIN-PGAVSS –0.5 - 0.5 V
G = 2.333 –0.4 - 0.4 V
G = 4.000 –0.2 - 0.2 V
G = 5.667 –0.15 - 0.15 V
R01DS0303EU0100 Rev.1.00 Page 100 of 115
Nov 3, 2016
S5D9 2. Electrical Characteristics
2.14 Flash Memory Characteristics
2.14.1 Code Flash Memory Characteristics
Note: The reprogram/erase cycle is the number of erasures for each block. When the reprogram/erase cycle is n times (n = 10,000),
erasing can be performed n times for each block. For example, when 128-byte programming is performed 64 times for different
addresses in 8-KB blocks, and then the entire block is erased, the reprogram/erase cycle is counted as one. However,
programming the same address several times as one erasure is not enabled. (Overwriting is prohibited.)
Note 1. This is the minimum number of times to guarantee all the characteristics after reprogramming. The guaranteed range is from 1
to the minimum value.
Note 2. This indicates the minimum value of the characteristic when reprogramming is performed within the specified range.
Note 3. This result is obtained from reliability testing.
Gain error G = 1.500 Gerr –1.0 - 1.0 %
G = 2.333 –1.0 - 1.0
G = 4.000 –1.0 - 1.0
G = 5.667 –1.0 - 1.0
Table 2.53 Code flash memory characteristics
Conditions: Program or erase: FCLK = 4 to 60 MHz
Read: FCLK 60 MHz
Item Symbol
FCLK = 4 MHz 20 MHz ≤ FCLK ≤ 60 MHz
Unit
Test
conditionsMin Typ Max Min Typ Max
Programming time
NPEC 100 times
128-byte tP128 - 1.1 13.2 - 0.52 6.0 ms
8-KB tP8K -75176-3480ms
32-KB tP32K - 299 704 - 136 320 ms
Programming time
NPEC > 100 times
128-byte tP128 - 1.4 15.8 - 0.62 7.2 ms
8-KB tP8K -90212-4196ms
32-KB tP32K - 359 848 - 163 384 ms
Erasure time
NPEC 100 times
8-KB tE8K - 92 216 - 51 120 ms
32-KB tE32K - 329 864 - 183 480 ms
Erasure time
NPEC > 100 times
8-KB tE8K - 110 260 - 61 144 ms
32-KB tE32K - 396 1040 - 220 576 ms
Reprogramming/erasure cycle*Note: NPEC 10000*1- - 10000*1--Times
Suspend delay during programming tSPD --264--120s
First suspend delay during erasure in
suspend priority mode
tSESD1 --216--120s
Second suspend delay during
erasure in suspend priority mode
tSESD2 --1.7--1.7ms
Suspend delay during erasure in
erasure priority mode
tSEED --1.7--1.7ms
Forced stop command tFD --32--20s
Data hold time*2tDRP 10*2, *3--10*
2, *3--Years
30*2, *3--30*
2, *3- - Ta = +85°C
Table 2.52 PGA characteristics in differential mode (2 of 2)
Item Symbol Min Typ Max Unit
R01DS0303EU0100 Rev.1.00 Page 101 of 115
Nov 3, 2016
S5D9 2. Electrical Characteristics
Figure 2.98 Suspension and forced stop timing for flash memory programming and erasure
2.14.2 Data Flash Memory Characteristics
Table 2.54 Data flash memory characteristics (1 of 2)
Conditions: Program or erase: FCLK = 4 to 60 MHz
Read: FCLK 60 MHz
Item Symbol
FCLK = 4 MHz 20 MHz ≤ FCLK ≤ 60 MHz
Unit
Test
conditionsMin Typ Max Min Typ Max
Programming time 4-byte tDP4 - 0.46 3.8 - 0.21 1.7 ms
8-byte tDP8 - 0.48 4.0 - 0.22 1.8
16-byte tDP16 - 0.53 4.5 - 0.24 2.0
Erasure time 64-byte tDE64 - 4.03 18 - 2.24 10 ms
128-byte tDE128 -6.227-3.415
256-byte tDE256 -11.650-6.428
Blank check time 4-byte tDBC4 --84--30s
Reprogramming/erasure cycle*1NDPEC 125000
*2
- - 125000
*2
---
FCU command
FSTATR0.FRDY
Programming pulse
• Suspension during programming
FCU command
FSTATR0.FRDY
Erasure pulse
• Suspension during erasure in suspend priority mode
FCU command
FSTATR0.FRDY
Erasure pulse
• Suspension during erasure in erasure priority mode
Program Suspend
Ready Not Ready Ready
Programming
tSPD
Erase Suspend
Ready Not Ready Ready
tSEED
Erasing
Erase Suspend Resume Suspend
Ready Not Ready Ready Not Ready
tSESD1 tSESD2
Erasing Erasing
tFD
• Forced Stop
FACI command
FSTATR.FRDY
Forced Stop
Not Ready Ready
R01DS0303EU0100 Rev.1.00 Page 102 of 115
Nov 3, 2016
S5D9 2. Electrical Characteristics
Note 1. The reprogram/erase cycle is the number of erasures for each block. When the reprogram/erase cycle is n times (n = 125,000),
erasing can be performed n times for each block. For example, when 4-byte programming is performed 16 times for different
addresses in 64-byte blocks, and then the entire block is erased, the reprogram/erase cycle is counted as one. However,
programming the same address several times as one erasure is not enabled. (Overwriting is prohibited.)
Note 2. This is the minimum number of times to guarantee all the characteristics after reprogramming. The guaranteed range is from 1
to the minimum value.
Note 3. This indicates the minimum value of the characteristic when reprogramming is performed within the specified range.
Note 4. This result is obtained from reliability testing.
2.15 Boundary Scan
Note 1. Boundary scan does not function until the power-on reset becomes negative.
Suspend delay during
programming
4-byte tDSPD --264--120s
8-byte - - 264 - - 120
16-byte - - 264 - - 120
First suspend delay
during erasure in
suspend priority mode
64-byte tDSESD1 --216--120s
128-byte - - 216 - - 120
256-byte - - 216 - - 120
Second suspend delay
during erasure in
suspend priority mode
64-byte tDSESD2 --300--300s
128-byte - - 390 - - 390
256-byte - - 570 - - 570
Suspend delay during
erasing in erasure
priority mode
64-byte tDSEED --300--300s
128-byte - - 390 - - 390
256-byte - - 570 - - 570
Forced stop command tFD --32--20s
Data hold time*3tDRP 10*3,*4- - 10*3,*4- - Year
30*3,*4- - 30*3,*4-- Ta = +85°C
Table 2.55 Boundary scan characteristics
Item Symbol Min Typ Max Unit
Test
conditions
TCK clock cycle time tTCKcyc 100 - - ns Figure 2.99
TCK clock high pulse width tTCKH 45 - - ns
TCK clock low pulse width tTCKL 45 - - ns
TCK clock rise time tTCKr --5ns
TCK clock fall time tTCKf --5ns
TMS setup time tTMSS 20 - - ns Figure 2.100
TMS hold time tTMSH 20 - - ns
TDI setup time tTDIS 20 - - ns
TDI hold time tTDIH 20 - - ns
TDO data delay tTDOD --40ns
Boundary scan circuit startup time*1TBSSTUP tRESWP ---Figure 2.101
Table 2.54 Data flash memory characteristics (2 of 2)
Conditions: Program or erase: FCLK = 4 to 60 MHz
Read: FCLK 60 MHz
Item Symbol
FCLK = 4 MHz 20 MHz ≤ FCLK ≤ 60 MHz
Unit
Test
conditionsMin Typ Max Min Typ Max
R01DS0303EU0100 Rev.1.00 Page 103 of 115
Nov 3, 2016
S5D9 2. Electrical Characteristics
Figure 2.99 Boundary scan TCK timing
Figure 2.100 Boundary scan input/output timing
Figure 2.101 Boundary scan circuit startup timing
2.16 Joint European Test Action Group (JTAG)
Table 2.56 JTAG
Item Symbol Min Typ Max Unit
Test
conditions
TCK clock cycle time tTCKcyc 40 - - ns Figure 2.99
TCK clock high pulse width tTCKH 15 - - ns
TCK clock low pulse width tTCKL 15 - - ns
TCK clock rise time tTCKr --5ns
TCK clock fall time tTCKf --5ns
tTCKcyc
tTCKH
tTCKf
tTCKL
tTCKr
TCK
tTMSS tTMSH
tTDIS tTDIH
tTDOD
TCK
TMS
TDI
TDO
VCC
RES
Boundary scan
execute
tBSSTUP
(= tRESWP)
R01DS0303EU0100 Rev.1.00 Page 104 of 115
Nov 3, 2016
S5D9 2. Electrical Characteristics
Figure 2.102 JTAG TCK timing
Figure 2.103 JTAG input/output timing
TMS setup time tTMSS 8- - nsFigure 2.100
TMS hold time tTMSH 8- - ns
TDI setup time tTDIS 8- - ns
TDI hold time tTDIH 8- - ns
TDO data delay time tTDOD --20ns
Table 2.56 JTAG
Item Symbol Min Typ Max Unit
Test
conditions
TCK
tTCKH
tTCKcyc
tTCKL
tTCKf
tTCKr
TCK
TMS
tTMSS tTMSH
TDI
tTDIS tTDIH
TDO
tTDOD
R01DS0303EU0100 Rev.1.00 Page 105 of 115
Nov 3, 2016
S5D9 2. Electrical Characteristics
2.17 Serial Wire Debug (SWD)
Figure 2.104 SWD SWCLK timing
Table 2.57 SWD
Item Symbol Min Typ Max Unit
Test
conditions
SWCLK clock cycle time tSWCKcyc 40 - - ns Figure 2.104
SWCLK clock high pulse width tSWCKH 15 - - ns
SWCLK clock low pulse width tSWCKL 15 - - ns
SWCLK clock rise time tSWCKr --5ns
SWCLK clock fall time tSWCKf --5ns
SWDIO setup time tSWDS 8- - nsFigure 2.105
SWDIO hold time tSWDH 8- - ns
SWDIO data delay time tSWDD 2 - 28 ns
SWCLK
tSWCKH
tSWCKcyc
tSWCKL
R01DS0303EU0100 Rev.1.00 Page 106 of 115
Nov 3, 2016
S5D9 2. Electrical Characteristics
Figure 2.105 SWD input/output timing
2.18 Embedded Trace Macro Interface (ETM)
Table 2.58 ETM
Conditions: High drive output is selected in the port drive capability bit in the PmnPFS register.
Item Symbol Min Typ Max Unit
Test
conditions
TCLK clock cycle time tTCLKcyc 33.3 - - ns Figure 2.106
TCLK clock high pulse width tTCLKH 13.6 - - ns
TCLK clock low pulse width tTCLKL 13.6 - - ns
TCLK clock rise time tTCLKr --3ns
TCLK clock fall time tTCLKf --3ns
TDATA[3:0] output setup time tTRDS 3.5 - - ns Figure 2.107
TDATA[3:0] output hold time tTRDH 2.5 - - ns
SWCLK
SWDIO
(Input)
tSWDS tSWDH
SWDIO
(Output)
tSWDD
SWDIO
(Output)
tSWDD
SWDIO
(Output)
tSWDD
R01DS0303EU0100 Rev.1.00 Page 107 of 115
Nov 3, 2016
S5D9 2. Electrical Characteristics
Figure 2.106 ETM TCLK timing
Figure 2.107 ETM output timing
TCLK
tTCLKH
tTCLKcyc
tTCLKL
tTCLKf
tTCLKr
TDATA[3:0]
TCLK
tTRDS tTRDS
tTRDH tTRDH
R01DS0303EU0100 Rev.1.00 Page 108 of 115
Nov 3, 2016
S5D9 Appendix 1. Package Dimensions
Appendix 1.Package Dimensions
For information on the latest version of the package dim ensions or mountings, go to “Packages” on the Renesas
Electronics Corporation website.
Figure 1.1 176-pin BGA
JEITA Package Code RENESAS Code Previous Code MASS (TYP.)
PLBG0176GE-A 176FHS-A 0.45 g
P-LFBGA176-13x13-0.80
e
A1
MaxNomMin
Dimension in Millimeters
Symbol
Reference
A
b
x
y
13.0
0.10
0.80
0.45 0.50 0.55
0.35 0.40 0.45
1.40
13.0
0.08
v
w
0.90
0.90
y10.2
0.20
0.15
ZE
ZD
SE
SD
E
D
1
E
D
1
A
x4
A
B
x M SAB
S
Sy
SwA SwB
v
Sy1
23456789101112131415
B
C
D
E
F
G
H
J
K
L
M
N
P
R
Ze
eZ
A
AE
D
b
R01DS0303EU0100 Rev.1.00 Page 109 of 115
Nov 3, 2016
S5D9 Appendix 1. Package Dimensions
Figure 1.2 176-pin LQFP
Figure 1.3 145-pin LGA
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
Dimension in Millimeters
Reference
Symbol Min Nom Max
bp
b1
c1
c
*2
E
HE
*1D
HD
Terminal cross section
Detail F
θ
c
L
F
M
S
S
y
e
L1
A1A2
A
x
bp
*3
Index mark
ZD
ZE
1
176
133
132 89
88
45
44
23.9 24.0 24.1
23.9 24.0
1.4
24.1
25.8 26.0 26.2
25.8 26.0 26.2
0.05 0.1
0.18
0.15
0.15 0.20 0.25
0.09 0.145
0.125
0.5
1.0
1.25
1.25
0° 8°
0.20
0.35 0.5 0.65
0.08
0.10
1.7
JEITA Package Code RENESAS Code Previous Code MASS[Typ.]
P-LFQFP176-24x24-0.50 PLQP0176KB-A 176P6Q-A/FP-176E/FP-176EV 1.8g
L1
c1
θ
b1
A1
A2
A
bp
HE
E
D
HD
ZE
ZD
L
y
x
e
c
0.5ZE
ZD0.5
0.290.250.21b
b1
y0.08
e0.5
x
A1.05
E7.0
D7.0
Reference
Symbol
Dimension in Millimeters
MinNom Max
0.29 0.340.39
0.08
w0.20
v0.15
PTLG0145KA-A145F0GP-TFLGA145-7x7-0.50 0.1g
MASS[Typ.]RENESAS CodeJEITA Package Code Previous Code
131211109
N
M
L
K
J
Index mark
(Laser mark)
x4
v
AB
A
B
S
AB
S
S
y
S
87654321
B
C
D
E
F
G
H
A
S
A
wS
wB
ZE
ZD
A
e
e
E
D
φb1M
φb
φ
φM
R01DS0303EU0100 Rev.1.00 Page 110 of 115
Nov 3, 2016
S5D9 Appendix 1. Package Dimensions
Figure 1.4 144-pin LQFP
MASS (Typ) [g]
1.2
Unit: mm
Previous CodeRENESAS Code
PLQP0144KA-B —
JEITA Package Code
P-LFQFP144-20x20-0.50
© 2016 Renesas Electronics Corporation. All rights reserved.
D
E
A
2
H
D
H
E
A
A
1
b
p
c
T
e
x
y
L
p
L
1
19.9
19.9
21.8
21.8
0.05
0.17
0.09
0q
0.45
Min Nom
Dimensions in millimeters
Reference
Symbol
Max
20.0
20.0
1.4
22.0
22.0
0.20
3.5q
0.5
0.6
1.0
20.1
20.1
22.2
22.2
1.7
0.15
0.27
0.20
8q
0.08
0.08
0.75
NOTE)
1. DIMENSIONS “*1” AND “*2” DO NOT INCLUDE MOLD FLASH.
2. DIMENSION “*3” DOES NOT INCLUDE TRIM OFFSET.
3. PIN 1 VISUAL INDEX FEATURE MAY VARY, BUT MUST BE
LOCATED WITHIN THE HATCHED AREA.
4. CHAMFERS AT CORNERS ARE OPTIONAL, SIZE MAY VARY.
HD
A2
A1
Lp
L1
Detail F
A
c
0.25
HE
D
E
108 73
72
37
109
144
136
F
NOTE 4
NOTE 3
Index area
*1
*2
*3
bp
T
eyS
S
M
R01DS0303EU0100 Rev.1.00 Page 111 of 115
Nov 3, 2016
S5D9 Appendix 1. Package Dimensions
Figure 1.5 100-pin LQFP
MASS (Typ) [g]
0.6
Unit: mm
Previous CodeRENESAS Code
PLQP0100KB-B —
JEITA Package Code
P-LFQFP100-14x14-0.50
© 2015 Renesas Electronics Corporation. All rights reserved.
D
E
A
2
H
D
H
E
A
A
1
b
p
c
T
e
x
y
L
p
L
1
13.9
13.9
15.8
15.8
0.05
0.15
0.09
0q
0.45
Min Nom
Dimensions in millimeters
Reference
Symbol Max
14.0
14.0
1.4
16.0
16.0
0.20
3.5q
0.5
0.6
1.0
14.1
14.1
16.2
16.2
1.7
0.15
0.27
0.20
8q
0.08
0.08
0.75
NOTE)
1. DIMENSIONS “*1” AND “*2” DO NOT INCLUDE MOLD FLASH.
2. DIMENSION “*3” DOES NOT INCLUDE TRIM OFFSET.
3. PIN 1 VISUAL INDEX FEATURE MAY VARY, BUT MUST BE
LOCATED WITHIN THE HATCHED AREA.
4. CHAMFERS AT CORNERS ARE OPTIONAL, SIZE MAY VARY.
T
HD
A2
A1
Lp
L1
Detail F
A
c
0.25
D
75
76
100 26
251
50
51
F
NOTE 4
NOTE 3
Index area
*1
HE
E
*2
*3bp
e
yS
S
M
S5D9 Microcontroller Datasheet
Proprietary Notice
All text, graphics, photographs, trademarks, logos, artwork and computer code, collectively known as content, contained in
this document is owned, controlled or licen sed by or to Renesas, and is protected by trade dress, copyright, patent and
trademark laws, and other intellectual property rights and unfair competition laws. Except as expressly provided herein, no
part of this document or content may be copied, reproduced, republished, posted, publicly displayed, encoded, translated,
transmitted or distributed in any other medium for publication or distribution or for any commercial enterprise, without prior
written consent from Renesas.
ARM® and Cortex® are registere d trademarks of ARM Limited. CoreSight™ is a trademark of ARM Limited.
CoreMark® is a registered trademark of the Embedded Microprocessor Benchmark Consorti um.
Magic Packet™ is a trademark of Advanced Micro Devices, Inc.
SuperFlash® is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United States
and Japan.
Other brands and n ames menti oned in this document may b e the trademarks or registered trademarks of their respective
holders.
Rev. Date Chapter Summary
1.00 Nov 3, 2016 — First Edition issued
Revision History
S5D9 Microcontroller Datasheet
Publication Date : Rev. 1.00 Nov 3, 2016
Published by: Renesas Electronics Corporation
Colophon
http://www.renesas.com
Refer to "http://www.renesas.com/" for the latest and detailed information.
Renesas Electronics America Inc.
2801 Scott Boulevard Santa Clara, CA 95050-2549, U.S.A.
Tel: +1-408-588-6000, Fax: +1-408-588-6130
Renesas Electronics Canada Limited
9251 Yonge Street, Suite 8309 Richmond Hill, Ontario Canada L4C 9T3
Tel: +1-905-237-2004
Renesas Electronics Europe Limited
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K
Tel: +44-1628-585-100, Fax: +44-1628-585-900
Renesas Electronics Europe GmbH
Arcadiastrasse 10, 40472 Düsseldorf, Germany
Tel: +49-211-6503-0, Fax: +49-211-6503-1327
Renesas Electronics (China) Co., Ltd.
Room 1709, Quantum Plaza, No.27 ZhiChunLu Haidian District, Beijing 100191, P.R.China
Tel: +86-10-8235-1155, Fax: +86-10-8235-7679
Renesas Electronics (Shanghai) Co., Ltd.
Unit 301, Tower A, Central Towers, 555 Langao Road, Putuo District, Shanghai, P. R. China 200333
Tel: +86-21-2226-0888, Fax: +86-21-2226-0999
Renesas Electronics Hong Kong Limited
Unit 1601-1611, 16/F., Tower 2, Grand Century Place, 193 Prince Edward Road West, Mongkok, Kowloon, Hong Kong
Tel: +852-2265-6688, Fax: +852 2886-9022
Renesas Electronics Taiwan Co., Ltd.
13F, No. 363, Fu Shing North Road, Taipei 10543, Taiwan
Tel: +886-2-8175-9600, Fax: +886 2-8175-9670
Renesas Electronics Singapore Pte. Ltd.
80 Bendemeer Road, Unit #06-02 Hyflux Innovation Centre, Singapore 339949
Tel: +65-6213-0200, Fax: +65-6213-0300
Renesas Electronics Malaysia Sdn.Bhd.
Unit 1207, Block B, Menara Amcorp, Amcorp Trade Centre, No. 18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia
Tel: +60-3-7955-9390, Fax: +60-3-7955-9510
Renesas Electronics India Pvt. Ltd.
No.777C, 100 Feet Road, HAL II Stage, Indiranagar, Bangalore, India
Tel: +91-80-67208700, Fax: +91-80-67208777
Renesas Electronics Korea Co., Ltd.
12F., 234 Teheran-ro, Gangnam-Gu, Seoul, 135-080, Korea
Tel: +82-2-558-3737, Fax: +82-2-558-5141
SALES OFFICES
© 2016 Renesas Electronics Corporation. All rights reserved.
Colophon 4.0
Address List
Renesas Synergy™ Platform
S5D9 Microcontroller
R01DS0303EU0100
Back cover
