October 2001
Advanced Information
Copyright © Alliance Semiconductor. All rights reserved.
®
AS7C25512PFS32A
AS7C25512PFS36A
10/3/01; v.0.9.1 Alliance Semiconductor 1 of 2
2.5V 512K × 32/36 pipeline burst synchronous SRAM
Features
• Organization: 524,288 words x 32/36 bits
• Fast clock speeds to 200MHz in LVTTL/LVCMOS
• Fast clock to data access: 3.0/3.5/4.0 ns
•Fast OE
access time: 3.0/3.5/4.0 ns
• Fully synchronous register-to-register operation
• Single register “Flow-through” mode
• Single-cycle deselect
- Dual-cycle deselect also available ( AS7C25512PFD32A/
AS7C25512PFD36A)
•Pentium®
* compatible architecture and timing
• Asynchronous output enable control
• 100-pin TQFP package
• 119-Ball BGA (7 x 17 Ball Grid Array Package)
• Byte write enables
• Multiple chip enables for easy expansion
• 2.5V core power supply
•2.5V I/O operation
•NTD™
* pipeline architecture available
(AS7C25512NTD32A/ AS7C25512NTD36A)
*Pentium
® is a registered trademark of Intel Corporation. NTD™ is a
trademark of Alliance Semiconductor Corporation. All trademarks
mentioned in this document are the property of their respective owners.
Logic Block Diagram:
Pin Arrangements:
DQPc/NC
DQc
DQc
VDDQ
VSSQ
DQc
DQc
DQc
DQc
VSSQ
VDDQ
DQc
DQc
FT
VDD
NC
VSS
DQd
DQd
VDDQ
VSSQ
DQd
DQd
DQd
DQd
VSSQ
VDDQ
DQd
DQd
DQPd/NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPb/NC
DQb
DQb
VDDQ
VSSQ
DQb
DQb
DQb
DQb
VSSQ
VDDQ
DQb
DQb
VSS
ZZ
DQa
DQa
VDDQ
VSSQ
DQa
DQa
DQa
DQa
VSSQ
VDDQ
DQa
DQa
DQPa/NC
LBO
A5
A4
A3
A2
A1
A0
NC
NC
VSS
VDD
A18
A17
A10
A11
A12
A13
A14
A15
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A6
A7
CE0
CE1
BWd
BWc
BWb
BWa
CE2
VDD
VSS
CLK
GWE
BWE
OE
ADSC
ADSP
ADV
A8
A9
NC
VDD
A16
Note: Pins 1,30,51,80 are NC for ×32
TQFP 14 × 20 mm
512K x 32A/36A
Q0
Q1 512K × 32/36
Memory
array
Burst logic
CLK
CLR
CE
Address
DQ
CE
CLK
DQd
CLK
DQ
Byte write
registers
register
DQc
CLK
DQ
Byte write
registers
DQb
CLK
DQ
Byte write
registers
DQa
CLK
DQ
Byte write
registers
Enable
CLK
DQ
register
Enable
CLK
DQ
delay
register
CE
Output
registers Input
registers
Power
down
DATA [35:0]
4
36/32
181618
19
GWE
BWE
BWd
ADV
ADSC
ADSP
CLK
CE0
CE1
CE2
BWc
BWb
BWa
OE
A[18:0]
ZZ
OE
FT
CLK CLK
36/32
DATA [31:0]
LBO
Selection guide -200 -166 -100 Units
Minimum cycle time 5 6 10 ns
Maximum clock frequency 200 166 100 MHz
Maximum pipelined clock access time 3.0 3.5 4.0 ns
Maximum operating current 280 230 150 mA
Maximum standby current 100 70 50 mA
Maximum CMOS standby current (DC) 30 30 30 mA
10/3/01; v.0.9.1 Alliance Semiconductor 2 of 2
AS7C25512PFS32A
AS7C25512PFS36A
®
© Copyright Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product
names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no
responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change
or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data
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does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of
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Pin Configuration
119 BGA Top View
1234567
AVDDQ AA
ADSP
AAV
DDQ
BNC A A
ADSC
AANC
C
FT
AAV
DD AANC
DDQC DQPc VSS NC VSS DQpb DQb
EDQC DQc VSS
CE0
VSS DQb DQb
FVDDQ DQc VSS
OE
VSS DQb VDDQ
GDQC DQc
BWc ADV BWb
DQb DQb
HDQC DQc VSS
GWE
VSS DQb DQb
JVDDQ VDD NC VDD NC VDD VDDQ
KDQd DQd VSS CLK VSS DQa DQa
LDQd DQd
BWd
NC
BWa
DQa DQa
MVDDQ DQd VSS
BWE
VSS DQa VDDQ
NDQd DQd VSS A1 VSS DQa DQa
PDQd DQpd VSS A0 VSS DQPa DQa
RNC A
LBO
VDD VDD ANC
TNC NC A A A NC ZZ
UVDDQ TMS TDI TCK TDO NC VDDQ
Note: For P/N AS7C25512PFS32A, 4 of the I/O Pins must be left open (N.C.)