2011 Microchip Technology Inc. DS80436D-page 1
PIC18F46J50 FAMILY
The PIC18F46J50 family devices that you have received
conform functionally to the current Device Data Sheet
(DS39931D), except for the anomalies described in this
document.
The silicon issues discussed in the following pages are
for silicon revisions with the Device and Revision IDs
listed in Table 1. The silicon issues are summarized in
Table 2.
The errata describ ed in this document will be addressed
in future revisions of the PIC18F46J 50 family silic on.
Data Sheet clarifications and corrections start on page 8,
following the discu ssion of silicon issues.
The silicon revision level can be identified using the
current version of MPLAB® IDE and Microchip’s
programmers, debuggers, and emulation tools, which
are available at the Microchip corporate web site
(www.microchip.com).
For example, to identify the silicon revision level using
MPLAB IDE in conjunction with MPLAB ICD 2 or
PICkit™ 3:
1. Using the appropriate interface, connect the
device to the MPLAB ICD 2 programmer/
debugger or PICkit™ 3.
2. From the main menu in MPLAB IDE, select
Configure>Select Device, and then select the
target part number in the dialog box.
3. Select the MPLAB hardware tool
(Debugger>Select Tool).
4. Perform a “Connect” operation to the device
(Debugger>Connect). Depending on the devel-
opment tool used, the part number and Device
Revisio n ID valu e appear in th e Output window.
The DEVREV values for the various PIC18F46J50 family
silicon revisions are shown in Table 1.
Note: This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated in the last column of
Table 2 apply to the current silicon
revision (Rev. A4). Note: If you are unable to extract the silicon
revision level, please contact your local
Microchip sales office for assistance.
TABLE 1: SILICON DEVREV VALUES
Part Number Device ID(1) Revision ID for Silicon Revision(2)
A2 A4
PIC18F24J50 4C0Xh
2h 4h
PIC18F25J50 4C2Xh
PIC18F26J50 4C4Xh
PIC18F44J50 4C6Xh
PIC18F45J50 4C8Xh
PIC18F46J50 4CAXh
PIC18LF24J50 4CCXh
PIC18LF25J50 4CEXh
PIC18LF26J50 4D0Xh
PIC18LF44J50 4D2Xh
PIC18LF45J50 4D4Xh
PIC18LF46J50 4D6Xh
Note 1: The De vice IDs (D EVID and DEVREV) a re loc ated a t the last t wo i mplemen ted ad dresse s of con figura tion
memory space. They are shown in hexadecimal in the format “DEVID DEVREV”.
2: Refer to the “PIC18F2XJXX/4XJXX Family Flash Microcontroller Programming Specification” (DS39687)
for detailed information on Device and Revision IDs for your specific device.
PIC18F46J50 Family
Silicon Errata and Data Sheet Clarification
PIC18F46J50 FAMILY
DS80436D-page 2 2011 Microchip Technology Inc.
TABLE 2: SILICON ISSUE SUMMARY
Module Feature Item
Number Issue Summary
Affected
Revisions(1)
A2 A4
MSSP I2C™
Modes 1. Must keep LATB<5:4> bits clear. X
MSSP I2C Slave 2. Module may not receive the correct data if there
is a delay in reading SSPxBUF af ter SSPxIF
interrupt. XX
EUSART Enable/
Disable 3. If interrupt s are ena ble d, a 2 TCY delay needed
after re-enabling the module. XX
A/D FOSC/2
Clock 4. FOSC/2 A/D Conversion mode may not meet
linearity error limits. XX
PMP PSP/PMP 5. The data bus may not work correctly. X
Low-Power
modes Deep Sleep 6. Wake-up events that occur dur ing Deep Sleep
entry may not generate an event. XX
DC
Characteristics Supply
Voltage 7. Minimu m opera ting v olt age (VDD) p ara meter for
“F” devices is 2.25V. X
A/D Band Ga p
Reference 8. At high VDD voltag es, performing an A/D
conversion on Channel 15 could have issues. XX
CTMU Constant
Current 9. Low voltages turn off constant current source. X
Note 1: Only those issues indicated in the last column apply to the current silicon revision.
2011 Microchip Technology Inc. DS80436D-page 3
PIC18F46J50 FAMILY
Silicon Errata Issues
1. Module: Master Synchronous Serial Port
(MSSP1)
If the LATB<5> or LATB<4> bit is set, the
MSSP1 module will not work correctly in the
I2C™ modes. If both LATB<5> and LATB<4>
are clear, the module will work normally.
Work around
Clear the bits, LATB<5:4>, prior to enabling the
MSSP1 mod ule in an I2C mode. Keep these bits
clear while using the module.
For operation in I2C modes, the TRISB<5:4>
bits should be set.
Affected Silicon Revisions
2. Module: Master Synchronous Serial Port
(MSSP)
In extremely rare cases, when configured for I2C™
slave reception, the MSSP module may not receive
the correct data. This occurs only if the Serial
Receive/Transmit Buffer Register (SSPxBUF) is not
read within a window after the SSPxIF interrupt
has occurred.
Work around
The iss ue c an be res ol ved i n e ith er o f th es e ways :
• Prior to the I2C slave reception, enable the
clock stretching feature.
This is done by setting the SEN bit
(SSPxCON2<0>).
• Each time the SSPxIF is set, read the
SSPxBUF before the first rising clock edge of
the next byte being received.
Affected Silicon Revisions
Note: This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (Rev. A4).
A2 A4
X
A2 A4
XX
PIC18F46J50 FAMILY
DS80436D-page 4 2011 Microchip Technology Inc.
3. Module: Enhanced Universal
Synchronous Asynchronous
Receiver Transmitter (EUSART)
In rare situations, when interrupts are enabled,
unexpected results may occur if:
• The EUSART is disabled (the SPEN bit,
RCSTAx<7> = 0)
• The EUSART is re-enabled (RCSTAx<7> = 1)
• A two-cycl e instructio n is execute d immediat ely
after setting SPEN = 1
Work around
Add a 2 TCY delay after any instruction that re-
enables the EUSART module (sets SPEN = 1).
Refer to Example 1.
EXAMPLE 1: RE-ENABLING A EUSART MODULE
Affected Silicon Revisions
;Initial conditions: SPEN = 0 (module disabled)
;To re-enable the module:
;Re-Initialize TXSTAx, BAUDCONx, SPBRGx, SPBRGHx registers (if needed)
;Re-Initialize RCSTAx register (if needed), but do not set SPEN = 1 yet
;Now enable the module, but add a 2-Tcy delay before executing any two-cycle
;instructions
bsf RCSTA1, SPEN ;or RCSTA2 if EUSART2
nop ;1 Tcy delay
nop ;1 Tcy delay (two total)
;CPU may now execute 2 cycle instructions
A2 A4
XX
2011 Microchip Technology Inc. DS80436D-page 5
PIC18F46J50 FAMILY
4. Module: 10-Bit Analog-to-Digital
Converter (ADC)
When the A/D conversion clock select bits are set
for FOSC/2 (ADCON1<2:0> = 000), the Integral
Linearit y Error (EIL) parameter (A03) and Dif feren-
tial Linearity Error (EDL) parameter (A04) may
exceed data sheet specifications.
Work around
Select one of the alternate AD clock sources
shown in Table 3. The EIL and EDL parameters
are met for the other clocking options.
Affected Silicon Revisions
5. Module: Parallel Master Port (PMP)
When configured for Parallel Slave Port
(PMMODEH<1:0> = 0x and PMPEN = 1), the data
bus (PMD<7:0>) may not work correctly and
incorrec t data c ould be c aptured into the PMDIN1 L
register.
When co nfi gured for Parall el Ma ster Port (PM MO-
DEH<1:0> = 1x and PMPEN = 1), clearing a
PMEx bit to disable a PMP address line also
disables the correspon din g PMDx data bus line.
Work around
None.
Affected Silicon Revisions
TABLE 3: ALTERNATE ADC SETTINGS
ADCON1<2:0>
ADCS<2:0> Clock Setting
110 FOSC/64
101 FOSC/16
100 FOSC/4
011 FRC
010 FOSC/32
001 FOSC/8
A2 A4
XX
A2 A4
X
PIC18F46J50 FAMILY
DS80436D-page 6 2011 Microchip Technology Inc.
6. Module: Low-Power Modes (De ep S leep)
Entering Deep Sleep mode takes approximately
2T
CY, following the SLEEP instruction. Wake-up
events that occur during this Deep Sleep entry
period may not generate a wake-up event.
Work around
If using the RTCC alarm for Deep Sleep wake-up,
code should only enter Deep Sleep mode when
the RTCC Value registers read synchronization bit
(RTCCFG<4>) is clear.
This will prevent missing an RTCC alarm that
could occur during the period after the SLEEP
instruction, but before the Deep Sleep mode has
not been fully entered.
The revision A4 silicon allows insertion of a single
instruction between setting the Deep Sleep Enable
bit (DSEN, DSCONH<7>) and issuing the SLEEP
instruction (see Example 2). The insertion of a NOP
instruc tion before the SLEEP instruc tion elim inates
the 2 TCY window where wake-up events could be
missed.
Before usin g this work around , users sh ould check
their device’s revision ID bits to verify that they
have the A4 silicon. This can be done at run time
by a table read from address, 3FFFFEh.
On re vision A2 s ilic on device s, the in struct ion can-
not be inserted between setting the DSEN bit and
executing the SLEEP instruction or the device will
enter conventional Sleep mode, not Deep Sleep.
Even on A4 silicon devices, if the firmware imme-
diately executes SLEEP after setting DSEN, the
device will enter Deep Sleep mode without
benefitting from this work around.
Affected Silicon Revisions
EXAMPLE 2: DEEP-S LEE P WAKE-UP WORK AROUND
EnterDeepSleep:
bsf DSCONH, DSEN ; Enter Deep Sleep mode on SLEEP instruction
nop ; Not compatible with A2 silicon
sleep ; Enter Deep Sleep mode
(…) ; Add code here to handle wake up events that may
; have been asserted prior to Deep Sleep entry
goto EnterDeepSleep ; re-attempt Deep Sleep entry if desired
A2 A4
X
2011 Microchip Technology Inc. DS80436D-page 7
PIC18F46J50 FAMILY
7. Module: DC Characteristics (Supply
Voltage)
The minimum operating voltage (VDD) parameter
(D001) for “F” devices is 2.25V. For “LF” devices
(such as the PIC18LF46J50), the minimum rated
VDD operating voltage is 2.0V.
Work around
None.
Affected Silicon Revisions
8. Module: Analog-to-Digital Converter
(Band Gap Reference)
At high VDD voltages (ex: >2.5V), performing an
ADC conv ersion on Channel 15 (the VBG absolute
reference) can temporarily disturb the reference
volt age su pplied to t he HLVD mod ule and co mpar-
ator module (only when configured to use the
VIRV). At lower VDD voltages, the disturbance will
be less or non-existent.
Work around
If precis e HLVD or comp arator V IRV thr eshol ds are
required at high VDD voltages, avoid performing
ADC conversions on Channel 15 while simultane-
ously using the HLVD or comparator VIRV. If an
ADC conversion is performed on Channel 15, a
settling time of approximately 100 s is needed
before the reference voltage fully returns to the
original value.
Affected Silicon Revisions
9. Module: Charge Time Measurement Unit
(CTMU)
On an “F” device, the CTMU current source will stop
sourcing current if the applied VDD voltage falls
below the LVDSTAT (WDTCON<6>) threshold
(2.45V nominal). When VDD is abo ve the LVDSTAT
threshold, the CTMU will function normally. This
issue does not apply to “LF” devices. The current
source will continue to func tion n ormally at all rated
volt ages for these devices .
Work around
None
Affected Silicon Revisions
A2 A4
X
A2 A4
XX
A2 A4
X
PIC18F46J50 FAMILY
DS80436D-page 8 2011 Microchip Technology Inc.
Data Sheet Clarifications
The foll owing ty pographic corrections and clar ification s
are t o be note d for the l atest ve rsion of the Devic e Data
Sheet (DS39931D):
1. Module: Special Features (CONFIG2L)
The “T1DIG” feature mentioned in the Device
Data Sheet (DS39931D) is not implemented in
this device family. The feature, associated with
bit 3 of the CONFIG2L Configuration register, is
discussed in Section 26.1 “Configuration
Bits” and Section 2.5.1 “Oscillator Control
Register”.
For application firmware to switch to the Timer1
clock source, it must first enable the crystal
driver by setting the T1OSCEN bit (T1CON<3>).
The microcontroller wil l igno re atte mp ts to clock
switch to the Timer1 clock source when the
crystal driver is disabled.
Note: Corrections are shown in bold. Where
possible, the original bold text formatting
has been removed for clarity.
2011 Microchip Technology Inc. DS80436D-page 9
PIC18F46J50 FAMILY
APPENDIX A: DOCUMENT
REVISION HISTORY
Rev A Document (2/2009)
First release of this document. Silicon issues
1 (T1DIG), 2-3 (MSSP), 4 (EUSART), 5 (ADC),
6 (PMP), 7 (Deep Sleep), 8 (Supply Voltage).
Rev B Document (5/2009)
Added silicon issues 9 (Band Gap Reference) and
10 (Charge Time Measurement Unit – CTMU).
Rev C Document (1/2010)
Converted existing document for the A2 silicon revision
to the new, combined format. (There were no other
silicon errata or data sheet clarification documents for
the device family.)
Removed silicon issue 1 (Special Features, T1DIG)
and modified decremented issue 1, formerly
2 (MSSP1) and 6 (Low-Power Modes – Deep Sleep).
Added data sheet clarifications 1 (Special Features –
CONFIG2L), 2 (DC Characteristics – Power-Down
Current) and 3 (DC Characteristics – Input Leakage).
Rev D Document (4/2011)
Updated text description for silicon issue 5 (Parallel
Master Port) and removed data sheet clarifications
2 (DC Characteristics – Power-Down Current) and 3
(DC Ch aracte ristic s – In put Le akage) si nce both cl arifi-
cations have been included in the PIC18F46J50 Data
Sheet.
PIC18F46J50 FAMILY
DS80436D-page 10 2011 Microchip Technology Inc.
NOTES:
2011 Microchip Technology Inc. DS80436D-page 11
Information contained in this publication regarding device
applications a nd t he lik e is provid ed only for your convenience
and may be su perseded by updates. I t is y our respo ns i bil it y to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPL AB, PIC , PI Cmi cro, PI CSTART,
PIC32 logo, rfPIC and UNI/O are registered trademark s of
Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Contro l
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONIT OR, FanSense, HI-TIDE, In - Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Cert ified
logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance,
TSHARC, UniWinDriver, WiperLock and ZENA are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip T echnology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2011, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-61341-066-0
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that it s family of products is one of t he most secure famili es of its kind on the market today, when used in t he
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is c onstantly evolving. We a t Microc hip are co m mitted to continuously improving the code prot ect ion featur es of our
products. Attempts to break Microchip’ s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperiph erals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS80436D-page 12 2011 Microchip Technology Inc.
AMERICAS
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Web Address:
www.microchip.com
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Chicago
Itasc a , IL
Tel: 630-285-0071
Fax: 630-285-0075
Cleveland
Independence, OH
Tel: 216-447-0464
Fax: 216-447-0643
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Detroit
Farmington Hills, MI
Tel: 248-538-2250
Fax: 248-538-2260
Indianapolis
Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
Los A n ge les
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
Santa Clara
Santa Clara, CA
Tel: 408-961-6444
Fax: 408-961-6445
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
ASIA/PACIFIC
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
China - Beijing
Tel: 86-10-8528-2100
Fax: 86-10-8528-2104
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
China - Chongqing
Tel: 86-23-8980-9588
Fax: 86-23-8980-9500
China - Hong Kong SAR
Tel: 852-2401-1200
Fax: 852-2401-3431
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
China - Shenzhen
Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
ASIA/PACIFIC
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11- 4160-8632
India - Pune
Tel: 91-20-2566-1512
Fax: 91-20-2566-1513
Japan - Yokohama
Tel: 81-45-471- 6166
Fax: 81-45-471-6122
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
Taiwan - Hsin Chu
Tel: 886-3-6578-300
Fax: 886-3-6578-370
Taiwan - Kaohsiung
Tel: 886-7-213-7830
Fax: 886-7-330-9305
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
EUROPE
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Cop e nha gen
Tel: 45-4450-2828
Fax: 45-4485-2829
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-14 4-44
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Spai n - Madri d
Tel: 34-91-708-08-90
Fax: 34-91-708-08 -91
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
Worldwide Sales and Service
02/18/11
