A AURELIA SPT Rev. N. 2 Data: 26/02/02 Title: Frost64 - Technical Specifications M i c r o e l e t t r o n i c a S. p. A. Technical Specification FROST64 A AURELIA M i c r o e l e t t r o n i c a S. p. A. Via Giuntini 13 - 56023 - frazione Navacchio Cascina (PI) - ITALIA Capitale sociale 350.000 int. vers. Registro delle imprese di Pisa n 2819/1998 REA 127299 C.F. P.I. n 01428250508 Document Type. SPT File Name FROST_manuale.doc Revision 3 Issued on 03/06/2002 Page 1 of 31 A AURELIA Title: Frost64 - Technical Specifications M i c r o e l e t t r o n i c a S. p. A. SPT Rev. N. 2 Data: 26/02/02 INDEX INDEX.......................................................................................................................................................................... 2 1. INTRODUCTION........................................................................................................................................... 4 1.1. Purpose............................................................................................................................................................. 4 1.2. Reference Documents...................................................................................................................................... 4 1.3. Glossary ........................................................................................................................................................... 4 2. PRODUCT DESCRIPTION .......................................................................................................................... 5 2.1. Short Description ............................................................................................................................................ 5 2.2. Main Characteristics....................................................................................................................................... 5 3.7.1 Analog Section........................................................................................................................................... 5 3.7.2 Digital section ............................................................................................................................................ 5 2.3. Pads Description.............................................................................................................................................. 7 2.4. Pads Distribution............................................................................................................................................. 7 3. FUNCTIONAL DESCRIPTION ................................................................................................................... 8 3.1. Analog channel ................................................................................................................................................ 9 3.2. Output Buffer ................................................................................................................................................ 11 3.3. Discriminator................................................................................................................................................. 11 3.4. Threshold regulation..................................................................................................................................... 11 3.5. Calibration..................................................................................................................................................... 16 3.6. Digital Section................................................................................................................................................ 16 3.6.1 Digital part features ............................................................................................................................... 16 3.6.3 Functions ............................................................................................................................................. 18 3.6.4 Timing................................................................................................................................................... 19 Document Type. SPT File Name FROST_manuale.doc Revision 3 Issued on 03/06/2002 Page 2 of 31 A AURELIA Title: Frost64 - Technical Specifications M i c r o e l e t t r o n i c a S. p. A. SPT Rev. N. 2 Data: 26/02/02 Reset mode ................................................................................................................................................... 19 Counting......................................................................................................................................................... 19 Reading.......................................................................................................................................................... 19 Testing ........................................................................................................................................................... 19 3.6.5 Layout of the digital part .............................................................................................................. 21 3.6.6 Chip connection ................................................................................................................................ 22 4 SPECIFICATIONS....................................................................................................................................... 23 3.7. Absolute maximum rating ............................................................................................................................ 23 3.8. System specification ...................................................................................................................................... 23 4.6.3 Power Supply ........................................................................................................................................... 23 4.6.4 Analog Section......................................................................................................................................... 23 4.6.5 Output Buffer ........................................................................................................................................... 24 4.6.6 Discriminator ........................................................................................................................................... 24 4.6.7 3 bit and 6 bit DACs ................................................................................................................................ 26 4.6.8 Thermal drift ............................................................................................................................................ 27 4.6.9 Digital section .......................................................................................................................................... 27 4.6.10 Loads........................................................................................................................................................ 28 5 PACKAGED SAMPLES .............................................................................................................................. 29 4. CONTACT US............................................................................................................................................... 31 Document Type. SPT File Name FROST_manuale.doc Revision 3 Issued on 03/06/2002 Page 3 of 31 A AURELIA Title: Frost64 - Technical Specifications M i c r o e l e t t r o n i c a S. p. A. SPT Rev. N. 2 Data: 26/02/02 1. INTRODUCTION 1.1. Purpose The technical specifications of Frost64, a fast and low noise photon counting ASIC developed for biomedical application are given in this document. 1.2. Reference Documents [1] 16_AS_CNTSHF datasheet [2] Franky: Datasheet e test 1.3. Glossary AI Analog Input Pin AO Analog Output Pin A I/O Analog Input/Output Pin DI Digital Input Pin DO Digital Output Pin D I/O Digital Input/Output Pin PG Power/Ground Pin Document Type. SPT File Name FROST_manuale.doc Revision 3 Issued on 03/06/2002 Page 4 of 31 A AURELIA SPT Rev. N. 2 Data: 26/02/02 Title: Frost64 - Technical Specifications M i c r o e l e t t r o n i c a S. p. A. 2. PRODUCT DESCRIPTION FUNCTION: TECHNOLOGY CELL SIZE POWER CONS. PACKAGE N. of PADS INPUT PAD PITCH 64-channel pixel detector AMS 0.8um CMOS CXQ 2 4555um x 11430um (52.0 mm ) 100 mA @ 5 V CQFP120 117 130um 2.1. Short Description 64-channel, fast and low noise single photon counting system developed in order to reach an acceptable time duration of the digital mammography exam. It consist in 64 identical channel. Each channel has an 2 analogue input section with a low noise preamplifier and a CR-RC shaper, a discriminator section with a 3 bit DAC in order to reach locally the discriminator threshold and a readout full-custom digital section. To set globally the discriminator threshold of all channels a 6 bit DAC is used. 2.2. Main Characteristics 3.7.1 3.7.2 Analog Section * Sensitivity: 150 mV/fC with 10pF of input capacitance. * Peaking time: 311 ns * Decay time: * polo/zero cancellation * Non Linearity < +/- 1,2% * Maximum noise @ Cin = 10pF: 850e rms * Gain time spread : +/-2,5% * Peaking time spread: +/- 1% * Adjustable threshold with 6 bit DAC * Minimum detectable signal: 1fC * Counting rate : 1 Mhz 0,55s - Digital section * 16 bit asynchronous counter with external reset and enable and serial output for each channel * Document Type. SPT 20MHz output speed File Name FROST_manuale.doc Revision 3 Issued on 03/06/2002 Page 5 of 31 A AURELIA SPT Rev. N. 2 Data: 26/02/02 Title: Frost64 - Technical Specifications Gate Vg vssc vddc CkOut Dout SerialUp vdd 111 110 109 108 107 106 105 104 6 vdda In 4 112 5 vssa vssa 113 4 BuffOut In 3 114 3 vdda In 2 115 2 vssa In 1 116 1 Test1 In 0 117 M i c r o e l e t t r o n i c a S. p. A. In 11 13 vssa 14 In 12 15 In 19 22 vssa 23 88 gnd 87 gnd SerialDown 89 86 Vdd CkIn 90 85 Common Din 91 84 ShiftUD vddc 92 83 gnd DAC_OUT 93 82 vdd vssc 94 81 ShiftCount VREF 95 80 TestEnable Vis 96 79 gnd Rbias6b 97 78 72 vdd Rbias3b In 63 98 77 71 ShiftClock vdda In 62 99 76 70 EnDir vssa In 61 100 75 69 gnd vdda In 60 101 74 68 vdd vssa vssa 102 73 67 OW Test2 In 59 103 Figure 1 Document Type. SPT File Name FROST_manuale.doc Revision 3 Issued on 03/06/2002 Page 6 of 31 A AURELIA SPT Rev. N. 2 Data: 26/02/02 Title: Frost64 - Technical Specifications M i c r o e l e t t r o n i c a S. p. A. 2.3. Pads Description Name Pin Type Note in0 - in63 1-4, 6-13,15-22,24-31,33-40,4249,51-58,60-67,69-72 73 AI Channel input (wired - bonding to silicon detector) AI 32-channel calibration input PG Ground of analogue section vdda 5,14,23,32,41,50,59,68, 74,76,113,116 75,77,112,115 PG Supply of analogue section rbias3b 78 A I/O DAC3 bias resistor rbias6b 79 A I/O DAC6 bias resistor Vis 80 A I/O Discriminator's hysteresis calibration VREF 81 AI DAC voltage reference vssc 82,109 PG Ground of discriminator section vddc 84,108 PG Supply of discriminator section DAC_OUT 83 AO DAC6 output D_in 85 DI Stream input to program discriminator section test2 gnda ck_in 86 DI Clock input to program discriminator section serial_down 87 D I/O Down shift register chain gnd 88,89,93,97,101 PG Ground of digital section vdd 90,94,98,102,104 PG Supply of digital section common 91 DI Counter input during test modality shift_UD 92 DI Selector for shift direction shift_count 95 DI Shift or count enable test_enable 96 DI Test modality enable shift_clock 99 DI Clock to serial readout en_dir 100 DI Clock phase during test modality ow 103 DO Overflow flag (wired-or) serial_up 105 D I/O Up shift register chain D_out 106 DO Stream output to program discriminator section ck_out 107 DO Clock output program discriminator section Vg 110 A I/O Discriminator bias forcing gate 111 AI Pole-zero cancellation BuffOut 114 AO Channel <0> analogue output Test 1 117 AI 32-channel calibration input Table 1 2.4. Pads Distribution Pads are distribute uniformly along each side of the chip with different pitch : 72 pads on left side (pads n. 1 - 72), pitch 130 um 15 pads on down side (pads n. 73 - 87), pitch 235 um 16 pads on right side (pad 88 103), pitch 620 um 14 pads on up side (pad 104 - 117), pitch 235um Chip Area: (X x Y): 4588 um x 11354 um = 52.09 mmq Document Type. SPT File Name FROST_manuale.doc Revision 3 Issued on 03/06/2002 Page 7 of 31 A AURELIA Title: Frost64 - Technical Specifications M i c r o e l e t t r o n i c a S. p. A. SPT Rev. N. 2 Data: 26/02/02 3. FUNCTIONAL DESCRIPTION The chip structure is depicted in Figure . It is mainly composed by 8 blocks of 8 channels each and a calibration section (including DACs and polarization circuits). The analog output of channel 0 is buffered and connected to pad to be easily tested. Output buffer in 0 8 analog channel 8 digital channel 8 analog channel 8 digital channel 8 analog channel 8 digital channel 8 analog channel 8 digital channel 8 analog channel 8 digital channel 8 analog channel 8 digital channel 8 analog channel 8 digital channel 8 analog channel 8 digital channel in 7 in 8 in 15 in 16 in 23 in 24 in 31 in 32 in 39 in 40 in 47 in 48 in 55 in 56 in 63 Calibration section (DAC6 and DAC3) Figure 2 Document Type. SPT File Name FROST_manuale.doc Revision 3 Issued on 03/06/2002 Page 8 of 31 A AURELIA Title: Frost64 - Technical Specifications M i c r o e l e t t r o n i c a S. p. A. SPT Rev. N. 2 Data: 26/02/02 The upper block of 32 channels and the lower block of 32 have separate voltage supply, whereas a ground pin exists for each block of 8 channels. Each 8 channels block structure is shown in Figure 1. Analog section CH 0 discrim. Digital. counter P_in<1> Analog section CH 1 discrim. Digital. counter P_in<2> Analog section CH 2 discrim. Digital. counter P_in<3> Analog section CH 3 discrim. Digital. counter P_in<0> Bias section Groun pad P_in<4> Analog section CH 4 discrim. Digital. counter P_in<5> Analog section CH 5 discrim. Digital. counter P_in<6> Analog section CH 6 discrim. Digital. counter P_in<7> Analog section CH 7 discrim. Digital. counter Figure 1 The Bias section provides bias currents and voltage references for each analog section of the channels. 3.1. Analog channel The analog channel is now described in more detail. Figure 2 shown its basic structure: charge 2 preamplifier , shaper and comparator. The shaper block provides a CR-RC shaping with pole-zero cancellation. Figure 3 shows how the circuit has been implemented. Two MOS resistor are used: one as feedback resistor for the charge preamplifier and one for the pole-zero cancellation network. All of the 64 Document Type. SPT File Name FROST_manuale.doc Revision 3 Issued on 03/06/2002 Page 9 of 31 A AURELIA SPT Rev. N. 2 Data: 26/02/02 Title: Frost64 - Technical Specifications M i c r o e l e t t r o n i c a S. p. A. channels have the gate of those transistor connected together to pad "P_vg ". The normal voltage to apply at this pad is 0 V but it may be decrease up to -0.2V if the feedback resistor became too large. Shaper Charge Integrator Comparator with adjustable threshold C2 CF Rc RF R2 R1 C R3 16 bit counter C3 6 bit DAC + 3 bit DAC Figure 2 The circuit contains three identical inverting amplifier, in this way the shaper output has the same DC voltage level of the preamplifier input. Dummy amplifier DUMMY GATE RMOS OUT NPUT Charge preamplifier Shaper block CSA_OUT SH_OUT Figure 3 There is only one "dummy amplifier" for 8 channel included in "Bias section" of Figure 1. Document Type. SPT File Name FROST_manuale.doc Revision 3 Issued on 03/06/2002 Page 10 of 31 A AURELIA Title: Frost64 - Technical Specifications M i c r o e l e t t r o n i c a S. p. A. SPT Rev. N. 2 Data: 26/02/02 3.2. Output Buffer This buffer let the output of channel 0 to be externally available at pin P_BuffOut. It shift the DC voltage of the shaper output of +1.0V and must be AC coupled at the scope input. All the characteristics of the shaped signal ( sensitivity , peaking time, rise time, fall time and linearity) are unaffected by the buffer. 3.3. Discriminator The discriminator compare the shaped signal with an adjustable threshold voltage that can be varied globally by a 6 bit DAC and locally (for a single discriminator) by a 3 bit DAC. It is provided of an hysteresis, for noise immunity, that can be regulated for all 64 discriminator by a voltage applied to the pin P_Vis. The commutation speed can by also adjusted changing the polarization current; this can be done forcing the pin P_Vg at different voltage level. 3.4. Threshold regulation The discriminator threshold can be set for all 64 channel by the 6 bit DAC and finely tuned for each discriminator by the 3 bit DAC. DACs connection and reference distributions are shown in Figure 4. A voltage reference must be applied to the pin P_VREF and two resistors must be connected between pads P_Rbias3b and P_Rbias6b to ground; they set the voltage range for DAC3 and DAC6 respectively. DAC6 generates a voltage always greater or equal to VREF. This voltage is passed to the block called "DAC3 references" that generates 8 voltage level distributed to all 64 DAC3. DAC3 is simply composed by 8 switch that let to connect the negative input of the discriminator to the desired voltage. They can be selected by a 3 bit data stored in a 3 bit shift register as shown in Figure 5. To set the voltage threshold for all the 64 channel a stream of 198 bit is needed. The clock must applied at pin "CkIn" and data enter serially at pin "P_Din" and exit at pin P_Dout. The first entering 3 bits set the threshold for channel 0 and the last 6 bit set the DAC6 voltage. The timing diagram is shown in Figure 6: the entering datum is sampled in the rising edge of the clock CKIn; when a datum enter at input Din one datum come out from pin Dout. Figure 7 shows how data are weighted when stored in the shift registers. Document Type. SPT File Name FROST_manuale.doc Revision 3 Issued on 03/06/2002 Page 11 of 31 A AURELIA Title: Frost64 - Technical Specifications M i c r o e l e t t r o n i c a S. p. A. P_Dout channel 0 SPT Rev. N. 2 Data: 26/02/02 P_CkOut 3bit shift DAC3 register 8 channel 1 3bit shift DAC3 register 8 channel 63 3bit shift DAC3 register 8 8 DAC3 references P_Rbias3b 6 bit DAC 6 bit Shift register P_Rbias6b P_VREF P_Din P_CkIn Figure 4 Document Type. SPT File Name FROST_manuale.doc Revision 3 Issued on 03/06/2002 Page 12 of 31 A AURELIA SPT Rev. N. 2 Data: 26/02/02 Title: Frost64 - Technical Specifications M i c r o e l e t t r o n i c a S. p. A. 3 bit shift register DAC3 Discriminatror channel 63 REF1 REF0 REF7 DAC3 references P_Rbias3b P_DAC_OUT Vdac6 Buffer P_Rbias6b Rbias6b Rbias3b 6 bit DAC P_VREF Vref Figure 5 Document Type. SPT File Name FROST_manuale.doc Revision 3 Issued on 03/06/2002 Page 13 of 31 A AURELIA SPT Rev. N. 2 Data: 26/02/02 Title: Frost64 - Technical Specifications M i c r o e l e t t r o n i c a S. p. A. Entering data "1" CkIn "0" 1 "0" 2 "1" "1" 3 n-1 n Din: Figure 6 DAC6 LSB DAC3 MSB MSB LSB Dout Din Figure 7 The structure of DAC6 and DAC3 references, and how they are connected together, is shown in Figure 8 . DAC6 is composed by a ladder network whereas DAC3 references are generate by a divider. The currents I0 and I1 set the step and range and are generate by means of two current generator which structure is shown in Figure 9 ; current I is mirrored and divider by a factor 4 to form the current I0 or i1 and its value is set by an internal voltage reference (band gap), of about 1.23 V, and the external resistor values (Rbias3b or Rbias6b). The output voltage range for both DACs is defined by the product of internal resistors and the current flowing in resistors Rbias3b and Rbias6b and can be expressed as: VREF0,VREF1,....,VREF7 = Vdac6+Range_dac3 / 7* 0,1,.....7, and Vdac6 = Vref + Range_dac6 /63 * N6 , N6=0,1,2, ......63. Document Type. SPT File Name FROST_manuale.doc Revision 3 Issued on 03/06/2002 Page 14 of 31 A AURELIA SPT Rev. N. 2 Data: 26/02/02 Title: Frost64 - Technical Specifications M i c r o e l e t t r o n i c a S. p. A. where VREF0, ..,VREF7 are the voltage at node REF0,....,REF7 , Range_dac3 and Range_dac6 are the maximum range, for a certain Rbias, for 3 bit and 6 bit DAC respectively. Resistor R and R1 have the nominal value of 24.12k and 1.25k and a process spread of 16% and 23% respectively. The external voltage VREF must set to guarantee the signal to be detectable, it can be set equal or lower the analog channel baseline (see table of section 4.6.4). Vdda Io Io Io Io Io Io DAC_OUT R R 2R Rpad=350 R Ohm R R 2R 2R 2R 2R Buffers R VREF vdda I1 R1 R1 R1 R1 R1 R1 R1 REF7 REF6 REF5 REF4 REF3 REF2 REF1 Buffers REF0 Figure 8 Document Type. SPT File Name FROST_manuale.doc Revision 3 Issued on 03/06/2002 Page 15 of 31 A AURELIA SPT Rev. N. 2 Data: 26/02/02 Title: Frost64 - Technical Specifications M i c r o e l e t t r o n i c a S. p. A. Vdda BAND GAP I Rpad 350 Ohm P_RbiasXb RbiasXb Figure 9 3.5. Calibration An integrated 200 fF capacitance for each channel can be used for calibration purpose. Pad "Test1" must used to calibrate channel 0 to 31 and pad "Test2" to calibrate channel 32 to 63. 3.6. Digital Section 3.6.1 Digital part features - 16-bit asynchronous counter ; - Counter input from comparator (comp_inp) , serial (serial_in) or common test pin (common); - two bi-directional output signals (serial_up, ,serial_down) : shift_UD pin selects direction; - serial readout or counting signal (shift_count); - serial readout clock signal (shift_clock); - fully testable system by means of test_enable , en_dir , shift_clock and common signals; - overflow signal ow (by means of owpout, owpin, ownor signals). 3.6.2 Block Diagram Document Type. SPT File Name FROST_manuale.doc Revision 3 Issued on 03/06/2002 Page 16 of 31 A AURELIA Title: Frost64 - Technical Specifications M i c r o e l e t t r o n i c a S. p. A. SPT Rev. N. 2 Data: 26/02/02 Device block diagram is shown below . The main blocks are: A) inmux; multiplexer to change the input signal of the counter. The shift_count and test_enable signals allow to select one of the following input: comp_inp (counting input), common (testing input), shift_in (serial input). The signal shift_in is connected to serial_up or serial_down , depending on shift_UD. B) clock_gen; this block drives the system in serial readout mode. Internally a four phases clock generator is used. C) 16counter; 16 bit asynchronous counter. In counter mode, each cell is an asynchronous toggle flipflop driven by the previous cell, while in serial reading mode it is a synchronous register controlled by en1, en2 e run signals. D) Overflow; this is the cell that generates the overflow signal and hold it up to the successive reset. It is possible to connect it to other identical devices for a multichannel system. Document Type. SPT File Name FROST_manuale.doc Revision 3 Issued on 03/06/2002 Page 17 of 31 A AURELIA Title: Frost64 - Technical Specifications M i c r o e l e t t r o n i c a S. p. A. SPT Rev. N. 2 Data: 26/02/02 3.6.3 Functions The device configuration in the various modes is as follow: A) reset (o preset) two ways exists to reset (or preset) the state of the counters : A) activate reading mode (shift_count HIGH level and test_enable LOW level), put the serial_in signal LOW (HIGH for preset) and shift in 16x64 data (16 for one cell); B) put test_enable, shift_count and common signals HIGH ( put common LOW for the preset), put en_dir LOW. In this case the serial_in is not necessary but it is mandatory to follow a correct timing B) counting function shift_count and test_enable signals must be set LOW. If the counter overflows, the ow signal (normally HIGH level) goes LOW up to the reset of the counter . The overflow signal is generated by means of a nor gate of the OW signals of each channel: in this way, if, the global ow signals gets LOW if one channel overflows. While in this mode, all changes on common, shift_clock, shift_UD, en_dir, serial_up, serial_down signals have not effect on device. C) reading The shift_count must be set HIGH ( test_enable LOW ) and the shift_clock is the reading clock. The data outputs from MSB to LSB. All changes on comp_inp and en_dir have not effect in this mode. D) test To enter test mode, test_enable signal must be set HIGH. The common pin is the counter input signal in this mode. In the test mode is possible to test all internal node by means of en_run, shift_clock and shift_count signals. Document Type. SPT File Name FROST_manuale.doc Revision 3 Issued on 03/06/2002 Page 18 of 31 A AURELIA Title: Frost64 - Technical Specifications M i c r o e l e t t r o n i c a S. p. A. SPT Rev. N. 2 Data: 26/02/02 3.6.4 Timing The timing follows must be respected for a proper functionality of the chip . Reset mode If the reset is made in mode A) the timing is the same as for reading mode, instead in B) mode it is mandatory to follow the following sequence between the test_enable, shift_count, en_dir and common signals. Counting In this mode the counter is clocked by the comp_inp signal. Each comp_inp pulse is counted from device (the pulse is a rectangular wave with LOW initial and final level and HIGH level intermediate). The I is the minimum length of the pulse whereas the minimum distance between two pulse successive is c. Reading The shift_clock must go HIGH before shift_count signal goes HIGH for proper functionality. A single shift for each shift_clock pulse is generated (in this case the pulse is a rectangular wave with HIGH final and initial level and LOW intermediate level). The sc is the minimum length of the pulse whereas the minimum distance between two pulse successive is fmax. Testing In this mode the device it's controlled from en_run, shift_clock, shift_count and common signals. The internal nodes of the device can be observed by a proper timing of external signals.In particular : Document Type. SPT File Name FROST_manuale.doc Revision 3 Issued on 03/06/2002 Page 19 of 31 A AURELIA Title: Frost64 - Technical Specifications M i c r o e l e t t r o n i c a S. p. A. - SPT Rev. N. 2 Data: 26/02/02 pulse counting: shift_count LOW, the input of the counter is the inverted common signal. Then the device counts each common pulse, where pulse is a rectangular waveform with HIGH final and initial level and LOW intermediate level - counter readout: shift_count HIGH level, whereas the clock is replaced from en_run and shift_clock. There is a shift if we are a en_run pulse and subsequently (no superimposes ) shift_clock pulse . - Internal node readout . Document Type. SPT File Name FROST_manuale.doc Revision 3 Issued on 03/06/2002 Page 20 of 31 A AURELIA Title: Frost64 - Technical Specifications M i c r o e l e t t r o n i c a S. p. A. SPT Rev. N. 2 Data: 26/02/02 3.6.5 Layout of the digital part The layout is described below: serial_up, owpout ownor, common shift_UD power, ground shift_clock test_enable en_dir shift_count comp_inp serial_down, owpin ownor, common shift_UD The comp_inp is a external signal (from the comparator section in counter mode ), the side signals allow to control the device, top and bottom signals are used for serial reading and overflow signalling. Document Type. SPT File Name FROST_manuale.doc Revision 3 Issued on 03/06/2002 Page 21 of 31 A AURELIA Title: Frost64 - Technical Specifications M i c r o e l e t t r o n i c a S. p. A. SPT Rev. N. 2 Data: 26/02/02 3.6.6 Chip connection The figure shows how the external overflow signal is generated through the connection of internal nodes of each channel : owpin owpout = owpin - owpin signal of the low channel : VDD value ; - ownor and owpout signals of the highly channel : connected owpout = owpin together ; owpout - owpout signal of the intermediate channel : connected to the ownor owpin signal of the channel successive; - owpin of the intermediate channel: connected of the owpout of the previously channel; - ownor of the intermediate channels : connected to the ownor of the previousl and following channel ; If the serial_down and serial up pins of different chips are connected together, a single serial readout chain can be implemented. Note that the common pin is the common input of all analogue channels while in test mode. Document Type. SPT File Name FROST_manuale.doc Revision 3 Issued on 03/06/2002 Page 22 of 31 A AURELIA SPT Rev. N. 2 Data: 26/02/02 Title: Frost64 - Technical Specifications M i c r o e l e t t r o n i c a S. p. A. 4 SPECIFICATIONS 3.7. Absolute maximum rating These are non destructive conditions but normal specification are not guaranteed. PARAMETER POWER SUPPLIES vdda Vddc vdd INOUT DIGITAL INPUTS ANALOG INPUTS DC OUTPUT CURRENTS ANALOG OUT SHORT CIRCUIT CURRENT TEMPERATURE JUNCTION TEMPERATURE CASE TEMPERATURE STORAGE TEMPERATURE With respect to MIN MAX Units vssa vssc vss -0.3 -0.3 -0.05 5.1 5.5 0.05 V V V vss vssa,vssc vss vssa vdda -0.3 -0.3 -20 -20 VDDD+0.3 VDDA+0.3 20 20 V V mA mA -65 150 100 150 C C C 3.8. System specification Specification are given for a typical temperature of 25 C if not otherwise specified. All thermal variation are valid for the temperature range from 10 up to 40 C. 4.6.3 Power Supply vdda vddc vdd vssa vssc gnd Min 4.75 4.75 4.75 Supply of analogue section Supply of discriminator section Supply Supply of analogue section ground of analogue section ground of discriminator section ground of digital section Typ 5 5 5 0 0 0 Max 5.25 5.25 5.25 Unit V V V V V V 4.6.4 Analog Section Some specification are given for two values of the voltage at pin P_Vg , Vg = 0 and -0.2V, that controls the feedback resistance of the charge preamplifier. The other specification are unaffected by this voltage. Temperature 27 C , VDDA = 5V 5% , VDDD = 5V 5% Parameter Total current consumption Gain Document Type. SPT Vg = 0V Min 82 2.53 Typ 110 Preamplifier 3.22 File Name FROST_manuale.doc Max 145 Unit mA Note (1) 4.20 mV/fC (2) Revision 3 Issued on 03/06/2002 Page 23 of 31 A AURELIA SPT Rev. N. 2 Data: 26/02/02 Title: Frost64 - Technical Specifications M i c r o e l e t t r o n i c a S. p. A. Risetime Falltime Vg = -0.2V Vg = 0V Vg = -0.2V Vg = 0V Vg = -0.2 2.50 39 36 16 1.2 Gain Gain Spread Peaking time Rise time Fall time Time spread Input capacitance Input dynamic range NonLinearity ENC Baseline Counting rate 130 200 93 375 0.25 0.82 3.00 3.70 55 105 46 58 x x 2.90 10.3 Preamplifier and shaper 170 210 5 270 370 130 180 625 880 5 3 5 +/- 1 850 0.97 1.11 1 ns (2) us (2) mV/fC % ns (3) (4) (3) ns % pF fC % e- (3) (3) (4) (5) (6) (3) (7) V MHz (1) This correspond to the total current consumption of the chip if the digital part is not switching. (2) Gain , rise and fall time are affected by the voltage at pin Vg which controls the preamplifier feedback resistor. For Vg = 0V high fall time can occur up to 1ms. (3) Input capacitance : 10 pF (4) Spread for channels of the same chip. (5) This include preamplifier and pad capacitance. (6) valid for input charge pulse up to 5 fC; The output buffer doesn't affect the non linearity error. (7) DC voltage at the shaper output (8) Min and max can be set changing the appropriate resistor value 4.6.5 Output Buffer Next table summarize the main characteristics of the output buffer. This buffer does not introduce appreciable distortion in the shaped signal when the capacitive load doesn't exceed 30 pF. Band Ao Rout 10 -300 200 Output Buffer 70 110 -160 -100 340 650 MHz mdB Ohm -3db band amplification in DC output resistance 4.6.6 Discriminator These specification are valid in the following condition: load 200fF, temperature25C, power supply 5V; input pulse signal with Trise=250ns, Tf=600nS, min value equal to 1.1V e max value equal to 1.3V. Vth=1.2V. Parameter min typ max unit vddc 4.5 5 5.5 V Document Type. SPT File Name FROST_manuale.doc Revision 3 note Power supply voltage Issued on 03/06/2002 Page 24 of 31 A AURELIA SPT Rev. N. 2 Data: 26/02/02 Title: Frost64 - Technical Specifications M i c r o e l e t t r o n i c a S. p. A. Temperature P_Vg Idd Iis 0 25 3.6 320 18 170 4 Sigma Propagation delay* rising edge falling edge rising edge falling edge rising edge falling edge Document Type. SPT 85 600 50 0.35 C V A A V/ns Bias voltage Power supply current Max. current ion hysteresis terminal (Vis=5V) Slew-rate rise min typ max unit 10 8 37 54 37 155 37 5 60 150 ns ns ns ns ns ns File Name FROST_manuale.doc Revision 3 note with Vis=1.6 V with Vis=1.6 V with Vis=5 V with Vis=5 V with Vis floating with Vis floating Issued on 03/06/2002 Page 25 of 31 A AURELIA SPT Rev. N. 2 Data: 26/02/02 Title: Frost64 - Technical Specifications M i c r o e l e t t r o n i c a S. p. A. hysteresis variation (Typ, 25C, 5V) The voltage at pin P_vis controls the hysteresis of all the discriminator as indicate in the following table: Vis (V) 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 >3.0 hyst. (mV) 3.9 11.2 19.7 26.4 32 37.7 40.3 43 44.5 4.6.7 3 bit and 6 bit DACs To choose of the more appropriate range and step for both DAC3 and DAC6 the next tables helps to identify the values for Rbias3b and Rbias6. Because of the process spread the values in the table are indicative. DAC6 range can be directly measured via pad DAC_OUT. DAC 6 bit Rbias6b (kOhm) DAC6 range (mV) DAC6 step (mV) 12 1200 19.0 15 980 15.5 19 780 12.4 23 620 9.8 30 500 7.9 37 400 6.3 47 320 5.1 59 250 3.9 75 200 3.2 DAC 3 bit Rbias3b (kOhm) 7.5 Document Type. SPT DAC3 range (mV) 340 DAC3 step (mV) 48.6 9.5 270 38.6 12 220 31.4 15 175 25 19 140 20 23 110 15.7 30 90 12.8 37 70 10 47 57 8.2 File Name FROST_manuale.doc Revision 3 Issued on 03/06/2002 Page 26 of 31 A AURELIA SPT Rev. N. 2 Data: 26/02/02 Title: Frost64 - Technical Specifications M i c r o e l e t t r o n i c a S. p. A. 59 45 6.4 75 36 5.1 4.6.8 Thermal drift Most of the circuit characteristics are not very sensitive to the temperature variation. A table of thermal variation in the range from 10 to 40 C is given in the next table where Reference temperature Tref is 25 C. Parameter Gain Risetime Falltime Gain Peaking time Rise time Fall time ENC Baseline Rbias6b = 75k Rbias6b = 12k Rbias6b = 75k Rbias3b = 7.5k Thermal Drift Unit Preamplifier -8.13 uV/C +86 ps/C -2.3 ns/C Preamplifier and Shaper -0.28 mV/C -0.29 ns/C 0.0 ns/C -0.7 ns/C +2.3 e-/C -1 mV/C DAC6, Output range drift +0.25 mV/C +1.48 mV/C DAC3, Output range drift +12.3 uV/C +142 uV/C Note (1) (1) (1) (1)(2) (1) (1) (1)(2) (1) (3) (3) (3) (3) Note: (1) A charge pulse of 5fC has been considered. (2) The same coefficient is valid at the buffer output (3) Thermal drift of the external resistor has not been considered 4.6.9 Digital section Max Counting rate Max Readout speed Document Type. SPT 1 20 File Name FROST_manuale.doc MHz MHz Revision 3 Issued on 03/06/2002 Page 27 of 31 A AURELIA SPT Rev. N. 2 Data: 26/02/02 Title: Frost64 - Technical Specifications M i c r o e l e t t r o n i c a S. p. A. 4.6.10 Loads The given specification are valid if the capacitive load don't exceed the values indicated in the table. Description Max Capacitive Load (PF) Name Pin Type DAC_OUT 83 A I/O 6 bit DAC output 50 rbias3b 78 A I/O DAC3 bias resistor 100 rbias6b 79 A I/O DAC6 bias resistor 100 BuffOut 114 AO Channel <0> analogue output 30 D_out 106 DO Stream output to program discriminator section 100p ck_out 107 DO Clock output program discriminator section 100p Analog Pads Digital Pads Document Type. SPT File Name FROST_manuale.doc Revision 3 Issued on 03/06/2002 Page 28 of 31 A AURELIA SPT Rev. N. 2 Data: 26/02/02 Title: Frost64 - Technical Specifications M i c r o e l e t t r o n i c a S. p. A. 5 PACKAGED SAMPLES Sample are housed in CQFP120 package. The pin to pad correspondence and bonding diagram are shown below (n.c. = not connected): pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 pad P_in<0> n.c. P_in<1> vssa P_in<4> n.c P_in<5> vssa P_in<12> n.c. P_in<13> vssa P_in<20> n.c P_in<21> vssa vssa P_in<36> n.c. P_in<37> vssa P_in<44> n.c. P_in<45> vssa P_in<52> n.c. P_in<53> vssa P_in<63> Document Type. SPT pin 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 pad n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. P_Test2 vssa vdda vssa vdda P_Rbias3b P_Rbias6b P_Vis P_VREF vssc P_DAC_OUT vddc P_Din P_CkIn SerialDown n.c. n.c. n.c. n.c. n.c. n.c. n.c. pin 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 File Name FROST_manuale.doc pad gnd gnd nc vdd n.c. P_Common n.c. P_ShiftUD n.c. gnd n.c. vdd n.c. P_ShiftCount n.c. n.c. P_TestEnable n.c. gnd n.c. vdd n.c. P_ShiftClock n.c. P_EnDir n.c. gnd n.c. vdd P_OW pin 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 Revision 3 pad n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. vdd SerialUP P_Dout P_CkOut vddc vssc P_Vg P_Gate vdda vssa P_BuffOut vdda vssa P_Test1 n.c. n.c. n.c. n.c. n.c. n.c. n.c. (ground) Issued on 03/06/2002 Page 29 of 31 A AURELIA Title: Frost64 - Technical Specifications M i c r o e l e t t r o n i c a S. p. A. SPT Rev. N. 2 Data: 26/02/02 Figure 10 Document Type. SPT File Name FROST_manuale.doc Revision 3 Issued on 03/06/2002 Page 30 of 31 A AURELIA Title: Frost64 - Technical Specifications M i c r o e l e t t r o n i c a S. p. A. SPT Rev. N. 2 Data: 26/02/02 4. CONTACT US Aurelia Microelettronica S.p.A. - CAEN Group operative office Via Giuntini, 13 - 56023 frazione Navacchio Cascina (PI) - ITALIA Tel. +39 050 754.260 - Fax. +39 050 754.261 E-mail:info@aurelia.micro.it URL: Choose from the web site http://www.caen.it/ CAEN headquarters Via Vetraia, 11 - 55049 - Viareggio (LU) - ITALIA Tel. +39 0584 388.398 - Fax. +39 0584 388.959 E-mail: info@caen.it Document Type. SPT File Name FROST_manuale.doc URL: http://www.caen.it/ Revision 3 Issued on 03/06/2002 Page 31 of 31