MAX9389EHJ+T - Maxim Integrated Products, Inc.

General Description

The MAX9389 is a fully differential, high-speed, low-jitter,

8-to-1 ECL/PECL multiplexer (mux) with dual output

buffers. The device is designed for clock and data distri-

bution applications, and features extremely low propa-

gation delay (310ps typ) and output-to-output skew

(30ps max).

Three single-ended select inputs, SEL0, SEL1, and SEL2,

control the mux function. The mux select inputs are com-

patible with ECL/PECL logic, and are internally refer-

enced to the on-chip reference output (VBB1, VBB2),

nominally VCC - 1.425V. The select inputs accept signals

between VCC and VEE. Internal pulldowns to VEE ensure

a low default condition if the select inputs are left open.

The differential inputs D_, D_ can be configured to

accept a single-ended signal when the unused comple-

mentary input is connected to the on-chip reference

output (VBB1, VBB2). All the differential inputs have

internal bias and clamping circuits that ensure a low

output state when the inputs are left open.

The MAX9389 operates with a wide supply range VCC -

VEE of 2.375V to 5.5V. The device is offered in 32-pin

TQFP and thin QFN packages, and operates over the

-40°C to +85°C extended temperature range.

Applications

High-Speed Telecom and Datacom Applications

Central-Office Backplane Clock Distribution

DSLAM/DLC

Features

♦310ps Propagation Delay

♦Guaranteed 2.7GHz Operating Frequency

♦0.3psRMS Random Jitter

♦<30ps Output-to-Output Skew

♦-2.375V to -5.5V Supplies for Differential

LVECL/ECL

♦+2.375V to +5.5V Supplies for Differential

LVPECL/PECL

♦Outputs Low for Open Inputs

♦Dual Output Buffers

♦>2kV ESD Protection (Human Body Model)

MAX9389

Differential 8:1 ECL/PECL Multiplexer with

Dual Output Buffers

________________________________________________________________ Maxim Integrated Products 1

MAX9389

TQFP

TOP VIEW

32 28

293031 25

VCC

VEE

VCC

SEL2

10 13 15

14 1611 12

23 SEL0

24 SEL1

VCC

VEE

8VCC

VBB1

VBB2

1VCC

Pin Configurations

Ordering Information

VBB1

VBB2

VCC

VEE

VCC

VEE

MUX

8:1

180kΩ

180kΩ165kΩ180kΩ

232kΩ

SEL0

SEL1

SEL2

D4 Q0

MAX9389

VEE

Functional Diagram

19-2688; Rev 0; 1/03

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

PART TEMP RANGE PIN-PACKAGE

MAX9389EHJ -40°C to +85°C 32 TQFP

MAX9389ETJ* -40°C to +85°C 32 Thin QFN

Pin Configurations continued at end of data sheet.

*Future product—contact factory for availability.

MAX9389

Differential 8:1 ECL/PECL Multiplexer with

Dual Output Buffers

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

DC ELECTRICAL CHARACTERISTICS

(VCC - VEE = 2.375V to 5.5V, outputs loaded with 50Ω±1% to VCC - 2V. Typical values are at VCC - VEE = 3.3V, VIHD = VCC - 1V,

VILD = VCC - 1.5V, unless otherwise noted.) (Notes 1–4)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

VCC - VEE ..............................................................-0.3V to +6.0V

Inputs (D_, D_, SEL_) to VEE ......................-0.3V to (VCC + 0.3V)

D_ to D_...............................................................................±3.0V

Continuous Output Current .................................................50mA

Surge Output Current........................................................100mA

VBB_ Sink/Source Current ..............................................±600µA

Continuous Power Dissipation (TA= +70°C)

32-Lead TQFP (derate 13.1mW/°C above +70°C) ...1047mW

θJA in Still Air..........................................................+76°C/W

θJC .........................................................................+25°C/W

32-Lead QFN (derate 21.3mW/°C above +70°C) .....1702mW

θJA in Still Air..........................................................+47°C/W

θJC ...........................................................................+2°C/W

Operating Temperature Range ...........................-40°C to +85°C

Junction Temperature......................................................+150°C

Storage Temperature Range .............................-65°C to +150°C

ESD Protection

Human Body Model (D_, D_, Q_, Q_, SEL_, VBB_) .............≥2kV

Soldering Temperature (10s) ...........................................+300°C

-40°C +25°C +85°C

PARAMETER SYMBOL CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS

INPUT (D_, D_, SEL_)

Single-Ended

Input High

Voltage

VIH VBB_ connected to the

unused input, Figure 1

VCC -

1.225

VCC -

0.880

VCC -

1.225

VCC -

0.880

VCC -

1.225

VCC -

0.880 V

Single-Ended

Input Low

Voltage

VIL VBB_ connected to the

unused input, Figure 1

VCC -

1.945

VCC -

1.625

VCC -

1.945

VCC -

1.625

VCC -

1.945

VCC -

1.625 V

Differential Input

High Voltage VIHD Figure 1 VEE +

1.2 VCC VEE +

1.2 VCC V

Differential Input

Low Voltage VILD Figure 1 VEE VCC -

0.095 VEE VCC -

0.095 V

VCC - VEE <

3.0V 0.095 VCC -

VEE 0.095 VCC -

VEE

Differential Input

Voltage

VIHD -

VILD Figure 1

VCC - VEE ≥

3.0V 0.095 3.000 0.095 3.000 0.095 3.000

Input Current IIN VIH, VIL, VIHD, VILD -60 +60 -60 +60 -60 +60 µA

OUTPUT (Q_, Q_)

Single-Ended

Output High

Voltage

VOH Figure 2 VCC -

1.145

VCC -

0.895

VCC -

1.145

VCC -

0.895

VCC -

1.145

VCC -

0.895 V

MAX9389

Differential 8:1 ECL/PECL Multiplexer with

Dual Output Buffers

_______________________________________________________________________________________ 3

DC ELECTRICAL CHARACTERISTICS (continued)

(VCC - VEE = 2.375V to 5.5V, outputs loaded with 50Ω±1% to VCC - 2V. Typical values are at VCC - VEE = 3.3V, VIHD = VCC - 1V,

VILD = VCC - 1.5V, unless otherwise noted.) (Notes 1–4)

-40°C +25°C +85°C

PARAMETER SYMBOL CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS

Single-Ended

Output Low

Voltage

VOL Figure 2 VCC -

1.945

VCC -

1.695

VCC -

1.945

VCC -

1.695

VCC -

1.945

VCC -

1.695 V

Differential

Output Voltage

VOH -

VOL Figure 2 650 830 650 840 650 840 mV

REFERENCE OUTPUT (VBB_ )

Reference

Voltage Output

VBB1

VBB2

IBB1 + IBB2 = ±0.5mA

(Note 5)

VCC -

1.525

VCC -

1.425

VCC -

1.325

VCC -

1.525

VCC -

1.425

VCC -

1.325

VCC -

1.525

VCC -

1.425

VCC -

1.325 V

POWER SUPPLY

Supply Current IEE (Note 6) 50 70 53 70 55 70 mA

AC ELECTRICAL CHARACTERISTICS

(VCC - VEE = 2.375V to 5.5V, outputs loaded with 50Ω±1% to VCC - 2V, VIHD - VILD = 0.15V to 1V, fIN ≤2.5GHz, input duty cycle = 50%,

input transition time = 125ps (20% to 80%). Typical values are at VCC - VEE = 3.3V, VIHD = VCC - 1V, VILD = VCC - 1.5V, fIN = 622 MHz,

input duty cycle = 50%, input transition time = 125ps (20% to 80%.)) (Note 7)

-40°C +25°C +85°C

PARAMETER SYMBOL CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS

Differential Input-

to-Output Delay

tPLHD,

tPHLD Figure 2 216 301 370 237 310 416 255 329 456 ps

SEL_-to-Output

Delay

tPLH2,

tPHL2

Figure 4, input

transition time = 500ps

(20% to 80%) (Note 8)

1.34 2 1.25 2 1.44 2 ns

Output-to-Output

Skew tSKOO Figure 5 (Note 9) 15 15 30 ps

Input-to-Output

Skew tSKIO Figure 6 (Note 10) 50 50 55 ps

Part-to-Part

Skew tSKPP (Note 11) 125 150 160 ps

fIN = 156MHz 0.3 1.15 0.3 1.15 0.3 1.15

fIN = 622MHz 0.3 1.15 0.3 1.15 0.3 1.15

Added Random

Jitter (Note 12) tRJ Clock

pattern fIN = 2.5GHz 0.3 1.15 0.3 1.15 0.3 1.15

psRMS

fIN = 156Mbps 33 95 33 95 33 95

Added

Deterministic

Jitter (Note 12)

TDJ PRBS

223 - 1 fIN = 622Mbps 21 61 21 61 21 61

psP-P

MAX9389

Differential 8:1 ECL/PECL Multiplexer with

Dual Output Buffers

4 _______________________________________________________________________________________

AC ELECTRICAL CHARACTERISTICS (continued)

(VCC - VEE = 2.375V to 5.5V, outputs loaded with 50Ω±1% to VCC - 2V, VIHD - VILD = 0.15V to 1V, fIN ≤2.5GHz, input duty cycle = 50%,

input transition time = 125ps (20% to 80%). Typical values are at VCC - VEE = 3.3V, VIHD = VCC - 1V, VILD = VCC - 1.5V, fIN = 622 MHz,

input duty cycle = 50%, input transition time = 125ps (20% to 80%.)) (Note 7)

-40°C +25°C +85°C

PARAMETER SYMBOL CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS

Switching

Frequency fMAX VOH - VOL ≥ 300mV,

Figure 2 2.7 2.7 2.7 GHz

Select Toggle

Frequency fSEL VOH - VOL ≥ 300mV,

Figure 4 100 100 100 MHz

Output Rise and

Fall Time

(20% to 80%)

tR, tFFigure 2 67 105 138 74 117 155 81 128 165 ps

Note 1: Measurements are made with the device in thermal equilibrium.

Note 2: Current into an I/O pin is defined as positive. Current out of an I/O pin is defined as negative.

Note 3: DC parameters production tested at TA= +25°C and guaranteed by design over the full operating temperature range.

Note 4: Single-ended data input operation using VBB_ is limited to (VCC - VEE) ≥3.0V.

Note 5: Use VBB_ only for inputs that are on the same device as the VBB_ reference.

Note 6: All pins open except VCC and VEE.

Note 7: Guaranteed by design and characterization. Limits are set at ±6 sigma.

Note 8: Measured from the 50% point of the input signal with the 50% point equal to VBB, to the 50% point of the output signal.

Note 9: Measured between outputs of the same part at the signal crossing points for a same-edge transition.

Note 10:Measured between input-to-output paths of the same part at the signal crossing points for a same-edge transition of the

differential input signal.

Note 11:Measured between outputs of different parts at the signal crossing points under identical conditions for a same-edge

transition.

Note 12:Device jitter added to the differential input signal.

SUPPLY CURRENT vs. TEMPERATURE

MAX9389 toc01

TEMPERATURE (°C)

SUPPLY CURRENT (mA)

6035-15 10

42.5

45.0

47.5

50.0

52.5

55.0

57.5

60.0

40.0

-40 85

ALL PINS ARE OPEN EXCEPT VCC AND VEE

DIFFERENTIAL OUTPUT VOLTAGE (VOH - VOL)

vs. FREQUENCY

MAX9389 toc02

FREQUENCY (GHz)

DIFFERENTIAL OUTPUT VOLTAGE (mV)

2.52.01.51.00.5

300

400

500

600

700

800

900

200

0 3.0

OUTPUT RISE/FALL TIME

vs. TEMPERATURE

MAX9389 toc03

RISE/FALL TIME (ps)

100

110

120

130

140

150

TEMPERATURE (°C)

603510-15-40

RISE

FALL

Typical Operating Characteristics

(VCC - VEE = 3.3V, VIHD = VCC - 1V, VILD = VCC - 1.5V, outputs loaded with 50Ω±1% to VCC - 2V, fIN = 622MHz, input duty cycle = 50%,

input transition time = 125ps (20% to 80%), unless otherwise noted.)

MAX9389

Differential 8:1 ECL/PECL Multiplexer with

Dual Output Buffers

_______________________________________________________________________________________ 5

PROPAGATION DELAY vs. HIGH VOLTAGE

OF DIFFERENTIAL INPUT (VIHD)

MAX9389 toc04

VIHD (V)

PROPAGATION DELAY (ps)

3.02.72.42.11.81.5

276

292

308

324

340

260

1.2 3.3

VIHD - VILD = 150mV

PROPAGATION DELAY vs. TEMPERATURE

MAX9389 toc05

TEMPERATURE (°C)

PROPAGATION DELAY (ps)

603510-15

270

290

310

330

350

250

-40

tPHL

tPLH

Typical Operating Characteristics (continued)

(VCC - VEE = 3.3V, VIHD = VCC - 1V, VILD = VCC - 1.5V, outputs loaded with 50Ω±1% to VCC - 2V, fIN = 622MHz, input duty cycle = 50%,

input transition time = 125ps (20% to 80%), unless otherwise noted.)

Pin Description

PIN NAME FUNCTION

1, 8, 22,

26, 29 VCC Positive Supply Input. Bypass each VCC to VEE with 0.1µF and 0.01µF ceramic capacitors. Place the

capacitors as close to the device as possible with the smaller value capacitor closest to the device.

BB2

Reference Output Voltage 2. Connect to the inverting or noninverting data input to provide a

reference for single-ended operation. When used, bypass VBB2 to VCC with a 0.01µF ceramic

capacitor. Otherwise leave open.

BB1

Reference Output Voltage 1. Connect to the inverting or noninverting data input to provide a

reference for single-ended operation. When used, bypass VBB1 to VCC with a 0.01µF ceramic

capacitor. Otherwise leave open.

4 D0 Noninverting Differential Input 0. Internal 232kΩ to VCC and 180kΩ to VEE.

5D0 Inverting Differential Input 0. Internal 180kΩ to VCC and 180kΩ to VEE.

6 D1 Noninverting Differential Input 1. Internal 232kΩ to VCC and 180kΩ to VEE.

7D1 Inverting Differential Input 1. Internal 180kΩ to VCC and 180kΩ to VEE.

9 D2 Noninverting Differential Input 2. Internal 232kΩ to VCC and 180kΩ to VEE.

10 D2 Inverting Differential Input 2. Internal 180kΩ to VCC and 180kΩ to VEE.

11 D3 Noninverting Differential Input 3. Internal 232kΩ to VCC and 180kΩ to VEE.

12 D3 Inverting Differential Input 3. Internal 180kΩ to VCC and 180kΩ to VEE.

13 D4 Noninverting Differential Input 4. Internal 232kΩ to VCC and 180kΩ to VEE.

14 D4 Inverting Differential Input 4. Internal 180kΩ to VCC and 180kΩ to VEE.

15 D5 Noninverting Differential Input 5. Internal 232kΩ to VCC and 180kΩ to VEE.

16 D5 Inverting Differential Input 5. Internal 180kΩ to VCC and 180kΩ to VEE.

17, 32 VEE Negative Supply Input

18 D6 Noninverting Differential Input 6. Internal 232kΩ to VCC and 180kΩ to VEE.

19 D6 Inverting Differential Input 6. Internal 180kΩ to VCC and 180kΩ to VEE.

MAX9389

Differential 8:1 ECL/PECL Multiplexer with

Dual Output Buffers

6 _______________________________________________________________________________________

Pin Description (continued)

PIN NAME FUNCTION

20 D7 Noninverting Differential Input 7. Internal 232kΩ to VCC and 180kΩ to VEE.

21 D7 Inverting Differential Input 7. Internal 180kΩ to VCC and 180kΩ to VEE.

23 SEL0 Select Logic Input 0. Internal 165kΩ pulldown to VEE.

24 SEL1 Select Logic Input 1. Internal 165kΩ pulldown to VEE.

25 SEL2 Select Logic Input 2. Internal 165kΩ pulldown to VEE.

27 Q1 Inverting Output 1. Typically terminate with 50Ω resistor to VCC - 2V.

28 Q1 Noninverting Output 1. Typically terminate with 50Ω resistor to VCC - 2V.

30 Q0 Inverting Output 0. Typically terminate with 50Ω resistor to VCC - 2V.

31 Q0 Noninverting Output 0. Typically terminate with 50Ω resistor to VCC - 2V.

—EP Exposed Pad (QFN Package Only). Connect to VEE.

DIFFERENTIAL INPUT VOLTAGE DEFINITION

VCC

VEE

VCC

VIH

VIL

VBB

VEE

VIHD - VILD

VIHD (MAX)

VILD (MAX)

VIHD (MIN)

VILD (MIN)

VIHD - VILD

SINGLE-ENDED INPUT VOLTAGE DEFINITION

Figure 1. Input Definitions

VOH

VOL

VIHD - VILD

VOH - VOL

VIHD

tPLHD

tRtF

tPHLD

VILD

20%

80%

DIFFERENTIAL OUTPUT

WAVEFORM 0V (DIFFERENTIAL)

20%

80%

Q_ - Q_

Figure 2. Differential Input-to-Output Propagation Delay Timing

Diagram

VOH - VOL

tPLH1 tPHL1

VOH

VOL

VIH

VBB

VBB VIL

D_ WHEN D_ = VBB

Figure 3. Single-Ended Input-to-Output Propagation Delay

Timing Diagram

VOH - VOL

tPLH2 tPHL2

VOH

VOL

VIH

VIHD

VBB VIL

VILD

VIHD - VILD

D_, D1

SEL_ = VIL OR OPEN

SELO

Figure 4. Select Input (SEL0) to Output (Q_,

) Delay Timing

Diagram

Detailed Description

The MAX9389 is a fully differential, high-speed, low-jitter

8-to-1 ECL/PECL mux with dual output buffers. The

device is designed for clock and data distribution appli-

cations, and features extremely low propagation delay

(310ps typ) and output-to-output skew (30ps max).

Three single-ended select inputs, SEL0, SEL1, and

SEL2, control the mux function (see Table 1). The mux

select inputs are compatible with ECL/PECL logic, and

are internally referenced to the on-chip reference output

(VBB1, VBB2), nominally VCC - 1.425V. The select inputs

accept signals between VCC and VEE. Internal 165kΩ

pulldowns to VEE ensure a low default condition if the

select inputs are left open. Leaving SEL0, SEL1, and

SEL2 open selects the D0, D0 inputs by default.

The differential inputs D_, D_ can be configured to

accept a single-ended signal when the unused comple-

mentary input is connected to the on-chip reference

voltage (VBB1, VBB2). Voltage reference outputs VBB1

and VBB2 provide the reference voltage needed for sin-

gle-ended operations. A single-ended input of at least

VBB_ ±100mV or a differential input of at least 100mV

switches the outputs to the VOH and VOL levels speci-

fied in the DC Electrical Characteristics table. The maxi-

mum magnitude of the differential input from D_ to D_ is

±3.0V. This limit also applies to the difference between a

single-ended input and any reference voltage input.

*Default output when SEL0, SEL1, and SEL2 are left open.

Single-Ended Operation

The recommended supply voltage for single-ended

operation is 3.0V to 3.8V. The differential inputs (D_,

D_) can be configured to accept single-ended inputs

when operating at supply voltages greater than 2.725V.

In single-ended mode operation, the unused comple-

mentary input needs to be connected to the on-chip

reference voltage, VBB1 or VBB2, as a reference. For

example, the differential D_, D_ inputs are converted to

a noninverting, single-ended input by connecting VBB1

or VBB2 to D_ and connecting the single-ended input to

D_. Similarly, an inverting input is obtained by connect-

ing VBB1 or VBB2 to D_ and connecting the single-

ended input to D_. The single-ended input can be

driven to VCC or VEE or with a single-ended

LVPECL/LVECL signal.

MAX9389

Differential 8:1 ECL/PECL Multiplexer with

Dual Output Buffers

_______________________________________________________________________________________ 7

tSKOO tSKOO

Figure 5. Output-to-Output Skew (tSKOO) Definition

D1–D7

tSKIO = | tPLHD* - tPLHD** | OR | tPHLD* - tPHLD** |

tPLHD*t

PHLD*

tPLHD** tPHLD**

Figure 6. Input-to-Output Skew (tSKIO) Definition

Table 1. Mux Select Input Truth Table

DATA

OUTPUT SEL0 SEL1 SEL2

D0* L or open L or open L or open

D1 H L or open L or open

D2 L or open H L or open

D3 H H L or open

D4 L or open L or open H

D5 H L or open H

D6 L or open H H

D7 H H H

MAX9389

In single-ended operation, ensure that the supply volt-

age (VCC -VEE) is greater than 2.725V. The input high

minimum level must be at least (VEE + 1.2V) or higher

for proper operation. The reference voltage VBB must

be at least (VEE + 1.2V) because it becomes the high-

level input when a single-ended input swings below it.

The minimum VBB output for the MAX9389 is (VCC -

1.525V). Substituting the minimum VBB output for (VBB

= VEE + 1.2V) results in a minimum supply (VCC - VEE)

of 2.725V. Rounding up to standard supplies gives the

recommended single-ended operating supply ranges

(VCC - VEE) of 3.0V to 5.5V.

When using the VBB reference output, bypass it with a

0.01µF ceramic capacitor to VCC. If VBB is not being

used, leave it unconnected. The VBB reference can

source or sink a total of 0.5mA (shared between VBB1

and VBB2), which is sufficient to drive eight inputs.

Applications Information

Output Termination

Terminate each output with a 50Ωto VCC - 2V or use an

equivalent Thevenin termination. Terminate each Q_

and Q_ output with identical termination for minimal dis-

tortion. When a single-ended signal is taken from the

differential output, terminate both Q_ and Q_.

Ensure that the output current does not exceed the cur-

rent limits specified in the Absolute Maximum Ratings

table. Under all operating conditions, the device’s total

thermal limits should not be exceeded.

Supply Bypassing

Bypass each VCC to VEE with high-frequency surface-

mount ceramic 0.1µF and 0.01µF capacitors. For PECL,

bypass each VCC to VEE. For ECL, bypass each VEE to

VCC. Place the capacitors as close to the device as pos-

sible with the 0.01µF capacitor closest to the device pins.

Use multiple vias when connecting the bypass capacitors

to ground. When using the VBB1 or VBB2 reference out-

puts, bypass each one with a 0.01µF ceramic capacitor

to VCC. If the VBB1 or VBB2 reference outputs are not

used, they can be left open.

Traces

Circuit board trace layout is very important to maintain the

signal integrity of high-speed differential signals.

Maintaining integrity is accomplished in part by reducing

signal reflections and skew, and increasing common-

mode noise immunity.

Signal reflections are caused by discontinuities in the

50Ωcharacteristic impedance of the traces. Avoid

discontinuities by maintaining the distance between

differential traces, not using sharp corners or using

vias. Maintaining distance between the traces also

increases common-mode noise immunity. Reducing

signal skew is accomplished by matching the electrical

length of the differential traces.

Chip Information

TRANSISTOR COUNT: 716

PROCESS: Bipolar

Differential 8:1 ECL/PECL Multiplexer with

Dual Output Buffers

8 _______________________________________________________________________________________

VEE

VCC

25 SEL2

16D5

VEE

NOTE: VEE IS CONNECTED

TO THE UNDERSIDE

METAL SLUG.

VCC

SEL0

VCC

VBB1

VBB2

MAX9389

THIN QFN

1VCC 24 SEL1

TOP VIEW

Pin Configurations (continued)

MAX9389

Differential 8:1 ECL/PECL Multiplexer with

Dual Output Buffers

_______________________________________________________________________________________ 9

Package Information

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,

go to www.maxim-ic.com/packages.)

32L TQFP, 5x5x01.0.EPS

MAX9389

Differential 8:1 ECL/PECL Multiplexer with

Dual Output Buffers

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

10 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

Package Information (continued)

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,

go to www.maxim-ic.com/packages.)

QFN THIN.EPS

(ND-1) X e

PIN # 1

I.D.

(NE-1) X e

E/2

0.08 C

0.10 C

A1 A3

DETAIL A

0.15 C B

0.15 C A

DOCUMENT CONTROL NO.

21-0140

PACKAGE OUTLINE

16, 20, 28, 32L, QFN THIN, 5x5x0.8 mm

PROPRIETARY INFORMATION

APPROVAL

TITLE:

REV.

E2/2

0.10 M C A B

PIN # 1 I.D.

0.35x45

D/2 D2/2

e e

21-0140

REV.DOCUMENT CONTROL NO.APPROVAL

PROPRIETARY INFORMATION

TITLE:

COMMON DIMENSIONS EXPOSED PAD VARIATIONS

1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.

2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.

3. N IS THE TOTAL NUMBER OF TERMINALS.

4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1

SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE

ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE.

5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm

FROM TERMINAL TIP.

6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.

7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.

8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.

9. DRAWING CONFORMS TO JEDEC MO220.

NOTES:

10. WARPAGE SHALL NOT EXCEED 0.10 mm.

PACKAGE OUTLINE

16, 20, 28, 32L, QFN THIN, 5x5x0.8 mm