PCA8574AD,512 - NXP Semiconductors / Philips Semiconductors

1. General description

The PCA8574/74A provide general purpose remote I/O expansion for most

microcontroller families via the two-line bidirectional I2C-bus (serial clock (SCL), serial

data (SDA)).

The devices consist of an 8-bit quasi-bidirectional port and an I2C-bus interface. The

PCA8574/74A have low current consumption and include latched outputs with 25 mA high

current drive capability for directly driving LEDs.

The PCA8574/74A also possess an interrupt line (INT) that can be connected to the

interrupt logic of the microcontroller. By sending an interrupt signal on this line, the remote

I/O can inform the microcontroller if there is incoming data on its ports without having to

communicate via the I2C-bus.

The internal Power-On Reset (POR) initializes the I/Os as inputs.

2. Features

n400 kHz I2C-bus interface

n2.3 V to 5.5 V operation with 5.5 V tolerant I/Os

n8-bit remote I/O pins that default to inputs at power-up

nLatched outputs with 25 mA sink capability for directly driving LEDs

nTotal package sink capability of 200 mA

nActive LOW open-drain interrupt output

n8 programmable slave addresses using 3 address pins

nReadable device ID (manufacturer, device type, and revision)

nLow standby current (10 µA max.)

n−40 °C to +85 °C operation

nESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per

JESD22-A115, and 1000 V CDM per JESD22-C101

nLatch-up testing is done to JEDEC standard JESD78 which exceeds 100 mA

nPackages offered: DIP16, SO16, TSSOP16, SSOP20

3. Applications

nLED signs and displays

nServers

nIndustrial control

nMedical equipment

nPLCs

PCA8574/74A

Remote 8-bit I/O expander for I2C-bus with interrupt

Rev. 02 — 14 May 2007 Product data sheet

Product data sheet Rev. 02 — 14 May 2007 2 of 27

NXP Semiconductors PCA8574/74A

Remote 8-bit I/O expander for I2C-bus with interrupt

nCellular telephones

nGaming machines

nInstrumentation and test measurement

4. Ordering information

5. Block diagram

Table 1. Ordering information

Type number Topside

mark Package

Name Description Version

PCA8574D PCA8574D SO16 plastic small outline package; 16 leads; body width 7.5 mm SOT162-1

PCA8574AD PCA8574AD

PCA8574N PCA8574N DIP16 plastic dual in-line package; 16 leads (300 mil); long body SOT38-1

PCA8574AN PCA8574AN

PCA8574PW PCA8574 TSSOP16 plastic thin shrink small outline package; 16 leads;

body width 4.4 mm SOT403-1

PCA8574APW PA8574A

PCA8574TS PCA8574 SSOP20 plastic shrink small outline package; 20 leads;

body width 4.4 mm SOT266-1

PCA8574ATS PCA8574A

Fig 1. Block diagram of PCA8574/74A

002aac677

INT

I2C-BUS

CONTROL

INTERRUPT

LOGIC

PCA8574

PCA8574A LP FILTER

AD0

AD1

AD2

INPUT

FILTER SHIFT

SDA

SCL 8 BITS

write pulse

read pulse

POWER-ON

RESET

VDD

VSS

I/O

PORT P0 to P7

Product data sheet Rev. 02 — 14 May 2007 3 of 27

NXP Semiconductors PCA8574/74A

Remote 8-bit I/O expander for I2C-bus with interrupt

6. Pinning information

6.1 Pinning

Fig 2. Simpliﬁed schematic diagram of P0 to P7

002aac109

write pulse

read pulse

CI S

power-on reset

data from Shift Register

Itrt(pu)

100 µAIOH

IOL

VDD

P0 to P7

VSS

CI S

data to Shift Register to interrupt logic

Fig 3. Pin conﬁguration for DIP16 Fig 4. Pin conﬁguration for SO16

PCA8574N

PCA8574AN

AD0 VDD

AD1 SDA

AD2 SCL

P0 INT

P1 P7

P2 P6

P3 P5

VSS P4

002aac679

PCA8574D

PCA8574AD

AD0 VDD

AD1 SDA

AD2 SCL

P0 INT

P1 P7

P2 P6

P3 P5

VSS P4

002aac678

Product data sheet Rev. 02 — 14 May 2007 4 of 27

NXP Semiconductors PCA8574/74A

Remote 8-bit I/O expander for I2C-bus with interrupt

6.2 Pin description

Fig 5. Pin conﬁguration for TSSOP16 Fig 6. Pin conﬁguration for SSOP20

PCA8574PW

PCA8574APW

AD0 VDD

AD1 SDA

AD2 SCL

P0 INT

P1 P7

P2 P6

P3 P5

VSS P4

002aac941

15 PCA8574TS

PCA8574ATS

INT P7

SCL P6

n.c. n.c.

SDA P5

VDD P4

AD0 VSS

AD1 P3

n.c. n.c.

AD2 P2

P0 P1

002aac680

Table 2. Pin description for DIP16, SO16, TSSOP16

Symbol Pin Description

AD0 1 address input 0

AD1 2 address input 1

AD2 3 address input 2

P0 4 quasi-bidirectional I/O 0

P1 5 quasi-bidirectional I/O 1

P2 6 quasi-bidirectional I/O 2

P3 7 quasi-bidirectional I/O 3

VSS 8 supply ground

P4 9 quasi-bidirectional I/O 4

P5 10 quasi-bidirectional I/O 5

P6 11 quasi-bidirectional I/O 6

P7 12 quasi-bidirectional I/O 7

INT 13 interrupt output (active LOW)

SCL 14 serial clock line

SDA 15 serial data line

VDD 16 supply voltage

Product data sheet Rev. 02 — 14 May 2007 5 of 27

NXP Semiconductors PCA8574/74A

Remote 8-bit I/O expander for I2C-bus with interrupt

Table 3. Pin description for SSOP20

Symbol Pin Description

INT 1 interrupt output (active LOW)

SCL 2 serial clock line

n.c. 3 not connected

SDA 4 serial data line

VDD 5 supply voltage

AD0 6 address input 0

AD1 7 address input 1

n.c. 8 not connected

AD2 9 address input 2

P0 10 quasi-bidirectional I/O 0

P1 11 quasi-bidirectional I/O 1

P2 12 quasi-bidirectional I/O 2

n.c. 13 not connected

P3 14 quasi-bidirectional I/O 3

VSS 15 supply ground

P4 16 quasi-bidirectional I/O 4

P5 17 quasi-bidirectional I/O 5

n.c. 18 not connected

P6 19 quasi-bidirectional I/O 6

P7 20 quasi-bidirectional I/O 7

Product data sheet Rev. 02 — 14 May 2007 6 of 27

NXP Semiconductors PCA8574/74A

Remote 8-bit I/O expander for I2C-bus with interrupt

7. Functional description

Refer to Figure 1 “Block diagram of PCA8574/74A”.

7.1 Device address

Following a START condition, the bus master must send the address of the slave it is

accessing and the operation it wants to perform (read or write). The address of the

PCA8574/74A is shown in Figure 7. Slave address pins AD2, AD1, and AD0 choose 1 of

8 slave addresses. To conserve power, no internal pull-up resistors are incorporated on

AD2, AD1, and AD0. Address values depending on AD2, AD1, and AD0 can be found in

Table 4 “PCA8574 address map” and Table 5 “PCA8574A address map”.

Remark: When using the PCA8574A, the General Call address (0000 0000b) and the

Device ID address (1111 100Xb) are reserved and cannot be used as device address.

Failure to follow this requirement will cause the PCA8574A not to acknowledge.

The last bit of the ﬁrst byte deﬁnes the operation to be performed. When set to logic 1 a

read is selected, while a logic 0 selects a write operation.

When AD2, AD1 and AD0 are held to VDD or VSS, the same address as the PCF8574 or

PCF8574A is applied.

7.1.1 Address maps

Fig 7. PCA8574/74A address

R/W

002aab636

A6 A5 A4 A3 A2 A1 A0

programmable

slave address

Table 4. PCA8574 address map

A6 A5 A4 A3 A2 A1 A0 Address

010000020h

010000121h

010001022h

010001123h

010010024h

010010125h

010011026h

010011127h

Product data sheet Rev. 02 — 14 May 2007 7 of 27

NXP Semiconductors PCA8574/74A

Remote 8-bit I/O expander for I2C-bus with interrupt

8. I/O programming

8.1 Quasi-bidirectional I/O architecture

The PCA8574/74A’s 8 ports (see Figure 2) are entirely independent and can be used

either as input or output ports. Input data is transferred from the ports to the

microcontroller in the Read mode (see Figure 9). Output data is transmitted to the ports in

the Write mode (see Figure 8).

This quasi-bidirectional I/O can be used as an input or output without the use of a control

signal for data directions. At power-on the I/Os are HIGH. In this mode only a current

source (IOH) to VDD is active. An additional strong pull-up to VDD (Itrt(pu)) allows fast rising

edges into heavily loaded outputs. These devices turn on when an output is written HIGH,

and are switched off by the negative edge of SCL. The I/Os should be HIGH before being

used as inputs. After power-on, as all the I/Os are set HIGH, all of them can be used as

inputs. Any change in setting of the I/Os as either inputs or outputs can be done with the

write mode.

Remark: If a HIGH is applied to an I/O which has been written earlier to LOW, a large

current (IOL) will ﬂow to VSS.

8.2 Writing to the port (Output mode)

To write, the master (microcontroller) ﬁrst addresses the slave device. By setting the last

bit of the byte containing the slave address to logic 0 the write mode is entered. The

PCA8574/74A acknowledges and the master sends the data byte for P7 to P0 and is

acknowledged by the PCA8574/74A. The 8-bit data is presented on the port lines after it

has been acknowledged by the PCA8574/74A.

The number of data bytes that can be sent successively is not limited. The previous data

is overwritten every time a data byte has been sent.

Table 5. PCA8574A address map

A6 A5 A4 A3 A2 A1 A0 Address

011100038h

011100139h

01110103Ah

01110113Bh

01111003Ch

01111013Dh

01111103Eh

01111113Fh

Product data sheet Rev. 02 — 14 May 2007 8 of 27

NXP Semiconductors PCA8574/74A

Remote 8-bit I/O expander for I2C-bus with interrupt

8.3 Reading from a port (Input mode)

All ports programmed as input should be set to logic 1. To read, the master

(microcontroller) ﬁrst addresses the slave device after it receives the interrupt. By setting

the last bit of the byte containing the slave address to logic 1 the Read mode is entered.

The data bytes that follow on the SDA are the values on the ports.

If the data on the input port changes faster than the master can read, this data may be

lost.

Fig 8. Write mode (output)

A5 A4 A3 A2 A1 A0 0 ASA6

slave address

START condition R/W acknowledge

from slave

002aac120

P6 1P7

data 1

acknowledge

from slave

12345678SCL 9

SDA A

acknowledge

from slave

write to port

data output from port

tv(Q)

data 2

DATA 2 VALID

P4 P3 P2 P1 P0 P7 P4 P3 P2 P1 P00

tv(Q) DATA 1 VALID

P5 output voltage

Itrt(pu) IOH

P5 pull-up output current

td(rst)

INT

A LOW-to-HIGH transition of SDA while SCL is HIGH is deﬁned as the STOP condition (P). Transfer of data can be stopped

at any moment by a STOP condition. When this occurs, data present at the last acknowledge phase is valid (Output mode).

Input data is lost.

Fig 9. Read input port register

A5 A4 A3 A2 A1 A0 1 ASA6

slave address

START condition R/W acknowledge

from slave

002aac121

data from port

acknowledge

from master

SDA 1

no acknowledge

from master

read from

port

data into

port

data from port

DATA 1

DATA 4

INT

DATA 4

DATA 2

DATA 3

STOP

condition

tv(Q) td(rst)

th(D) tsu(D)

td(rst)

Product data sheet Rev. 02 — 14 May 2007 9 of 27

NXP Semiconductors PCA8574/74A

Remote 8-bit I/O expander for I2C-bus with interrupt

8.4 Power-on reset

When power is applied to VDD, an internal Power-On Reset (POR) holds the

PCA8574/74A in a reset condition until VDD has reached VPOR. At that point, the reset

condition is released and the PCA8574/74A registers and I2C-bus/SMBus state machine

will initialize to their default states. Thereafter VDD must be lowered below 0.2 V to reset

the device.

8.5 Interrupt output (INT)

The PCA8574/74A provides an open-drain interrupt (INT) which can be fed to a

corresponding input of the microcontroller (see Figure 8,Figure 9, and Figure 10). This

gives these chips a kind of master function which can initiate an action elsewhere in the

system.

An interrupt is generated by any rising or falling edge of the port inputs. After time tv(D) the

signal INT is valid.

The interrupt disappears when data on the port is changed to the original setting or data is

read from or written to the device which has generated the interrupt.

In the write mode, the interrupt may become deactivated (HIGH) on the rising edge of the

write to port pulse. On the falling edge of the write to port pulse the interrupt is deﬁnitely

deactivated (HIGH).

The interrupt is reset in the read mode on the rising edge of the read from port pulse.

During the resetting of the interrupt itself, any changes on the I/Os may not generate an

interrupt. After the interrupt is reset any change in I/Os will be detected and transmitted as

an INT.

Fig 10. Application of multiple PCA8574s with interrupt

002aac682

VDD

MICROCOMPUTER

INT

PCA8574

INT

PCA8574

INT

device 1 device 2

PCA8574

INT

device 8

Product data sheet Rev. 02 — 14 May 2007 10 of 27

NXP Semiconductors PCA8574/74A

Remote 8-bit I/O expander for I2C-bus with interrupt

9. Characteristics of the I2C-bus

The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two

lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be

connected to a positive supply via a pull-up resistor when connected to the output stages

of a device. Data transfer may be initiated only when the bus is not busy.

9.1 Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must remain

stable during the HIGH period of the clock pulse as changes in the data line at this time

will be interpreted as control signals (see Figure 11).

9.1.1 START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW

transition of the data line while the clock is HIGH is deﬁned as the START condition (S). A

LOW-to-HIGH transition of the data line while the clock is HIGH is deﬁned as the STOP

condition (P) (see Figure 12.)

9.2 System conﬁguration

A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The

device that controls the message is the ‘master’ and the devices which are controlled by

the master are the ‘slaves’ (see Figure 13).

Fig 11. Bit transfer

mba607

data line

stable;

data valid

change

of data

allowed

SDA

SCL

Fig 12. Deﬁnition of START and STOP conditions

mba608

SDA

SCL P

STOP condition

SDA

SCL

START condition

Product data sheet Rev. 02 — 14 May 2007 11 of 27

NXP Semiconductors PCA8574/74A

Remote 8-bit I/O expander for I2C-bus with interrupt

9.3 Acknowledge

The number of data bytes transferred between the START and the STOP conditions from

transmitter to receiver is not limited. Each byte of eight bits is followed by one

acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,

whereas the master generates an extra acknowledge related clock pulse.

A slave receiver which is addressed must generate an acknowledge after the reception of

each byte. Also a master must generate an acknowledge after the reception of each byte

that has been clocked out of the slave transmitter. The device that acknowledges has to

pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable

LOW during the HIGH period of the acknowledge related clock pulse; set-up and hold

times must be taken into account.

A master receiver must signal an end of data to the transmitter by not generating an

acknowledge on the last byte that has been clocked out of the slave. In this event, the

transmitter must leave the data line HIGH to enable the master to generate a STOP

condition.

Fig 13. System conﬁguration

002aaa966

MASTER

TRANSMITTER/

RECEIVER

SLAVE

RECEIVER SLAVE

TRANSMITTER/

RECEIVER

MASTER

TRANSMITTER MASTER

TRANSMITTER/

RECEIVER

SDA

SCL

I2C-BUS

MULTIPLEXER

SLAVE

Fig 14. Acknowledgement on the I2C-bus

002aaa987

START

condition

9821

clock pulse for

acknowledgement

not acknowledge

acknowledge

data output

by transmitter

data output

by receiver

SCL from master

Product data sheet Rev. 02 — 14 May 2007 12 of 27

NXP Semiconductors PCA8574/74A

Remote 8-bit I/O expander for I2C-bus with interrupt

10. Application design-in information

10.1 Bidirectional I/O expander applications

In the 8-bit I/O expander application shown in Figure 15, P0 and P1 are inputs, and P2 to

P7 are outputs. When used in this conﬁguration, during a write, the input (P0 and P1)

must be written as HIGH so the external devices fully control the input ports. The desired

HIGH or LOW logic levels may be written to the I/Os used as outputs (P2 to P7). During a

read, the logic levels of the external devices driving the input ports (P0 and P1) and the

previous written logic level to the output ports (P2 to P7) will be read.

The GPIO also has an interrupt line (INT) that can be connected to the interrupt logic of

the microprocessor. By sending an interrupt signal on this line, the remote I/O informs the

microprocessor that there is incoming data or a change of data on its ports without having

to communicate via the I2C-bus.

10.2 High current-drive load applications

The GPIO has a maximum sinking current of 25 mA per bit. In applications requiring

additional drive, two port pins in the same octal may be connected together to sink up to

50 mA current. Both bits must then always be turned on or off together. Up to 8 pins (one

octal) can be connected together to drive 200 mA.

Fig 15. Bidirectional I/O expander application

002aac123

VDD

temperature sensor

battery status

control for latch

control for switch

control for audio

control for camera

control for MP3

VDD

SDA

SCL

INT

AD0

AD1

AD2

CORE

PROCESSOR

VDD

Fig 16. High current-drive load application

002aac124

VDD

SDA

SCL

INT

AD0

AD1

AD2

CORE

PROCESSOR

VDD

LOAD

Product data sheet Rev. 02 — 14 May 2007 13 of 27

NXP Semiconductors PCA8574/74A

Remote 8-bit I/O expander for I2C-bus with interrupt

11. Limiting values

[1] Total package (maximum) output current is 400 mA.

Table 6. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

VDD supply voltage −0.5 +6 V

IDD supply current - ±100 mA

ISS ground supply current - ±400 mA

VIinput voltage VSS −0.5 5.5 V

IIinput current - ±20 mA

IOoutput current [1] -±50 mA

Ptot total power dissipation - 400 mW

P/out power dissipation per output - 100 mW

Tstg storage temperature −65 +150 °C

Tamb ambient temperature operating −40 +85 °C

Product data sheet Rev. 02 — 14 May 2007 14 of 27

NXP Semiconductors PCA8574/74A

Remote 8-bit I/O expander for I2C-bus with interrupt

12. Static characteristics

[1] The power-on reset circuit resets the I2C-bus logic with VDD <V

POR and sets all I/Os to logic 1 (with current source to VDD).

[2] Each bit must be limited to a maximum of 25 mA and the total package limited to 200 mA due to internal busing limits.

[3] The value is not tested, but veriﬁed on sampling basis.

Table 7. Static characteristics

= 2.3 V to 5.5 V; V

=0V; T

amb

−

Cto+85

C; unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

Supplies

VDD supply voltage 2.3 - 5.5 V

IDD supply current Operating mode; no load;

VI=V

DD or VSS;f

SCL = 400 kHz;

AD0, AD1, AD2 = static H or L

- 200 500 µA

Istb standby current Standby mode; no load;

VI=V

DD or VSS; fSCL = 0 kHz - 4.5 10 µA

VPOR power-on reset voltage [1] - 1.8 2.0 V

Input SCL; input/output SDA

VIL LOW-level input voltage −0.5 - +0.3VDD V

VIH HIGH-level input voltage 0.7VDD - 5.5 V

IOL LOW-level output current VOL = 0.4 V; VDD = 2.3 V 20 35 - mA

VOL = 0.4 V; VDD = 3.0 V 25 44 - mA

VOL = 0.4 V; VDD = 4.5 V 30 57 - mA

ILleakage current VI=V

DD or VSS −1- +1 µA

Ciinput capacitance VI=V

SS - 5 10 pF

I/Os; P0 to P7

IOL LOW-level output current VOL = 0.5 V; VDD = 2.3 V [2] 12 26 - mA

VOL = 0.5 V; VDD = 3.0 V [2] 17 33 - mA

VOL = 0.5 V; VDD = 4.5 V [2] 25 40 - mA

IOL(tot) total LOW-level output current VOL = 0.5 V; VDD = 4.5 V [2] - - 200 mA

IOH HIGH-level output current VOH =V

SS −30 −138 −300 µA

Itrt(pu) transient boosted pull-up current VOH =V

SS; see Figure 8 −0.5 −1.0 - mA

Ciinput capacitance [3] - 2.1 10 pF

Cooutput capacitance [3] - 2.1 10 pF

Interrupt INT (see Figure 8 and Figure 9)

IOL LOW-level output current VOL = 0.4 V 3.0 - - mA

Cooutput capacitance - 3 5 pF

Inputs AD0, AD1, AD2

VIL LOW-level input voltage −0.5 - +0.3VDD V

VIH HIGH-level input voltage 0.7VDD - 5.5 V

ILI input leakage current −1- +1 µA

Ciinput capacitance - 3.5 5 pF

Product data sheet Rev. 02 — 14 May 2007 15 of 27

NXP Semiconductors PCA8574/74A

Remote 8-bit I/O expander for I2C-bus with interrupt

13. Dynamic characteristics

[1] tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW.

[2] tVD;DAT = minimum time for SDA data out to be valid following SCL LOW.

[3] A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the VIL of the SCL signal) in order to

bridge the undeﬁned region SCL’s falling edge.

[4] The maximum tf for the SDA and SCL bus lines is speciﬁed at 300 ns. The maximum fall time for the SDA output stage tf is speciﬁed at

250 ns. This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without

exceeding the maximum speciﬁed tf.

[5] Cb= total capacitance of one bus line in pF.

[6] Input ﬁlters on the SDA and SCL inputs suppress noise spikes less than 50 ns.

Table 8. Dynamic characteristics

= 2.3 V to 5.5 V; V

=0V; T

amb

−

Cto+85

C; unless otherwise speciﬁed. Limits are for Fast-mode I

C-bus.

Symbol Parameter Conditions Min Typ Max Unit

fSCL SCL clock frequency 0 - 400 kHz

tBUF bus free time between a STOP and START

condition 1.3 - - µs

tHD;STA hold time (repeated) START condition 0.6 - - µs

tSU;STA set-up time for a repeated START condition 0.6 - - µs

tSU;STO set-up time for STOP condition 0.6 - - µs

tHD;DAT data hold time 0 - - ns

tVD;ACK data valid acknowledge time[1] 0.1 - 0.9 µs

tVD;DAT data valid time[2] 50 - - ns

tSU;DAT data set-up time 100 - - ns

tLOW LOW period of the SCL clock 1.3 - - µs

tHIGH HIGH period of the SCL clock 0.6 - - µs

tffall time of both SDA and SCL signals [3][4] 20 + 0.1Cb[5] - 300 ns

trrise time of both SDA and SCL signals 20 + 0.1Cb[5] - 300 ns

tSP pulse width of spikes that must be suppressed

by the input ﬁlter[6] - - 50 ns

Port timing; CL≤100 pF (see Figure 8 and Figure 9)

tv(Q) data output valid time - - 4 µs

tsu(D) data input set-up time 0 - - µs

th(D) data input hold time 4 - - µs

Interrupt timing; CL≤100 pF (see Figure 8 and Figure 9)

tv(D) data input valid time - - 4 µs

td(rst) reset delay time - - 4 µs

Product data sheet Rev. 02 — 14 May 2007 16 of 27

NXP Semiconductors PCA8574/74A

Remote 8-bit I/O expander for I2C-bus with interrupt

Rise and fall times refer to VIL and VIH.

Fig 17. I2C-bus timing diagram

SCL

SDA

tHD;STA tSU;DAT tHD;DAT

tBUF

tSU;STA tLOW tHIGH

tVD;ACK

002aab175

tSU;STO

protocol START

condition

(S)

bit 7

MSB

(A7)

bit 6

(A6) bit 0

(R/W) acknowledge

(A)

STOP

condition

(P)

1/fSCL

tVD;DAT

Product data sheet Rev. 02 — 14 May 2007 17 of 27

NXP Semiconductors PCA8574/74A

Remote 8-bit I/O expander for I2C-bus with interrupt

14. Package outline

Fig 18. Package outline SOT38-1 (DIP16)

UNIT A

max. 1 2 b1cEe M

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

SOT38-1 99-12-27

03-02-13

min. A

max. bmax.

1.40

1.14

0.055

0.045

0.53

0.38 0.32

0.23 21.8

21.4

0.86

0.84

6.48

6.20

0.26

0.24

3.9

3.4

0.15

0.13

0.2542.54 7.62

0.3

8.25

7.80

0.32

0.31

9.5

8.3

0.37

0.33

2.2

0.087

4.7 0.51 3.7

0.15 0.021

0.015 0.013

0.009 0.010.10.020.19

050G09 MO-001 SC-503-16

(e )

seating plane

pin 1 index

0 5 10 mm

scale

Note

1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

(1) (1)

D(1)

DIP16: plastic dual in-line package; 16 leads (300 mil); long body SOT38-1

Product data sheet Rev. 02 — 14 May 2007 18 of 27

NXP Semiconductors PCA8574/74A

Remote 8-bit I/O expander for I2C-bus with interrupt

Fig 19. Package outline SOT162-1 (SO16)

UNIT A

max. A1A2A3bpcD

(1) E(1) (1)

ELL

pQZ

ywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

2.65 0.3

0.1 2.45

2.25 0.49

0.36 0.32

0.23 10.5

10.1 7.6

7.4 1.27 10.65

10.00 1.1

1.0 0.9

0.4 8

0.25 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

1.1

0.4

SOT162-1

detail X

0.25

075E03 MS-013

pin 1 index

0.1 0.012

0.004 0.096

0.089 0.019

0.014 0.013

0.009 0.41

0.40 0.30

0.29 0.05

1.4

0.055

0.419

0.394 0.043

0.039 0.035

0.016

0.01

0.25

0.01 0.004

0.043

0.016

0.01

vMA

(A )

0 5 10 mm

scale

SO16: plastic small outline package; 16 leads; body width 7.5 mm SOT162-1

99-12-27

03-02-19

Product data sheet Rev. 02 — 14 May 2007 19 of 27

NXP Semiconductors PCA8574/74A

Remote 8-bit I/O expander for I2C-bus with interrupt

Fig 20. Package outline SOT403-1 (TSSOP16)

UNIT A1A2A3bpcD

(1) E(2) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.05 0.95

0.80 0.30

0.19 0.2

0.1 5.1

4.9 4.5

4.3 0.65 6.6

6.2 0.4

0.3 0.40

0.06 8

0.13 0.10.21

DIMENSIONS (mm are the original dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

0.75

0.50

SOT403-1 MO-153 99-12-27

03-02-18

0.25

16 9

detail X

(A )

vMA

0 2.5 5 mm

scale

TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1

max.

1.1

pin 1 index

Product data sheet Rev. 02 — 14 May 2007 20 of 27

NXP Semiconductors PCA8574/74A

Remote 8-bit I/O expander for I2C-bus with interrupt

Fig 21. Package outline SOT266-1 (SSOP20)

UNIT A1A2A3bpcD

(1) E(1) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

01.4

1.2 0.32

0.20 0.20

0.13 6.6

6.4 4.5

4.3 0.65 1 0.2

6.6

6.2 0.65

0.45 0.48

0.18 10

0.13 0.1

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.20 mm maximum per side are not included.

0.75

0.45

SOT266-1 MO-152 99-12-27

03-02-19

detail X

vMA

(A )

0.25

110

20 11

pin 1 index

0 2.5 5 mm

scale

SSOP20: plastic shrink small outline package; 20 leads; body width 4.4 mm SOT266-1

max.

1.5

Product data sheet Rev. 02 — 14 May 2007 21 of 27

NXP Semiconductors PCA8574/74A

Remote 8-bit I/O expander for I2C-bus with interrupt

15. Handling information

Inputs and outputs are protected against electrostatic discharge in normal handling.

However, to be completely safe you must take normal precautions appropriate to handling

integrated circuits.

16. Soldering

16.1 Introduction

There is no soldering method that is ideal for all surface mount IC packages. Wave

soldering can still be used for certain surface mount ICs, but it is not suitable for ﬁne pitch

SMDs. In these situations reﬂow soldering is recommended.

16.2 Through-hole mount packages

16.2.1 Soldering by dipping or by solder wave

Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 °C

or 265 °C, depending on solder material applied, SnPb or Pb-free respectively.

The total contact time of successive solder waves must not exceed 5 seconds.

The device may be mounted up to the seating plane, but the temperature of the plastic

body must not exceed the speciﬁed maximum storage temperature (Tstg(max)). If the

printed-circuit board has been pre-heated, forced cooling may be necessary immediately

after soldering to keep the temperature within the permissible limit.

16.2.2 Manual soldering

Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the

seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is

less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is

between 300 °C and 400 °C, contact may be up to 5 seconds.

16.3 Surface mount packages

16.3.1 Reﬂow soldering

Key characteristics in reﬂow soldering are:

•Lead-free versus SnPb soldering; note that a lead-free reﬂow process usually leads to

higher minimum peak temperatures (see Figure 22) than a PbSn process, thus

reducing the process window

•Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

•Reﬂow temperature proﬁle; this proﬁle includes preheat, reﬂow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

Product data sheet Rev. 02 — 14 May 2007 22 of 27

NXP Semiconductors PCA8574/74A

Remote 8-bit I/O expander for I2C-bus with interrupt

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classiﬁed in accordance with

Table 9 and 10

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reﬂow

soldering, see Figure 22.

For further information on temperature proﬁles, refer to Application Note

AN10365

“Surface mount reﬂow soldering description”

Table 9. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm3)

< 350 ≥ 350

< 2.5 235 220

≥ 2.5 220 220

Table 10. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm3)

< 350 350 to 2000 > 2000

< 1.6 260 260 260

1.6 to 2.5 260 250 245

> 2.5 250 245 245

MSL: Moisture Sensitivity Level

Fig 22. Temperature proﬁles for large and small components

001aac844

temperature

time

minimum peak temperature

= minimum soldering temperature

maximum peak temperature

= MSL limit, damage level

peak

temperature

Product data sheet Rev. 02 — 14 May 2007 23 of 27

NXP Semiconductors PCA8574/74A

Remote 8-bit I/O expander for I2C-bus with interrupt

16.3.2 Wave soldering

Conventional single wave soldering is not recommended for surface mount devices

(SMDs) or printed-circuit boards with a high component density, as solder bridging and

non-wetting can present major problems.

To overcome these problems the double-wave soldering method was speciﬁcally

developed.

If wave soldering is used the following conditions must be observed for optimal results:

•Use a double-wave soldering method comprising a turbulent wave with high upward

pressure followed by a smooth laminar wave.

•For packages with leads on two sides and a pitch (e):

–larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be

parallel to the transport direction of the printed-circuit board;

–smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the

transport direction of the printed-circuit board.

The footprint must incorporate solder thieves at the downstream end.

•For packages with leads on four sides, the footprint must be placed at a 45° angle to

the transport direction of the printed-circuit board. The footprint must incorporate

solder thieves downstream and at the side corners.

During placement and before soldering, the package must be ﬁxed with a droplet of

adhesive. The adhesive can be applied by screen printing, pin transfer or syringe

dispensing. The package can be soldered after the adhesive is cured.

Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 °C

or 265 °C, depending on solder material applied, SnPb or Pb-free respectively.

A mildly-activated ﬂux will eliminate the need for removal of corrosive residues in most

applications.

16.3.3 Manual soldering

Fix the component by ﬁrst soldering two diagonally-opposite end leads. Use a low voltage

(24 V or less) soldering iron applied to the ﬂat part of the lead. Contact time must be

limited to 10 seconds at up to 300 °C.

When using a dedicated tool, all other leads can be soldered in one operation within

2 seconds to 5 seconds between 270 °C and 320 °C.

16.4 Package related soldering information

Table 11. Suitability of IC packages for wave, reﬂow and dipping soldering methods

Mounting Package[1] Soldering method

Wave Reﬂow[2] Dipping

Through-hole mount CPGA, HCPGA suitable −−

DBS, DIP, HDIP, RDBS, SDIP, SIL suitable[3] −suitable

Through-hole-surface

mount PMFP[4] not suitable not suitable −

Product data sheet Rev. 02 — 14 May 2007 24 of 27

NXP Semiconductors PCA8574/74A

Remote 8-bit I/O expander for I2C-bus with interrupt

[1] For more detailed information on the BGA packages refer to the

(LF)BGA Application Note

(AN01026); order a copy from your NXP

Semiconductors sales ofﬁce.

[2] All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with

respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of

the moisture in them (the so called popcorn effect).

[3] For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board.

[4] Hot bar soldering or manual soldering is suitable for PMFP packages.

[5] These transparent plastic packages are extremely sensitive to reﬂow soldering conditions and must on no account be processed

through more than one soldering cycle or subjected to infrared reﬂow soldering with peak temperature exceeding 217 °C±10 °C

measured in the atmosphere of the reﬂow oven. The package body peak temperature must be kept as low as possible.

[6] These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate

between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the

heatsink surface.

[7] If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint

must incorporate solder thieves downstream and at the side corners.

[8] Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is deﬁnitely not suitable for

packages with a pitch (e) equal to or smaller than 0.65 mm.

[9] Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is deﬁnitely

not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

[10] Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted on ﬂex foil.

However, the image sensor package can be mounted by the client on a ﬂex foil by using a hot bar soldering process. The appropriate

soldering proﬁle can be provided on request.

Surface mount BGA, HTSSON..T[5], LBGA,

LFBGA,SQFP,SSOP..T[5],TFBGA,

VFBGA, XSON

not suitable suitable −

DHVQFN, HBCC, HBGA, HLQFP,

HSO, HSOP, HSQFP, HSSON,

HTQFP, HTSSOP, HVQFN,

HVSON, SMS

not suitable[6] suitable −

PLCC[7], SO, SOJ suitable suitable −

LQFP, QFP, TQFP not recommended[7][8] suitable −

SSOP, TSSOP, VSO, VSSOP not recommended[9] suitable −

CWQCCN..L[10], WQCCN..L[10] not suitable not suitable −

Table 11. Suitability of IC packages for wave, reﬂow and dipping soldering methods

…continued

Mounting Package[1] Soldering method

Wave Reﬂow[2] Dipping

Product data sheet Rev. 02 — 14 May 2007 25 of 27

NXP Semiconductors PCA8574/74A

Remote 8-bit I/O expander for I2C-bus with interrupt

17. Abbreviations

18. Revision history

Table 12. Abbreviations

Acronym Description

CDM Charged Device Model

CMOS Complementary Metal Oxide Semiconductor

ESD ElectroStatic Discharge

GPIO General Purpose Input/Output

HBM Human Body Model

LED Light Emitting Diode

IC Integrated Circuit

I2C-bus Inter-Integrated Circuit bus

ID Identiﬁcation

LSB Least Signiﬁcant Bit

MM Machine Model

MSB Most Signiﬁcant Bit

PLC Programmable Logic Controller

PWM Pulse Width Modulation

RAID Redundant Array of Independent Disks

SMBus System Management Bus

Table 13. Revision history

Document ID Release date Data sheet status Change notice Supersedes

PCA8574_PCA8574A_2 20070514 Product data sheet - PCA8574_PCA8574A_1

Modiﬁcations: •Section 2 “Features”, last bullet item: changed “TSSOP20” to “TSSOP16”

•Table 1 “Ordering information”: changed package from TSSOP20 (SOT360-1) to

TSSOP16 (SOT403-1)

•Section 6.1 “Pinning”: deleted pin conﬁguration for TSSOP20; added pin conﬁguration for

TSSOP16

•Table 2 title changed (added TSSOP16)

•Table 3 title changed (deleted TSSOP20)

•Section 14 “Package outline”: changed package from TSSOP20 (SOT360-1) to

TSSOP16 (SOT403-1)

PCA8574_PCA8574A_1 20070117 Product data sheet - -

Product data sheet Rev. 02 — 14 May 2007 26 of 27

NXP Semiconductors PCA8574/74A

Remote 8-bit I/O expander for I2C-bus with interrupt

19. Legal information

19.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Deﬁnitions”.

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

19.2 Deﬁnitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

19.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of a NXP Semiconductors product can reasonably be expected to

result in personal injury, death or severe property or environmental damage.

NXP Semiconductors accepts no liability for inclusion and/or use of NXP

Semiconductors products in such equipment or applications and therefore

such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

19.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

I2C-bus — logo is a trademark of NXP B.V.

20. Contact information

For additional information, please visit: http://www.nxp.com

For sales ofﬁce addresses, send an email to: salesaddresses@nxp.com

Document status[1][2] Product status[3] Deﬁnition

Objective [short] data sheet Development This document contains data from the objective speciﬁcation for product development.

Preliminary [short] data sheet Qualiﬁcation This document contains data from the preliminary speciﬁcation.

Product [short] data sheet Production This document contains the product speciﬁcation.

NXP Semiconductors PCA8574/74A

Remote 8-bit I/O expander for I2C-bus with interrupt

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 14 May 2007

Document identifier: PCA8574_PCA8574A_2

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

21. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

4 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2

6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3

6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

7 Functional description . . . . . . . . . . . . . . . . . . . 6

7.1 Device address. . . . . . . . . . . . . . . . . . . . . . . . . 6

7.1.1 Address maps. . . . . . . . . . . . . . . . . . . . . . . . . . 6

8 I/O programming . . . . . . . . . . . . . . . . . . . . . . . . 7

8.1 Quasi-bidirectional I/O architecture . . . . . . . . . 7

8.2 Writing to the port (Output mode). . . . . . . . . . . 7

8.3 Reading from a port (Input mode) . . . . . . . . . . 8

8.4 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 9

8.5 Interrupt output (INT) . . . . . . . . . . . . . . . . . . . . 9

9 Characteristics of the I2C-bus. . . . . . . . . . . . . 10

9.1 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

9.1.1 START and STOP conditions . . . . . . . . . . . . . 10

9.2 System conﬁguration . . . . . . . . . . . . . . . . . . . 10

9.3 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 11

10 Application design-in information . . . . . . . . . 12

10.1 Bidirectional I/O expander applications . . . . . 12

10.2 High current-drive load applications . . . . . . . . 12

11 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 13

12 Static characteristics. . . . . . . . . . . . . . . . . . . . 14

13 Dynamic characteristics . . . . . . . . . . . . . . . . . 15

14 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 17

15 Handling information. . . . . . . . . . . . . . . . . . . . 21

16 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 21

16.2 Through-hole mount packages. . . . . . . . . . . . 21

16.2.1 Soldering by dipping or by solder wave . . . . . 21

16.2.2 Manual soldering . . . . . . . . . . . . . . . . . . . . . . 21

16.3 Surface mount packages . . . . . . . . . . . . . . . . 21

16.3.1 Reﬂow soldering. . . . . . . . . . . . . . . . . . . . . . . 21

16.3.2 Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 23

16.3.3 Manual soldering . . . . . . . . . . . . . . . . . . . . . . 23

16.4 Package related soldering information . . . . . . 23

17 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 25

18 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 25

19 Legal information . . . . . . . . . . . . . . . . . . . . . . 26

19.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 26

19.2 Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

19.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 26

19.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 26

20 Contact information . . . . . . . . . . . . . . . . . . . . 26

21 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27