General Description
The MAX5959/MAX5960 quad hot-plug controllers are
designed for PCI Express®(PCIe) applications. These
devices provide hot-plug control for the main 12V, 3.3V,
and 3.3V auxiliary supplies of four PCIe slots. The
MAX5959/MAX5960s’ logic inputs/outputs allow interfac-
ing directly with the system hot-plug management con-
troller or through an SMBus™ with an external I/O
expander such as the MAX7313. An integrated
debounced attention switch and present-detect signals
simplify system design.
The MAX5959/MAX5960 drive eight external n-channel
MOSFETs to control the 12V and 3.3V main outputs. The
3.3V auxiliary outputs are controlled through 0.2Ωn-chan-
nel MOSFETs. Internal charge pumps provide the gate
drive for the 12V outputs while the gate drive of the 3.3V
output is driven by the 12V input supply clamped to 5.5V
above the respective 3.3V main supply rail. The 3.3V aux-
iliary outputs are completely independent from the main
outputs with their own charge pumps.
At power-up, the MAX5959/MAX5960 keep all the
MOSFETs off until the supplies rise above their respective
undervoltage lockout (UVLO) thresholds. Upon a turn-on
command, the MAX5959/MAX5960 enhance the external
and internal MOSFETs slowly with a constant gate current
to limit the power-supply inrush current.
The MAX5959/MAX5960 actively limit the current to pro-
tect all outputs at all times and shut down if an overcur-
rent condition persists longer than the programmable
overcurrent timeout. After an overcurrent or overtempera-
ture fault condition, the MAX5959L/MAX5960L latch off
while the MAX5959A/MAX5960A automatically restart
after a restart time delay. The MAX5959/MAX5960 are
offered in latch-off or autorestart versions (see the
Selector Guide
).
The MAX5959/MAX5960 are available in an 80-pin TQFP
package and operate over the -40°C to +85°C tempera-
ture range.
Applications
Servers
Desktop Mobile Server Platforms
Workstations
Features
♦PCIe Compliant
♦Hot Swap 12V, 3.3V, and 3.3V Auxiliary for 4
PCIe Slots
♦Integrated Power MOSFETs for Auxiliary Supply
Rails
♦Controls di/dt and dV/dt
♦Active Current Limiting Protects Against
Overcurrent/Short-Circuit Conditions
♦Programmable Current-Limit Timeout
♦PWRGD Signal Outputs with Programmable
Power-On Reset (POR) (160ms Default)
♦Latched FAULT Signal Output After Overcurrent
or Overtemperature Fault
♦Attention Switch Inputs/Outputs with 4ms
Debounce
♦Present-Detect Inputs
♦Force-On Inputs Facilitate Testing/Debug
♦Thermal Shutdown
♦Allow Control Through SMBus with an I/O
Expander
MAX5959/MAX5960
Quad PCI Express, Hot-Plug Controllers
________________________________________________________________
Maxim Integrated Products
1
PART TEMP RANGE PIN-
PACKAGE
PKG
CODE
MAX5959AECS+ -40°C to +85°C 80 TQFP C80-1
MAX5959LECS+ -40°C to +85°C 80 TQFP C80-1
MAX5960AECS+ -40°C to +85°C 80 TQFP C80-1
MAX5960LECS+ -40°C to +85°C 80 TQFP C80-1
PART LATCH OFF AUTORESTART GUARANTEED AUX CURRENT (mA)
MAX5959AECS+ √375
MAX5959LECS+ √375
MAX5960AECS+ √550
MAX5960LECS+ √550
Selector Guide
Ordering Information
19-0856; Rev 0; 7/07
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
+
Denotes a lead-free package.
Pin Configuration and Typical Application Circuit appear at
end of data sheet.
EVALUATION KIT
AVAILABLE
PCI Express is a registered trademark of PCI-SIG Corp.
SMBus is a trademark of Intel Corp.
MAX5959/MAX5960
Quad PCI Express, Hot-Plug Controllers
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(V12VIN = V12S_+ = V12S_- = 12V, V3.3S_+ = V3.3S_- = V3.3AUXIN = VON_ = VAUXON_ = VFON_ = 3.3V, PWRGD_ = FAULT_ = PORADJ
= TIM = OUTPUT_ = 12G_ = 3.3G_ = OPEN, INPUT_ = PRES-DET_ = PGND = GND, TA= TJ= -40°C to +85°C, unless otherwise
noted. Typical values are at TA= TJ= +25°C.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
(All voltages referenced to GND, unless otherwise noted.)
12VIN......................................................................-0.3V to +14V
12G_ ..........................................................-0.3V to (V12VIN + 6V)
12S_+, 12S_-, 3.3G_ ..............................-0.3V to (V12VIN + 0.3V)
3.3VAUXIN, ON_, FAULT_, PWRGD_.......................-0.3V to +6V
PGND ....................................................................-0.3V to +0.3V
All Other Pins ..................................-0.3V to (V3.3VAUXIN + 0.3V)
Continuous Power Dissipation (TA= +70°C)
80-Pin TQFP (derate 23.3mW/°C above +70°C).........1860mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
12V SUPPLY (MAIN)
12V Supply Input-Voltage Range V12VIN 10.8 12 13.2 V
V12VIN rising 9.5 10 10.5
12V Undervoltage Lockout V12UVLO Hysteresis 0.1 V
12V Undervoltage Lockout
Deglitch Time tDEG,UVLO V12IN falling below V12UVLO to UVLO
assertion 30 µs
12V Supply Current I12VIN V12VIN = 13.2V 1 2.5 mA
12VIN CONTROL
12VIN Current-Limit Threshold
(V12S+ - V12S-)V12ILIM 49 54 59 mV
12G_ Gate Charge Current I12G, CHG V12G_ = GND 4 5 6 µA
Normal turn-off, ON_ = GND,
V12G_ = 2V 50 150 250 µA
12G_ Gate Discharge Current I12G_, DIS Output short-circuit condition, strong
gate pulldown to regulation,
(V12S+ - V12S-) ≥ 1V, V12G_ = 5V
60 120 200 mA
12G_ Gate High Voltage
(V12G_ - V12VIN)V12G, H I12G_ = 1µA 4.8 5.3 5.8 V
12G_ Threshold Voltage for
PWRGD_ Assertion VPGTH12
Referred to V12VIN, I12G_ = 1µA
(Note 2) 3 4 4.8 V
12S_- Input Bias Current 1µA
12S_+ Input Bias Current 10 30 µA
3.3V SUPPLY (MAIN)
3.3V Supply Voltage Range V3.3S_+ 3.0 3.3 3.6 V
3.3SA+ rising 2.50 2.65 2.78 V
Undervoltage Lockout (Note 3) Hysteresis 30 mV
MAX5959/MAX5960
Quad PCI Express, Hot-Plug Controllers
_______________________________________________________________________________________ 3
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
3.3V CONTROL
3.3V Current-Limit Threshold
(V3.3S_+ - V3.3S_-)V3.3ILIM 17 20 23 mV
3.3G_ Gate Charge Current I3.3G_
,
CHG V3.3G_ = GND 4 5 6 µA
Normal turn-off, ON_ = GND,
V3.3G_ = 2V 50 150 250 µA
3.3G_ Gate Discharge Current I3.3G_, DIS Output short-circuit condition, strong
gate pulldown to regulation,
V3.3S_+ - V3.3S_- ≥ 1V, V3.3G_ = 5V
90 150 250 mA
3.3G_ Gate High Voltage
(V3.3G_- V3.3S_+)V3.3G_H ISOURCE = 1µA 4.5 5.5 6.8 V
3.3G_ Threshold Voltage for
PWRGD_ Assertion VPGTH3.3 Referred to V3.3AUXIN, I3.3G_ = 1µA
(Note 2) 3 4 4.5 V
3.3S_- Input Bias Current 1µA
3.3S_+ Input Bias Current 20 60 µA
3.3V AUXILIARY SUPPLY
3.3VAUXIN Supply Input Voltage
Range V3.3AUXIN 3.0 3.3 3.6 V
V3.3VAUXIN rising 2.50 2.65 2.78 V
3.3VAUXIN Undervoltage
Lockout V3.3VAUXUVLO Hysteresis 30 mV
3.3VAUXIN Supply Current V3.3VAUXIN = 3.6V 2.5 5 mA
I3.3VAUXO_ = 550mA (MAX5960) 280
3.3VAUXIN to 3.3VAUXO_
Maximum Dropout I3.3VAUXO_ = 375mA (MAX5959) 225 mV
MAX5959 376 450 564
3.3VAUXO_ Current-Limit
Threshold
3.3VAUXO_ shorted to
GND MAX5960 560 700 850 mA
3.3VAUXO_ Threshold for
PWRGD_ Assertion (V3.3VAUXIN
- V3.3VAUXO_)
VPGTH3.3AUX (Note 2) 400 mV
LOGIC SIGNALS
Rising edge 1.0 2.0 V
Input-Logic Threshold (ON_,
FON_, AUXON_, PRES-DET_,
INPUT_) Hysteresis 25 mV
Input Bias Current (ON_,
AUXON_, INPUT_) 1µA
FON_, PRES-DET_ Internal 25 50 75 kΩ
ON_, AUXON_ High-to-Low
Deglitch Time 4µs
ELECTRICAL CHARACTERISTICS (continued)
(V12VIN = V12S_+ = V12S_- = 12V, V3.3S_+ = V3.3S_- = V3.3AUXIN = VON_ = VAUXON_ = VFON_ = 3.3V, PWRGD_ = FAULT_ = PORADJ
= TIM = OUTPUT_ = 12G_ = 3.3G_ = OPEN, INPUT_ = PRES-DET_ = PGND = GND, TA= TJ= -40°C to +85°C, unless otherwise
noted. Typical values are at TA= TJ= +25°C.) (Note 1)
MAX5959/MAX5960
Quad PCI Express, Hot-Plug Controllers
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(V12VIN = V12S_+ = V12S_- = 12V, V3.3S_+ = V3.3S_- = V3.3AUXIN = VON_ = VAUXON_ = VFON_ = 3.3V, PWRGD_ = FAULT_ = PORADJ
= TIM = OUTPUT_ = 12G_ = 3.3G_ = OPEN, INPUT_ = PRES-DET_ = PGND = GND, TA= TJ= -40°C to +85°C, unless otherwise
noted. Typical values are at TA= TJ= +25°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
PRES-DET_ High-to-Low
Deglitch Time tDEG 357ms
VPORADJ = GND 1 µs
PORADJ = unconnected 90 160 250
RPORADJ = 20kΩ35 55 75
RPORADJ = 100kΩ145 265 380
PWRGD_ Power-On Reset
Deglitch Time (Note 2) tPOR_HL
RPORADJ = 200kΩ530
ms
PWRGD_ Low-to-High Deglitch
Time tPOR_LH 4µs
ISINK = 2mA 0.1
PWRGD_, FAULT_ Output Low
Voltage ISINK = 30mA 0.8 V
PWRGD_, FAULT_ Output High
Leakage Current PWRGD_, FAULT_ = 5.5V 1 µA
TIM = open 5.5 11 17
RTIM = 15kΩ1.4 2.6 3.8
RTIM = 120kΩ12 22 32
FAULT_ Timeout tFAULT
RTIM = 300kΩ53
ms
FAULT_ Timeout During Startup tSU 2 x
tFAULT ms
Autorestart Delay Time tRESTART 64 x
tFAULT ms
Fault Reset Minimum Pulse Width tRESET (Note 4) 100 µs
Thermal Shutdown Threshold tSD TJ rising 150
Thermal Shutdown Hysteresis 20 °C
OUT_ Debounce Time tDBC 2.6 4.4 6.2 ms
OUT_ Voltage High ISOURCE = 2mA V3.3AUXIN
- 0.3 V3.3AUXIN V
Note 1: All devices are 100% production tested at TA= +25°C. Limits over temperature are guaranteed by design.
Note 2: PWRGD_ asserts a time tPOR_HL after VPGTH12, VPGTH3.3, and VPGTH3.3AUX conditions are met.
Note 3: The UVLO for the 3.3V supply is sensed at 3.3SA+.
Note 4: This is the time that ON_ or AUXON_ must stay low when resetting a fault condition.
MAX5959/MAX5960
Quad PCI Express, Hot-Plug Controllers
_______________________________________________________________________________________
5
12V INPUT SUPPLY CURRENT
vs. TEMPERATURE
MAX5959 toc01
TEMPERATURE (°C)
3.3VAUXIN SUPPLY CURRENT (mA)
603510-15
0.92
0.94
0.96
0.98
1.00
1.02
1.04
1.06
1.08
1.10
0.90
-40 85
3.3VAUXIN SUPPLY CURRENT
vs. TEMPERATURE
MAX5959 toc02
TEMPERATURE (°C)
3.3VAUXIN SUPPLY CURRENT (mA)
603510-15
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0
-40 85
ON AND AUXON LOW-TO-HIGH THRESHOLD
VOLTAGE vs. TEMPERATURE
MAX5959 toc03
TEMPERATURE (°C)
THRESHOLD VOLTAGE (V)
603510-15
1.25
1.30
1.35
1.40
1.45
1.50
1.55
1.60
1.20
-40 85
ON THRESHOLD
AUXON THRESHOLD
3.3VAUXO_ OUTPUT VOLTAGE
vs. OUTPUT CURRENT
MAX5959 toc04
OUTPUT CURRENT (A)
OUTPUT VOLTAGE (V)
0.80.60.40.2 0.90.70.50.30.1
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0
0 1.0
MAX5959 MAX5960
12G_ AND 3.3G_ GATE CHARGE
CURRENT vs. TEMPERATURE
MAX5959 toc05
TEMPERATURE (°C)
GATE CHARGE CURRENT (μA)
603510-15
4.80
4.85
4.90
4.95
5.00
5.05
5.10
5.15
5.20
4.75
-40 85
12G_
3.3G_
12G_ AND 3.3G_ GATE DISCHARGE
CURRENT vs. TEMPERATURE
MAX5959 toc06
TEMPERATURE (°C)
GATE DISCHARGE CURRENT (μA)
603510-15
160
165
170
175
180
150
155
-40 85
3.3G_
12G_
3.3VAUX INTERNAL SWITCH
MAXIMUM DROPOUT vs. TEMPERATURE
MAX5959 toc07
TEMPERATURE (°C)
DROPOUT VOLTAGE (V)
603510-15
0.02
0.04
0.06
0.08
0.10
0.12
0.14
0.16
0.18
0.20
0
-40 85
ILOAD = 550mA
MAX5960
ILOAD = 375mA
MAX5959
12V AND 3.3V CURRENT-LIMIT THRESHOLD
VOLTAGE vs. TEMPERATURE
MAX5959 toc08
TEMPERATURE (°C)
12V AND 3.3V MAIN CURRENT-LIMIT THRESHOLD (mV)
603510-15
10
20
30
40
50
60
0
-40 85
12V CURRENT-LIMIT
THRESHOLD
3.3V CURRENT-LIMIT
THRESHOLD
AUXILIARY CURRENT LIMIT
vs. TEMPERATURE
MAX5959 toc09
TEMPERATURE (°C)
AUXILIARY CURRENT (mA)
603510-15
0.10
0.30
0.20
0.40
0.50
0.60
0.70
0.80
0.90
1.00
0
-40 85
MAX5960
MAX5959
Typical Operating Characteristics
(V12VIN = V12S_+ = 12V, V3.3S_+ = V3.3S_- = V3.3AUXIN = VON_ = VAUXON_ = VFON_ = 3.3V, PWRGD_= FAULT_ = PORADJ = TIM =
OUTPUT_ = OPEN, INPUT_ = PRES-DET_ = PGND = GND. See the
Typical Application Circuit
.)
MAX5959/MAX5960
Quad PCI Express, Hot-Plug Controllers
6 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(V12VIN = V12S_+ = 12V, V3.3S_+ = V3.3S_- = V3.3AUXIN = VON_ = VAUXON_ = VFON_ = 3.3V, PWRGD_= FAULT_ = PORADJ = TIM =
OUTPUT_ = OPEN, INPUT_ = PRES-DET_ = PGND = GND. See the
Typical Application Circuit
.)
12V UNDERVOLTAGE LOCKOUT
THRESHOLD vs. TEMPERATURE
MAX5959 toc10
TEMPERATURE (°C)
UVLO THRESHOLD (V)
6035-15 10
9.85
9.90
9.95
10.00
10.05
10.10
10.15
10.20
9.80
-40 85
3.3VAUXON UNDERVOLTAGE LOCKOUT
THRESHOLD vs. TEMPERATURE
MAX5959 toc11
TEMPERATURE (°C)
UVLO THRESHOLD (V)
603510-15
2.54
2.58
2.62
2.66
2.70
2.52
2.56
2.60
2.64
2.68
2.50
-40 85
12V TURN-ON/OFF TIME
MAX5959 toc12
40ms/div
12V OUTPUT
VOLTAGE
12G_
ON_
PWRGD_
10V/div
20V/div
5V/div
5V/div
3.3V TURN-ON/OFF TIME
MAX5959 toc13
40ms/div
3.3V OUTPUT
5V/div
3.3G_
10V/div
ON_
5V/div
PWRGD_
5V/div
3.3V AUXILIARY TURN-ON/OFF TIME
MAX5959 toc14
40ms/div
3.3AUXO_OUTPUT
VOLTAGE
2V/div
AUXON_
2V/div
PWRGD_
2V/div
TURN-ON DELAY 3.3V OUTPUT AND
3.3V AUXILIARY OUTPUT
MAX5959 toc15
4ms/div
5V/div
5V/div
5V/div
5V/div
10V/div
3.3VAUXO_
OUTPUT VOLTAGE
3.3 OUTPUT VOLTAGE
3.3 INPUT,
3.3VAUXIN
3.3G_
PWRGD
FAULT CONDITION ON 12V MAIN OUTPUT
(AUTORESTART OPTION)
MAX5959 toc16
12G_
20V/div
0A
0V
0V
0V
FAULT_
5V/div
12V OUTPUT CURRENT
5A/div
100ms/div
12V OUTPUT VOLTAGE
10V/div
tRESTART
RLOAD STEP TO 1.5Ω
MAX5959/MAX5960
Quad PCI Express, Hot-Plug Controllers
_______________________________________________________________________________________
7
FAULT CONDITION ON 3.3V MAIN OUTPUT
(AUTORESTART OPTION)
MAX5959 toc17
3.3G_
10V/div
FAULT_
5V/div
3.3V MAIN OUTPUT CURRENT
2A/div
100ms/div
3.3V OUTPUT VOLTAGE
5V/div
tRESTART
RLOAD STEP TO 0.5Ω
0A
0V
0V
0V
FAULT CONDITION ON AUXILIARY OUTPUT
(AUTORESTART OPTION)
MAX5959 toc18
FAULT_
2V/div
3.3VAUXO_ OUTPUT CURRENT
500mA/div
100ms/div
3.3VAUXO_ OUTPUT VOLTAGE
2V/div
tRESTART
RLOAD STEP TO 4Ω
0A
0V
0V
FAULT CONDITION ON 12V MAIN OUTPUT
(LATCH-OFF OPTION)
MAX5959 toc19
12G_
20V/div
FAULT_
5V/div
12V OUTPUT CURRENT
5A/div
100ms/div
12V OUTPUT VOLTAGE
10V/div
RLOAD STEP TO 1.5Ω
FAULT CONDITION ON 12V OUTPUT
MAX5959 toc20
12G_
20V/div
FAULT_
5V/div
12V OUTPUT CURRENT
5A/div
4ms/div
12V OUTPUT VOLTAGE
10V/div
RLOAD STEP
TO 1.5ΩtFAULT
FAULT CONDITION ON 3.3V MAIN OUTPUT
(LATCH-OFF OPTION)
MAX5959 toc21
3.3G_
10V/div
FAULT_
5V/div
3.3V OUTPUT CURRENT
2A/div
40ms/div
3.3V OUTPUT VOLTAGE
5V/div
RLOAD STEP TO 0.5Ω
FAULT CONDITION ON 3.3V MAIN OUTPUT
MAX5959 toc22
3.3G_
10V/div
FAULT_
5V/div
3.3V OUTPUT CURRENT
2A/div
4ms/div
3.3V OUTPUT VOLTAGE
5V/div
RLOAD
STEP TO 0.5Ω
tFAULT
Typical Operating Characteristics (continued)
(V12VIN = V12S_+ = 12V, V3.3S_+ = V3.3S_- = V3.3AUXIN = VON_ = VAUXON_ = VFON_ = 3.3V, PWRGD_= FAULT_ = PORADJ = TIM =
OUTPUT_ = OPEN, INPUT_ = PRES-DET_ = PGND = GND. See the
Typical Application Circuit
.)
MAX5959/MAX5960
Quad PCI Express, Hot-Plug Controllers
8 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(V12VIN = V12S_+ = 12V, V3.3S_+ = V3.3S_- = V3.3AUXIN = VON_ = VAUXON_ = VFON_ = 3.3V, PWRGD_= FAULT_ = PORADJ = TIM =
OUTPUT_ = OPEN, INPUT_ = PRES-DET_ = PGND = GND. See the
Typical Application Circuit
.)
FAULT CONDITION ON AUXILIARY OUTPUT
MAX5959 toc24
FAULT_
2V/div
3.3VAUXO_ OUTPUT CURRENT
500mA/div
10ms/div
3.3VAUXO_ OUTPUT VOLTAGE
2V/div
RLOAD
STEP TO 3Ω
tFAULT
MAX5960
SHORT CIRCUIT ON 12V MAIN OUTPUT
MAX5959 toc25
12G_
20V/div
FAULT_
5V/div
12V OUTPUT CURRENT
5A/div
2ms/div
12V OUTPUT VOLTAGE
10V/div
SHORT CIRCUIT ON 12V MAIN OUTPUT
MAX5959 toc26
12G_
20V/div
FAULT_
5V/div
12V OUTPUT CURRENT
10A/div
4μs/div
12V OUTPUT VOLTAGE
10V/div
0V
0V
0V
SHORT CIRCUIT ON 3.3V MAIN OUTPUT
MAX5959 toc27
3.3G_
5V/div
FAULT_
5V/div
3.3V OUTPUT CURRENT
2A/div
2ms/div
3.3V OUTPUT VOLTAGE
5V/div
SHORT CIRCUIT ON 3.3V MAIN OUTPUT
MAX5959 toc28
3.3G_
5V/div
FAULT_
5V/div
3.3V OUTPUT CURRENT
10A/div
2μs/div
3.3V OUTPUT VOLTAGE
5V/div
0V
MAX5959/MAX5960
Quad PCI Express, Hot-Plug Controllers
_______________________________________________________________________________________
9
Typical Operating Characteristics (continued)
(V12VIN = V12S_+ = 12V, V3.3S_+ = V3.3S_- = V3.3AUXIN = VON_ = VAUXON_ = VFON_ = 3.3V, PWRGD_= FAULT_ = PORADJ = TIM =
OUTPUT_ = OPEN, INPUT_ = PRES-DET_ = PGND = GND. See the
Typical Application Circuit
.)
SHORT CIRCUIT ON 3.3VAUXO_
(AUXILIARY OUTPUT)
MAX5959 toc30
FAULT_
5V/div
3.3VAUXO_ OUTPUT CURRENT
5A/div
0A
0A
4μs/div
3.3VAUXO_ OUTPUT VOLTAGE
2V/div
MAX5960
POWER-UP INTO FAULT
(AUXILIARY SUPPLY)
MAX5959 toc31
3.3VAUXO_ OUTPUT VOLTAGE
2V/div
FAULT_
5V/div
3.3VAUXO_ OUTPUT CURRENT
500mA/div
4ms/div
AUXON_
5V/div
tSU
RLOAD = 3Ω
MAX5960
POWER-UP INTO FAULT (3.3V MAIN)
MAX5959 toc32
4ms/div
3.3V OUTPUT
CURRENT
FAULT_
3.3G_
3.3V OUTPUT
VOLTAGE
ON_, AUXON_
5A/div
5V/div
5V/div
2V/div
5V/div
POWER-UP INTO FAULT
(12V MAIN OUTPUT)
MAX5959 toc33
12V OUTPUT VOLTAGE
10V/div
FAULT_
5V/div
12V OUTPUT CURRENT
5A/div
4ms/div
ON_, AUXON_
5V/div
tSU
12G_
10V/div
PRESENT-DETECT (ON/OFF) OPERATION
MAX5959 toc34
40ms/div
12V OUTPUT
VOLTAGE
PWRGD_
3.3VAUXO_
OUTPUT VOLTAGE
PRES-DET_
10V/div
5V/div
5V/div
5V/div
MAX5959/MAX5960
Quad PCI Express, Hot-Plug Controllers
10 ______________________________________________________________________________________
Typical Operating Characteristics (continued)
(V12VIN = V12S_+ = 12V, V3.3S_+ = V3.3S_- = V3.3AUXIN = VON_ = VAUXON_ = VFON_ = 3.3V, PWRGD_= FAULT_ = PORADJ = TIM =
OUTPUT_ = OPEN, INPUT_ = PRES-DET_ = PGND = GND. See the
Typical Application Circuit
.)
FORCED-ON (ON/OFF) OPERATION
MAX5959 toc36
40ms/div
12V OUTPUT
VOLTAGE
PWRGD_
3.3V AUXO_
OUTPUT VOLTAGE
FON_
10V/div
5V/div
5V/div
5V/div
FORCED-ON (ON/OFF) OPERATION
MAX5959 toc37
4ms/div
12V OUTPUT
VOLTAGE
PWRGD_
3.3V OUTPUT
VOLTAGE
FON_
10V/div
5V/div
5V/div
5V/div
DEBOUNCED INPUT/OUTPUT OPERATION
MAX5959 toc38
INPUT_
2V/div
10ms/div
OUTPUT_
2V/div
POWER-ON-RESET TIME
vs. PORADJ RESISTOR
MAX5959 toc39
RPORADJ (kΩ)
tPOR_HL (ms)
900800600 700200 300 400 500100
200
400
600
800
1000
1200
1400
1600
1800
2000
2200
2400
0
0 1000
tFAULT TIME DELAY vs. TIM RESISTOR
MAX5959 toc40
RTIM (kΩ)
tFAULT (ms)
800600200 400
20
40
60
80
100
120
140
160
180
200
0
0 1000
MAX5959/MAX5960
Quad PCI Express, Hot-Plug Controllers
______________________________________________________________________________________ 11
Pin Description
PIN NAME FUNCTION
1 12SB- Slot B 12V Negative Current-Sense Input. Connect 12SB- to the negative side of the current-sense
resistor using the Kelvin-sensing technique to ensure accurate current sensing.
2 12SB+ Slot B 12V Positive Current-Sense Input. Connect the positive terminal of the current-sense resistor to
12SB+ using the Kelvin-sensing technique to ensure accurate current sensing.
3 AUXONB Slot B 3.3V Auxiliary Output Enable. A logic-high at AUXONB turns on the slot B auxiliary output.
4 ONB Slot B 12V and 3.3V Main Outputs Enable. A logic-high at ONB turns on the 12V and 3.3V main outputs
of slot B (see Table 2).
5 INPUT1 Digital Logic Gate Input 1
6 OUTPUT1 Digital Output 1. 4ms debounced digital output of INPUT1.
7 INPUT2 Digital Logic Gate Input 2
8 OUTPUT2 Digital Output 2. 4ms debounced digital output of INPUT2.
9, 61, 80 N.C. No Connection. Not internally connected. Leave unconnected.
10 FOND
Slot D Forced-On Input. FOND has a 50kΩ internal pullup to 3.3VAUXIN. A logic-low on FOND turns on
all slot D outputs as long as the power inputs are within their operating range, regardless of the status
of the other input signals. Leave FOND unconnected for normal operation.
11 PRES-DETD
Slot D Present-Detect Input. PRES-DETD accepts inputs from PRSNT#_# on a PCIe connector. PRES-
DETD has an internal 50kΩ pullup to 3.3VAUXIN. When PRES-DETA is low, the outputs follow the
command from OND and AUXOND after a 4ms debounced time. When PRES-DETD goes from low to
high, all outputs of the respective slot shut down with no delay.
12 OND Slot D 12V and 3.3V Main Outputs Enable. A logic-high at OND turns on the 12V and 3.3V main outputs
of slot D (see Table 2).
13 AUXOND Slot D 3.3V Auxiliary Output Enable. A logic-high at AUXOND turns on the slot D auxiliary output.
14 GND Ground
15 FONC
Slot C Forced-On Input C. FONC has a 50kΩ internal pullup to 3.3VAUXIN. A logic-low on FONC turns
on all slot C outputs as long as the power inputs are within their operating range, regardless of the
status of the other input signals. Leave FONC unconnected for normal operation.
16 PRES-DETC
Slot C Present-Detect Input. PRES-DETC accepts inputs from PRSNT#_# on a PCIe connector. PRES-
DETC has an internal 50kΩ pullup to 3.3VAUXIN. When PRES-DETC is low, the outputs follow the
command from ONC and AUXONC after a 4ms debounced time. When PRES-DETC goes from low to
high, all outputs of the respective slot shut down with no delay.
17 ONC Slot C 12V And 3.3V Main Outputs Enable. A logic-high at ONC turns on the 12V and 3.3V main outputs
of slot C (see Table 2).
18 AUXONC Slot C 3.3V Auxiliary Output Enable. A logic-high at AUXONC turns on the slot C auxiliary output.
19 12SC+ Slot C 12V Positive Current-Sense Input. Connect the positive terminal of the current-sense resistor to
12SC+ using the Kelvin-sensing technique to ensure accurate current sensing.
20 12SC- Slot C 12V Negative Current-Sense Input. Connect 12SC- to the negative side of the current-sense
resistor using the Kelvin-sensing technique to ensure accurate current sensing.
21 12GC Slot C 12V Gate-Drive Output. Connect 12GC to the gate of slot C’s 12V MOSFET. At power-up, 12GC
is raised to the internal charge-pump voltage level by a constant current.
22 3.3SC+ Slot C 3.3V Positive Current-Sense Input. Connect the positive side of the current-sense resistor to
3.3SC+ using the Kelvin-sensing technique to ensure accurate current sensing.
MAX5959/MAX5960
Quad PCI Express, Hot-Plug Controllers
12 ______________________________________________________________________________________
Pin Description (continued)
PIN NAME FUNCTION
23 3.3SC- Slot C 3.3V Negative Current-Sense Input. Connect to the negative side of the sense resistor using the
Kelvin-sensing technique to ensure accurate current sensing.
24 3.3GC
Slot C 3.3V Gate-Drive Output. Connect 3.3GC to the gate of slot C’s 3.3V MOSFET. At power-up,
3.3GC is charged to 5.5V above the 3.3V supply by a constant current derived from V12VIN. V3.3GC‘s
rise time is determined by the external gate capacitance.
25 FAULTC
Open-Drain Fault Output Signal. FAULTC latches active-low whenever slot C outputs are shut down due
to a fault. A fault is either of:
• An overcurrent condition lasting longer than the overcurrent timeout.
• A device over temperature condition.
If the fault is detected in the main outputs, FAULTC must be reset by toggling the ONC input. If the fault
is in the auxiliary output, FAULTC must be reset by toggling both ONC and AUXONC. For the
autorestart version, FAULTC is reset when the part initiates the next power-on cycle.
26 PWRGDC Open-Drain Power-Good Output. PWRGDC goes low 160ms after all outputs of slot C reach their final
value and the power MOSFETs are fully enhanced.
27,28 3.3AUXOC Slot C 3.3V Auxiliary Power-Supply Output
29, 30, 31,
69, 70, 71 3.3VAUXIN
3.3V Auxiliary Supply Input. 3.3VAUXIN is the input to a charge pump that drives the internal MOSFETs
connecting 3.3AUXIN to 3.3AUXO_. V3.3AUXIN is also used to power the internal control logic and
analog references of the MAX5959/MAX5960 and must always be connected to a supply between 3V
and 3.6V. Bypass 3.3AUXIN with at least a 0.1µF capacitor to GND.
32, 33 3.3AUXOD Slot D 3.3V Auxiliary Power-Supply Output
34, 66 PGND Power Ground. Connect externally to GND.
35 PWRGDD Open-Drain Power-Good Output. PWRGDD goes low 160ms after all outputs of slot D reach their final
value and the power MOSFETs are fully enhanced.
36 FAULTD
Open-Drain Fault Output Signal. FAULTD latches active-low whenever slot D outputs are shut down due
to a fault. A fault is either of:
• An overcurrent condition lasting longer than the overcurrent timeout.
• A device over temperature condition.
If the fault is detected in the main outputs, FAULTD must be reset by toggling the OND input. If the fault
is in the auxiliary output, FAULTD must be reset by toggling both OND and AUXOND. For the
autorestart version, FAULTD is reset when the part initiates the next power-on cycle.
37 TIM Overcurrent Timeout Programming Input. Connect a resistor between 500Ω and 500kΩ from TIM to
GND to program tFAULT. Leave TIM unconnected for a default timeout of 11ms.
38 PORADJ
Power-On-Reset Programming Input. Connect a resistor between 500Ω and 500kΩ from PORADJ to
GND to program the POR timing. Leave unconnected for a default value of 160ms. Connect PORADJ to
GND to completely skip the POR time delay for PWRGD_ assertion.
39 GND Ground
40 12VIN
12V Supply Input. V12VIN drives the gates of the MOSFETs connected to 3.3G_. 12VIN powers an
internal charge pump that drives the gates of the MOSFETs connected to 12G_. Bypass 12VIN with a
1µF capacitor to GND. See the Typical Application Circuit and Input Transients section.
41 12GD Slot D 12V Gate-Drive Output. Connect 12GD to the gate of slot D’s 12V MOSFET. At power-up, V12GD
is raised to the internal charge-pump voltage level by a constant current.
42 12SD- Slot D 12V Negative Current-Sense Input. Connect 12SD- to the negative side of the current-sense
resistor using the Kelvin-sensing technique to ensure accurate current sensing.
MAX5959/MAX5960
Quad PCI Express, Hot-Plug Controllers
______________________________________________________________________________________ 13
Pin Description (continued)
PIN NAME FUNCTION
43 12SD+ Slot D 12V Positive Current-Sense Input. Connect the positive terminal of the current-sense resistor to
12SD+ using the Kelvin-sensing technique to ensure accurate current sensing.
44 3.3GD
Slot D 3.3V Gate-Drive Output. Connect 3.3GD to the gate of slot D’s 3.3V MOSFET. At power-up,
V3.3GD is charged to 5.5V above the 3.3V supply by a constant current derived from V12VIN. V3.3GD’s
rise time is determined by the external gate capacitance.
45 3.3SD- Slot D 3.3V Negative Current-Sense Input. Connect to the negative side of the sense resistor using the
Kelvin-sensing technique to ensure accurate current sensing.
46 3.3SD+ Slot D 3.3V Positive Current-Sense Input. Connect the positive side of the current-sense resistor to
3.3SD+ using the Kelvin-sensing technique to ensure accurate current sensing.
47 PRES-DETB
Slot B Present-Detect Input. PRES-DETB accepts inputs from PRSNT#_# on a PCIe connector.
PRES-DETB has an internal 50kΩ pullup to 3.3VAUXIN. When PRES-DETB is low, the outputs follow the
command from ONB and AUXONB after a 4ms debounced time. When PRES-DETB goes from low to
high, all outputs of the respective slot shut down with no delay.
48 FONB
Slot B Forced-On Input. FONB has a 50kΩ internal pullup to 3.3VAUXIN. A logic-low on FONB turns on
all slot B outputs as long as the power inputs are within their operating range, regardless of the status of
the other input signals. Leave FONB unconnected for normal operation.
49 PRES-DETA
Slot A Present-Detect Input. PRES-DETA accepts inputs from PRSNT#_# on a PCIe connector.
PRES-DETA has an internal 50kΩ pullup to 3.3VAUXIN. When PRES-DETA is low, the outputs follow the
command from ONA and AUXONA after a 4ms debounced time. When PRES-DETA goes from low to
high, all outputs of the respective slot shut down with no delay.
50 FONA
Slot A Forced-On Input. FONA has a 50kΩ internal pullup to 3.3VAUXIN. A logic-low on FONA turns on
all slot A outputs as long as the power inputs are within their operating range, regardless of the status of
the other input signals. Leave FONA unconnected for normal operation.
51 OUTPUT4 Digital Output 4. 4ms debounced digital output of INPUT4.
52 INPUT4 Digital Logic Gate Input 4
53 OUTPUT3 Digital Output 3. 4ms debounced digital output of INPUT3.
54 INPUT3 Digital Logic Gate Input 3
55 ONA Slot A 12V and 3.3V Outputs Enable. A logic-high at ONA turns on the 12V and 3.3V outputs of slot A
(see Table 2).
56 AUXONA Slot A 3.3V Auxiliary Output Enable. A logic-high at AUXONA turns on the slot A auxiliary output.
57 12SA+ Slot A 12V Positive Current-Sense Input. Connect the positive terminal of the current-sense resistor to
12SA+ using the Kelvin-sensing technique to ensure accurate current sensing.
58 12SA- Slot A 12V Negative Current-Sense Input. Connect 12SA- to the negative side of the current-sense
resistor using the Kelvin-sensing technique to ensure accurate current sensing.
59 12GA Slot A 12V Gate-Drive Output. Connect 12GA to the gate of slot A’s 12V MOSFET. At power-up, V12GA
is raised to the internal charge-pump voltage level by a constant current.
60 3.3SA+ Slot A 3.3V Positive Current-Sense Input. Connect the positive side of the current-sense resistor to
3.3SA+ using the Kelvin-sensing technique to ensure accurate current sensing.
62 3.3SA- Slot A 3.3V Negative Current-Sense Input. Connect to the negative side of the sense resistor using the
Kelvin-sensing technique to ensure accurate current sensing.
MAX5959/MAX5960
Quad PCI Express, Hot-Plug Controllers
14 ______________________________________________________________________________________
Pin Description (continued)
PIN NAME FUNCTION
63 3.3GA
Slot A 3.3V Gate-Drive Output. Connect 3.3GA to the gate of slot A’s 3.3V MOSFET. At power-up,
V3.3GA is charged to 5.5V above the 3.3V supply by a constant current derived from V12VIN. V3.3GA‘s
rise time is determined by the external gate capacitance.
64 FAULTA
Open-Drain Fault Output Signal. FAULTA latches active low whenever slot A outputs are shut down due
to a fault. A fault is either of:
• An overcurrent condition lasting longer than the overcurrent timeout.
• A device over temperature condition.
If the fault is detected in the main outputs, FAULTA must be reset by toggling the ONA input. If the fault
is in the auxiliary output, FAULTA must be reset by toggling both ONA and AUXONA. For the autorestart
version, FAULTA is reset when the part initiates the next power-on cycle.
65 PWRGDA Open-Drain Power-Good Output. PWRGDA goes low 160ms after all outputs of slot A reach their final
value and the power MOSFETs are fully enhanced.
67, 68 3.3AUXOA Slot A 3.3V Auxiliary Power-Supply Output
72, 73 3.3AUXOB Slot B 3.3V Auxiliary Power-Supply Output
74 PWRGDB Open-Drain Power-Good Output. PWRGDB goes low 160ms after all outputs of slot B reach their final
value and the power MOSFETs are fully enhanced.
75 FAULTB
Open-Drain Fault Output Signal. FAULTB latches active-low whenever slot B outputs are shut down due
to a fault. A fault is either of:
• An overcurrent condition lasting longer than the overcurrent timeout.
• A device over temperature condition.
If the fault is detected in the main outputs, FAULTB must be reset by toggling the ONB input. If the fault
is in the auxiliary output, FAULTB must be reset by toggling both ONB and AUXONB. For the autorestart
version, FAULTB is reset when the part initiates the next power-on cycle.
76 3.3GB
Slot B 3.3V Gate-Drive Output. Connect 3.3GB to the gate of slot B’s 3.3V MOSFET. At power-up,
V3.3GB is charged to 5.5V above the 3.3V supply by a constant current derived from V12VIN. V3.3GB‘s
rise time is determined by the external gate capacitance.
77 3.3SB- Slot B 3.3V Negative Current-Sense Input. Connect to the negative side of the sense resistor using the
Kelvin-sensing technique to ensure accurate current sensing.
78 3.3SB+ Slot B 3.3V Positive Current-Sense Input. Connect the positive side of the current-sense resistor to
3.3SB+ using the Kelvin-sensing technique to ensure accurate current sensing.
79 12GB Slot B 12V Gate-Drive Output. Connect 12GB to the gate of slot B’s 12V MOSFET. At power-up, V12GB
is raised to the internal charge-pump voltage level by a constant current.
Detailed Description
The MAX5959/MAX5960 quad hot-plug controllers are
designed for PCIe applications. The devices provide
hot-plug control for 12V, 3.3V, and 3.3V auxiliary sup-
plies for three PCIe slots. The MAX5959/MAX5960s’
logic inputs/outputs allow interfacing directly with the
system hot-plug-management controller or through an
SMBus with an external I/O expander. An integrated
debounced attention switch and present-detect signals
are included to simplify system design (Figure 1).
The MAX5959/MAX5960 drive eight external n-chan-
nel MOSFETs to control the 12V and 3.3V main out-
puts. The 3.3V auxiliary outputs are controlled through
internal 0.2Ωn-channel MOSFETs. Internal charge
pumps provide a gate drive for the 12V outputs while
the gate drive of the 3.3V output is driven by the 12V
input supply. The 3.3V auxiliary outputs are complete-
ly independent from the main outputs with their own
charge pumps.
MAX5959/MAX5960
Quad PCI Express, Hot-Plug Controllers
______________________________________________________________________________________ 15
5μA
12S_-
12G_
12S_+
54mV
108mV RSENSE
150μA
10μA
100μA
-
+
-
+
10μA
120mA
5μA
3.3S_-
3.3G_
3.3S_+
20mV40mV
150μA
3.3AUXO
PRES-DET_FON_
AUXON_
UVLO
VREF
ON_
RSENSE
-
+
-
+
10μA
150mA
CHARGE
PUMP
-
+
RTIM
TIM IN OUT 12VIN PWRGD_ FAULT_
RPORADJ
PORADJ
DEBOUNCE
FAST
OSCILLATOR
CONTROL LOGIC
MAIN-CHANNEL
CONTROL LOGIC
AUX-CHANNEL
INPUT COMPARATOR AND
CHIP CONTROL LOGIC
tFAULT
tPOR
OSCILLATOR
MAX5959
BIAS, REFERENCES,
AND UVLO
CONTROL LOGIC
MAIN-CHANNEL
CONTROL LOGIC
AUX-CHANNEL
CHARGE
PUMP
100μA
Figure 1. Single-Channel Internal Block Diagram
MAX5959/MAX5960
Quad PCI Express, Hot-Plug Controllers
16 ______________________________________________________________________________________
At power-up, the MAX5959/MAX5960 keep all the
external MOSFETs off until all supplies rise above their
respective UVLO thresholds. These devices keep the
internal MOSFETs off only until the 3.3VAUXIN supply
rises above its UVLO threshold. Upon a turn-on com-
mand, the MAX5959/MAX5960 enhance the external
and internal MOSFETs slowly with a constant gate cur-
rent to limit the power-supply inrush current. The
MAX5959/MAX5960 actively limit the current of all out-
puts at all times and shut down the corresponding
channel if an overcurrent condition persists for longer
than a resistor-programmable overcurrent timeout (see
the
Fault Management
section). Thermal protection cir-
cuitry also shuts down all outputs if the die temperature
exceeds +150°C. After an overcurrent or overtempera-
ture fault condition, the MAX5959/MAX5960 latch off or
automatically restart depending on the version, after a
restart time delay.
The power requirement for PCIe connectors is defined
by the PCIe card specification and summarized in
Table 1.
Startup
The main supply outputs can become active only after
all the following events have occurred:
•V
3.3AUXIN is above its UVLO threshold.
•V
12VIN and V3.3SA+ are both above their UVLO
threshold.
• ON_ is driven high.
•PRES-DET_ is low for more than 4ms.
The auxiliary supply output is made available only after
the following events have occurred:
•V
3.3AUXIN is above its UVLO threshold.
• AUXON_ is driven high.
•PRES-DET_ is low for more than 4ms.
The FON_ input overrides all other control signals and
turns on the respective slot when driven low, as long as
the UVLO thresholds have been reached. Table 2 sum-
marizes the logic conditions required for startup. The aux-
iliary supply input powers the internal control logic and
analog references of the MAX5959/MAX5960, so the main
supplies cannot be enabled, if V3.3VAUXIN is not present.
When an output is enabled, a programmable startup
timer (tSU) begins to count the startup time duration.
The value of tSU is set to 2x the fault timeout period
(tFAULT). RTIM externally connected from TIM to GND
sets the duration of tFAULT.
Table 1. Power Requirement for PCIe Connectors
POWER FAIL X1 CONNECTOR X4/8 CONNECTOR X16 CONNECTOR
3.3V
Voltage Tolerance ±9% (max) ±9% (max) ±9% (max)
Supply Current 3.0A (max) 3.0A (max) 3.0A (max)
Capacitive Load 1000µF (max) 1000µF (max) 1000µF (max)
12V
Voltage Tolerance ±8% (max) ±8% (max) ±8% (max)
Supply Current 0.5A (max) 2.1A (max) 5.5A (max)
Capacitive Load 300µF (max) 1000µF (max) 2000µF (max)
3.3V AUXILIARY
Voltage Tolerance ±9% (max) ±9% (max) ±9% (max)
Supply Current, Wake Enabled 375mA (max) 375mA (max) 375mA (max)
Supply Current, Nonwake Enabled 20mA (max) 20mA (max) 20mA (max)
Capacitive Load 150µF (max) 150µF (max) 150µF (max)
MAX5959/MAX5960
Quad PCI Express, Hot-Plug Controllers
______________________________________________________________________________________ 17
Table 2. Control Logic Truth Table
*
PRES-DET_ high-to-low transition has a 4ms delay (tDEG).
ON_ AUXON_ FON_ PRES-DET 12V_ AND 3.3V_
OUTPUTS
3.3VAUXO_AUXILIARY
OUTPUTS
X X Low X On On
X X High High Off Off
Low Low High Low* Off Off
High Low High Low* On Off
Low High High Low* Off On
High High High Low* On On
Figure 2. Power-Up Timing, No Fault
VON_,TH
ON_, AUXON_
PWRGD_
FAULT_
12G_, 3.3G_
12VO_, 3.3VO_
3.3VAUXO_
VPGTH12
VPGTH3.3
VPGTH3.3AUX
3.3AUXIN
RISING
EDGE
PWRGD_ IS PULLED UP TO 3.3.
FAULT_ IS PULLED UP TO 3.3AUXIN.
tPOR_HL
Figure 3. 12V Power-Up Timing (Turn-On into Output
Overcurrent/Short Circuit)
FAULT_
3.3VAUXIN
RISING
EDGE
PWRGD_ IS PULLED UP TO 3.3VAUXO_.
FAULT_ IS PULLED UP TO 3.3VAUXIN.
A FAULT ON THE 3.3V OUTPUT OR 3.3VAUXO_ OUTPUT PRODUCES SIMILAR RESULTS.
VON_,TH
ON_
2 x tFAULT
PWRGD_
12G_
12V OUTPUT
CURRENT
3.3VAUXO_
V12ILIM,TH
RSENSE
MAX5959/MAX5960
Quad PCI Express, Hot-Plug Controllers
18 ______________________________________________________________________________________
12V and 3.3V Outputs Normal Operation
The MAX5959/MAX5960 monitor and actively limit the
current of the 12V and 3.3V outputs after the startup
period. Each output has its own overcurrent threshold.
If any of the monitored output currents rise above the
overcurrent threshold for a period tFAULT, FAULT_
asserts and the controller disengages both the 12V and
3.3V outputs for the particular slot (see the
Fault
Management
section).
3.3V Auxiliary Output Normal Operation
The auxiliary output current is internally monitored and
actively limited to the maximum current-limit value. An
overcurrent fault condition occurs when the output cur-
rent exceeds the overcurrent threshold for longer than
tFAULT. A fault on an auxiliary channel causes all sup-
plies of the affected channel to be disabled after a pro-
grammable time period tFAULT.
A fault condition on a main channel (V12VIN or V3.3VIN)
causes all the channel’s main outputs to shut down
after the tFAULT period and then either latch off or auto-
matically restart after the tRESTART (tRESTART = 64 x
tFAUALT) period, depending on the device version. A
fault on any of the channel’s main output does not
affect the auxiliary channel (V3.3AUXIN).
Power-Good (PWRGD_)
Power-good (PWRGD_) is an open-drain output that
pulls low a time (tPOR_HL) after all the outputs of the
respective slot are fully on. All outputs are considered
fully on when 3.3G_ has risen to VPGTH3.3, 12G_ has
risen to VPGTH12, and V3.3AUXO_is less than
VPGTH3.3AUX. tPOR_HL is adjustable from 2.4ms to 1.5s
by connecting a resistor from PORADJ to GND. See the
Setting the Power-On Reset
and
Timeout Period
(t
POR_HL
)
sections. Connect PORADJ to GND to com-
pletely skip the POR time delay for PWRGD_ assertion.
Thermal Shutdown
When the die temperature goes above (TSD) +150°C, an
overtemperature fault occurs and the MAX5959/
MAX5960 shut down all outputs. The device waits for the
junction temperature to decrease below TSD - hysteresis
before entering fault management (see the
Fault
Management
section):
Fault Management
A fault occurs when an overcurrent or 12G_ or 3.3G_
below their power-good threshold lasts longer than
tFAULT or when the device experiences an overtemper-
ature condition:
• A fault on a main output (12V or 3.3V) shuts down
both main outputs of the respective slot. The 3.3V
auxiliary is not affected.
• A fault on the 3.3V auxiliary output shuts down all
three outputs of the respective slot.
The MAX5959A/MAX5960A automatically restart from a
fault shutdown after the tRESTART period while the
MAX5959L/MAX5960L latch off. If an overcurrent fault
occurred on a main output, bring ON_ low for at least
tRESET (100µs) and high again to reset the fault and
restart the outputs. If the overcurrent fault occurred on
an auxiliary output or an overtemperature fault
occurred, bring both ON_ and AUXON_ low for a mini-
mum of tRESET to reset the fault. Toggle ON_ or only
AUXON_ to reset the fault condition. If ON_ and
AUXON are toggled before tRESTART time counting has
elapsed, the MAX5959L/MAX5960L store the informa-
tion and restart when the delay is finished. The
MAX5959A/MAX5960A (autoretry versions) restart all
channels automatically after tRESTART.
Figure 4. 12 Output Overcurrent/Short Circuit During Normal
Operation
FAULT_
PWRGD_ IS PULLED UP TO 3.3VAUXO_.
FAULT_ IS PULLED UP TO 3.3VAUXIN.
A FAULT ON THE 3.3V OUTPUT OR 3.3VAUXO_ OUTPUT PRODUCES SIMILAR RESULTS.
tFAULT
PWRGD_
12G_
12V OUTPUT
CURRENT
V12ILIM,TH
RSENSE
MAX5959/MAX5960
Quad PCI Express, Hot-Plug Controllers
______________________________________________________________________________________ 19
Debounced Logic Gate
(INPUT_ and OUTPUT_)
INPUT1, INPUT2, and INPUT3 accept inputs from
mechanical switches. The corresponding outputs are
OUTPUT1, OUTPUT2, OUTPUT3, and OUTPUT4. OUT-
PUT_ is debounced for 4ms. When INPUT_ goes from
high to low, OUTPUT_ goes low immediately and stays
low for at least 4ms. After the debounce time, OUT-
PUT_ follows INPUT_. If INPUT_ goes from low to high,
OUTPUT_ goes high immediately and stays high for at
least 4ms. After the debounce time, OUTPUT_ follows
INPUT_. Figure 5 shows the timing diagram describing
the INPUT_/OUTPUT_ debounced feature.
Present-Detect and Forced-On Inputs
(PRES-DET_, FON_)
PRES-DET_ input detects the PRSNT_# pin on a PCIe
connector. When the card is plugged in, PRES-DET_
goes low and allows the turn-on of the outputs of the
respective slot after a 4ms debounced time. When the
card is removed, an internal 50kΩpullup resistor forces
PRES-DET_ high and the respective slot is shut down
with no delay. PRES-DET_ works in conjunction with
ON_ and AUXON_ and only enables the device when
ON_ and AUXON_ are high.
A logic-low on FON_ forces the respective slot (main
supplies and auxiliary) to turn on regardless of the sta-
tus of the other logic inputs, provided the UVLO thresh-
olds are exceeded on all the inputs.
Active Current Limits
Active current limits are provided for all three outputs of
the four slots (slot A, slot B, slot C, and slot D). Connect
a current-sense resistor between 12S_+ and 12S_- to
set the current limit for the 12V outputs. The current
limit is set to 54mV / RSENSE12. Connect a current-
sense resistor between 3.3S_+ and 3.3S_- to set the
current limit for the 3.3V main outputs to 20mV /
RSENSE3.3. For the auxiliary output (3.3VAUXO_) the
current limit is fixed at 450mA in the MAX5959 and
700mA in the case of the MAX5960.
When the voltage across RSENSE12 or RSENSE3.3
reaches the current-limit threshold voltage, the
MAX5959/MAX5960 regulate the gate voltage to main-
tain the current-limit threshold voltage across the sense
resistor. If the current limit lasts for tFAULT, then an
overcurrent fault occurs. The MAX5959/MAX5960 shut
down both the 12V and 3.3V outputs and assert the
FAULT_ output of the respective slot.
When the auxiliary output reaches the current limit 450mA
(MAX5959) or 700mA (MAX5960) for longer than tFAULT, a
fault occurs and the device shuts down all outputs and
asserts FAULT of the respective slot.
UVLO Threshold
The UVLO thresholds prevent the internal auxiliary
MOSFETs and the external main channel MOSFETs
from turning on if V12VIN, V3.3VIN, and V3.3VAUXIN are
not present. Internal comparators monitor the main
supplies and the auxiliary supply and keep the gate-
drive outputs (12GA, 12GB, 12GC, 12GD, 3.3GA,
3.3GB, 3.3GC, and 3.3GD) low until the supplies rise
above their UVLO threshold. The 12V main supply is
monitored at 12VIN and has a UVLO threshold of 10V.
The 3.3V main supply is monitored at 3.3SA+ and has
a UVLO threshold of 2.65V. The auxiliary supply is
monitored at 3.3AUXIN and has a 2.65V UVLO thresh-
old. For either main channels to operate, V3.3AUXIN
must be above its UVLO threshold.
Figure 5. INPUT_ AND OUTPUT_ Debounced Feature
INPUT
DEBOUNCED
OUTPUT
tDBC tDBC tDBC
MAX5959/MAX5960
Quad PCI Express, Hot-Plug Controllers
20 ______________________________________________________________________________________
ENABLE CHARGE ON
INTERNAL AUXILIARY
MOSFET DRIVING 3.3AUXO_.
START COUNTING tSU
FAULT ON 12V
OR 3.3V OUTPUTS
RESET tFAULT
COUNTER
FAULT
STILL PRESENT?
Y
Y
Y
Y
Y
SHUT DOWN
12V AND 3.3V OUTPUTS.
ASSERT FAULT_
STAY WAITING FOR
tRESTART
tFAULT ELAPSED?
N
N
N
N
3.3VAUXIN IS OK,
AUXON_ IS HIGH,
PRES_DET IS LOW
RESET FAULT_
START COUNTING
tFAULT
Y
N
N
N
ARE ALL
MAIN OUTPUTS OK?
NO FAULT
DETECTED
LATCH-OFF
OPTION?
N
ON_ TOGGLED
HIGH ≥ LOW ≥ HIGH
MAIN INPUTS ARE
OK, ON_ IS HIGH
Y
Y
N
ENABLE CHARGE
ON 3.3G_ AND 12G_.
START
COUNTING tSU
tSU
ELAPSED?
Y
START PGOOD
THRESHOLD
MONITORING
START COUNTING
tFAULT
ALL PGOOD
THRESHOLDS
REACHED?
N
N
N
N
Y
YY
Y
ASSERT PWRGD_
AFTER tPOR_HL
DELAY
RESET PWRGD_
POWER ON
AUXILIARY OUTPUT.
FAULT_ AND PWRGD_ ARE
HIGH IMPEDANCE
SHUT DOWN ALL OUTPUTS.
ASSERT FAULT_.
STAY WAITING
FOR tRESTART
RESET FAULT_
ON_ AND
AUXON_ TOGGLED
HIGH ≥ LOW
≥ HIGH
tSU
ELAPSED?
AUX OUTPUT OK?
NO FAULT DETECTED
FAULT ON 3.3AUXO_?
N
N
tFAULT ELAPSED?
Y
FAULT
STILL PRESENT?
N
YY
LATCH-OFF
OPTION?
RESET tFAULT
COUNTER
Figure 6. Fault Management Flowchart
MAX5959/MAX5960
Quad PCI Express, Hot-Plug Controllers
______________________________________________________________________________________ 21
External MOSFET Gate Drivers
(12G_ and 3.3G_)
The gate drive for the external MOSFETs is provided at
12GA, 12GB, 12GC, 12GD, 3.3GA, 3.3GB, 3.3GC, and
3.3GD. 12G_ is the gate drive for the 12V main supply
and is boosted to 5.3V above V12VIN by its internal
charge pump. During turn-on, 12G_ sources 5µA into
the external gate capacitance to control the turn-on
time of the external MOSFET. During turn-off, 12G_
sinks 150µA from the external gate capacitance to
quickly turn off the external MOSFET. During short-cir-
cuit events, an internal 120mA current sink activates to
rapidly bring the load current into the regulation limits.
3.3G_ is the gate drive for the 3.3V main supply’s MOS-
FET and is driven to 5.5V above the 3.3V main supply.
The power for 3.3G_ is supplied from 12VIN and has no
internal charge pump. During turn-on, 3.3G_ sources
5µA into the external gate capacitance to control the
turn-on time of the external MOSFET. During turn-off,
3.3G_ sinks 150µA to quickly turn off the external MOS-
FET. During short-circuit events, an internal 120mA cur-
rent sink activates to rapidly turn off the appropriate
external MOSFET.
Auxiliary Supply (3.3VAUXIN)
3.3VAUXIN provides power to the auxiliary outputs as
well as the internal logic and references. The drains of
the internal auxiliary MOSFETs connect to 3.3AUXIN
through internal sense resistors and the sources con-
nect to the auxiliary outputs (3.3VAUXO_). Both
MOSFETs have typical on-resistance of 0.2Ω. Each
channel’s internal charge pump boosts the gate-drive
voltage to fully turn on the internal n-channel MOSFETs.
The auxiliary supplies have an internal current limit set
to 450mA (MAX5959) or 700mA (MAX5960).
Applications Information
Setting the Power-On Reset
tFAULT is the time an overcurrent or overtemperature
fault must remain for the MAX5959/MAX5960 to disable
the main or auxiliary channels of a particular slot.
Program the fault timeout period (tFAULT) by connect-
ing a resistor (RTIM) from TIM to GND. tFAULT can be
calculated by the following equation:
tFAULT = (166ns / Ω) x RTIM
The tFAULT programmed time duration must be chosen
according to the total capacitance load connected to
the 12G_ and 3.3G_ pins. To properly power up the
main supply outputs, the following constraints need to
be taken:
tSU ≥(VGATE x CLOAD) / ICHG
where tSU = 2 x tFAULT and where:
•I
CHG = 5µA.
•V
GATE = 4.8V +V12VIN for 12G_ and VGATE = 6.8V
+V3.3VIN for 3.3G_.
•C
LOAD is the total capacitance load at the gate.
Maximum and minimum values for RTIM are 500Ωand
500kΩ, respectively. Leave TIM floating for a default
tFAULT of 10ms.
Timeout Period (tPOR_HL)
tPOR_HL is the time from when the gate voltages of all
outputs of a slot reach their power-good threshold to
when PWRGD_ pulls low. Program the POR timeout
period (tPOR) by connecting a resistor (RPORADJ) from
PORADJ to GND. tPOR_HL can be calculated by the fol-
lowing equation:
tPOR_HL = (2.5µs / Ω) x RPORADJ
Maximum and minimum values for RPORADJ are 500Ω
and 500kΩ, respectively. Leave PORADJ floating for a
default tPOR of 150ms. Connect PORADJ to GND in
order to completely skip the power-on delay time prior
to the PWRGD_ assertion.
Component Selection
Select the external n-channel MOSFET according to the
applications current requirement. Limit the switch
power dissipation by choosing a MOSFET with an
RDS_ON low enough to have a minimum voltage drop at
full load. High RDS_ON causes larger output ripple if
there are pulsed loads. High RDS_ON can also trigger
an external undervoltage fault at full load. Determine
the MOSFET’s power-rating requirement to accommo-
date a short-circuit condition on the board during start-
up. Table 3 lists the MOSFETs and sense resistor
manufacturers.
MAX5959/MAX5960
Quad PCI Express, Hot-Plug Controllers
22 ______________________________________________________________________________________
Additional External Gate Capacitance
External capacitance can be added from the gate of
the external MOSFETs to GND to slow down the dV/dt
of the 12V and 3.3V outputs. The maximum gate
capacitance load at 12G_ and 3.3G_ must be consis-
tent with the conditions described in the
Setting the
Power-On Reset
section.
Maximum Load Capacitance
Large capacitive loads at the 12V output, the 3.3V out-
put, and the 3.3V auxiliary output can cause a problem
when inserting discharged PCI cards into live back-
planes. A fault occurs if the time needed to charge the
capacitance of the board is greater than the typical
startup time (2 x tFAULT). The MAX5959/MAX5960 with-
stand large capacitive loads due to their adjustable
startup times and adjustable current-limit thresholds.
Calculate the maximum load capacitance as follows:
CLOAD < (tSU x ILIM) / VOUT
VOUT is either the 3.3V output, the 12V output, or the
3.3V auxiliary output for slot A, slot B, slot C, or slot D.
Input Transients
The 12V input (12VIN), the 3.3V input (3.3SA+), and the
3.3V auxiliary (3.3AUXIN) must be above their UVLO
thresholds before startup can occur. Input transients
can cause the input voltage to sag below the UVLO
threshold. The MAX5959/MAX5960 reject transients on
the input supplies that are shorter than 4µs (typ).
Because some load fault conditions can cause voltage
transients to propagate to the supply inputs with dura-
tion of greater than 4µs, it is recommended that a small
Schottky diode be placed in series with the 12VIN pin
connection, upstream of the 1µF bypass capacitor. This
provides a hold-up supply that will prevent the 12VIN
input from dropping below V12UVLO during severe tran-
sients. See the
Typical Application Circuit
.
Table 3. Component Manufacturers
COMPONENT MANUFACTURER PHONE WEBSITE
Vishay-Date 402-564-3131 www.vishay.com
Sense Resistor IRC 704-264-8861 www.irctt.com
Fairchild 888-522-5372 www.fairchildsemi.com
International Rectifier 310-322-3331 www.irf.com
Motorola 602-244-3576 www.mot-sps.com/ppd
MOSFETs
Vishay-Siliconix — www.vishay.com
MAX5959/MAX5960
Quad PCI Express, Hot-Plug Controllers
______________________________________________________________________________________ 23
Typical Application Circuit
V3.3VAUXIN
10kΩ
PWRGD_
INTSMBus AO–A2
LEDs
MRL
PRSNT1#
PCI EXPRESS
SLOT_
+12V
PWRGD
3.3VAUX 3.3VAUXO_
GND
+3.3V
PRSNT2#
GND
ATTENTION
SWITCH
AUXON_ ON_ INPUT_ OUTPUT_
FON_
PRES-DET_
3.3G_ 3.3S_- 3.3S_+
12S_+
V3.3VAUX
IN5819
RPORADJ =
OPEN
V12VMAIN
V3.3VMAIN
12G_
10kΩ
12S_- 3.3VAUXIN
ONE OF FOUR SLOTS SHOWN
12VIN PORADJ
22
MAX7313ATG
16-BIT I/O
EXPANDER
MAX5959
MAX5960
FAULT_
RTIM =
OPEN
TIM
R1
8mΩ
R2
5mΩ
0.1μF2.2μF
0.1μF
MAX5959/MAX5960
Quad PCI Express, Hot-Plug Controllers
24 ______________________________________________________________________________________
Pin Configuration
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
N.C.
12GB
3.3SB+
3.3SB-
3.3GB
FAULTB
PWRGDB
3.3AUXOB
3.3AUXOB
3.3AUXIN
3.3AUXIN
60 3.3SA+
12GA
12SA-
12SA+
AUXONA
ONA
INPUT3
OUTPUT3
INPUT4
OUTPUT4
FONA
PRES-DETA
FONB
PRES-DETB
3.3SD+
3.3SD-
3.3GD
12SD+
12SD-
12GD
12SB-
12SB+
AUXONB
ONB
INPUT1
OUTPUT1
INPUT2
OUTPUT2
N.C.
FOND
PRES-DETD
OND
AUXOND
GND
FONC
PRES-DETC
ONC
AUXONC
12SC+
12SC-
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
1+
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
3.3AUXIN
3.3AUXOA
3.3AUXOA
PGND
PWRGDA
64
63
62
61
FAULTA
3.3GA
3.3SA-
N.C.
12GC
3.3SC+
3.3SC-
3.3GC
FAULTC
PWRGDC
3.3AUXOC
3.3AUXOC
3.3AUXIN
3.3AUXIN
3.3AUXIN
3.3AUXOD
3.3AUXOD
PGND
PWRGDD
FAULTD
37
38
39
40
TIM
PORADJ
GND
12VIN
TQFP
MAX5959
MAX5960
TOP VIEW
Chip Information
PROCESS: BiCMOS
MAX5959/MAX5960
Quad PCI Express, Hot-Plug Controllers
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________
25
© 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
TQFP12x12mm.EPS
PACKAGE OUTLINE,
21-0072 1
1
C
80L TQFP, 12x12x1.0mm