Product Brief August 2000 ATM ABR Cell Manager/Processor CSC for ORCA(R) FPGAs Features Complete available bit rate (ABR) service solution when used with the Lucent Technologies AtlantaTM ATM chipset Implements Lucent Bell Labs dynamic max rate algorithm (DMRCA) for ABR 50 MHz operation Intel*/Motorola microprocessor interface Includes resource management (RM) Cell manager (RMCM) providing the framework for a user-provided RM cell marking algorithm. Description UTOPIA 2 TO/FROM MPHYs INGRESS RMCM/ RMCP ALM TO/FROM SWITCH INGRESS EGRESS ABM EGRESS P 0391(F) Standards Compliance ATM forum's traffic management specification version 4.0 Benefits Faster FPGA development for improved time-tomarket with ATM ABR functions Lower development cost through design reuse VHDL source code for easy design integration and migration to gate arrays or ASICs ORCA-specific optimization, tailor-made for high performance Ample design flexibility using VHDL generics Verified functionality and standards compliance * Intel is a registered trademark of Intel Corporation. Motorola is a registered trademark of Motorola, Inc. VHDL is a registered trademark of Gateway Automation Corporation. Figure 1. RMCM/RMCP Application The resource management (RM) cell processor (RMCP), shown in Figure 1, operates in conjunction with Lucent Technologies' ATM layer manager (ALM) and ATM buffer manager (ABM) to provide a complete solution for available bit rate (ABR) switch processing in compliance with the ATM forum's traffic management 4.0 specification. The RMCP is located between the ABM and the ALM (Figure 1). ATM ABR Cell Manager/Processor CSC for ORCA FPGAs Product Brief August 2000 Description (continued) Design Package In the egress direction, the RMCP performs the following: The RM cell processor/manager CSC packages contain the following: Receives all egress cells from the ABM in the long format (62 bytes). Extracts the ABR's traffic congestion level information from the cells' local headers. Calculates and stores relative and explicit rates (RR and ER). Converts all cells to the short format (56 bytes). Passes the cells to the ALM. VHDL source code VHDL testbench Scripts and data files for simulation (behavioral, gatelevel, and back-annotated), synthesis, and FPGA layout Detailed documentation: -- Reference guide: CSC features, architecture, interfaces, and operation -- User's guide: CSC simulation, synthesis, and FPGA layout step-by step procedures In the ingress direction, the RMCP. Receives all ingress cells from the ALM. Passes non-RM cells through to the ABM. Required Tools Injects RR and ER information in backward RM cells, and passes them to the ABM. Lucent Technologies ORCA Foundry for FPGA layout MTI V-system for simulation Exemplar Galileo* extreme for synthesis The congestion level information is used in the algorithm for the relative rate (RR) and explicit rate (ER) algorithms. The resource management (RM) cell manager (RMCM) is a stand-alone VHDL CSC which is included with the RMCP or can be purchased separately. This CSC provides the framework for a user-provided algorithm. The RMCM is located between the ABM and the ALM (Figure 1). In the ingress direction, the RMCM performs the following: Receives all ingress cells from the ALM. Passes user cells to ABM. Allows the user algorithm to write backward RM cells, updates the CRC-10, and passes the cells to the ABM. In the egress direction, the RMCM performs the following: Receives all egress cells from the ABM in the long format (62 bytes). Extracts and sends congestion and other data to the user's algorithm. Converts all cells to the short format (56 bytes) and passes the cells to the ALM. Additional Resources Lucent Technologies LUC4AU01 ATM Layer UNI Manager (ALM)--July 1997 Lucent Technologies LUC4AB01 ATM Buffer Manager (ABM)--October 1997 ATM Forum Traffic Management Specification Version 4.0--April 1996 Ordering Information Modelware, Inc. Tel: (732)936-1808 Fax: (732)936-1838 E-mail: sales@modelware.com Internet: www.modelware.com * Galileo is a trademark of Exemplar Logic, Modelware is a registered trademark of Modelware, Inc. The RMCM synthesizes into an OR2T26A-5 and the RMCP into an OR2T40A-6. 2 Lucent Technologies Inc. Product Brief August 2000 ATM ABR Cell Manager/Processor CSC for ORCA FPGAs Notes: Lucent Technologies Inc. 3 For additional information, contact your Microelectronics Group Account Manager or the following: http://www.lucent.com/micro, or for FPGA information, http://www.lucent.com/orca INTERNET: docmaster@micro.lucent.com E-MAIL: N. AMERICA: Microelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA PACIFIC: Microelectronics Group, Lucent Technologies Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 778 8833, FAX (65) 777 7495 CHINA: Microelectronics Group, Lucent Technologies (China) Co., Ltd., A-F2, 23/F, Zao Fong Universe Building, 1800 Zhong Shan Xi Road, Shanghai 200233 P. R. China Tel. (86) 21 6440 0468, ext. 325, FAX (86) 21 6440 0652 JAPAN: Microelectronics Group, Lucent Technologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700 EUROPE: Data Requests: MICROELECTRONICS GROUP DATALINE: Tel. (44) 7000 582 368, FAX (44) 1189 328 148 Technical Inquiries: GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Ascot), FRANCE: (33) 1 40 83 68 00 (Paris), SWEDEN: (46) 8 594 607 00 (Stockholm), FINLAND: (358) 9 3507670 (Helsinki), ITALY: (39) 02 6608131 (Milan), SPAIN: (34) 1 807 1441 (Madrid) Lucent Technologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No rights under any patent accompany the sale of any such product(s) or information. ORCA is a registered trademark of Lucent Technologies Inc. Atlanta is a trademark of Lucent Technologies, Inc. Copyright (c) 2000 Lucent Technologies Inc. All Rights Reserved August 2000 PB00-091NCIP