Product Brief
August 2000
ATM ABR Cell Manager/Processor CSC
for
ORCA
® FPGAs
Features
■Complete available bit rate
(
ABR
)
service solution
when used with the Lucent Technolo
g
ies
Atlanta
™
ATM chipset
■Implement s Luc ent Bel l Labs d
y
namic max rate
al
g
orithm
(
DMRCA
)
for ABR
■50 MHz operation
■
Intel
*/
Motorola
† microprocessor interface
■Includes resource mana
g
ement
(
RM
)
Cell manager (RMCM) providing the framework for a
user-provided RM cell markin
g
al
g
orithm.
Standards Compliance
■ATM forum’s traffic mana
g
ement specification ver-
sion 4.0
Benefits
■Faster FPGA development for improved time-to-
market with ATM ABR functions
■Lower development cost throu
g
h desi
g
n reuse
■
VHDL
‡ source code for eas
y
desi
g
n int e
g
ration
and mi
g
ration to
g
ate arra
y
s or ASICs
■
ORCA
-specific optimization, tailor-made for hi
g
h
performance
■Ample desi
g
n flexibilit
y
usin
g
VHDL
g
enerics
■Verified functionalit
y
and standa rds co mpl ia nce
*
Intel
is a registered trademark of Intel Corporation.
†
Motorola
is a registered trademar k of Motorola, Inc.
‡
VHDL
is a registered trademark of Gateway Automation Corpo-
ration.
Description
0391(F)
Figure 1. RMCM/RMCP Application
The resource management (RM) cell processor
(RMCP), shown in Figure 1, operates in conjunction
with Lucent Technologies' ATM layer manager (ALM)
and ATM buffer manager (ABM) to provide a com-
plete solution for available bit rate (ABR) switch pro-
cessing in compliance with the ATM forum's traffic
management 4.0 specification.
The RMCP is located between the ABM and the ALM
(
Fi
g
ure 1
)
.
RMCM/
INGRESS
ABM
RMCP
EGRESS
INGRESS
ALM
EGRESS
UTOPIA 2
TO/FROM
MPHYs TO/FROM
SWITCH
µP
22 Lucent Technologies Inc.
Product Brief
August 2000
for ORCA FPGAs
ATM ABR Cell Manager/Processor CSC
Description (continued)
In the egress direction, the RMCP performs the f o llow-
ing:
■Receives all e
g
ress cells from the ABM in the lon
g
format
(
62 b
y
tes
)
.
■Extracts the ABR’s traffic con
g
estion level informa-
tion from the cells' local headers.
■Calculate s and store s relat iv e and expli cit rates
(
RR
and ER
)
.
■Converts all cells to the short format
(
56 b
y
tes
)
.
■Passes the cells to the ALM.
In the ingress direction, the RMCP.
■Receives all in
g
ress cells from the ALM.
■Passes non-RM cells throu
g
h to the ABM.
■In
j
ects RR and ER information in backward RM cells,
and passes them to the ABM.
The congestion level information is used in the al
g
o-
rithm for the relative rate
(
RR
)
and explicit rate
(
ER
)
al
g
orithms. The resource mana
g
ement
(
RM
)
cell man-
a
g
er
(
RMCM
)
is a stand-alone
VHDL
CSC which is
included with the RMCP or can be purchased sepa-
ratel
y
. This CSC provides the framework for a user-pro-
vided al
g
orithm.
The RMCM is located between the AB M and the ALM
(
Fi
g
ure 1
)
. In t he in
g
ress direction, the RMCM perf orms
the following:
■Receives all ingress cells from the ALM.
■Passes user cells to ABM.
■Allows the user algorithm to write backward RM
cells, updates the CRC-10, and passes the cells to
the ABM.
In the egress direction, the RMCM performs the follow-
ing:
■Receives all egress cells from the ABM in the long
format (62 bytes).
■Extracts and sends congestion and other data to the
user's algorithm.
■Converts all cells to the short format (56 bytes) and
passes the cells to the ALM.
The RMCM synthesizes into an OR2T26A-5 and the
RMCP into an OR2T40A-6.
Design Package
The RM cell processor/manager CSC packa
g
es con-
tain the following:
■VHDL source code
■VHDL testbench
■Scripts and data files for simulation
(
behavioral,
g
ate-
level, and back-annotated
)
, s
y
nthesis, and FPGA
la
y
out
■Detailed documentation:
— Reference
g
uide: CSC features, architecture,
interfaces, and operation
— User's guide: CSC simulation, synthesis, and
FPGA layout step-by step procedures
Required Tools
■Lucent Technolo
g
ies
ORCA
Foundr
y
for FPGA la
y
-
out
■MTI V-s
y
stem for simulation
■Exemplar
Galileo
* extreme for s
y
nthesis
Additional Resources
■Lucent Technolo
g
ies
LUC4AU01 ATM Layer UNI
Manager (ALM)
—Jul
y
1997
■Lucent Technolo
g
ies
LUC4AB01 ATM Buffer Man-
age r (A BM)
—October 1997
■
ATM Forum Traffic Management Specification Ver-
sion 4.0
—April 1996
Ordering Information
Modelware
†, Inc.
Tel: (732)936-1808
Fax: (732)936-1838
E-mail: sales@modelware.com
Internet: www.modelware.com
*
Galileo
is a trademark of Exemplar Logic,
†
Modelware
is a registered tradem ar k of Mod elware, Inc.
Lucent Technologies Inc. 3
Product Brief
August 2000 for ORCA FPGAs
ATM ABR Cell Manager/Processor CSC
Notes:
Lucent Technologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No
rights under a ny patent accom pany the sale of an y such product(s) or i nfo rmation.
ORCA
is a register ed trademark of Lucent Technologies Inc.
Atlanta
is a trade mark of Lucent Technologies , Inc.
Copyright © 2000 Lucent Technologies Inc.
All Rights Reserved
August 2000
PB00-091NCIP
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