AS8SLC512K32 - Austin Semiconductor, Inc.

AS8SLC512K32

Rev. 2.5 5/09

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

1

SRAMSRAM

SRAM

AS8SLC512K32

Austin Semiconductor, Inc.

CS

\

GENERAL DESCRIPTION

The Austin Semiconductor, Inc. AS8SLC512K32 is a 3.3V

16 Megabit CMOS SRAM Module organized as 512Kx32 bits. The

AS8SLC512K32 achieves very high speed access, low power

consumption and high reliability by employing advanced CMOS

memory technology.

This military temperature grade product is ideally suited for

commercial, industrial, and military applications when asynchronous high

speed switching and low ACTIVE opening power & ultra Fast Asyn-

chronous Access is mandated.

FEATURES

• Fast access times: 10, 12, 15, 17 and 20ns

• Fast OE\ access times: 6ns

• Ultra-low operating power < 1W worst case

• Single +3.3V ±0.3V power supply

• Fully static -- no clock or timing strobes necessary

• All inputs and outputs are TTL-compatible

• Easy memory expansion with CE\ and OE\ options

• Automatic CE\ power down

• High-performance, low-power consumption, CMOS

OPTIONS MARKINGS

•Timing

10ns -10

12ns -12

15ns -15

17ns -17

20ns -20

• Package

Ceramic Quad Flatpack Q No. 702

Ceramic Quad Flatpak(.054min SO) Q1

Pin Grid Array P No.904

• Operating Temperature Ranges

Military (-55oC to +125oC) XT

Industrial (-40oC to +85oC) IT

• 2V data retention/low power L

PIN ASSIGNMENT

(Top View)

68 Lead CQFP (Q & Q1)

512K x 32 SRAM

SRAM Memory Array MCM

BLOCK DIAGRAM

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61

27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

GND

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

I/O 16

I/O 17

I/O 18

I/O 19

I/O 20

I/O 21

I/O 22

I/O 23

GND

I/O 24

I/O 25

I/O 26

I/O 27

I/O 28

I/O 29

I/O 30

I/O 31

NC

A0

A1

A2

A3

A4

A5

CE\3

GND

CE\4

WE\1

A6

A7

A8

A9

A10

Vcc

A11

A12

A13

A14

A15

A16

CE\1

OE

CE\2

A17

WE\2

WE\3

WE\4

A18

NC

For more products and information

please visit our web site at

www.austinsemiconductor.com

M1

M2

M3

M4

66 Lead PGA (P)

AS8SLC512K32

Rev. 2.5 5/09

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

2

SRAMSRAM

SRAM

AS8SLC512K32

Austin Semiconductor, Inc.

ABSOLUTE MAXIMUM RATINGS*

Voltage of Vcc Supply Relative to Vss...........-0.5V to +4.6V

Storage Temperature.....................................-65°C to +150°C

Short Circuit Output Current(per I/O)............................20mA

Voltage on Any Pin Relative to Vss............-.5V to Vcc+4.6V

Maximum Junction Temperature**.............................+150°C

*Stresses greater than those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device.

This is a stress rating only and functional operation on the

device at these or any other conditions above those indicated

in the operational sections of this specification is not implied.

Exposure to absolute maximum rating conditions for extended

periods may affect reliability.

**Junction temperature depends upon package type, cycle

time, loading, ambient temperature and airflow. See the Ap-

plication Information section at the end of this datasheet for

more information.

ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS

(-55oC < TA < 125oC and -40oC to +85oC; Vcc = 3.3V ±0.3V)

DESCRIPTION CONDITIONS SYMBOL MIN MAX UNITS NOTES

Input High (logic 1) Voltage V

IH

2.2 V

CC

+0.3 V1

Input Low (logic 1) Voltage V

IL

-0.3 0.8 V 1

Input Leakage Current

ADD,OE

I

LI1

-10 10 µA

Input Leakage Current

WE,CE

I

LI2

-10 10 µA

Output Leakage Current

I/O

Output(s) Disabled

0V<V

OUT

<V

CC

I

LO

-10 10 µA

Output High Voltage I

OH

=-4.0mA V

OH

2.4 V 1

Output Low Voltage I

OL

=8.0mA V

OL

0.5 V 1

0V<V

IN

<V

CC

DESCRIPTION SYMBOL -10 -12 -15 -17 -20 UNITS NOTES

350 320 280 260 240

Low Power (L) 280 240 200 180 160

--- --- --- --- ---

Low Power (L) 120 80 80 80 80

--- --- --- --- ---

Low Power (L) 80 40 40 40 40

100 80 80 80 80

Low Power (L) 80 60 60 60 60

80 60 60 60 60

Low Power (L) 50 36 36 36 36

I

CC2

CS\<V

IL

; V

CC

= MAX

f = MAX = 1/ t

RC

(MIN)

Outputs Open, OE\ = V

IH

MAX

I

CC3

I

CC1

V

IN

= V

CC

- 0.2V, or V

SS

+0.2V

V

CC

=Max; f = 0Hz

CONDITIONS

CS\>V

IH

; V

CC

= MAX

f = MAX = 1/ t

RC

(MIN)

Outputs Open, OE\=V

IH

Low Speed

Power Supply

Current: Operating

Low Speed

Power Supply

Current: Operating

CS\<V

IL

; V

CC

= MAX

f = 10 MHz, OE\ = V

IH

CS\<V

IL

; V

CC

= MAX

f = 1 MHz, OE\ = V

IH

Power Supply

Current: Standby

CMOS Standby

Hi

g

h Speed

Power Supply

Current: Operating

2

mA

mA 2

2, 3,13

I

SBT2

I

SBT1

mA 3, 13

mA

AS8SLC512K32

Rev. 2.5 5/09

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

3

SRAMSRAM

SRAM

AS8SLC512K32

Austin Semiconductor, Inc.

AC TEST CONDITIONS

NOTE:

*This parameter is sampled.

CAPACITANCE (VIN = 0V, f = 1MHz, TA = 25oC)*

SYMBOL PARAMETER MAX UNITS

C

ADD

A0 - A18 Capacitance 40 pF

C

OE

OE\ Capacitance 40 pF

C

WE,

C

CS

WE\ and CS\ Capacitance 12 pF

C

IO

I/O 0- I/O 31 Capacitance 15 pF

Input pulse levels...........................................VSS to 3V

Input rise and fall times...........................................1ns/V

Input timing reference levels...............................1.5V

Output reference levels........................................1.5V

Output load..........................................See Figure 1, 2

TEST SPECIFICATIONS

FIGURE 1

Q

30 pF

RL = 50Ω

VL = 1.5V

ZO = 50Ω

3.3V

Q

333Ω5 pF

319Ω

FIGURE 2

AS8SLC512K32

Rev. 2.5 5/09

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

4

SRAMSRAM

SRAM

AS8SLC512K32

Austin Semiconductor, Inc.

ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS

(NOTE 5) (-55oC<TA < 125oC and -40oC to +85oC; VCC = 3.3V ±0.3V)

MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX

READ CYCLE

READ cycle time

t

RC 10 12 15 17 20 ns

Address access time

t

AA 10 12 15 17 20 ns

Chip select access time

t

ACS 10 12 15 17 20 ns

Output hold from address change

t

OH 12222 ns

Chip select to output in Low-Z

t

LZCS 12222 ns4,6,7

Chip select to output in High-Z

t

HZCS 5 6 7 7.5 8 ns 4,6,7

Output enable access time

t

AOE 050607 7.508 ns

Output enable to output in Low-Z

t

LZOE 00000 ns4,6

Output disable to output in High-Z

t

HZOE 5 6 7 7.5 8 ns 4,6

WRITE CYCLE

WRITE cycle time

t

WC 10 12 15 17 20 ns

Chip select to end of write

t

CW 7 8 10 11 12 ns

Address valid to end of write

t

AW 7 8 10 11 12 ns

Address setup time

t

AS 00000 ns

Address hold from end of write

t

AH 00000 ns

WRITE pulse width, CS\ controlled

t

WP1 9 10121415 ns

WRITE pulse width, WE\ controlled

t

WP2 9 10121415 ns

Data setup time

t

DS 5677.58 ns

Data hold time

t

DH 11111 ns

Write disable to output in Low-z

t

LZWE 22222 ns4,6,7

Write enable to output in High-Z

t

HZWE 5 5 6 6.5 7 ns 4,6,7

NOTES

-10 -17 UNITS

-20

DESCRIPTION -15-12

SYMBOL

AS8SLC512K32

Rev. 2.5 5/09

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

5

SRAMSRAM

SRAM

AS8SLC512K32

Austin Semiconductor, Inc.

LOW VCC DATA RETENTION WAVEFORM

LOW POWER CHARACTERISTICS (L Version Only)

123456789012345678

12345

1

234

5

1

234

5

1

234

5

1

234

5

1

234

5

1

234

5

1

234

5

12345

12345678

1

234567

8

1

234567

8

1

234567

8

1

234567

8

1

234567

8

12345678

123456789012345678

12345

1

234

5

1

234

5

1

234

5

1

234

5

1

234

5

1

234

5

1

234

5

12345

12345678

1

234567

8

1

234567

8

1

234567

8

1

234567

8

1

234567

8

12345678

DATA RETENTION MODE

4.5V 4.5V

VDR > 2V

VDR

tCDR tR

VCC

CS\ 1-4

DESCRIPTION SYMBOL MIN MAX UNITS NOTES

V

CC

for Retention Data V

DR

2V

V

CC

= 2V I

CCDR

24 mA

V

CC

= 3V I

CCDR

32 mA

Chip Deselect to Data

Retention Time tCDR 0ns4

Operation Recovery Time tR20 ms 4, 11

Data Retention Current

All Inputs @ Vcc + 0.2V

or Vss + 0.2V,

CS\ = Vcc + 0.2V

CONDITIONS

7. At any given temperature and voltage condition,

tHZCS, is less than tLZCS, and tHZWE is less than tLZWE.

8. WE\ is HIGH for READ cycle.

9. Device is continuously selected. Chip selects and

output enable are held in their active state.

10. Address valid prior to or coincident with latest

occurring chip enable.

11. tRC= READ cycle time.

12. Chip enable (CS\) and write enable (WE\) can initiate

and terminate a WRITE cycle.

13. ICC is for full 32 bit mode.

NOTES

1. All voltages referenced to VSS (GND).

2. Worst case address switching.

3. ICC is dependent on output loading and cycle rates.

The specified value applies with the outputs

4. This parameter guaranteed but not tested.

5. Test conditions as specified with output loading as

shown in Fig. 1 & 2 unless otherwise noted.

6. tHZCS, tHZOE and tHZWE are specified with CL= 5pF as in

Fig. 2. Transition is measured +/- 200 mV typical from

steady state voltage, allowing for actual tester RC time

constant.

RC(MIN)

unloaded, and f= HZ.

t

1

AS8SLC512K32

Rev. 2.5 5/09

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

6

SRAMSRAM

SRAM

AS8SLC512K32

Austin Semiconductor, Inc.

READ CYCLE NO. 1

READ CYCLE NO. 2

12345

1234567

1

23456

7

1

23456

7

1

23456

7

1234567

12

ADDRESS

DATA I/O PREVIOUS DATA VALID NEW DATA VALID

tOH

tAA

tRC

ADDRESS

tRC

123456789

1234

1

23

4

1

23

4

1

23

4

1234

12345

1

234

5

1

234

5

1

234

5

12345

12345678

123456

1

2345

6

1

2345

6

1

2345

6

123456

1234567

1

23456

7

1

23456

7

1

23456

7

1234567

1234567890123

1234

1

23

4

1

23

4

1234

12345

1

234

5

1

234

5

12345

12345678901

123456

1

2345

6

1

2345

6

123456

1234567

1

23456

7

1

23456

7

1234567

123456

12345

1234

1

23

4

1

23

4

1234

12

1

HIGH IMPEDANCE DATA VALID

tAA

tACS

tLZCS tHZCS

tHZOE

tAOE

tLZOE

CS\

OE\

DATA I/O

AS8SLC512K32

Rev. 2.5 5/09

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

7

SRAMSRAM

SRAM

AS8SLC512K32

Austin Semiconductor, Inc.

WRITE CYCLE NO. 2

(Write Enable Controlled)

WRITE CYCLE NO. 1

(Chip Select Controlled)

ADDRESS

tWC

123456789

1234

1

23

4

1

23

4

1

23

4

1234

12345

1

234

5

1

234

5

1

234

5

12345

1234567890123

123456

1

2345

6

1

2345

6

1

2345

6

123456

1234567

1

23456

7

1

23456

7

1

23456

7

1234567

12345

1234

12345678901234

1

234567890123

4

12345678901234

1

DATA VALID

tAW tCW

tAS

tAH

tLZWE

tWP11

tHZWE

CS\

WE\

DATA I/O

1234

123

1

2

3

123

1234

1

23

4

1234

tDH

tDS

ADDRESS

tWC

123456

DATA VALID

tAW

tAS

tWP21

tCW

CS\

WE\

DATA I/O tDH

tDS

123456789

1234567890123

123456

1

2345

6

1

2345

6

123456

1234567

1

23456

7

1

23456

7

1234567

tAH

NOTES

1. All voltages referenced to VSS (GND).

AS8SLC512K32

Rev. 2.5 5/09

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

8

SRAMSRAM

SRAM

AS8SLC512K32

Austin Semiconductor, Inc.

MECHANICAL DEFINITIONS*

ASI Case #702 (Package Designator Q)

DETAIL A

L1

1o - 7o

R

B

*All measurements are in inches.

4 x D2

4 x D1

D

b

e

A2

SEE DETAIL A

A

A1

E

MIN MA

X

A0.123 0.196

A1 0.118 0.186

A2 0.000 0.020

B

b0.013 0.017

D

D1 0.870 0.890

D2 0.980 1.000

E0.936 0.956

e

R0.005 ---

L1 0.035 0.045

SYMBOL

SMD SPECIFICATIONS

0.010 REF

0.050 BSC

0.800 BSC

AS8SLC512K32

Rev. 2.5 5/09

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

9

SRAMSRAM

SRAM

AS8SLC512K32

Austin Semiconductor, Inc.

MECHANICAL DEFINITIONS*

ASI Case #904 (Package Designator P)

*All measurements are in inches.

4 x D

D1

D2

E1

Pin 66 ePin 11

Pin 1

(identified by

0.060 square pad)

Pin 56

A

A1

L

φb

e

φb1

MIN

MAX

A 0.144 0.181

A1 0.025 0.035

φ

b0.016 0.020

φ

b1 0.045 0.055

D 1.065 1.085

D1/E1

D2

e

L 0.145 0.155

0.600 TYP

0.100 TYP

SYMBOL

1.000 TYP

SMD SPECIFICATIONS

AS8SLC512K32

Rev. 2.5 5/09

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

10

SRAMSRAM

SRAM

AS8SLC512K32

Austin Semiconductor, Inc.

MECHANICAL DEFINITIONS*

ASI Case (Package Designator Q1)

Case Outline A

*All measurements are in inches.

MIN MA

X

A--- 0.196

A1 0.054 ---

b0.013 0.017

B

c0.009 0.012

D/E 0.980 1.000

D1/E1 0.870 0.890

D2/E2

e

L0.035 0.045

R

SYMBOL

SMD SPECIFICATIONS

0.010 TYP

0.800 BSC

0.050 BSC

AS8SLC512K32

Rev. 2.5 5/09

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

11

SRAMSRAM

SRAM

AS8SLC512K32

Austin Semiconductor, Inc.

*AVAILABLE PROCESSES

XT = Extended Temperature Rang -55oC to +125oC

IT = Industrial Temperature Range -40oC to +85oC

883C = Military Processing -55oC to +125oC

OPTION DEFINITIONS

L = 2V data retention/low power

ORDERING INFORMATION

Device Number Package

Type

Speed

ns Options Process

AS8SLC512K32 Q -10 L /*

AS8SLC512K32 Q -12 L /*

AS8SLC512K32 Q -15 L /*

AS8SLC512K32 Q -17 L /*

AS8SLC512K32 Q -20 L /*

Device Number Package

Type

Speed

ns Options Process

AS8SLC512K32 P -10 L /*

AS8SLC512K32 P -12 L /*

AS8SLC512K32 P -15 L /*

AS8SLC512K32 P -17 L /*

AS8SLC512K32 P -20 L /*

Device Number Package

Type

Speed

ns Options Process

AS8SLC512K32 Q1 -10 L /*

AS8SLC512K32 Q1 -12 L /*

AS8SLC512K32 Q1 -15 L /*

AS8SLC512K32 Q1 -17 L /*

AS8SLC512K32 Q1 -20 L /*

EXAMPLE: AS8SLC512K32Q-17L/XT

EXAMPLE: AS8SLC512K32P-12/IT

EXAMPLE: AS8SLC512K32Q1-12/XT

AS8SLC512K32

Rev. 2.5 5/09

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

12

SRAMSRAM

SRAM

AS8SLC512K32

Austin Semiconductor, Inc.

DOCUMENT TITLE

512K x 32 SRAM SRAM Memory Array MCM

REVISION HISTORY

Rev # History Release Date Status

2.5 Updated Q & Q1 Package Specs May 2009Release

Page 8 & 10