M2732A-25F1 - STMicroelectronics

AI00780B

A0-A11 Q0-Q7

VCC

M2732A

GVPP

VSS

Fig ure 1. L og ic Diag ra m

M2732A

NMOS 32K (4K x 8) UV EPROM

FAST ACCESS T IME: 200ns

EXTENDED TEMPERATURE RANGE

SINGLE 5V SUPPL Y VOLTAGE

LOW STANDBY CURRENT: 35mA max

INPUT S and OUTP UT S TT L COMPATIB LE

D URING READ and PRO GR AM

CO MPL ETELY STATIC

DESCRIPTION

The M2732A is a 32,768 bit UV erasable and

electrically programmable memory EPROM. It is

organized as 4,096 words by 8 bits. The M2732A

w ith its single 5V pow er supply an d w ith an acc ess

time of 200 ns, is ideal suited for applications where

fast turn around an d pattern experimentation one

important requirements.

The M2732A is honsed in a 24 pin Window Ceramic

Frit-Seal Dual-in-Line package. The transparent lid

allows the user to expose the chip to ultraviolet light

to eras e the bit pattern. A new pattern can be t he n

w ritten t o the cleric e by following the programm i ng

procedure.

A0 - A1 1 Address Inputs

Q0 - Q7 Data Outputs

E Chip Enable

GVPP Output Enable / Program Supply

VCC Supply Voltage

VSS Ground

Table 1. Signal Names

FDIP24W (F)

July 1994 1/9

VSS

GVPP

A10

A11

VCC

AI00781

M2732A

A5 A9

Figu re 2. DIP Pin Connecti ons

Symbol Parameter Value Unit

TAAmbient Operating Temperature grade 1

grade 6 0 to 70

–40 to 85 °C

TBIAS Temperature Under Bias grade 1

grade 6 –10 to 80

–50 to 95 °C

TSTG Storage Temperature –65 to 125 °C

VIO Input or Output Voltages –0.6 to 6 V

VCC Supply Voltage –0.6 to 6 V

VPP Program Supply Voltage –0.6 to 22 V

Note: Except f or the rat ing "Operating Temperature Range", stresses above t hose lis ted in the Table "A bsolute Max imum R atings" may cause

permanent damage to the device. These a re stress ratings only and operation of the device a t these or any o ther conditions above those

indicated in the Operating sections of this specification is not implied. Exposure to A bsolut e Maximum Rat ing conditions for extended periods

may affect device reli ability. Refer also to the SGS-THOMSON SURE Program and other relevant quality documents.

Tab le 2. Absolu te Maxim um Ratin g s

DEVI CE OPERAT IO N

The six modes of operation for the M2732A are

listed in the Operating Modes Table. A single 5V

power supply is required in the read mode. All

inputs are TTL level except for V PP.

Read Mode

The M2732A has two control functions, both of

which must be logically satisf ied in order to obtain

data at the o utputs. Chip Enable (E) is the power

control and should be used for device selection.

Out put Enable (G) is the o utput control and should

be used to gate data to the output pins, inde-

pendent of device selection.

Assuming that the add resses are stable, address

access time (tAVAQ) is equal to the delay from E to

output (tELQV). Data is available at the outputs after

the falling edge of G, assuming that E has been low

and the addresses have been stable for at least

tAVQV-tGLQV.

S tan dby Mo d e

The M2732A has a standby mode which reduces

the active power current by 70 %, from 125 mA to

35 mA. The M2732A is placed in the standby mode

by applying a TTL high signal to E input. When in

standby mode, the outputs are in a high impedance

state, independent of the GVPP input .

Two Line Output Control

Because M2732A’s are usually used in larger mem-

ory arrays, this product features a 2 line control

function which accommodates the use of multiple

memory connection. The two line control function

allows:

a. the low est poss ible memory power dissipation,

b. complete ass urance that out put bus c ontent io n

will not occur.

To most efficiently use these two control lines, it is

recomm ended that E be decoded and used as the

primary device selecting function, while G should

be made a common connection to all devices in the

array and connected to the READ line from the

sys tem cont rol bus.

This ensures that all deselected memory devices

are in their low power standby mode and that the

output pins are only active when data is required

from a particular memory device.

2/9

M2732A

Programming

W hen delivered, and after each erasure, all bits of

the M2732A are in the “1" state. Data is introduced

by selectively programming ”0’s" into the desired

bit locations. Although only “0’s” will be pro-

gramm ed, both “1’ s” and “0’s ” can be present ed i n

the data word. The only way to change a “0" to a

”1" is by ultraviolet light erasure.

The M2732A is in the programming mode when the

GVPP input is at 21V. A 0.1µF capacitor must be

placed across GVPP and ground to suppress spu-

rious voltage transients which may damage the

device. The data to be programmed is applied, 8

bits in parallel , to the data output pins. The levels

required for the addr es s and dat a inputs are TTL.

When the address and data are stable, a 50ms,

active low, TTL program pulse is appl ied t o the E

input. A program pulse must be applied at each

address location to be programmed. Any location

can be programmed at any time - either individually,

sequentially, or at random. The program pulse has

a maximum width of 55ms. The M2732A must not

be programmed with a DC signal applied to the E

input.

Programming of multiple M2732As in parallel with

the same data can be easily ac complished due to

the simplicity of the programming requirements.

Inputs of the paralleled M2732As may be con-

nected together when they are programmed with

the same data. A low level TTL pulse applied to the

E input programs the paralleled 2732As.

Pro gram Inhibit

Programming of multiple M2732As in parallel with

different data is also easily accomplished. Except

for E, all like inputs ( including GVPP) of the parallel

M2732As may be common. A TTL level program

pulse applied to a M2732A’s E input with GVPP at

21V will program that M2732A. A high level E input

inhibits the other M2732As from being pro-

grammed.

Program Verify

A verify should be performed on the programmed

bits to determine that they were correctly pro-

grammed. The verify i s carried out with GVPP and

E a t VIL.

ERASURE OPERATION

The erasure characteristics of the M2732A are

such that erasure begins when the cells are ex-

posed to light with wavelengths shorter than ap-

proximately 4000 Å. It should be noted that sunlight

and certai n ty pes of fluorescent lamps have wave-

lengths in the 3000-4000 Å range. Research shows

that constant exposure to room level fluorescent

lighting could erase a typical M2732A in approxi-

mately 3 years, while it would take ap proximately

1 week to cause erasure when exposed to the

direct sunlight. If the M2732A is to be exposed to

these types of lighting conditions for extended pe-

riods of t ime, it is suggested t hat opaque labels b e

put over the M2732A window to prevent uninten-

tio nal erasure.

The recommended erasure procedure for the

M27 32A is exposure to shortwave ultraviolet light

which has a wav elength of 2537 Å. The int egrated

dose (i.e. UV intensity x exposure time) for erasure

sho uld be a minimum of 15 W-sec/ cm 2. The era-

sure time with this dosage is approximately 15 to

20 minutes using an ultraviolet lamp with 12000

µW/cm2 power rating. The M2732A should be

placed within 2.5 cm of the lamp tubes during

erasure. Some lamps have a filter on their tubes

which should be removed before erasure.

Mode E GVPP VCC Q0 - Q7

Read VIL VIL VCC Data Out

Program VIL Pulse VPP VCC Data In

Verify VIL VIL VCC Data Out

Program Inhibit VIH VPP VCC Hi-Z

Standby VIH XV

CC Hi-Z

Note: X = V IH or VIL.

Table 3. O perati ng Mod es

3/9

M2732A

AI00827

2.4V

0.45V

2.0V

0.8V

Figure 3. AC Testing I nput Outp ut W avefo rm s

Input Rise and Fall Times ≤ 20ns

Input Pulse Voltages 0.45V to 2.4V

Input and Output Timing Ref. Voltages 0.8V to 2.0V

AC MEASUREMENT CONDITI ONS

AI00828

1.3V

OUT

CL = 100pF

CL includes JIG capacitance

3.3kΩ

1N914

DEVICE

UNDER

TEST

Fi gure 4. AC Testing L oad Ci rcui t

Note that Output Hi-Z is defined as the point where data

is no longer driven.

Symbol Parameter Test Condition Min Max Unit

CIN Input Capacitance (except GVPP)V

IN = 0V 6 pF

CIN1 Input Capacitance (GVPP)V

IN = 0V 20 pF

COUT Output Capacitance VOUT = 0V 12 pF

Note: 1. Sampled only, not 100% tested.

Table 4. Capacit ance (1) (TA = 2 5 °C, f = 1 MHz )

AI00782

tAXQX

tEHQZ

DATA OUT

A0-A11

Q0-Q7

tAVQV

tGHQZ

tGLQV

tELQV

VALID

Hi-Z

Figur e 5. Read Mode AC Wavefor m s

4/9

M2732A

Symbol Alt Parameter Test

Condition

M2732A Unit

-2, -20 blank, -25 -3 -4

Min Max Min Max Min Max Min Max

tAVQV tACC Address Valid to

Output Valid E = VIL,

G = VIL 200 250 300 450 ns

tELQV tCE Chip Enable Low to

Output Valid G = VIL 200 250 300 450 ns

tGLQV tOE Output Enable Low

to Output Valid E = VIL 100 100 150 150 ns

tEHQZ (2) tDF Chip Enable High to

Output Hi-Z G = VIL 0 60 0 60 0 130 0 130 ns

tGHQZ (2) tDF Output Enable High

to Output Hi-Z E = VIL 0 60 0 60 0 130 0 130 ns

tAXQX tOH Address Transition to

Output Transiti on E = VIL,

G = VIL 0000ns

Notes: 1. VCC must be ap plie d simultaneously with or befo re VPP and removed si multaneously or aft er VPP.

2. Sampled only, not 100% tested.

Tab le 6. Read Mode AC Ch aracterist ics (1)

(TA = 0 to 70 °C or –40 to 85 °C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC)

Symbol Parameter Test Condition Value Unit

Min Max

ILI Input Leakage Current 0 ≤ VIN ≤ VCC ±10 µA

ILO Output Leakage Current VOUT = VCC ±10 µA

ICC Supply Current E = VIL, G = VIL 125 mA

ICC1 Supply Current (Standby) E = VIH, G = VIL 35 mA

VIL Input Low Voltage –0.1 0.8 V

VIH Input High Voltage 2 VCC + 1 V

VOL Output Low Voltage IOL = 2.1mA 0.45 V

VOH Output High Voltage IOH = –400µA 2.4 V

Note: 1. VCC must be applied simultaneously wit h or bef o re VPP and removed simultaneously or afte r VPP.

Tabl e 5. Read Mod e DC Characteristics (1)

(TA = 0 to 70 °C or –40 to 85 °C; VCC = 5V ± 5% or 5V ± 10%; V PP = VCC)

5/9

M2732A

Symbol Parameter Test Condition Min Max Units

ILI Input Leakage Current VIL ≤ VIN ≤ VIH ±10 µA

ICC Supply Current E = VIL, G = VIL 125 mA

IPP Program Current E = VIL, G = VPP 30 mA

VIL Input Low Voltage –0.1 0.8 V

VIH Input High Voltage 2 VCC + 1 V

VOL Output Low Vol tage IOL = 2.1mA 0.45 V

VOH Output High Voltage IOH = –400µA 2.4 V

Note: 1. VCC must be applied simultaneously with or before VPP and remov ed si multaneously or aft er VPP.

Tabl e 7. P rog rammi ng Mode DC Characteri stics (1)

(TA = 25 °C; VCC = 5V ± 5%; VPP = 21V ± 0.5V)

Symbol Alt Parameter Test Condition Min Max Units

tAVEL tAS Address Valid to Chip Enable

Low 2µs

tQVEL tDS Input Valid to Chip Enable Low 2 µs

tVPHEL tOES VPP High to Chip Enable Low 2 µs

tVPL1VPL2 tPRT VPP Rise T i me 50 ns

tELEH tPW Chip Enable Program Pulse

Width 45 55 ms

tEHQX tDH Chip Enable High to Input

Transition 2µs

tEHVPX tOEH Chip Enable High to VPP

Transition 2µs

tVPLEL tVR VPP Low to Chip Enable Low 2 µs

tELQV tDV Chip Enable Low to Output

Valid E = VIL, G = VIL 1µs

tEHQZ tDF Chip Enable High to Output

Hi-Z 0 130 ns

tEHAX tAH Chip Enable High to Address

Transition 0ns

Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.

Table 8. Program ming Mode AC Charact eristi cs (1)

(TA = 25 °C; VCC = 5V ± 5% ; VPP = 21V ± 0.5V )

6/9

M2732A

AI00783

tVPLEL

PROGRAM

DATA IN

A0-A11

GVPP

Q0-Q7 DATA OUT

tAVEL

tQVEL

tVPHEL

tEHQX

tEHVPX

tELEH

tELQV

tEHAX

tEHQZ

VERIFY

VALID

Figur e 6. Pro g rammi ng and Verify Mo des AC Waveform s

Speed and VCC Tolerance

-2 200 ns, 5V ±5%

blank 250 ns, 5V ±5%

-3 300 ns, 5V ±5%

-4 450 ns, 5V ±5%

-20 200 ns, 5V ±10%

-25 250 ns, 5V ±10%

Package

F FDIP24W

Temperature Range

1 0 to 70 °C

6 –40 to 85 °C

Exam ple: M2732A - 2 F 1

OR D ERI NG I NF OR MATION SC H EM E

For a list of available options (Speed, VCC T olerance, Package, etc...) refer to the current Memory Shortform

catalogue.

For fur ther information on any aspect of this device, please contac t SGS -T HOMSO N Sales Office nearest

to you.

7/9

M2732A

FDIPW-a

B1 B e1

E1 E

CαeA

∅

Symb mm inches

Typ Min Max Typ Min Max

A 5.71 0.225

A1 0.50 1.78 0.020 0.070

A2 3.90 5.08 0.154 0.200

B 0.40 0.55 0.016 0.022

B1 1.17 1.42 0.046 0.056

C 0.22 0.31 0.009 0.012

D 32.30 1.272

E 15.40 15.80 0.606 0.622

E1 13.05 13.36 0.514 0.526

e1 2.54 – – 0.100 – –

e3 27.94 – – 1.100 – –

eA 16.17 18.32 0.637 0.721

L 3.18 4.10 0.125 0.161

S 1.52 2.49 0.060 0.098

∅7.11 – – 0.280 – –

α4°15°4°15°

N24 24

FDIP24W

Drawing is not to scale

FDIP24W - 24 pin Ceramic Frit-seal DIP, wi th w indow

8/9

M2732A

Info rmation furnished is believed to b e accurate an d r eliable. However, SGS-THOMSON Microelectronics assumes no responsibilit y for the

consequences of use o f such information nor for any infringement of patents or other rights of third parties which may result from its use. No

license is granted by implication or ot herwise under any patent o r pat ent rights of SGS-THOMSON Microelect ronic s. Specif ications mentioned

in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.

SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express

written approval of SGS-THOMSON Mic roelectronics .

SGS-THOMSON Microelect ro nics GROUP OF COMPANIES

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9/9

M2732A