MCP662-E/SN - Microchip Technology

MCP660/1/2/3/4/5/9

Features

• Gain Bandwidth Product: 60 MHz (typical)

• Short Circuit Current: 90 mA (typical)

• Noise: 6.8 nV/√Hz (typical, at 1 MHz)

• Rail-to-Rail Output

• Slew Rate: 32 V/µs (typical)

• Supply Current: 6.0 mA (typical)

• Power Supply: 2.5V to 5.5V

• Extended Temperature Range: -40°C to +125°C

Typical Applications

• Driving A/D Converters

• Power Amplifier Control Loops

• Barcode Scanners

• Optical Detector Amplifier

Design Aids

• SPICE Macro Models

•FilterLab

® Software

• Microchip Advanced Part Selector (MAPS)

• Analog Demonstration and Evaluation Boards

• Application Notes

Description

The Microchip Technology, Inc. MCP660/1/2/3/4/5/9

family of operational amplifiers (op amps) features high

gain bandwidth product (60 MHz, typical) and high

output short circuit current (90 mA, typical). Some also

provide a Chip Select pin (CS) that supports a Low

Power mode of operation. These amplifiers are

optimized for high speed, low noise and distortion,

single-supply operation with rail-to-rail output and an

input that includes the negative rail.

This family is offered in single (MCP661), single with

CS pin (MCP663), dual (MCP662) and dual with two

CS pins (MCP665), triple (MCP660), quad (MCP664)

and quad with two CS pins (MCP669). All devices are

fully specified from -40°C to +125°C.

Typical Application Circuit

Power Driver with High Gain

R1R2

VIN

VDD/2 VOUT

R3RL

MCP66X

60 MHz, 6 mA Op Amps

MCP660/1/2/3/4/5/9

Package Types

MCP661

SOIC

MCP662

SOIC

VIN+

VIN-

VSS

VDD

VOUT

5NC

NCNC

VINA+

VINA-

VSS

VOUTA VDD

VOUTB

VINB-

VINB+

MCP665

MSOP

VINA+

VINA-

VSS

VOUTA VDD

VOUTB

VINB-

VINB+

CSA5 6 CSB

MCP662

3x3 DFN*

VINA+

VINA-

VSS

VOUTA VDD

VOUTB

VINB-

VINB+

MCP665

3x3 DFN*

* Includes Exposed Thermal Pad (EP); see Table 3-1.

VINA+

VINA-

CSA

VOUTA VDD

VOUTB

VINB-

CSB

VSS VINB+

MCP663

SOIC

VIN+

VIN-

VSS

VDD

VOUT

5NC

MCP660

SOIC, TSSOP

VDD

NC VOUTC

VINC-

VINC+

VSS

VINA+510 VINB+

VINA-69

VOUTA 7 8 VOUTB

VINB-

MCP669

4x4 QFN*

VDD

VINB+

VINA-VIND+

VSS

VINB-

VINC+

VOUTB

CSBC

VOUTC

VINC-

VOUTA

CSAD

VOUTD

VIND-

VINA+EP

15 14 13

5678

MCP664

SOIC, TSSOP

VINA+

VINA-

VDD

VOUTA VOUTD

VIND-

VIND+

VSS

VINB+510 VINC+

VINB-69

VOUTB 7 8 VOUTC

VINC-

MCP660

4x4 QFN*

VDD

VINA+

NC VINC+

VSS

VINA-

VINB+

VOUTA

VOUTB

VINB-

VOUTC

VINC-

NC EP

15 14 13

5678

VIN+

VOUT

VSS

VIN-

MCP663

SOT-23-6

VDD

VIN+

VOUT

VSS

VIN-

MCP661

SOT-23-5

VDD

MCP661

2x3 TDFN *

VIN+

VIN–

VSS

VDD

VOUT

5NC

CSNC

MCP660/1/2/3/4/5/9

1.0 ELECTRICAL

CHARACTERISTICS

1.1 Absolute Maximum Ratings †

VDD – VSS .......................................................................6.5V

Current at Input Pins ....................................................±2 mA

Analog Inputs (VIN+ and VIN–) †† . VSS – 1.0V to VDD + 1.0V

All other Inputs and Outputs .......... VSS – 0.3V to VDD + 0.3V

Output Short Circuit Current ................................ Continuous

Current at Output and Supply Pins ..........................±150 mA

Storage Temperature ...................................-65°C to +150°C

Max. Junction Temperature ........................................ +150°C

ESD protection on all pins (HBM, MM) ................≥ 1 kV, 200V

† Notice: Stresses above those listed under “Absolute

Maximum Ratings” may cause permanent damage to

the device. This is a stress rating only and functional

operation of the device at those or any other conditions

above those indicated in the operational listings of this

specification is not implied. Exposure to maximum rat-

ing conditions for extended periods may affect device

reliability.

†† See Section 4.1.2 “Input Voltage and Current

Limits”.

1.2 Specifications

TABLE 1-1: DC ELECTRICAL SPECIFICATIONS

Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND,

VCM = VDD/3, VOUT ≈ VDD/2, VL = VDD/2, RL = 1 kΩ to VL and CS = VSS (refer to Figure 1-2).

Parameters Sym Min Typ Max Units Conditions

Input Offset

Input Offset Voltage VOS -8 ±1.8 +8 mV

Input Offset Voltage Drift ΔVOS/ΔTA—±2.0—µV/°CT

A= -40°C to +125°C

Power Supply Rejection Ratio PSRR 61 76 — dB

Input Current and Impedance

Input Bias Current IB—6—pA

Across Temperature IB—130—pAT

A = +85°C

Across Temperature IB— 1700 5,000 pA TA = +125°C

Input Offset Current IOS —±10—pA

Common Mode Input

Impedance

ZCM —10

13||9 — Ω||pF

Differential Input Impedance ZDIFF —10

13||2 — Ω||pF

Common Mode

Common-Mode Input Voltage

Range

VCMR VSS − 0.3 — VDD − 1.3 V (Note 1)

Common-Mode Rejection Ratio CMRR 64 79 — dB VDD = 2.5V, VCM = -0.3 to 1.2V

CMRR 66 81 — dB VDD = 5.5V, VCM = -0.3 to 4.2V

Open Loop Gain

DC Open Loop Gain

(large signal)

AOL 88 117 — dB VDD = 2.5V, VOUT = 0.3V to

2.2V

AOL 94 126 — dB VDD = 5.5V, VOUT = 0.3V to

5.2V

Note 1: See Figure 2-5 for temperature effects.

2: The ISC specifications are for design guidance only; they are not tested.

MCP660/1/2/3/4/5/9

Output

Maximum Output Voltage Swing VOL, VOH VSS + 25 — VDD −25 mV VDD = 2.5V, G = +2,

0.5V Input Overdrive

VOL, VOH VSS + 50 — VDD −50 mV VDD = 5.5V, G = +2,

0.5V Input Overdrive

Output Short Circuit Current ISC ±45 ±90 ±145 mA VDD = 2.5V (Note 2)

ISC ±40 ±80 ±150 mA VDD = 5.5V (Note 2)

Power Supply

Supply Voltage VDD 2.5 — 5.5 V

Quiescent Current per Amplifier IQ3 6 9 mA No Load Current

TABLE 1-2: AC ELECTRICAL SPECIFICATIONS

Electrical Characteristics: Unless indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2,

VOUT ≈ VDD/2, VL = VDD/2, RL = 1 kΩ to VL, CL = 20 pF and CS = VSS (refer to Figure 1-2).

Parameters Sym Min Typ Max Units Conditions

AC Response

Gain Bandwidth Product GBWP — 60 — MHz

Phase Margin PM — 65 — ° G = +1

Open Loop Output Impedance ROUT —10— Ω

AC Distortion

Total Harmonic Distortion plus Noise THD+N — 0.003 — % G = +1, VOUT = 2VP-P

, f = 1 kHz,

VDD = 5.5V, BW = 80 kHz

Differential Gain, Positive Video

(Note 1)

DG — 0.3 — % NTSC, VDD = +2.5V, VSS = -2.5V,

G = +2, VL = 0V, DC VIN = 0V to

0.7V

Differential Gain, Negative Video

(Note 1)

DG — 0.3 — % NTSC, VDD = +2.5V, VSS = -2.5V,

G = +2, VL = 0V,

DC VIN = 0V to -0.7V

Differential Phase, Positive Video

(Note 1)

DP — 0.3 — ° NTSC, VDD = +2.5V, VSS = -2.5V,

G = +2, VL = 0V,

DC VIN = 0V to 0.7V

Differential Phase, Negative Video

(Note 1)

DP — 0.9 — ° NTSC, VDD = +2.5V, VSS = -2.5V,

G = +2, VL = 0V,

DC VIN = 0V to -0.7V

Step Response

Rise Time, 10% to 90% tr— 5 — ns G = +1, VOUT = 100 mVP-P

Slew Rate SR — 32 — V/µs G = +1

Noise

Input Noise Voltage Eni —14—µV

P-P f = 0.1 Hz to 10 Hz

Input Noise Voltage Density eni —6.8—nV/√Hz f = 1 MHz

Input Noise Current Density ini 4—fA/√Hz f = 1 kHz

Note 1: These specifications are described in detail in Section 4.3 “Distortion”. (NTSC refers to a National

Television Standards Committee signal.)

TABLE 1-1: DC ELECTRICAL SPECIFICATIONS (CONTINUED)

Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND,

VCM = VDD/3, VOUT ≈ VDD/2, VL = VDD/2, RL = 1 kΩ to VL and CS = VSS (refer to Figure 1-2).

Parameters Sym Min Typ Max Units Conditions

Note 1: See Figure 2-5 for temperature effects.

2: The ISC specifications are for design guidance only; they are not tested.

MCP660/1/2/3/4/5/9

TABLE 1-3: DIGITAL ELECTRICAL SPECIFICATIONS

Electrical Characteristics: Unless indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2,

VOUT ≈ VDD/2, VL = VDD/2, RL = 1 kΩ to VL, CL = 20 pF and CS = VSS (refer to Figure 1-1 and Figure 1-2).

Parameters Sym Min Typ Max Units Conditions

CS Low Specifications

CS Logic Threshold, Low VIL VSS —0.2V

CS Input Current, Low ICSL —-0.1—nACS = 0V

CS High Specifications

CS Logic Threshold, High VIH 0.8VD

VDD V

CS Input Current, High ICSH —-0.7—µACS = VDD

GND Current ISS -2 -1 —µA

CS Internal Pull Down Resistor RPD —5—MΩ

Amplifier Output Leakage IO(LEAK

)

—40—nACS = VDD, TA = +125°C

CS Dynamic Specifications

CS Input Hysteresis VHYST —0.25 —V

CS High to Amplifier Off Time

(output goes High-Z)

tOFF — 200 — ns G = +1 V/V, VL = VSS

CS = 0.8VDD to VOUT = 0.1(VDD/2)

CS Low to Amplifier On Time tON —210µs

G = +1 V/V, VL = VSS,

CS = 0.2VDD to VOUT = 0.9(VDD/2)

TABLE 1-4: TEMPERATURE SPECIFICATIONS

Electrical Characteristics: Unless indicated, all limits are specified for: VDD = +2.5V to +5.5V, VSS = GND.

Parameters Sym Min Typ Max Units Conditions

Temperature Ranges

Specified Temperature Range TA-40 — +125 °C

Operating Temperature Range TA-40 — +125 °C (Note 1)

Storage Temperature Range TA-65 — +150 °C

Thermal Package Resistances

Thermal Resistance, 5L-SOT-23 θJA — 220.7 — °C/W

Thermal Resistance, 6L-SOT-23 θJA — 190.5 — °C/W

Thermal Resistance, 8L-3x3 DFN θJA — 56.7 — °C/W (Note 2)

Thermal Resistance, 8L-SOIC θJA — 149.5 — °C/W

Thermal Resistance, 8L-2x3 TDFN θJA — 52.5 — °C/W

Thermal Resistance, 10L-3x3 DFN θJA — 53.3 — °C/W (Note 2)

Thermal Resistance, 10L-MSOP θJA —202—°C/W

Thermal Resistance, 14L-SOIC θJA — 95.3 — °C/W

Thermal Resistance, 14L-TSSOP θJA —100—°C/W

Thermal Resistance, 16L-QFN θJA — 45.7 — °C/W

Note 1: Operation must not cause TJ to exceed Maximum Junction Temperature specification (+150°C).

2: Measured on a standard JC51-7, four layer printed circuit board with ground plane and vias.

MCP660/1/2/3/4/5/9

1.3 Timing Diagram

FIGURE 1-1: Timing Diagram.

1.4 Test Circuits

The circuit used for most DC and AC tests is shown in

Figure 1-2. This circuit can independently set VCM and

VOUT

; see Equation 1-1. Note that VCM is not the

circuit’s Common mode voltage ((VP + VM)/2), and that

VOST includes VOS plus the effects (on the input offset

error, VOST) of temperature, CMRR, PSRR and AOL.

EQUATION 1-1:

FIGURE 1-2: AC and DC Test Circuit for

Most Spe cific ations.

VOUT

ISS

ICS

-1 µA

High-Z

1 µA

-6 mA -1 µA

tON tOFF

High-Z

0 nA 1 µA

CS VIL VIH

(typical) (typical) (typical)

(typical)

(typical) (typical)

GDM RFRG

⁄

VCM VPVDD 2

⁄

+()2

⁄

VOUT VDD 2

⁄

()VPVM

–()VOST 1G

+()++=

Where:

GDM = Differential Mode Gain (V/V)

VCM = Op Amp’s Common Mode

Input Voltage

(V)

VOST = Op Amp’s Total Input Offset

Voltage

(mV)

VOST VIN– VIN+

–=

VDD

RGRF

VOUT

CB2

CB1

10 kΩ

RGRF

VDD/2

10 kΩ

20 pF1 kΩ

2.2 µF100 nF

VIN-

VIN+

6.8 pF

MCP66X

MCP660/1/2/3/4/5/9

2.0 TYPICAL PERFORMANCE CURVES

Note: Unless indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2,

RL = 1 kΩ to VL, CL = 20 pF and CS = VSS.

2.1 DC Signal Inputs

FIGURE 2-1: Input Offset Voltage.

FIGURE 2-2: Input Offset Voltage Drift.

FIGURE 2-3: Input Offset Voltage vs.

Power Supply Voltage with VCM = 0V.

FIGURE 2-4: Input Offset Voltage vs.

Output Voltage.

FIGURE 2-5: Low Input Common Mode

Voltage Headroom vs. Ambient Temperature.

FIGURE 2-6: High Input Common Mode

Voltage Headroom vs. Ambient Temperature.

Note: The graphs and tables provided following this note are a statistical summary based on a limited number of

samples and are provided for informational purposes only. The performance characteristics listed herein

are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified

operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

10%

12%

14%

16%

18%

20%

22%

-6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6

Input Offset Voltage (mV)

Percentage of Occurrences

100 Samples

TA = +25°C

VDD = 2.5V and 5.5V

10%

12%

14%

16%

18%

20%

22%

24%

-12 -10 -8 -6 -4 -2 0 2 4 6 8 10 12

Input Offset Voltage Drift (µV/°C)

Percentage of Occurrences

100 Samples

VDD = 2.5V and 5.5V

TA = -40°C to +125°C

-2.0

-1.8

-1.6

-1.4

-1.2

-1.0

-0.8

-0.6

-0.4

-0.2

0.0

1.52.02.53.03.54.04.55.05.56.06.5

Power Supply Voltage (V)

Input Offset Voltage (mV)

+125°C

+85°C

+25°C

-40°C

Representative Part

VCM = VSS

0.6

0.7

0.8

0.9

1.0

1.1

1.2

1.3

1.4

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Output Voltage (V)

Input Offset Voltage (mV)

VDD = 2.5V

VDD = 5.5V

Representative Part

-0.5

-0.4

-0.3

-0.2

-0.1

0.0

-50 -25 0 25 50 75 100 125

Ambient Temperature (°C)

Low Input Common

Mode Headroom (V)

VDD = 2.5V

1 Lot

Low (VCMR_L – VSS)

VDD = 5.5V

1.0

1.1

1.2

1.3

1.4

-50 -25 0 25 50 75 100 125

Ambient Temperature (°C)

High Input Common

Mode Headroom (V)

VDD = 2.5V

VDD = 5.5V

1 Lot

High (VDD – VCMR_H)

MCP660/1/2/3/4/5/9

Note: Unless indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2,

RL = 1 kΩ to VL, CL = 20 pF and CS = VSS.

FIGURE 2-7: Input Offset Voltage vs.

Common Mode Voltage with VDD = 2.5V.

FIGURE 2-8: Input Offset Voltage vs.

Common Mode Voltage with VDD = 5.5V.

FIGURE 2-9: CMRR and PSRR vs.

Ambient Temperature.

FIGURE 2-10: DC Open-Loop Gain vs.

Ambient Temp eratu re .

FIGURE 2-11: DC Open-Loop Gain vs.

Load Resistance.

FIGURE 2-12: In put Bias and Offset

Currents vs. Ambient Temperature with

VDD = +5.5V.

-2.0

-1.5

-1.0

-0.5

0.0

0.5

1.0

1.5

2.0

-0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

Input Common Mode Voltage (V)

Input Offset Voltage (mV)

VDD = 2.5V

Representative Part

-40°C

+25°C

+85°C

+125°

-2.0

-1.5

-1.0

-0.5

0.0

0.5

1.0

1.5

2.0

-0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

Input Common Mode Voltage (V)

Input Offset Voltage (mV)

VDD = 5.5V

Representative Part

+125°

+85°C

+25°C

40°C

100

105

110

-50 -25 0 25 50 75 100 125

Ambient Temperature (°C)

CMRR, PSRR (dB)

PSRR

CMRR, VDD = 2.5V

CMRR, VDD = 5.5V

100

105

110

115

120

125

130

-50 -25 0 25 50 75 100 125

Ambient Temperature (°C)

DC Open-Loop Gain (dB)

VDD = 5.5V

VDD = 2.5V

100

105

110

115

120

125

130

1.E+02 1.E+03 1.E+04 1.E+05

Load Resistance (Ω)

DC Open-Loop Gain (dB)

VDD = 5.5V

VDD = 2.5V

100 1k 10k 100k

1.E-12

1.E-11

1.E-10

1.E-09

1.E-08

25 45 65 85 105 125

Ambient Temperature (°C)

Input Bias, Offset Currents

(pA)

VDD = 5.5V

VCM = VCMR_H

| IOS |

10p

100p

10n

MCP660/1/2/3/4/5/9

Note: Unless indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2,

RL = 1 kΩ to VL, CL = 20 pF and CS = VSS.

FIGURE 2-13: Input Bias Current vs. Input

Voltage (below VSS).

FIGURE 2-14: Input Bias and Offset

Currents vs. Common Mode Input Voltage with

TA = +85°C.

FIGURE 2-15: In put Bias and Offset

Currents vs. Common Mode Input Voltage with

TA = +125°C.

1.E-12

1.E-11

1.E-10

1.E-09

1.E-08

1.E-07

1.E-06

1.E-05

1.E-04

1.E-03

-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0

Input Voltage (V)

Input Current Magnitude (A)

+125°C

+85°C

+25°C

-40°C

100µ

10µ

1µ

100n

10n

100p

10p

-120

-100

-80

-60

-40

-20

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

Common Mode Input Voltage (V)

Input Bias, Offset Currents

(pA)

Representative Part

TA = +85°C

VDD = 5.5V

IOS

-400

-200

200

400

600

800

1000

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

Common Mode Input Voltage (V)

Input Bias, Offset Currents

(pA)

Representative Part

TA = +125°C

VDD = 5.5V

IOS

MCP660/1/2/3/4/5/9

Note: Unless indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2,

RL = 1 kΩ to VL, CL = 20 pF and CS = VSS.

2.2 Other DC Voltages and Currents

FIGURE 2-16: Output Voltage Headroom

vs. Output Current.

FIGURE 2-17: Output Voltage Headroom

vs. Ambient Temperature .

FIGURE 2-18: Output Short Circuit Current

vs. Power Supply Voltage.

FIGURE 2-19: Supply Current vs. Power

Supply Voltage.

FIGURE 2-20: Supply Current vs. Common

Mode Input Voltage.

100

1000

0.1 1 10 100

Output Current Magnitude (mA)

Output Voltage Headroom

(mV)

VDD = 2.5V

VDD = 5.5

VDD – VOH

VOL – VSS

-50-25 0 255075100125

Ambient Temperature (°C)

Output Headroom (mV)

VDD = 5.5V

VOL – VSS

VDD = 2.5

VDD – VOH

RL = 1 kΩ

-100

-80

-60

-40

-20

100

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

6.5

Power Supply Voltage (V)

Output Short Circuit Current

(mA)

+125°C

+85°C

+25°C

-40°C

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

6.5

Power Supply Voltage (V)

Supply Current

(mA/amplifier)

+125°C

+85°C

+25°C

-40°C

-0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

Common Mode Input Voltage (V)

Supply Current

(mA/amplifier)

VDD = 2.5V

VDD = 5.5

MCP660/1/2/3/4/5/9

Note: Unless indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2,

RL = 1 kΩ to VL, CL = 20 pF and CS = VSS.

2.3 Frequency Response

FIGURE 2-21: CMRR and PSRR vs.

Frequency.

FIGURE 2-22: Open-Loop Gain vs.

Frequency.

FIGURE 2-23: Gain Bandwidth Product

and Phase Margin vs. Ambient Temperature.

FIGURE 2-24: Gain Bandwidth Product

and Phase Margin vs. Common Mode Input

Voltage.

FIGURE 2-25: Gain Bandwidth Product

and Phase Margin vs. Output Voltage.

FIGURE 2-26: Closed-Loop Output

Impedance vs. Frequency.

100

1.E+2 1.E+3 1.E+4 1.E+5 1.E+6 1.E+7

Frequency (Hz)

CMRR, PSRR (dB)

100 1M10k 10M100k1k

CMRR

PSRR+

PSRR-

-20

100

120

140

1.E+

Frequency (Hz)

Open-Loop Gain (dB)

-240

-210

-180

-150

-120

-90

-60

-30

Open-Loop Phase (°)

| AOL |

∠AOL

100 10k 1M 100M1 1k 100k 10M 1G10

-50-250 255075100125

Ambient Temperature (°C)

Gain Bandwidth Product

(MHz)

Phase Margin (°)

GBWP

VDD = 5.5V

VDD = 2.5V

-0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

Common Mode Input Voltage (V)

Gain Bandwidth Product

(MHz)

Phase Margin (°)

GBWP

VDD = 5.5V

VDD = 2.5V

0.00.51.01.52.02.53.03.54.04.55.05.5

Output Voltage (V)

Gain Bandwidth Product

(MHz)

Phase Margin (°)

GBWP

VDD = 5.5V

VDD = 2.5V

0.1

100

1.0E+04 1.0E+05 1.0E+06 1.0E+07 1.0E+08

Frequency (Hz)

10k 1M 10M 100M

Closed-Loop Output Impedance (Ω)

100k

G = 101 V/V

G = 11 V/V

G = 1 V/V

MCP660/1/2/3/4/5/9

Note: Unless indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2,

RL = 1 kΩ to VL, CL = 20 pF and CS = VSS.

FIGURE 2-27: Gain Peaking vs.

Normalized Capacitive Load. FIGURE 2-28: Channel-to-Channel

Separation vs . Frequ enc y.

1.0E-11 1.0E-10 1.0E-09

Normalized Capacitive Load; CL/GN (F)

Gain Peaking (dB)

10p 100p 1n

GN = 1 V/

GN = 2 V/

GN ≥ 4 V/

100

110

120

130

140

150

1.E+03 1.E+04 1.E+05 1.E+06 1.E+07

Frequency (Hz)

Channel-to-Channel

Separation; RTI (dB)

1k 10k 100k

VCM = VDD/2

G = +1 V/V

RS= 10 kΩ

RS = 100 kΩ

1M 10M

RS = 0Ω

RS = 100Ω

RS = 1 kΩ

MCP660/1/2/3/4/5/9

Note: Unless indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2,

RL = 1 kΩ to VL, CL = 20 pF and CS = VSS.

2.4 Noise and Distortion

FIGURE 2-29: Input Noise Voltage Density

vs. Frequency.

FIGURE 2-30: Input Noise Voltage Density

vs. Input Common Mode V oltage with f = 100 Hz.

FIGURE 2-31: Input Noise Voltage Density

vs. Input Common Mode Voltage with f = 1 MHz.

FIGURE 2-32: Input Noise vs. Time with

0.1 Hz Filter.

FIGURE 2-33: THD+N vs. Frequency.

FIGURE 2-34: Change in Gain Magnitude

and Phase vs. DC Input Voltage.

1.E+0

1.E+1

1.E+2

1.E+3

1.E+4

1.E-1 1.E+0 1.E+1 1.E+2 1.E+3 1.E+4 1.E+5 1.E+6 1.E+7

Frequency (Hz)

0.1 100 10k 1M

Input Noise Voltage Density (V/√Hz)

1 1k 100k 10M10

100n

1µ

10µ

10n

100

120

140

160

180

200

-0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

Common Mode Input Voltage (V)

VDD = 5.5

VDD = 2.5V

Input Noise Voltage Density

(nV/√Hz)

f = 100 Hz

-0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

Common Mode Input Voltage (V)

VDD = 5.5V

VDD = 2.5

Input Noise Voltage Density

(nV/√Hz)

f = 1 MHz

-20

-15

-10

-5

0 5 10 15 20 25 30 35 40 45 50 55 60 65

Time (min)

Input Noise; eni(t) (µV)

Representative Part

Analog NPBW = 0.1 Hz

Sample Rate = 2 SPS

VOS = -953 µV

0.0001

0.001

0.01

0.1

1.E+2 1.E+3 1.E+4 1.E+5

Frequency (Hz)

THD + Noise (%)

VDD = 5.0V

VOUT = 2 VP-P

100 1k 10k 100k

BW = 22 Hz to 80 kHz

BW = 22 Hz to > 500 kHz G = 1 V/V

G = 11 V/V

-1.0

-0.9

-0.8

-0.7

-0.6

-0.5

-0.4

-0.3

-0.2

-0.1

0.0

0.1

0.2

-0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8

DC Input Voltage (V)

Change in

Gain Magnitude (%)

-1.0

-0.9

-0.8

-0.7

-0.6

-0.5

-0.4

-0.3

-0.2

-0.1

0.0

0.1

0.2

Change in

Gain Phase (°)

Representative Part

VDD = 2.5V

VSS = -2.5V

VL = 0V

RL = 150Ω

Normalized to DC VIN = 0V

NTSC

Positive Video

Negative Video

∆

(|G|)

∆

(∠G)

MCP660/1/2/3/4/5/9

Note: Unless indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2,

RL = 1 kΩ to VL, CL = 20 pF and CS = VSS.

2.5 Time Response

FIGURE 2-35: Non-inverting Small Signal

Step Respon se .

FIGURE 2-36: Non-inverting Large Signal

Step Respon se .

FIGURE 2-37: Inverting Small Signal Step

Response.

FIGURE 2-38: Inverting Large Signal Step

Response.

FIGURE 2-39: The MCP660/1/2/ 3/4/ 5/9

family shows no input phase reversal with

overdrive.

FIGURE 2-40: Slew Rate vs. Ambien t

Temperature.

0 20 40 60 80 100 120 140 160 180 200

Time (ns)

Output Voltage (10 mV/div)

VDD = 5.5V

G = 1

VIN VOUT

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

0 100 200 300 400 500 600 700 800

Time (ns)

Output Voltage (V)

VDD = 5.5V

G = 1

VIN VOUT

0 50 100 150 200 250 300 350 400 450 500

Time (ns)

Output Voltage (10 mV/div)

VDD = 5.5V

G = -1

RF = 402Ω

VIN

VOUT

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

0 100 200 300 400 500 600

Time (ns)

Output Voltage (V)

VDD = 5.5V

G = -1

RF = 402Ω

VIN

VOUT

-1

012345678910

Time (µs)

Input, Output Voltages (V)

VDD = 5.5V

G = 2

VOUT

VIN

-50 -25 0 25 50 75 100 125

Ambient Temperature (°C)

Slew Rate (V/µs)

Falling Edge

Rising Edge

VDD = 2.5V

VDD = 5.5V

MCP660/1/2/3/4/5/9

Note: Unless indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2,

RL = 1 kΩ to VL, CL = 20 pF and CS = VSS.

FIGURE 2-41: Maximum Output Voltage

Swing vs. Frequency.

0.1

1.E+05 1.E+06 1.E+07 1.E+08

Frequency (Hz)

Maximum Output Voltage

Swing (VP-P)

VDD = 5.5

VDD = 2.5

100k 1M 10M 100M

MCP660/1/2/3/4/5/9

Note: Unless indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2,

RL = 1 kΩ to VL, CL = 20 pF and CS = VSS.

2.6 Chip Select Response

FIGURE 2-42: CS Current vs. Power

Supply Voltage.

FIGURE 2-43: CS and Output Voltages vs.

Time with VDD = 2.5V.

FIGURE 2-44: CS and Output Voltages vs.

Time with VDD = 5.5V.

FIGURE 2-45: CS Hysteresis vs. Ambient

Temperature.

FIGURE 2-46: CS Turn On Time vs.

Ambient Temp eratu re .

FIGURE 2-47: CS’s Pull-down Resistor

(RPD) vs. Ambient Temperature.

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Power Supply Voltage (V)

CS Current (µA)

CS = VDD

-0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

0 2 4 6 8 10 12 14 16 18 20

Time (µs)

CS, VOUT (V)

VDD = 2.5V

G = 1

VL = 0V

VOUT

OffOff

-1

012345678910

Time (µs)

CS, VOUT (V)

VDD = 5.5V

G = 1

VL = 0V

VOUT

OffOff

0.00

0.05

0.10

0.15

0.20

0.25

0.30

0.35

0.40

-50 -25 0 25 50 75 100 125

Ambient Temperature (°C)

CS Hysteresis (V)

VDD = 2.5V

VDD = 5.5V

-50 -25 0 25 50 75 100 125

Ambient Temperature (°C)

CS Turn On Time (µs)

VDD = 2.5V

VDD = 5.5V

-50-25 0 255075100125

Ambient Temperature (°C)

CS Pull-down Resistor

(MΩ)

Representative Part

MCP660/1/2/3/4/5/9

Note: Unless indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2,

RL = 1 kΩ to VL, CL = 20 pF and CS = VSS.

FIGURE 2-48: Quiescent Current in

Shutdown vs. Power Supply Voltage. FIGURE 2-49: Output Leakage Current vs.

Output Voltage.

-2.0

-1.8

-1.6

-1.4

-1.2

-1.0

-0.8

-0.6

-0.4

-0.2

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

6.5

Power Supply Voltage (V)

Negative Power Supply

Current; ISS (µA)

CS = VDD

+125°C

+85°C

+25°C

-40°C

1.E-11

1.E-10

1.E-09

1.E-08

1.E-07

1.E-06

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

Output Voltage (V)

Output Leakage Current (A)

+25°C

+125°C

+85°C

CS = VDD = 5.5V

1µ

100n

10n

100p

10p

MCP660/1/2/3/4/5/9

NOTES:

MCP660/1/2/3/4/5/9

3.0 PIN DESCRIPTIONS

Descriptions of the pins are listed in Table 3-1.

TABLE 3-1: PIN FUNCTION TABLE

MCP660 MCP661 MCP662 MCP663 MCP664 MCP665 MCP669

Symbol Description

4x4 QFN

SOIC,

TSSOP

SOIC

2x3 TDFN

SOT-23

SOIC

DFN

SOIC

SOT-23

SOIC,

TSSOP

MSOP

DFN

4x4 QFN

562

242224 2 22 1 V

IN-, VINA- Inverting Input (op amp A)

453

333333 3 33 2 V

IN+, VINA+ Non-inverting Input (op amp A)

347

758876 4 10103 V

DD Positive Power Supply

10 10 — ——55—— 5 77 4 V

INB+ Non-inverting Input (op amp B)

99—

——66—— 6 88 5 V

INB- Inverting Input (op amp B)

88—

——77—— 7 99 6 V

OUTB Output (op amp B)

———

—————— — —— 7 CS

BC Chip Select Digital Input (op amps B and C)

14 14 — —————— 8 —— 8 V

OUTC Output (op amp C)

13 13 — —————— 9 —— 9 V

INC- Inverting Input (op amp C)

12 12 — —————— 10 —— 10 V

INC+ Non-inverting Input (op amp C)

11 11 4 424442 11 4411 V

SS Negative Power Supply

———

—————— 12 —— 12 V

IND+ Inverting Input (op amp D)

———

—————— 13 —— 13 V

IND- Inverting Input (op amp D)

———

—————— 14 —— 14 V

OUTD Output (op amp D)

———

—————— — —— 15 CS

AD Chip Select Digital Input (op amps A and D)

676

611161 1 1116 V

OUT

, VOUTA Output (op amp A)

17 ———— — 9 — — — — 11 17 EP Exposed Thermal Pad (EP); must be

connected to VSS

————— ——8 5 — 55 — CS, CSAChip Select Digital Input (op amp A)

——— ————— — 66 — CS

BChip Select Digital Input (op amp B)

1, 2, 7,

15, 16

1, 2, 3 1, 5, 8 1,2 — — — 1, 5 — — — — — NC No Internal Connection

MCP660/1/2/3/4/5/9

3.1 Analog Outputs

The analog output pins (VOUT) are low-impedance

voltage sources.

3.2 Analog Inputs

The non-inverting and inverting inputs (VIN+, VIN-, …)

are high-impedance CMOS inputs with low bias

currents.

3.3 Power Supply Pins

The positive power supply (VDD) is 2.5V to 5.5V higher

than the negative power supply (VSS). For normal

operation, the other pins are between VSS and VDD.

Typically, these parts are used in a single (positive)

supply configuration. In that case, VSS is connected to

ground and VDD is connected to the supply. VDD will

need bypass capacitors.

3.4 Chip Select Digital Input (CS)

The input (CS) is a CMOS, Schmitt-triggered input that

places the part into a Low Power mode of operation.

3.5 Exposed Thermal Pad (EP)

There is an internal connection between the exposed

thermal pad (EP) and the VSS pin; they must be con-

nected to the same potential on the printed circuit

board (PCB).

This pad can be connected to a PCB ground plane to

provide a larger heat sink. This improves the package

thermal resistance (θJA).

MCP660/1/2/3/4/5/9

4.0 APPLICATIONS

The MCP660/1/2/3/4/5/9 family is manufactured using

the Microchip state-of-the-art CMOS process. It is

designed for low-cost, low-power and high-speed

applications. Its low supply voltage, low quiescent cur-

rent and wide bandwidth make the MCP660/1/2/3/4/5/9

ideal for battery-powered applications.

4.1 Input

4.1.1 PHASE REVERSAL

The input devices are designed to not exhibit phase

inversion when the input pins exceed the supply volt-

ages. Figure 2-39 shows an input voltage exceeding

both supplies with no phase inversion.

4.1.2 INPUT VOLTAGE AND CURRENT

LIMITS

The electrostatic discharge (ESD) protection on the

inputs can be depicted as shown in Figure 4-1. This

structure was chosen to protect the input transistors,

and to minimize input bias current (IB). The input ESD

diodes clamp the inputs when they try to go more than

one diode drop below VSS. They also clamp any

voltages that go too far above VDD; their breakdown

voltage is high enough to allow normal operation, and

low enough to bypass quick ESD events within the

specified limits.

FIGURE 4-1: Simplified Analog Input ESD

Structures.

In order to prevent damage and/or improper operation

of these amplifiers, the circuit must limit the currents

(and voltages) at the input pins (see Section 1.1

“Absolute Maximum Ratings †”). Figure 4-2 shows

the recommended approach to protecting these inputs.

The internal ESD diodes prevent the input pins (VIN+

and VIN-) from going too far below ground, and the

resistors R1 and R2 limit the possible current drawn out

of the input pins. Diodes D1 and D2 prevent the input

pins (VIN+ and VIN-) from going too far above VDD, and

dump any currents onto VDD.

When implemented as shown, resistors R1 and R2 also

limit the current through D1 and D2.

FIGURE 4-2: Protecting the Analog

Inputs.

It is also possible to connect the diodes to the left of the

resistor R1 and R2. In this case, the currents through

the diodes D1 and D2 need to be limited by some other

mechanism. The resistors then serve as in-rush current

limiters; the DC current into the input pins (VIN+ and

VIN-) should be very small.

A significant amount of current can flow out of the

inputs (through the ESD diodes) when the Common

mode voltage (VCM) is below ground (VSS); see

Figure 2-13. Applications that are high impedance may

need to limit the usable voltage range.

4.1.3 NORMAL OPERATION

The input stage of the MCP660/1/2/3/4/5/9 op amps

use a differential PMOS input stage. It operates at low

Common mode input voltages (VCM), with VCM

between VSS – 0.3V and VDD – 1.3V. To ensure proper

operation, the input offset voltage (VOS) is measured at

both VCM = VSS – 0.3V and VDD – 1.3V. See Figure 2-

5 and Figure 2-6 for temperature effects.

When operating at very low non-inverting gains, the

output voltage is limited at the top by the VCM range

(<VDD – 1.3V); see Figure 4-3.

FIGURE 4-3: Unity Gain Voltage

Limitations for Linear Operation.

Bond

Pad

Bond

Pad

Bond

Pad

VDD

VIN+

VSS

Input

Stage

Bond

Pad VIN-

VDD

R1 > VSS – (minimum expected V1)

2 mA

VOUT

R2 > VSS – (minimum expected V2)

2 mA

MCP66X

VIN

VDD

VOUT

VSS V

IN V

OUT VDD 1.3V–

≤

MCP66X

MCP660/1/2/3/4/5/9

4.2 Rail-to-Rail Output

4.2.1 MAXIMUM OUTPUT VOLTAGE

The Maximum Output Voltage (see Figure 2-16 and

Figure 2-17) describes the output range for a given

load. For example, the output voltage swings to within

50 mV of the negative rail with a 1 kΩ load tied to

VDD/2.

4.2.2 OUTPUT CURRENT

Figure 4-4 shows the possible combinations of output

voltage (VOUT) and output current (IOUT), when VDD =

5.5V.

IOUT is positive when it flows out of the op amp into the

external circuit.

FIGURE 4-4: Output Current.

4.2.3 POWER DISSIPATION

Since the output short circuit current (ISC) is specified

at ±90 mA (typical), these op amps are capable of both

delivering and dissipating significant power.

FIGURE 4-5: Diagram for Power

Calculations.

Figure 4-5 shows the power calculations used for a sin-

gle op amp:

•R

SER is 0Ω in most applications, and can be used

to limit IOUT

•V

OUT is the op amp’s output voltage.

•V

L is the voltage at the load.

•V

LG is the load’s ground point.

•V

SS is usually ground (0V).

The input currents are assumed to be negligible. The

currents shown in Figure 4-5 can be approximated

using Equation 4-1:

EQUATION 4-1:

The instantaneous op amp power (POA(t)), RSER power

(PRSER(t)) and load power (PL(t)) are calculated in

Equation 4-2:

EQUATION 4-2:

The maximum op amp power, for resistive loads,

occurs when VOUT is halfway between VDD and VLG or

halfway between VSS and VLG

EQUATION 4-3:

The maximum ambient to junction temperature rise

(ΔTJA) and junction temperature (TJ) can be calculated

using POAmax, ambient temperature (TA), the package

thermal resistance (θJA – found in Ta b l e 1 - 4 ), and the

number of op amps in the package (assuming equal

power dissipations), as shown in Equation 4-4:

EQUATION 4-4:

-0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

-120

-100

-80

-60

-40

-20

100

120

IOUT (mA)

VOUT (V)

RL = 10Ω

RL = 100Ω

RL = 1 kΩ

VOH Limited

VOL Limited

-ISC Limited

+ISC Limited

(VDD = 5.5V)

VDD

VLG

IDD

ISS

IOUT RSER

VOUT

VSS

MCP66X

VOUT – VLG

IOUT = IL = RSER + RL

IDD

≈

IQ + max(0, IOUT)

ISS

≈

–IQ + min(0, IOUT)

Where:

IQ= quiescent supply current

POA(t) = IDD (VDD – V OUT) + ISS (VSS – VOUT)

PRSER(t) = IOUT2RSER

PL(t) = IL2RL

POAmax

≤

max2(VDD – VLG, – VSS)

4(RSER + RL)

TJA = POA(t)

≤

n POAmax

TJ = TA +

TJA

Where:

n = number of op amps in package (1, 2)

MCP660/1/2/3/4/5/9

The power derating across temperature for an op amp

in a particular package can be easily calculated

(assuming equal power dissipations):

EQUATION 4-5:

Several techniques are available to reduce ΔTJA for a

given POAmax:

• Lower θJA

- Use another package

- PCB layout (ground plane, etc.)

- Heat sinks and air flow

• Reduce POAmax

- Increase RL

- Limit IOUT (using RSER)

- Decrease VDD

4.3 Distortion

Differential gain (DG) and differential phase (DP) refer

to the non-linear distortion produced by an NTSC or a

phase-alternating line (PAL) video component. Table 1 -

2 and Figure 2-34 show the typical performance of the

MCP661, configured as a gain of +2 amplifier (see

Figure 4-10), when driving one back-matched video

load (150Ω, for 75Ω cable). Microchip tests use a sine

wave at NTSC’s color sub-carrier frequency of 3.58

MHz, with a 0.286VP-P magnitude. The DC input volt-

age is changed over a +0.7V range (positive video) or

a -0.7V range (negative video).

DG is the peak-to-peak change in the AC gain magni-

tude (color hue), as the DC level (luminance) is

changed, in percentile units (%). DP is the peak-to-

peak change in the AC gain phase (color saturation),

as the DC level (luminance) is changed, in degree (°)

units.

4.4 Improving Stability

4.4.1 CAPACITIVE LOADS

Driving large capacitive loads can cause stability

problems for voltage feedback op amps. As the load

capacitance increases, the phase margin (stability) of

the feedback loop decreases and the closed-loop

bandwidth is reduced. This produces gain peaking in

the frequency response, with overshoot and ringing in

the step response. A unity gain buffer (G = +1) is the

most sensitive to capacitive loads, though all gains

show the same general behavior.

When driving large capacitive loads with these op

amps (e.g., >20 pF when G = +1), a small series resis-

tor at the output (RISO in Figure 4-6) improves the

phase margin of the feedback loop by making the out-

put load resistive at higher frequencies. The bandwidth

generally will be lower than bandwidth without the

capacitive load.

FIGURE 4-6: Output Resistor, RISO

Stabilize s Large Capacitiv e Loads.

Figure 4-7 gives recommended RISO values for

different capacitive loads and gains. The x-axis is the

normalized load capacitance (CL/GN), where GN is the

circuit’s noise gain. For non-inverting gains, GN and the

Signal Gain are equal. For inverting gains, GN is

1+|Signal Gain| (e.g., -1 V/V gives GN = +2 V/V).

FIGURE 4-7: Recommended RISO Values

for Capacitive Loads.

After selecting RISO for the circuit, double-check the

resulting frequency response peaking and step

response overshoot. Modify RISO’s value until the

response is reasonable. Bench evaluation and simula-

tions with the MCP660/1/2/3/4/5/9 SPICE macro model

are helpful.

TJmax – TA

POAmax

≤

Where:

TJmax = absolute max. junction temperature

RISO

VOUT

RGRF

RNMCP66X

100

1.E-11 1.E-10 1.E-09 1.E-08

Normalized Capacitance; CL/GN (F)

Recommended RISO (Ω)

GN = +1

GN ≥ +2

10p 100p 1n 10n

MCP660/1/2/3/4/5/9

4.4.2 GAIN PEAKING

Figure 4-8 shows an op amp circuit that represents

non-inverting amplifiers (VM is a DC voltage and VP is

the input) or inverting amplifiers (VP is a DC voltage

and VM is the input). The capacitances CN and CG rep-

resent the total capacitance at the input pins; they

include the op amp’s Common mode input capacitance

(CCM), board parasitic capacitance and any capacitor

placed in parallel.

FIGURE 4-8: Amplifier with Parasitic

Capacitance.

CG acts in parallel with RG (except for a gain of +1 V/V),

which causes an increase in gain at high frequencies.

CG also reduces the phase margin of the feedback

loop, which becomes less stable. This effect can be

reduced by either reducing CG or RF

CN and RN form a low-pass filter that affects the signal

at VP

. This filter has a single real pole at 1/(2πRNCN).

The largest value of RF that should be used, depends

on noise gain (see GN in Section 4.4.1 “Capacitive

Loads”), CG and the open-loop gain’s phase shift.

Figure 4-9 shows the maximum recommended RF for

several CG values. Some applications may modify

these values to reduce either output loading or gain

peaking (step response overshoot).

FIGURE 4-9: Maximum Recommended

RF vs. Gain.

Figure 2-35 and Figure 2-36 show the small signal and

large signal step responses at G = +1 V/V. The unity

gain buffer usually has RF = 0Ω and RG open.

Figure 2-37 and Figure 2-38 show the small signal and

large signal step responses at G = -1 V/V. Since the

noise gain is 2 V/V and CG ≈ 10 pF, the resistors were

chosen to be RF = RG = 401Ω and RN = 200Ω.

It is also possible to add a capacitor (CF) in parallel with

RF to compensate for the destabilizing effect of CG

This makes it possible to use larger values of RF

. The

conditions for stability are summarized in Equation 4-6.

EQUATION 4-6:

VOUT

RGCG

MCP66X

1.E+02

1.E+03

1.E+04

1.E+05

110100

Noise Gain; GN (V/V)

Maximum Recommended R F

(Ω)

GN > +1 V/V

100

10k

100k

CG= 10 pF

CG= 32 pF

CG= 100 pF

CG= 320 pF

CG= 1 nF

fFfGBWP 2GN2

()

⁄

, GN1 GN2

<≤

We need:

GN1 1R

FRG

⁄

GN2 1C

GCF

⁄

fF12

RFCF

()

⁄

fZfFGN1 GN2

⁄

()=

Given:

fFfGBWP 4GN1

()

⁄

, GN1 GN2

>≤

MCP660/1/2/3/4/5/9

4.5 MCP663 and MCP665 Chip Select

The MCP663 is a single amplifier with Chip Select

(CS). When CS is pulled high, the supply current drops

to 1 µA (typical) and flows through the CS pin to VSS.

When this happens, the amplifier output is put into a

high-impedance state. By pulling CS low, the amplifier

is enabled. The CS pin has an internal 5 MΩ (typical)

pulldown resistor connected to VSS, so it will go low if

the CS pin is left floating. Figure 1-1, Figure 2-43 and

Figure 2-44 show the output voltage and supply current

response to a CS pulse.

The MCP665 is a dual amplifier with two CS pins; CSA

controls op amp A, and CSB controls op amp B. These

op amps are controlled independently, with an enabled

quiescent current (IQ) of 6 mA/amplifier (typical) and a

disabled IQ of 1 µA/amplifier (typical). The IQ seen at

the supply pins is the sum of the two op amps’ IQ; the

typical value for the IQ of the MCP665 will be 2 µA, 6

mA or 12 mA when there are 0, 1 or 2 amplifiers

enabled, respectively.

4.6 Power Supply

With this family of operational amplifiers, the power

supply pin (VDD for single supply) should have a local

bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm

for good high frequency performance. Surface mount,

multilayer ceramic capacitors, or their equivalent,

should be used.

These op amps require a bulk capacitor (i.e., 2.2 µF or

larger) within 50 mm to provide large, slow currents.

Tantalum capacitors, or their equivalent, may be a good

choice. This bulk capacitor can be shared with other

nearby analog parts as long as crosstalk through the

power supplies does not prove to be a problem.

4.7 High Speed PCB Layout

These op amps are fast enough that a little extra care

in the printed circuit board (PCB) layout can make a

significant difference in performance. Good PC board

layout techniques will help you achieve the perfor-

mance shown in the specifications and typical

performance curves; it will also help to minimize

electromagnetic compatibility (EMC) issues.

Use a solid ground plane. Connect the bypass local

capacitor(s) to this plane with minimal length traces.

This cuts down inductive and capacitive crosstalk.

Separate digital from analog, low speed from high

speed, and low power from high power. This will reduce

interference.

Keep sensitive traces short and straight. Separate

them from interfering components and traces. This is

especially important for high frequency (low rise time)

signals.

Sometimes, it helps to place guard traces next to victim

traces. They should be on both sides of the victim

trace, and as close as possible. Connect guard traces

to ground plane at both ends, and in the middle for long

traces.

Use coax cables, or low inductance wiring, to route sig-

nal and power to and from the PCB. Mutual and self

inductance of power wires is often a cause of crosstalk

and unusual behavior.

MCP660/1/2/3/4/5/9

4.8 Typical Applications

4.8.1 50Ω LINE DRIVER

Figure 4-10 shows the MCP661 driving a 50Ω line. The

large output current (e.g., see Figure 2-18) makes it

possible to drive a back-matched line (RM2, the 50Ω

line and the 50Ω load at the far end) to more than ±2V

(the load at the far end sees ±1V). It is worth mention-

ing that the 50Ω line and the 50Ω load at the far end

together can be modeled as a simple 50Ω resistor to

ground.

FIGURE 4-10: 50

Line Driver.

The output headroom limits would be VOL = -2.3V and

VOH = +2.3V (see Figure 2-16), leaving some design

room for the ±2V signal. The open-loop gain (AOL)

typically does not decrease significantly with a 100Ω

load (see Figure 2-11). The maximum power dissipated

is about 48 mW (see Section 4.2.3 “Power

Dissipation”), so the temperature rise (for the

MCP661 in the SOIC-8 package) is under 8°C.

4.8.2 OPTICAL DETECTOR AMPLIFIER

Figure 4-11 shows a transimpedance amplifier, using

the MCP661 op amp, in a photo detector circuit. The

photo detector is a capacitive current source. RF pro-

vides enough gain to produce 10 mV at VOUT

. CF stabi-

lizes the gain and limits the transimpedance bandwidth

to about 1.1 MHz. The parasitic capacitance of RF (e.g.,

0.2 pF for a 0805 SMD) acts in parallel with CF

FIGURE 4-11: Transimpedance Amplifier

for an Optical Detector.

4.8.3 H-BRIDGE DRIVER

Figure 4-12 shows the MCP662 dual op amp used as

an H-bridge driver. The load could be a speaker or a

DC motor.

FIGURE 4-12: H-Bridge Driv er.

This circuit automatically makes the noise gains (GN)

equal, when the gains are set properly, so that the fre-

quency responses match well (in magnitude and in

phase). Equation 4-7 shows how to calculate RGT and

RGB so that both op amps have the same DC gains;

GDM needs to be selected first.

EQUATION 4-7:

Equation 4-8 gives the resulting Common mode and

Differential mode output voltages.

EQUATION 4-8:

301Ω

RM1

49.9Ω

50Ω

RM2

49.9Ω

50Ω

Line

+2.5V

-2.5V

MCP66X

Photo

Detector

VDD/2

30pF

100 kΩ

1.5 pF

100 nA

VOUT

MCP661

VIN

VOT

RGB

VOB

VDD/2

RGT RL

½ MCP662

GDM VOT VOB

–

VIN VDD 2

⁄

–

----------- ------------ ------- -- 1 V/V

≥≡

RGT RF

GDM 2

⁄

()1–

---------------------------------=

RGB RF

GDM 2

⁄

-------------------=

VOT V+OB

---------------------------VDD

-----------=

VOT V–OB GDM VIN VDD

-----------–

⎝⎠

⎛⎞

MCP660/1/2/3/4/5/9

5.0 DESIGN AIDS

Microchip provides the basic design aids needed for

the MCP660/1/2/3/4/5/9 family of op amps.

5.1 SPICE Macro Model

The latest SPICE macro model for the

MCP660/1/2/3/4/5/9 op amps is available on the Micro-

chip web site at www.microchip.com. This model is

intended to be an initial design tool that works well in

the linear region of operation over the temperature

range of the op amp. See the model file for information

on its capabilities.

Bench testing is a very important part of any design and

cannot be replaced with simulations. Also, simulation

results using this macro model need to be validated, by

comparing them to the data sheet specifications and

characteristic curves.

5.2 FilterLab® Software

Microchip’s FilterLab® software is an innovative soft-

ware tool that simplifies analog active filter (using op

amps) design. Available at no cost from the Microchip

web site at www.microchip.com/filterlab, the Filter-Lab

design tool provides full schematic diagrams of the filter

circuit with component values. It also outputs the filter

circuit in SPICE format, which can be used with the

macro model to simulate actual filter performance.

5.3 Microchip Advanced Part Selector

(MAPS)

MAPS is a software tool that helps efficiently identify

Microchip devices that fit a particular design

requirement. Available at no cost from the Microchip

web site at www.microchip.com/maps, the MAPS is an

overall selection tool for Microchip’s product portfolio

that includes Analog, Memory, MCUs and DSCs. Using

this tool, a filter can be defined to sort features for a

parametric search of device, and export side-by-side

technical comparison reports. Helpful links are also

provided for data sheets, purchase and sampling of

Microchip parts.

5.4 Analog Demonstration and

Evaluation Boards

Microchip offers a broad spectrum of analog demon-

stration and evaluation boards that are designed to

help customers achieve faster time to market. For a

complete listing of these boards and their correspond-

ing user’s guides and technical information, visit the

Microchip web site at www.microchip.com/analog

tools.

Some boards that are especially useful are:

• MCP6XXX Amplifier Evaluation Board 1

• MCP6XXX Amplifier Evaluation Board 2

• MCP6XXX Amplifier Evaluation Board 3

• MCP6XXX Amplifier Evaluation Board 4

• Active Filter Demo Board Kit

• 8-Pin SOIC/MSOP/TSSOP/DIP Evaluation Board,

P/N SOIC8EV

• MCP661 Line Driver Demo Board

5.5 Design and Application Notes

The following Microchip Analog Design Note and Appli-

cation Notes are recommended as supplemental refer-

ence resources. They are available on the Microchip

web site at www.microchip.com/appnotes.

•ADN003: “Select the Right Operational Amplifier

for your Filtering Circuits”, DS21821

•AN722: “Operationa l Amplifier Topologies and DC

Specifications”, DS00722

•AN723: “Operational Amplifier AC Specifications

and Applications”, DS00723

•AN884: “Driving Capaci tive Loads With Op

Amps”, DS00884

•AN990: “Analog Sensor Conditioning Circuits –

An Overview”, DS00990

•AN1228: “Op Amp Precision Design: Random

Noise”, DS01228

Some of these application notes, and others, are listed

in the “Signal Chain Design Guide”, DS21825.

MCP660/1/2/3/4/5/9

NOTES:

MCP660/1/2/3/4/5/9

6.0 PACKAGING INFORMATION

6.1 Package Marking Information

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanumeric traceability code

Pb-free JEDEC designator for Matte Tin (Sn)

*This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

Device Code

MCP662T-E/MF DABQ

Note: Applies to 8-Lead 3x3 DFN

8-Lead DFN (3x3)(MCP662) Example

DABQ

1129

Example

5-Lead SOT-23 (MCP661)

6-Lead SOT-23 ( MCP663)Example

XXNN

YX25

XXNN

JE25

8-Lead TDFN (2 x 3) (MCP661) Example:

ABJ

129

MCP660/1/2/3/4/5/9

Package Marking Information (Continued)

14-Lead SOIC (.150”) (MCP660, MCP664) Example

14-Lead TSSOP (MCP660, MCP664) Example

MCP660

E/SL ^^

1129256

YYWW

NNN

XXXXXXXX

664E/ST

1129

256

16-Lead QFN (4x4)

(MCP669)

Example

PIN 1 PIN 1

669

E/ML ^^

129256

10-Lead MSOP (MCP665) Example:

665EUN

129256

10-Lead DFN (3×3) (MCP665) Example

Device Code

MCP665 BAFD

Note: Applies to 10-Lead 3x3 DFN

BAFD

1129

256

NNN

8-Lead SOIC (150 mil) (MCP661, MCP662, MCP663) Example:

MCP661E

SN ^^1129

256

MCP660/1/2/3/4/5/9

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123

A2 c

   

MCP660/1/2/3/4/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

MCP660/1/2/3/4/5/9

6-Lead Plastic Small Outline Transistor (CHY) [SOT-23]

Notes:

1. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.127 mm per side.

2. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units MILLIMETERS

Dimension Limits MIN NOM MAX

Number of Pins N 6

Pitch e 0.95 BSC

Outside Lead Pitch e1 1.90 BSC

Overall Height A 0.90 – 1.45

Molded Package Thickness A2 0.89 – 1.30

Standoff A1 0.00 – 0.15

Overall Width E 2.20 – 3.20

Molded Package Width E1 1.30 – 1.80

Overall Length D 2.70 – 3.10

Foot Length L 0.10 – 0.60

Footprint L1 0.35 – 0.80

Foot Angle 0° – 30°

Lead Thickness c 0.08 – 0.26

Lead Width b 0.20 – 0.51

PIN 1 ID BY

LASER MARK

123

A2 c

Microchip Technology Drawing C04-028B

MCP660/1/2/3/4/5/9

6-Lead Plastic Small Outline Transistor (CHY) [SOT-23]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

MCP660/1/2/3/4/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

MCP660/1/2/3/4/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

MCP660/1/2/3/4/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

MCP660/1/2/3/4/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

MCP660/1/2/3/4/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

MCP660/1/2/3/4/5/9

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MCP660/1/2/3/4/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

MCP660/1/2/3/4/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

MCP660/1/2/3/4/5/9

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MCP660/1/2/3/4/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

MCP660/1/2/3/4/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

MCP660/1/2/3/4/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

MCP660/1/2/3/4/5/9

8&40194



 

 

 

 



 

   

  

  

    

    

    

  

  

  

    

  

   

    

    

NOTE 1

A2 c

   

MCP660/1/2/3/4/5/9

10-Lead Plastic Micro Small Outline Package (UN) [MSOP]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

MCP660/1/2/3/4/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

MCP660/1/2/3/4/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

MCP660/1/2/3/4/5/9



MCP660/1/2/3/4/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

MCP660/1/2/3/4/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

MCP660/1/2/3/4/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

MCP660/1/2/3/4/5/9

8;</#014!=5=5&$%'*</





 



 



 

   

  

  

    

    

  

  

    

  

    

    

    

    

EXPOSED

PAD

NOTE 1

TOP VIEW BOTTOM VIEW

   

MCP660/1/2/3/4/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

MCP660/1/2/3/4/5/9

APPENDIX A: REVISION HISTORY

Revision C (November 2011)

The following is the list of modifications:

1. Added the SOT-23 (5L) and TDFN (8L) package

option for MCP661 and SOT-23 (6L) package

options for MCP663 and the related information

throughout the document. Updated Package

Types drawing with pin designation for each

new package.

2. Updated Ta b l e 1 - 4 to show the temperature

specifications for new packages.

3. Updated Ta b l e 3 - 1 to show all the pin functions.

4. Updated Section 6.0 “Packaging Informa-

tion” with markings for the new additions.

Added the corresponding SOT-23 (5L and 6L)

and 2x3 TDFN (8L) package options and related

information.

5. Updated table description and examples in the

Product Identification System section.

Revision B (September 2011)

The following is the list of modifications:

1. Added the MCP660, MCP664 and MCP669

amplifiers to the product family and the related

information throughout the document.

2. Added the 4x4 QFN (16L) package option for

MCP660 and MCP669, SOIC and TSSOP (14L)

package options for MCP660 and MCP665 and

the related information throughout the

document. Updated Package Types drawing

with pin designation for each new package.

3. Updated Ta b l e 1 - 4 to show the temperature

specifications for new packages.

4. Updated Ta b l e 3 - 1 to show all the pin functions.

5. Updated Section 6.0 “Packaging Informa-

tion” with markings for the new additions.

Added the corresponding SOIC and TSSOP

(14L), and 4x4 QFN (16L) package options and

related information.

6. Updated table description and examples in

Product Identification System.

Revision A (July 2009)

Original release of this document.

MCP660/1/2/3/4/5/9

NOTES:

MCP660/1/2/3/4/5/9

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO. -X /XX

PackageTemperature

Range

Device

Device: MCP660 Triple Op Amp

MCP660T Triple Op Amp (Tape and Reel)

(SOIC, TSSOP, QFN)

MCP661 Single Op Amp

MCP661T Single Op Amp (Tape and Reel)

(SOIC SOT-23 and TDFN)

MCP662 Dual Op Amp

MCP662T Dual Op Amp (Tape and Reel)

(DFN and SOIC)

MCP663 Single Op Amp with CS

MCP663T Single Op Amp with CS (Tape and Reel)

(SOIC and SOT-23)

MCP664 Quad Op Amp

MCP664T Quad Op Amp (Tape and Reel)

(SOIC, TSSOP)

MCP665 Dual Op Amp with CS

MCP665T Dual Op Amp with CS (Tape and Reel)

(DFN and MSOP)

MCP669 Quad Op Amp with CS

MCP669T Quad Op Amp with CS (Tape and Reel)

(QFN)

Temperature Range: E = -40°C to +125°C

Package: CHY = Plastic Small Outline (SOT-23), 6-lead

MF = Plastic Dual Flat, No Lead (3×3 DFN),

8-lead, 10-lead

ML = Plastic Quad Flat, No Lead Package (4x4 QFN),

(4x4x0.9 mm), 16-lead

MNY= Plastic Dual Flat, No Lead (2x3 TDFN),

8-lead

OT = Plastic Small Outline (SOT-23), 5-lead

SL = Plastic Small Outline, Narrow, (3.90 mm SOIC),

14-lead

SN = Plastic Small Outline (3.90 mm), 8-lead

ST = Plastic Thin Shrink Small Outline, (4.4 mm TSSOP),

14-lead

UN = Plastic Micro Small Outline (MSOP), 10-lead

* Y = Nickel palladium gold manufacturing designator.

Only available on the TDFN package.

Examples:

a) MCP660T-E/ML: Tape and Reel

Extended temperature,

16LD QFN package

b) MCP660T-E/SN: Tape and Reel

Extended temperature,

14LD SOIC package

c) MCP660T-E/ST: Tape and Reel

Extended temperature,

14LD TSSOP package

d) MCP661T-E/SN: Tape and Reel

Extended temperature,

8LD SOIC package

e) MCP661T-E/MNY: Tape and Reel,

Extended Temperature

8LD TDFN package

f) MCP662T-E/MF: Tape and Reel

Extended temperature,

8LD DFN package

g) MCP662T-E/SN: Tape and Reel

Extended temperature,

8LD SOIC package

h) MCP663T-E/SN: Tape and Reel

Extended temperature,

8LD SOIC package

i) MCP663T-E/CHY: Tape and Reel,

Extended Temperature,

6LD SOT-23 package.

j) MCP664T-E/SN: Tape and Reel

Extended temperature,

14LD SOIC package

k) MCP664T-E/ST: Tape and Reel

Extended temperature,

14LD TSSOP package

l) MCP665T-E/MF: Tape and Reel

Extended temperature,

10LD DFN package

m) MCP665T-E/UN: Tape and Reel

Extended temperature,

10LD MSOP package

n) MCP669T-E/ML: Tape and Reel

Extended temperature,

16LD QFN package

MCP660/1/2/3/4/5/9

NOTES:

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,

KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,

PIC32 logo, rfPIC and UNI/O are registered trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,

MXDEV, MXLAB, SEEVAL and The Embedded Control

Solutions Company are registered trademarks of Microchip

Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, chipKIT,

chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,

dsPICworks, dsSPEAK, ECAN, ECONOMONITOR,

FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP,

Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB,

MPLINK, mTouch, Omniscient Code Generation, PICC,

PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE,

rfLAB, Select Mode, Total Endurance, TSHARC,

UniWinDriver, WiperLock and ZENA are trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

ISBN: 978-1-61341-738-6

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2009 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC® MCU s and dsPI C® DSCs, KEELOQ® code hopping

devices, Serial EEPROMs, microperiph erals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

AMERICAS

Corporate Office

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support:

http://www.microchip.com/

support

Web Address:

www.microchip.com

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Tel: 678-957-9614

Fax: 678-957-1455

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Tel: 216-447-0464

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Fax: 86-571-2819-3189

China - Hong Kong SAR

Tel: 852-2401-1200

Fax: 852-2401-3431

China - Nanjing

Tel: 86-25-8473-2460

Fax: 86-25-8473-2470

China - Qingdao

Tel: 86-532-8502-7355

Fax: 86-532-8502-7205

China - Shanghai

Tel: 86-21-5407-5533

Fax: 86-21-5407-5066

China - Shenyang

Tel: 86-24-2334-2829

Fax: 86-24-2334-2393

China - Shenzhen

Tel: 86-755-8203-2660

Fax: 86-755-8203-1760

China - Wuhan

Tel: 86-27-5980-5300

Fax: 86-27-5980-5118

China - Xian

Tel: 86-29-8833-7252

Fax: 86-29-8833-7256

China - Xiamen

Tel: 86-592-2388138

Fax: 86-592-2388130

China - Zhuhai

Tel: 86-756-3210040

Fax: 86-756-3210049

ASIA/PACIFIC

India - Bangalore

Tel: 91-80-3090-4444

Fax: 91-80-3090-4123

India - New Delhi

Tel: 91-11-4160-8631

Fax: 91-11-4160-8632

India - Pune

Tel: 91-20-2566-1512

Fax: 91-20-2566-1513

Japan - Yokohama

Tel: 81-45-471- 6166

Fax: 81-45-471-6122

Korea - Daegu

Tel: 82-53-744-4301

Fax: 82-53-744-4302

Korea - Seoul

Tel: 82-2-554-7200

Fax: 82-2-558-5932 or

82-2-558-5934

Malaysia - Kuala Lumpur

Tel: 60-3-6201-9857

Fax: 60-3-6201-9859

Malaysia - Penang

Tel: 60-4-227-8870

Fax: 60-4-227-4068

Philippines - Manila

Tel: 63-2-634-9065

Fax: 63-2-634-9069

Singapore

Tel: 65-6334-8870

Fax: 65-6334-8850

Taiwan - Hsin Chu

Tel: 886-3-5778-366

Fax: 886-3-5770-955

Taiwan - Kaohsiung

Tel: 886-7-536-4818

Fax: 886-7-330-9305

Taiwan - Taipei

Tel: 886-2-2500-6610

Fax: 886-2-2508-0102

Thailand - Bangkok

Tel: 66-2-694-1351

Fax: 66-2-694-1350

EUROPE

Austria - Wels

Tel: 43-7242-2244-39

Fax: 43-7242-2244-393

Denmark - Copenhagen

Tel: 45-4450-2828

Fax: 45-4485-2829

France - Paris

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

Spain - Madrid

Tel: 34-91-708-08-90

Fax: 34-91-708-08-91

UK - Wokingham

Tel: 44-118-921-5869

Fax: 44-118-921-5820

Worldwide Sales and Service

08/02/11