1. General description
74AHC1G00 an d 74 AHC T1 G 00 are high -s pe e d Si-g at e CM OS de vice s. The y pr ov ide a
2-input NAND function.
The AHC device has CMOS input switching levels and supply voltage range 2 V to 5.5 V.
The AHCT device has TTL input switching levels and supply voltage range 4.5 V to 5.5 V.
2. Features and benefits
Symmetrical output impedance
High noise immunity
Low power dissipation
Balanced propagation delays
SOT353-1 and SOT753 package options
ESD protection:
HBM JESD22-A114E: exceeds 2000 V
MM JESD22-A115-A: exceeds 200 V
CDM JESD22-C101C: exceeds 1000 V
Specified from 40 C to +125 C
3. Ordering information
74AHC1G00; 74AHCT1G00
2-input NAND gate
Rev. 7 — 5 November 2014 Product data sheet
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74AHC1G00GW 40 C to +125 C TSSOP5 plastic thin shrink small outline package;
5 leads; body width 1.25 mm SOT353-1
74AHCT1G00GW
74AHC1G00GV 40 C to +125 C SC-74A plastic surface-mounted package; 5 leads SOT753
74AHCT1G00GV
74AHC_AHCT1G00 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 7 — 5 November 2014 2 of 12
NXP Semiconductors 74AHC1G00; 74AHCT1G00
2-input NAND gate
4. Marking
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
6. Pinning information
6.1 Pinning
6.2 Pin description
Table 2. Marking codes
Type number Marking[1]
74AHC1G00GW AA
74AHC1G00GV A00
74AHCT1G00GW CA
74AHCT1G00GV C00
Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram
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Table 3. Pin description
Symbol Pin Description
B 1 data input
A 2 data input
GND 3 ground (0 V)
Y 4 data output
VCC 5 supply voltage
74AHC_AHCT1G00 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 7 — 5 November 2014 3 of 12
NXP Semiconductors 74AHC1G00; 74AHCT1G00
2-input NAND gate
7. Functional description
8. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For both TSSOP5 and SC-74A packages: above 87.5 C the value of Ptot derates linearly with 4.0 mW/K.
9. Recommended operating conditions
Table 4. Function table
H = HIGH voltage level; L = LOW voltage level
Inputs Output
ABY
LLH
LHH
HLH
HHL
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 0.5 +7.0 V
VIinput voltage 0.5 +7.0 V
IIK input clamping current VI < 0.5 V 20 - mA
IOK output clamping current VO < 0.5 V or VO>V
CC +0.5V [1] -20 mA
IOoutput current 0.5 V < VO <V
CC +0.5V - 25 mA
ICC supply current - 75 mA
IGND ground current 75 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation Tamb = 40 C to +125 C[2] - 250 mW
Table 6. Recommended operating con ditions
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 74AHC1G00 74AHCT1G00 Unit
Min Typ Max Min Typ Max
VCC supply voltage 2.0 5.0 5.5 4.5 5.0 5.5 V
VIinput voltage 0 - 5.5 0 - 5.5 V
VOoutput voltage 0 - VCC 0-V
CC V
Tamb ambient temperature 40 +25 +125 40 +25 +125 C
t/V input transition rise
and fall rate VCC = 3.3 V 0.3 V - - 100 - - - ns/V
VCC = 5.0 V 0.5 V - - 20 - - 20 ns/V
74AHC_AHCT1G00 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 7 — 5 November 2014 4 of 12
NXP Semiconductors 74AHC1G00; 74AHCT1G00
2-input NAND gate
10. Static characteristics
Table 7. Static characteristics
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
For type 74AHC1G00
VIH HIGH-level
input voltage VCC = 2.0 V 1.5 - - 1.5 - 1.5 - V
VCC = 3.0 V 2.1 - - 2.1 - 2.1 - V
VCC = 5.5 V 3.85 - - 3.85 - 3.85 - V
VIL LOW-level
input voltage VCC = 2.0 V - - 0.5 - 0.5 - 0.5 V
VCC = 3.0 V - - 0.9 - 0.9 - 0.9 V
VCC = 5.5 V - - 1.65 - 1.65 - 1.65 V
VOH HIGH-level
output voltage VI= VIH or VIL
IO= 50 A; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V
IO= 50 A; VCC = 3.0 V 2.9 3.0 - 2.9 - 2.9 - V
IO= 50 A; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V
IO= 4.0 mA; VCC = 3.0 V 2.58 - - 2.48 - 2.40 - V
IO= 8.0 mA; VCC = 4.5 V 3.94 - - 3.8 - 3.70 - V
VOL LOW-level
output voltage VI= VIH or VIL
IO= 50 A; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V
IO= 50 A; VCC = 3.0 V - 0 0.1 - 0.1 - 0.1 V
IO= 50 A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V
IO= 4.0 mA; VCC = 3.0 V - - 0.36 - 0.44 - 0.55 V
IO= 8.0 mA; VCC = 4.5 V - - 0.36 - 0.44 - 0.55 V
IIinput leakage
current VI= 5.5 V or GND;
VCC =0Vto5.5V - - 0.1 - 1.0 - 2.0 A
ICC supply current VI=V
CC or GND; IO = 0 A;
VCC = 5.5 V - - 1.0 - 10 - 40 A
CIinput
capacitance - 1.5 10 - 10 - 10 pF
For type 74AHCT1G00
VIH HIGH-level
input voltage VCC = 4.5 V to 5.5 V 2.0 - - 2.0 - 2.0 - V
VIL LOW-level
input voltage VCC = 4.5 V to 5.5 V - - 0.8 - 0.8 - 0.8 V
VOH HIGH-level
output voltage VI= VIH or VIL; VCC = 4.5 V
IO= 50 A 4.4 4.5 - 4.4 - 4.4 - V
IO= 8.0 mA 3.94 - - 3.8 - 3.70 - V
VOL LOW-level
output voltage VI= VIH or VIL; VCC = 4.5 V
IO= 50 A - 0 0.1 - 0.1 - 0.1 V
IO= 8.0 mA - - 0.36 - 0.44 - 0.55 V
IIinput leakage
current VI= 5.5 V or GND;
VCC =0Vto5.5V - - 0.1 - 1.0 - 2.0 A
74AHC_AHCT1G00 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 7 — 5 November 2014 5 of 12
NXP Semiconductors 74AHC1G00; 74AHCT1G00
2-input NAND gate
11. Dynamic characteristics
[1] tpd is the same as tPLH and tPHL.
[2] Typical values are measured at VCC = 3.3 V.
[3] Typical values are measured at VCC = 5.0 V.
[4] CPD is used to determine the dynamic power dissipation PD(W).
PD=C
PD VCC2fi+(CLVCC2fo)where:
fi= input frequency in MHz;
fo= output frequency in MHz;
CL= output load capacitance in pF;
VCC = supply voltage in Volts.
ICC supply current VI=V
CC or GND; IO = 0 A;
VCC = 5.5 V - - 1.0 - 10 - 40 A
ICC additional
supply current per input pi n; V I=3.4V;
other inputs at VCC or GND;
IO=0 A; V
CC = 5.5 V
- - 1.35 - 1.5 - 1.5 mA
CIinput
capacitance - 1.5 10 - 10 - 10 pF
Table 7. Static characteristics …continued
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
Table 8. Dynamic characteristics
GND = 0 V; tr = tf =
3.0 ns. For test circuit see Figure 6.
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
For type 74AHC1G00
tpd propagation
delay A and B to Y; see Figure 5 [1]
VCC = 3.0 V to 3.6 V [2]
CL= 15 pF - 4.5 7.9 1.0 9.5 1.0 10.5 ns
CL= 50 pF - 6.5 11.4 1.0 13.0 1.0 14 .5 ns
VCC = 4.5 V to 5.5 V [3]
CL= 15 pF - 3.5 5.5 1.0 6.5 1. 0 7.0 ns
CL= 50 pF - 4.9 7.5 1.0 8.5 1. 0 9.5 ns
CPD power
dissipation
capacitance
per buffer;
CL=50pF;f=1 MHz;
VI=GNDtoV
CC
[4] -17- - - - - pF
For type 74AHCT1G00
tpd propagation
delay A and B to Y ; see Figure 5 [1]
VCC = 4.5 V to 5.5 V [3]
CL= 15 pF - 3.6 6.2 1.0 7.1 1. 0 8.0 ns
CL= 50 pF - 5.0 7.9 1.0 9.0 1.0 10.0 ns
CPD power
dissipation
capacitance
per buffer;
VI=GNDtoV
CC
[4] -18- - - - - pF
74AHC_AHCT1G00 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 7 — 5 November 2014 6 of 12
NXP Semiconductors 74AHC1G00; 74AHCT1G00
2-input NAND gate
12. Waveforms
Measurement points are given in Table 9.
Fig 5. The inputs (A and B) to outpu t (Y) propagation delays
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Table 9. Measurement point
Type Input Output
VIVMVM
74AHC1G00 GND to VCC 0.5 VCC 0.5 VCC
74AHCT1G00 GND to 3.0 V 1.5 V 0.5 VCC
Test data is given in Table 8. Definitions for test circuit:
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
Fig 6. Test circuit for measuring switching times
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74AHC_AHCT1G00 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 7 — 5 November 2014 7 of 12
NXP Semiconductors 74AHC1G00; 74AHCT1G00
2-input NAND gate
13. Package outline
Fig 7. Package outline SOT353-1 (TSSOP5)
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74AHC_AHCT1G00 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 7 — 5 November 2014 8 of 12
NXP Semiconductors 74AHC1G00; 74AHCT1G00
2-input NAND gate
Fig 8. Package outline SOT753 (SC-74A)
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74AHC_AHCT1G00 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 7 — 5 November 2014 9 of 12
NXP Semiconductors 74AHC1G00; 74AHCT1G00
2-input NAND gate
14. Abbreviations
15. Revision history
Table 10. Abbreviations
Acronym Description
CDM Charged Device Mo del
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model
TTL Transi stor-Transistor Logic
Table 11. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74AHC_AHCT1G00 v.7 20141105 Product data sheet - 74AHC_AHCT1G00 v.6
Modifications: •Section 4: table note added.
74AHC_AHCT1G00 v.6 20070530 Product data sheet - 74AHC_AHCT1G00 v.5
Modifications: •The format of this data sheet has been redesigned to comply with the new iden tity
guidelines of NXP Semiconductors.
•Legal texts have been adapted to the new company name where appropriate.
•Package SOT353 changed to SOT353-1 in Section 3 and Section 13.
•Quick reference data and Soldering sections removed.
74AHC_AHCT1G00 v.5 20020527 Product specification - 74AHC_AHCT1G0 0 v.4
74AHC_AHCT1G00 v.4 20020227 Product specification - 74AHC_AHCT1G0 0 v.3
74AHC_AHCT1G00 v.3 20010131 Product specification - 74AHC_AHCT1G0 0 v.2
74AHC_AHCT1G00 v.2 19990127 Product specification - 74AHC_AHCT1G0 0_N v.1
74AHC_AHCT1G00 _N v.1 19981125 Preliminary specification - -
74AHC_AHCT1G00 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 7 — 5 November 2014 10 of 12
NXP Semiconductors 74AHC1G00; 74AHCT1G00
2-input NAND gate
16. Legal information
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[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
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Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specificati on for product development.
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74AHC_AHCT1G00 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 7 — 5 November 2014 11 of 12
NXP Semiconductors 74AHC1G00; 74AHCT1G00
2-input NAND gate
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Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors prod uct is automotive qualified,
the product is not suitable for aut omo tive use. It i s neit her qualif ied nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automot ive specifications and standard s, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifica tions, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting f rom customer design an d
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specif ications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
16.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respect i ve ow ners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an em ail to: salesaddresses@nxp.com
NXP Semiconductors 74AHC1G00; 74AHCT1G00
2-input NAND gate
© NXP Semiconductors N.V. 2014. All rights reserved.
For more information, please visit: http://www.nxp.co m
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 5 November 2014
Document identifier: 74AHC_AHCT1G00
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
18. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 1
4 Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 2
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2
7 Functional description . . . . . . . . . . . . . . . . . . . 3
8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3
9 Recommended operating conditions. . . . . . . . 3
10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4
11 Dynamic characteristics . . . . . . . . . . . . . . . . . . 5
12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 7
14 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . . 9
15 Revision history. . . . . . . . . . . . . . . . . . . . . . . . . 9
16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 10
16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 10
16.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
16.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 10
16.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 11
17 Contact information. . . . . . . . . . . . . . . . . . . . . 11
18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12