[AK7719]
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The AK7719 is a highly integrated digital signal processor (DSP) with four digital interface ports. AKM’s
DSP core is optimized for both narrowband and wideband voice processing, as well as full bandwidth
digital audio processing. An integrated clock generator for the DSP master clock eliminates the need for
external clocks. The RAM-based DSP can be programmed for user requirements. The AK7719 is housed
in a 25-pin CSP package. It is a very low power device, suitable for mobile applications.
□ Embedded DSP
- Flexible programming with built-in program and data memories
- Hardware accelerator
- Word length: 24-bits (Data RAM 24-bit floating point)
- Multiplier 20 x 20 Æ 40-bits (double precision available)
- Divider 20 / 20 Æ 20-bits
- ALU: 44-bit arithmetic operation (with 4-bit overflow margin)
24-bit floating point arithmetic and logic operation
- Program RAM: 4096w x 36-bits
- Coefficient RAM: 2048w x 20-bits
- Data RAM: 2048w x 24-bits (24-bit floating point)
- Offset Register: 32w x 15-bits
- Delay RAM: 16384w x 24-bits(24-bit floating point)
- 5625 steps at 16kHz sampling rate, 1875 steps at 48kHz sampling rate
- Internal clock generator
□ Audio Interface Format
- 24-bit Left justified, I2S,
- 16/24bit linear, 8-bit A-law, 8-bit µ-law PCM
- Sampling rate 8kHz ~ 48kHz
- Up/Down Sampling rate converter for Port#2 (8kHz → 16kHz)
□ μC I/F: I2C-Compatible, SPI
□ Operational, Sleep, Power down
□ Power Supply
VDD (DSP Core): 1.2V ±0.1V
TVDD (PCM I/F): 1.6V ~ 3.6V
□ Operating Temperature Range: -20°C ~ 85°C
□ Package: 25-Pin WL-CSP (2.62mm x2.93mm, 0.5mm pitch)
□ Power Consumption: 7.4mA (8.9mW) typ. (Narrowband Handset mode operation)
GENERAL DESCRIPTION
FEATURES
Low Power DSP for Voice and Audio Processing
AK7719
[AK7719]
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■ Block Diagram
Memory
DIN2
DOUT2
SDIN2
SDOUT2
SYNC2
BCLK2
DIN1
DOUT1
BCLK1
SYNC1
SDIN1
SDOUT1
VDDTVDDVSS
PDN
DSPCLK
AKM
DSP
Core
Control
Interface SI/CAD1
CSN/SCL
SO/SD
A
I2C
SCLK/CAD0
SDIN3
SDOUT3/GP0
PCM
Interface1
(Port#1)
DOUT3/GP0
DIN3
PCM
Interface3
(Port#3) RDY
WDT
/
CRC STO/RDY
SYNC3/JX1
BCLK3/JX0
CGU
(CLK
Gen
Unit)
JX1
JX0
TEST
DIN4
DOUT4/GP1
SDIN4
SDOUT4/GP1
PCM
Interface2
(Port#2)
PCM
Interface4
(Port#4)
Figure 1. Block Diagram
[AK7719]
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■ Ordering Guide
AK7719ECB -20 ∼ +85°C 25-pin CSP (0.5mm pitch) Black type
AKD7719 Evaluation board for AK7719
■ Pin Layout
A B C E D
5
3
4
1
2
Top View
MARK
INDEX
EDC A B
5
3
4
1
2
Bottom View
5 PDN SDIN1 SDOUT1 BCLK1 SYNC1
4 VDD
BCLK3/
JX0 SDIN3 SDOUT3/
GP0 SYNC2
3 VSS
SYNC3/
JX1 TEST STO/
RDY BCLK2
2 TVDD I2C SDIN4 SDOU4/
GP1 SDIN2
1 SI/CAD1 SCLK/
CAD0
CSN/
SCL SO/ SDA SDOUT2
A B C D E
TOP View
[AK7719]
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PIN/FUNCTION
NO Pin Name I/O Function
A4 VDD - Core Power Supply Pin 1.2V
A2 TVDD -
I/O power Supply Pin 1.6∼3.6V
A3 VSS - Ground Pin 0V
A5 PDN I
P Power-Down Mode Pin
“H”: Power-up, “L”: Power-down, reset the control register.
The AK7719 must be reset once upon power-up.
STO Status Output Pin (Active High) (STRDY bit = “0”)
D3 RDY O Data Write Ready output pin for control I/F (STRDY bit = “1”)
E5 SYNC1 I
Frame Sync 1 pin
D5 BCLK1 I
Serial Data Clock 1 Pin
AK7719 goes into standby state when BCLK1 is not present.
B5 SDIN1 I
Serial Data Input 1 Pin
C5 SDOUT1 O
Serial Data Output 1 Pin
E4 SYNC2 O
Frame Sync 1 pin
E3 BCLK2 O
Serial Data Clock 2 Pin
E2 SDIN2 I Serial Data Input 2 Pin
E1 SDOUT2 O
Serial Data Output 2 Pin
SYNC3 Frame Sync 3 pin (SELPT bit = “1”)
B3 JX1 I Conditional Jump 1 Pin (SELPT bit = “0”)
BCLK3 Serial Data Clock 3 Pin (SELPT bit = “1”)
B4 JX0 I Conditional Jump 0 Pin (SELPT bit = “0”)
C4 SDIN3 I Serial Data Input 3 Pin
SDOUT3 Serial Data Output 3 Pin (SELDO3 bit = “0”)
D4 GP0 O DSP Programmable output 0 Pin (SELDO3 bit = “1”)
C2 SDIN4 I Serial Data Input 4 Pin
SDOUT4 Serial Data Output 4 Pin (SELDO4 bit = “0”)
D2 GP1 O DSP Programmable output 1 Pin (SELDO4 bit = “1”)
B2 I2C I Control Interface Mode Select Pin “H”: I2C, “L”: SPI
SCLK Serial Clock Input pin SPI (I2C pin = “L”)
B1 CAD0 I Slave Address 0 Input pin I2C (I2C pin = “H”)
CSN Chip select pin SPI (I2C pin = “L”)
C1 SCL I Control Interface clock input pin I2C (I2C pin = “H”)
SO O
Serial data output pin SPI (I2C pin = “L”)
D1 SDA I/O Control Interface input/output acknowledge pin I2C (I2C pin = “H”)
SI Serial data input pin SPI (I2C pin = “L”)
A1 CAD1 I Slave Address 1 Input pin I2C(I2C pin = “H”)
C3 TEST I Test pin (pull-down resistor) must be connected to VSS.
Note 1. All input pins must not be allowed to float.
Note 2. I2C and CAD0/1 pins must be fixed to “L” (VSS) or “H” (TVDD).
[AK7719]
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DSP Block Diagram
CP0, CP1 DP0, DP1
Data RAM
2048w x 24-Bit
MPX20 MPX20
X Y
Multiply
20 x 20 → 40- Bit
Mi con I/F
Control
PRAM
4096w x 36-Bit
DEC
PC
Stack: 5 levels(max)
MUL DBUS
S
HIFT
A B
ALU
44-Bit
Overflow Margin: 4-Bit
DR0
∼ 3
Over Flow Data
Generator
Division 20÷20→20 Peak Detector
Seri al I/F
CBUS(20-Bit)
DBUS(24-Bit)
40-Bit 24-Bit
40-Bit
44-Bit
40-Bit
16384w x 24-Bit
PTMP(LIFO) 6 x 24-Bit
DLP0, DLP1
DIN1
2 x 16/ 24-Bit
2 x 16/ 24-Bit
40-Bit DOUT1
TMP 12 x 24-Bit
2 x 16/ 24-Bit
DOUT2
DOUT3
2 x 16/24-Bit
2 x 16/ 24-Bit D IN 3
DIN2 2 x 16/ 24-Bit
Accelerator
Offset Reg
32w x 15 -Bit
2 x 16/ 24-Bit DOUT4
2 x 16/ 24-Bit DIN4
Delay RAM
Coef ficient RAM
2048w x 20-Bit
Pointe r
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■ Handling of Unused Pins
Unused I/O pins must be connected appropriately:
Pin Name Setting
STO/RDY, SDOUT3/GPO, SDOUT4/GP1 Leave Open
SYNC1, BCLK1, SDIN1, SDIN2, SDIN3, SDIN4,
SYNC3/JX1, BCLK3/JX0, TEST Connect to VSS.
■ Pin States in Power-down Mode
The table below shows pin states when the PDN pin= “L”.
NO Pin Name I/O Pin state
STO
D3 RDY O Low
C5 SDOUT1 O SDIN2 data output
E4 SYNC2 O SYNC1 data output
E3 BCLK2 O BCLK1 data output
E1 SDOUT2 O SDIN1 data output
SDOUT3
D4 GP0 O SDIN4 data output
SDOUT4
D2 GP1 O SDIN3 data output
SO O
Low level (I2C pin = “L”: SPI)
D1 SDA I/O Hi-z (I2C pin = “H” :I2C)
ABSOLUTE MAXIMUM RATINGS
(VSS=0V; All voltages are with respect to ground.)
Parameter Symbol min max Unit
Power Supply Voltage (DSP Core) VDD −0.3 1.6 V
Power Supply Voltage (Digital I/O) TVDD −0.3 4.1 V
Input Current (except for power supply pins) IIN - ±10 mA
Input Voltage VIND −0.3 TVDD+0.3 V
Operating Ambient Temperature Ta −20 85 °C
Storage Temperature Tstg −65 150 °C
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATION CONDITION
(VSS=0V; All voltages are with respect to ground.)
Parameter Symbol min typ max Unit
Supply Voltage Range (DSP core) VDD 1.1 1.2 1.3 V
Supply Voltage Range (I/Os) TVDD 1.6 1.8 3.6 V
Note 3. The power-up sequence with VDD and TVDD is not critical. The PDN pin should be held “L” when power is
supplied. The PDN pin is allowed to be “H” after all power supplies are applied and settled.
Note 4. The external pull-up resistors at the SDA and SCL pins should be connected to TVDD voltage or less.
WARNING: AKM assumes no responsibility for the usage beyond the conditions in the datasheet.
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ELECTRIC CHARACTERISTICS
(Ta=-20ºC~85ºC; VDD=1.2V, TVDD =1.6V~3.6V; VSS =0V)
Parameter Symbol min typ max Unit
High level input voltage VIH 70%TVDD V
Low level input voltage VIL 30%TVDD V
High level inptu voltage Iout=-200μA (Note 5) VOH TVDD-0.2 V
Low level input voltage Iout= 200μA (Note 5) VOL 0.2 V
TVDD ≥ 2.0V 0.4 V SDA low level output
voltage Iout=3mA TVDD < 2.0V VOL 20%TVDD V
Input leak current Iin ±10 μA
Note 5. Except for the SDA pin.
(Ta=25ºC; VDD=1.2V; TVDD=1.8V; VSS =0V, fin=1 KHz, fs=8kHz 16 bit (FS bits=0h, LAW bits = 0h, DIF bit = 2h,
TESTC bit = 1h, DSP running with programmed connecting DIN1 with DOUT2 and DIN2 with DOUT1.
Parameter min typ max Unit
Power Supplies:
Power-Up (PDN pin = “H”) DSP-Operational State
All Circuit Power-up
VDD - 3.1 - mA
TVDD
VDD=1.2V
TVDD=1.8V (Note 6)- 0.02 - mA
Power Consumption - 3.76 mW
All Circuit Power-up
VDD - 20 mA
TVDD
VDD=1.3V
TVDD=3.6V (Note 6)- 2.0 mA
Power Consumption - 33.2 mW
Power-Down state (PDN pin = “L”), (Note 7)
VDD - 2.4 8
μA
TVDD - 0.2 1
μA
Note 6. The current of VDD, TVDD changes depending on the system frequency and contents of the DSP program.
Note 7. All digital input pins are fixed to TVDD or VSS.
DC CHARACTERISTICS
POWER CONSUMPTION
[AK7719]
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■ System Clock
(Ta= -20ºC ~ 85ºC, VDD=1.2V, TVDD= 1.6V ~ 3.6V, VSS=0V) CL=20pF (except SDA pin) or 400pF (SDA pin);
unless otherwise specified
Parameter Symbol min typ max Unit
Normal Operation mode: SYNC1/3, BCLK1/BCLK3 Input Timing
SYNC1/3 Input Timing
SYNC1/3 frequency fs 8 48 kHz
BCLK1 Input Timing (Note 8, Note 9) fBCLK 64 3072 kHz
BCLK1/3 Pulse width Low tBCKL 0.4 x tBCLK ns
BCLK1/3 Pulse width High tBCKH 0.4x tBCLK ns
Note 8. SYNC1 and BCLK1 or SYNC3 and BCLK3 should be synchronized and their sampling rates (fs) should be stable
Note 9. Required fBCLK: ≥ 2 (Data length set by LAW bit) x SYNC2 frequency
■ Reset and Standby
(Ta= -20ºC ~ 85ºC, VDD=1.2V, TVDD= 1.6V ~ 3.6V, VSS=0V)
Parameter Symbol min typ max Unit
PDN (Note 10) tPDN 600 ns
Note 10. The AK7719 can be reset by bringing the PDN pin = “L” upon power-up.
■ Serial Data Interface
(Ta= -20ºC ~ 85ºC, TVDD= 1.6V ~ 3.6V, VSS=0V, CL=20pF)
Parameter Symbols min typ max Unit
SDIN1, SDIN3, SDIN4, SDOUT1, SDOUT3, SDOUT4
Delay Time from BCLK1 “↑” to SYNC1 “↑” (Note 11) tBSYD 20 ns
Delay Time from SYNC1 “↓” to BCLK1 “↑” tSYBD 100 ns
Serial Data Input Latch Setup Time tB1IDS 40 ns
Serial Data Input Latch Hold Time tB1IDH 40 ns
Delay Time from SYNC1 to Serial Data Output tSY1OD 40 ns
Delay Time from BCLK1 “↓” to Serial Data Output (Note 12) tB1OD 40 ns
SDIN2, SDOUT2
SYNC2 Duty cycle 50 %
Serial Data Input Latch Setup Time tB2IDS 40 ns
Serial Data Input Latch Hold Time tB2IDH 40 ns
Delay Time from SYNC2 to Serial Data Outputs tSY2OD 40 ns
Delay Time from BCLK2 “↓”to Serial Data Output (Note 13) tB2OD 40 ns
SDINn → SDOUTn (n=1, 2, 3)
Delay time from SDINn to SDOUTn Output tIOD 60 ns
Note 11. When the polarity of BCLK1 is inverted, delay time is from BCLK1 “↓”
Note 12. When the polarity of BCLK1 is inverted, delay time is from BCLK1 “↑”.
Note 13. When the polarity of BCLK2 is inverted, delay time is from BCLK2 “↑”.
SWITCHING CHARACTERISTICS
[AK7719]
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■ Timing Diagram
1/fs
1/fs
VIH
VIL
SYNC1/3
1/fBCLK
1/fBCLK
VIH
VIL
BCLK1/3
tBCLK=1/fBCLK
ts=1/fs
Figure 2. System Clock
VIL
tPDN
PDN
Figure 3. Power-down
[AK7719]
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tB1IDS
tBSYD tSYBD
VIH
SYNC1/3
BCLK1/3
VIL
VIH
VIL
VIH
VIL
tB1IDH
SDIN1/3/4
tSY1OD
SDOUT1/3/4 50%TVDD
tB1OD
VIH
VIL
SDIN2/4/3
tIOD
Figure 4. Serial Data Interface (Port#1, 3, 4)
tB2IDS
SYNC2
BCLK2
VIH
VIL
tB2IDH
SDIN2
tSY2OD
SDOUT2 50%TVDD
tB2OD
50%TVDD
50%TVDD
VIH
VIL
SDIN1
tIOD
Figure 5. Serial Data Interface (Port#2)
[AK7719]
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■ μP Interface (SPI Mode)
(Ta= -20ºC ~ 85ºC, VDD=1.2V; TVDD=1.6~3.6V, VSS =0V; CL=20pF)
Note 14. Except when input the eighth bit of the command code.
tSCLKH
tSCLKL
1/fSCLK
1/fSCLK
tRST1 tIRRQ
SCLK
VIH
VIL
tSF tSR
PDN
CSN
VIL
VIH
VIL
VIH
Figure 6. μP Interface 1 (SPI)
Parameter Symbol min typ max Unit
μP Interface Timing (SPI mode)
SCLK Fall Time tSF 30 ns
SCLK Rise Time tSR 30 ns
SCLK Frequency fSCLK 4.0 MHz
SCLK Low Level Width tSCLKL 120 ns
SCLK High Level Width tSCLKH 120 ns
CSN High Level Width tWRQH 500 ns
From CSN “↑” to PDN “↑”
From PDN “↑” to CSN “↓”
tRST1
tIRRQ
600
100
ns
μs
From SCLK “↓” to CSN “↑” tWSC 500 ns
From SCLK “↑” to CSN “↑” tSCW 800 ns
SI Latch Setup Time tSIS 100 ns
SI Latch Hold Time tSIH 100 ns
AK7719 → μP
Delay Time from SCLK “↓”to SO Output tSOS 100 ns
Hold Time from SCLK “↑” to SO Output (Note 14) tSOH 100 ns
[AK7719]
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tWRQH
tSIS tSIH
tSCW tSCW tWSC
CSN
SI
VIH
VIL
VIH
tWSC
SCLK VIL
VIH
VIL
Figure 7. μP Interface 2 (SPI)
tSOS tSOH
SCLK
VIL
VIH
SO
VIH
VIL
Figure 8. μP Interface 3 (SPI)
CONFIDENTIAL [AK7719]
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■ I²CBUS Interface
(Ta=-20ºC~85ºC, VDD=1.2V, VDD=1.6~3.6V, VSS =0V, CL=20pF)
Parameter Symbol min typ max Unit
I²C Timing
SCL clock frequency fSCL 30 400 kHz
Bus Free Time Between Transmissions tBUF 1.3 μs
Start Condition Hold Time
(prior to first Clock pulse) tHD:STA 0.6 μs
Clock Low Time tLOW 1.3 μs
Clock High Time tHIGH 0.6 μs
Setup Time for Repeated Start Condition tSU:STA 0.6 μs
SDA Hold Time from SCL Falling tHD:DAT 0 0.9 μs
SDA Setup Time from SCL Rising tSU: DAT 0.1 μs
Rise Time of Both SDA and SCL Lines tR 0.3
μs
Fall Time of Both SDA and SCL Lines tF 0.3
μs
Setup Time for Stop Condition tSU:STO 0.6 μs
Pulse Width of Spike Noise Suppressed
by Input Filter tSP 0 50 ns
Capacitive load on bus Cb 400 pF
Note 15. I2C-bus is a trademark of NXP B.V.
tHIGH
SCL
SDA
VIH
tLOW
tBUF
tHD:STA
tR tF
tHD:DAT tSU:DAT tSU:STA
Stop Start Start Stop
tSU:STO
VIL
VIH
VIL
tSP
Figure 9. I2C Bus Interface
CONFIDENTIAL [AK7719]
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PACKAGE
0.345±0.029
0.180±0.03
0.075
C
C
0.565±0.059
(0.040)
0.5
2.93±0.03
EDC A B
5 3 4
1 2
0.5
30 -φ0.285
± 0.03
2.62±0.03
A
Top View
771
9
XXXX
1
25pin CSP (Unit: mm)
A
φ 0.05 M
φ 0.15 M A
C
CB
B
■ Material & Lead Finish
Package: Epoxy, Halogen (bromine and chlorine) free
Solder ball material: SnAgCu
CONFIDENTIAL [AK7719]
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MARKING
A
1
7719
XXX
X
XXXX: Date code (4 digit)
Date (Y/M/D) Revision Reason Page Contents
12/01/12 00 First Edition
12/05/10 01 Specification
Change
1 FEATURES
Power Consumption: 6.2mA(7.5mW) → 7.4mA (8.9mW)
typ.
7 POWER CONSUMPTION
Measurement Conditions: “TESTC bit =1h” was added.
Power-Up, VDD=1.2V, TVDD=1.8V
VDD: 1.7 → 3.1mA (typ)
Power Consumption: 2.1 → 3.76mW (typ)
13/02/06 02 Error
Correction
14 PACKAGE
Package drawing dimensions were changed.
REVISION HISTORY
CONFIDENTIAL [AK7719]
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IMPORTANT NOTICE
z These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
Microdevices Corporation (AKM) or authorized distributors as to current status of the products.
z Descriptions of external circuits, application circuits, software and other related information contained in this
document are provided only to illustrate the operation and application examples of the semiconductor products. You
are fully responsible for the incorporation of these external circuits, application circuits, software and other related
information in the design of your equipments. AKM assumes no responsibility for any losses incurred by you or third
parties arising from the use of these information herein. AKM assumes no liability for infringement of any patent,
intellectual property, or other rights in the application or use of such information contained herein.
z Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange,
or strategic materials.
z AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or
other hazard related device or systemNote2), and AKM assumes no responsibility for such use, except for the use
approved with the express written consent by Representative Director of AKM. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and
which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety
or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or
perform may reasonably be expected to result in loss of life or in significant injury or damage to person or
property.
z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places
the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer
or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all
claims arising from the use of said product in the absence of such notification.
Thank you for your access to AKM product information.
More detail product information is available, please contact our
sales office or authorized distributors.
