MAX1181ECM+D - Maxim Integrated Products, Inc.

General Description

The MAX1181 is a 3V, dual 10-bit, analog-to-digital

converter (ADC) featuring fully-differential wideband

track-and-hold (T/H) inputs, driving two pipelined, nine-

stage ADCs. The MAX1181 is optimized for low-power,

high-dynamic performance applications in imaging,

instrumentation, and digital communication applica-

tions. The MAX1181 operates from a single 2.7V to 3.6V

supply, consuming only 246mW, while delivering a typi-

cal signal-to-noise ratio (SNR) of 59dB at an input fre-

quency of 20MHz and a sampling rate of 80Msps. The

T/H driven input stages incorporate 400MHz (-3dB)

input amplifiers. The converters may also be operated

with single-ended inputs. In addition to low operating

power, the MAX1181 features a 2.8mA sleep mode, as

well as a 1µA power-down mode to conserve power

during idle periods.

An internal 2.048V precision bandgap reference sets

the full-scale range of the ADC. A flexible reference

structure allows the use of the internal or external

reference, if desired for applications requiring

increased accuracy or a different input voltage range.

The MAX1181 features parallel, CMOS-compatible

three-state outputs. The digital output format is set to

two’s complement or straight offset binary through a

single control pin. The device provides for a separate

output power supply of 1.7V to 3.6V for flexible interfac-

ing. The MAX1181 is available in a 7mm ✕7mm, 48-pin

TQFP package, and is specified for the extended

industrial (-40°C to +85°C) temperature range.

Pin-compatible higher and lower speed versions of the

MAX1181 are also available. Please refer to the

MAX1180 datasheet for 105Msps, the MAX1182

datasheet for 65Msps, the MAX1183 datasheet for

40Msps, and the MAX1184 datasheet for 20Msps. In

addition to these speed grades, this family includes a

20Msps multiplexed output version (MAX1185), for

which digital data is presented time-interleaved on a

single, parallel 10-bit output port.

Applications

High-Resolution Imaging

I/Q Channel Digitization

Multichannel IF Undersampling

Instrumentation

Video Application

Features

♦Single 3V Operation

♦Excellent Dynamic Performance

59dB SNR at fIN = 20MHz

73dB SFDR at fIN = 20MHz

♦Low Power

82mA (Normal Operation)

2.8mA (Sleep Mode)

1µA (Shutdown Mode)

♦0.02dB Gain and 0.25° Phase Matching (typ)

♦Wide ±1VP-P Differential Analog Input Voltage

Range

♦400MHz, -3dB Input Bandwidth

♦On-Chip 2.048V Precision Bandgap Reference

♦User-Selectable Output Format—Two’s

Complement or Offset Binary

♦48-Pin TQFP Package with Exposed Pad for

Improved Thermal Dissipation

♦Evaluation Kit Available

MAX1181

Dual 10-Bit, 80Msps, 3V, Low-Power ADC

with Internal Reference and Parallel Outputs

________________________________________________________________ Maxim Integrated Products 1

D1A

D0A

OGND

OVDD

OGND

D0B

D1B

D2B

D3B

D4B

D5B

COM

VDD

GND

INA+

INA-

VDD

GND

INB-

INB+

GND

VDD

CLK

48 TQFP-EP

MAX1181

GND

VDD

GND

VDD

T/B

SLEEP

D9B

D8B

D7B

D6B

REFN

REFP

REFIN

REFOUT

D9A

D8A

D7A

D6A

D5A

D4A

D3A

D2A

EP*

NOTE: THE PIN 1 INDICATOR FOR LEAD-FREE PACKAGES IS REPLACED

BY A "+" SIGN.

Pin Configuration

Ordering Information

19-2093; Rev 1; 2/07

EVALUATION KIT

AVAILABLE

PART TEMP RANGE PIN-PACKAGE

MAX1181ECM -40°C to +85°C 48 TQFP-EP*

MAX1181ECM+

-40°C to +85°C 48 TQFP-EP*

Functional Diagram appears at end of data sheet.

*EP = Exposed paddle.

+Denotes a lead-free package.

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,

or visit Maxim's website at www.maxim-ic.com.

ELECTRICAL CHARACTERISTICS

(VDD = 3V, OVDD = 2.5V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a

10kΩresistor, VIN = 2VP-P (differential with respect to COM), CL= 10pF at digital outputs (Note 1), fCLK = 83.333MHz, TA= TMIN to

TMAX, unless otherwise noted. Typical values are at TA= +25°C.) (Note 2)

MAX1181

Dual 10-Bit, 80Msps, 3V, Low-Power ADC

with Internal Reference and Parallel Outputs

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

VDD, OVDD to GND ...............................................-0.3V to +3.6V

OGND to GND.......................................................-0.3V to +0.3V

INA+, INA-, INB+, INB- to GND ...............................-0.3V to VDD

REFIN, REFOUT, REFP, REFN, CLK,

COM to GND ...........................................-0.3V to (VDD + 0.3V)

OE, PD, SLEEP, T/B, D9A–D0A,

D9B–D0B to OGND ..............................-0.3V to (OVDD + 0.3V)

Continuous Power Dissipation (TA= +70°C)

48-Pin TQFP-EP (derate 30.4mW/°C above +70°C) ...2430mW

Operating Temperature Range ...........................-40°C to +85°C

Junction Temperature......................................................+150°C

Storage Temperature Range .............................-60°C to +150°C

Lead Temperature (soldering, 10s) .................................+300°C

PARAMETER

SYMBOL

CONDITIONS

MIN TYP MAX

UNITS

DC ACCURACY

Resolution 10 Bits

Integral Nonlinearity INL fIN = 7.47MHz

±0.6 ±2.2

LSB

Differential Nonlinearity DNL

fIN = 7.47MHz, no missing codes guaranteed ±0.4 ±1.0

LSB

Offset Error -2 +2

% FS

Gain Error 0±2

% FS

ANALOG INPUT

Differential Input Voltage Range

VDIFF Differential or single-ended inputs

±1.0

Common-Mode Input Voltage

Range VCM VDD/2

± 0.5

Input Resistance RIN Switched capacitor load 25 kΩ

Input Capacitance CIN 5pF

CONVERSION RATE

Maximum Clock Frequency fCLK 80

MHz

Data Latency 5Clock

Cycles

DYNAMIC CHARACTERISTICS

fINA or B = 7.47MHz, TA = +25°C

56.5 59.5

fINA or B = 20MHz, TA = +25°C5659

Signal-to-Noise Ratio

(Note 3) SNR

fINA or B = 39.9MHz 59

fINA or B = 7.47MHz, TA = +25°C5659

fINA or B = 20MHz, TA = +25°C

55.3 58.5

Signal-to-Noise And Distortion

(Note 3)

SINAD

fINA or B = 39.9MHz

58.5

fINA or B = 7.47MHz, TA = +25°C6575

fINA or B = 20MHz, TA = +25°C6473

Spurious-Free Dynamic

Range (Note 3) SFDR

fINA or B = 39.9MHz 71

dBc

fINA or B = 7.47MHz -76

fINA or B = 20MHz -76

Third-Harmonic Distortion

(Note 3) HD3

fINA or B = 39.9MHz -75

dBc

MAX1181

Dual 10-Bit, 80Msps, 3V, Low-Power ADC

with Internal Reference and Parallel Outputs

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS (continued)

(VDD = 3V, OVDD = 2.5V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a

10kΩresistor, VIN = 2VP-P (differential with respect to COM), CL= 10pF at digital outputs (Note 1), fCLK = 83.333MHz, TA= TMIN to

TMAX, unless otherwise noted. Typical values are at TA= +25°C.) (Note 2)

PARAMETER

SYMBOL

CONDITIONS

MIN TYP MAX

UNITS

fINA or B = 7.47MHz, TA = +25°C

-73 -64

fINA or B = 20MHz, TA = +25°C

-70 -63

Total Harmonic Distortion

(First Four Harmonics) (Note 3) THD

fINA or B = 39.9MHz

-70

dBc

Intermodulation Distortion

(First Five Odd-Order IMDs) IMD

fINA or B = 38.1546MHz at -6.5dBFS

fINA or B = 41.9532MHz at -6.5dBFS

(Note 4)

-73.5

dBc

Small-Signal Bandwidth Input at -20dBFS, differential inputs

500

MHz

Full-Power Bandwidth FPBW Input at -0.5dBFS, differential inputs

400

MHz

Aperture Delay tAD 1ns

Aperture Jitter tAJ 2ps

RMS

Overdrive Recovery Time For 1.5 x full-scale input 2 ns

Differential Gain

±1

Differential Phase

±0.25

degrees

Output Noise INA+ = INA- = INB+ = INB- = COM

0.2

LSBRMS

INTERNAL REFERENCE

Reference Output Voltage

REFOUT 2.048

±3%

Reference Temperature

Coefficient

TCREF 60

ppm/°C

Load Regulation

1.25

mV/mA

BUFFERED EXTERNAL REFERENCE (VREFIN = 2.048V)

REFIN Input Voltage

VREFIN 2.048

Positive Reference Output

Voltage VREFP

2.012

Negative Reference Output

Voltage

VREFN 0.988

Differential Reference Output

Voltage Range

ΔVREF

ΔVREF = VREFP - VREFN

0.95 1.024 1.10

REFIN Resistance

RREFIN > 50

MΩ

Maximum REFP, COM Source

Current

ISOURCE > 5

Maximum REFP, COM Sink

Current ISINK

250

µA

Maximum REFN Source Current

ISOURCE 250

µA

Maximum REFN Sink Current ISINK

> 5

UNBUFFERED EXTERNAL REFERENCE (VREFIN = AGND, reference voltage applied to REFP, REFN and COM )

REFP, REFN Input Resistance

RREFP

RREFN

Measured between REFP and COM and

REFN and COM 4kΩ

MAX1181

Dual 10-Bit, 80Msps, 3V, Low-Power ADC

with Internal Reference and Parallel Outputs

4 _______________________________________________________________________________________

PARAMETER

SYMBOL

CONDITIONS

MIN TYP MAX

UNITS

Differential Reference Input

Voltage

ΔVREF

ΔVREF = VREFP - VREFN 1.024

± 10% V

COM Input Voltage VCOM VDD / 2

± 10% V

REFP Input Voltage VREFP VCOM

+ ΔVREF / 2 V

REFN Input Voltage

VREFN

VCOM

- ΔVREF / 2 V

DIGITAL INPUTS (CLK, PD, OE, SLEEP, T/B)

CLK 0.8 x

VDD

Input High Threshold VIH

PD, OE, SLEEP, T/B 0.8 x

OVDD

CLK 0.2 x

VDD

Input Low Threshold VIL

PD, OE, SLEEP, T/B 0.2 x

OVDD

Input Hysteresis VHYST 0.1 V

IIH VIH = OVDD or VDD (CLK) ±5

Input Leakage IIL VIL = 0 ±5µA

Input Capacitance CIN 5pF

DIGITAL OUTPUTS (D9A–D0A, D9B–D0B)

Output-Voltage Low VOL ISINK = 200µA 0.2 V

Output-Voltage High VOH ISOURCE = 200µA OVDD

- 0.2

Three-State Leakage Current ILEAK OE = OVDD

±10

µA

Three-State Output Capacitance

COUT OE = OVDD 5pF

POWER REQUIREMENTS

Analog Supply Voltage Range VDD 2.7 3.0 3.6 V

Output Supply Voltage Range OVDD 1.7 2.5 3.6 V

Operating, fINA or B = 20MHz at -0.5dBFS 82 97

Sleep mode 2.8 mA

Analog Supply Current IVDD

Shutdown, clock idle, PD = OE = OVDD 115µA

Operating, CL = 15pF , fINA or B = 20MHz at

-0.5dBFS 13 mA

Sleep mode 100

Output Supply Current IOVDD

Shutdown, clock idle, PD = OE = OVDD 210

µA

Operating, fINA or B = 20MHz at -0.5dBFS 246

291

Sleep mode 8.4Power Dissipation

PDISS

Shutdown, clock idle, PD = OE = OVDD 345

µW

ELECTRICAL CHARACTERISTICS (continued)

(VDD = 3V, OVDD = 2.5V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a

10kΩresistor, VIN = 2VP-P (differential with respect to COM), CL= 10pF at digital outputs (Note 1), fCLK = 83.333MHz, TA= TMIN to

TMAX, unless otherwise noted. Typical values are at TA= +25°C.) (Note 2)

MAX1181

Dual 10-Bit, 80Msps, 3V, Low-Power ADC

with Internal Reference and Parallel Outputs

_______________________________________________________________________________________ 5

-100

-80

-90

-60

-70

-40

-50

-30

-10

-20

010155 2025303540

FFT PLOT CHA (8192-POINT RECORD,

DIFFERENTIAL INPUT)

MAX1181 toc01

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dB)

fINA = 6.0449MHz

fINB = 7.5099MHz

fCLK = 80.0006MHz

AINA = -0.46dBFS

CHA

-100

-80

-90

-60

-70

-40

-50

-30

-10

-20

010155 2025303540

FFT PLOT CHB (8192-POINT RECORD,

DIFFERENTIAL INPUT)

MAX1181 toc02

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dB)

fINA = 6.0449MHz

fINB = 7.5099MHz

fCLK = 80.0006MHz

AINB = -0.52dBFS

CHB

-100

-80

-90

-60

-70

-40

-50

-30

-10

-20

010155 2025303540

FFT PLOT CHA (8192-POINT RECORD,

DIFFERENTIAL INPUT)

MAX1181 toc03

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dB)

fINA = 19.9123MHz

fINB = 24.9123MHz

fCLK = 80.0006MHz

AINA = -0.52dBFS

CHA

Typical Operating Characteristics

(VDD = 3V, OVDD = 2.5V, internal reference, differential input at -0.5dBFS, fCLK = 80.0006MHz, CL≈10pF. TA= +25°C, unless other-

wise noted.)

PARAMETER

SYMBOL

CONDITIONS

MIN TYP MAX

UNITS

Offset

±0.2

mV/V

Power Supply Rejection PSRR Gain

±0.1

%/V

TIMING CHARACTERISTICS

CLK Rise to Output Data Valid tDO Figure 3 (Note 5) 5 8 ns

Output Enable Time

tENABLE

Figure 4

Output Disable Time

tDISABLE

Figure 4

1.5

CLK Pulse-Width High tCH Figure 3 clock period: 12ns

6 ±1

CLK Pulse-Width Low tCL Figure 3 clock period: 12ns

6 ±1

Wakeup from sleep mode

0.28

Wake-Up Time (Note 6) tWAKE Wakeup from shutdown

1.5

µs

CHANNEL-TO-CHANNEL MATCHING

Crosstalk fINA or B = 20MHz at -0.5dBFS

-70

Gain Matching fINA or B = 20MHz at -0.5dBFS

0.02 ±0.2

Phase Matching fINA or B = 20MHz at -0.5dBFS

0.25

degrees

ELECTRICAL CHARACTERISTICS (continued)

(VDD = 3V, OVDD = 2.5V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a

10kΩresistor, VIN = 2VP-P (differential with respect to COM), CL= 10pF at digital outputs (Note 1), fCLK = 83.333MHz, TA= TMIN to

TMAX, unless otherwise noted. Typical values are at TA= +25°C.) (Note 2)

Note 1: Equivalent dynamic performance is obtainable over full OVDD range with reduced CL.

Note 2: Specifications at ≥+25°C are guaranteed by production test and < +25°C are guaranteed by design and characterization.

Note 3: SNR, SINAD, THD, SFDR, and HD3 are based on an analog input voltage of -0.5dBFS, referenced to a +1.024V full-scale

input voltage range.

Note 4: Intermodulation distortion is the total power of the intermodulation products relative to the individual carrier. This number is

6dB or better, if referenced to the two-tone envelope.

Note 5: Digital outputs settle to VIH, VIL. Parameter guaranteed by design.

Note 6: With REFIN driven externally, REFP, COM, and REFN are left floating while powered down.

MAX1181

Dual 10-Bit, 80Msps, 3V, Low-Power ADC

with Internal Reference and Parallel Outputs

6 _______________________________________________________________________________________

-100

-80

-90

-60

-70

-40

-50

-30

-10

-20

010155 2025303540

FFT PLOT CHB (8192-POINT RECORD,

DIFFERENTIAL INPUT)

MAX1181 toc04

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dB)

INA

= 19.9123MHz

INB

= 24.9123MHz

CLK

= 80.0006MHz

INB

= -0.53dBFS

CHB

-100

-80

-90

-60

-70

-40

-50

-30

-10

-20

010155 2025303540

FFT PLOT CHA (8192-POINT RECORD,

DIFFERENTIAL INPUT)

MAX1181 toc05

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dB)

fINA = 40.4202MHz

fINB = 47.0413MHz

fCLK = 80.0006MHz

AINA = -0.52dBFS

CHA

-100

-80

-90

-60

-70

-40

-50

-30

-10

-20

010155 2025303540

FFT PLOT CHB (8192-POINT RECORD,

DIFFERENTIAL INPUT)

MAX1181 toc06

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dB)

fINA = 40.4202MHz

fINB = 47.0413MHz

fCLK = 80.0006MHz

AINB = -0.53dBFS

CHB

-100

-80

-90

-60

-70

-40

-50

-30

-10

-20

010155 2025303540

TWO-TONE IMD PLOT (8192-POINT RECORD,

COHERENT SAMPLING)

MAX1181 toc07

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dB)

fIN1 = 38.1546MHz

fIN2 = 41.9632MHz

fCLK = 80.0006MHz

AIN1 = AIN2 = -6dBFS

2nd ORDER IMD

fIN1

fIN2

0403010 20 50 60 70 80 90 100

SIGNAL-TO-NOISE RATIO

vs. ANALOG INPUT FREQUENCY

MAX1181 toc08

ANALOG INPUT FREQUENCY (MHz)

SNR (dB)

CHA

CHB

0403010 20 50 60 70 80 90 100

SIGNAL-TO-NOISE AND DISTORTION

vs. ANALOG INPUT FREQUENCY

MAX1181 toc09

ANALOG INPUT FREQUENCY (MHz)

SINAD (dB)

CHA

CHB

-80

-77

-74

-71

-68

-65

0405020 3010 60 70 80 90 100

TOTAL HARMONIC DISTORTION

vs. ANALOG INPUT FREQUENCY

MAX1181 toc10

ANALOG INPUT FREQUENCY (MHz)

THD (dBc)

CHA

CHB

0405020 3010 60 70 80 90 100

SPURIOUS-FREE DYNAMIC RANGE

vs. ANALOG INPUT FREQUENCY

MAX1181 toc11

ANALOG INPUT FREQUENCY (MHz)

SFDR (dBc)

CHA

CHB

1 10 100 1000

FULL-POWER INPUT BANDWIDTH

vs. ANALOG INPUT FREQUENCY

(SINGLE-ENDED)

MAX1181 toc12

ANALOG INPUT FREQUENCY (MHz)

GAIN (dB)

-8

-6

-2

-4

Typical Operating Characteristics (continued)

(VDD = 3V, OVDD = 2.5V, internal reference, differential input at -0.5dBFS, fCLK = 80.0006MHz, CL≈10pF. TA= +25°C, unless other-

wise noted.)

MAX1181

Dual 10-Bit, 80Msps, 3V, Low-Power ADC

with Internal Reference and Parallel Outputs

_______________________________________________________________________________________ 7

1 10 100 1000

SMALL-SIGNAL INPUT BANDWIDTH

vs. ANALOG INPUT FREQUENCY

(SINGLE-ENDED)

MAX1181 toc13

ANALOG INPUT FREQUENCY (MHz)

GAIN (dB)

-8

-6

-2

-4

VIN = 100mVP-P

SIGNAL-TO-NOISE RATIO

vs. ANALOG INPUT POWER (fIN = 20MHz)

MAX1181 toc14

ANALOG INPUT POWER (dBFS)

SNR (dB)

-9 -6 -5-8 -7 -4 -3 -2 -1 0

SIGNAL-TO-NOISE AND DISTORTION

vs. ANALOG INPUT POWER (fIN = 20MHz)

MAX1181 toc15

ANALOG INPUT POWER (dBFS)

SINAD (dB)

-9 -6 -5-8 -7 -4 -3 -2 -1 0

-100

-85

-95

-90

-70

-80

-75

-60

-65

-55

-45

-50

-40

-9 -7 -6 -5-8 -4 -3 -2 -1 0

TOTAL HARMONIC DISTORTION vs. ANALOG

INPUT POWER (fIN = 20MHz)

MAX1181 toc16

ANALOG INPUT POWER (dBFS)

THD (dBc)

100

-9 -7 -6 -5-8 -4 -3 -2 -1 0

SPURIOUS-FREE DYNAMIC RANGE vs. ANALOG

INPUT POWER (fIN = 20MHz)

MAX1181 toc17

ANALOG INPUT POWER (dBFS)

SFDR (dBc)

-1.0

-0.6

-0.8

-0.2

-0.4

0.2

0.4

0.8

0.6

1.0

0 256 384128 512 640 768 896 1024

INTEGRAL NONLINEARITY

(BEST-STRAIGHT-LINE FIT)

MAX1181 toc18

DIGITAL OUTPUT CODE

INL (LSB)

-1.0

-0.6

-0.8

-0.2

-0.4

0.2

0.4

0.8

0.6

1.0

0 256 384128 512 640 768 896 1024

DIFFERENTIAL NONLINEARITY

MAX1181 toc19

DIGITAL OUTPUT CODE

DNL (LSB)

-2

-1

-40 10-15 35 60 85

GAIN ERROR vs. TEMPERATURE,

EXTERNAL REFERENCE (VREFIN = 2.048V)

MAX1181 toc20

TEMPERATURE (°C)

GAIN ERROR (LSB)

CHA

CHB

-5

-3

-1

-40 10-15 35 60 85

OFFSET ERROR vs. TEMPERATURE,

EXTERNAL REFERENCE (VREFIN = 2.048V)

MAX11811 toc21

TEMPERATURE (°C)

OFFSET ERROR (LSB)

CHA

CHB

Typical Operating Characteristics (continued)

(VDD = 3V, OVDD = 2.5V, internal reference, differential input at -0.5dBFS, fCLK = 80.0006MHz, CL≈10pF. TA= +25°C, unless other-

wise noted.)

MAX1181

Dual 10-Bit, 80Msps, 3V, Low-Power ADC

with Internal Reference and Parallel Outputs

8 _______________________________________________________________________________________

100

2.70 3.002.85 3.15 3.30 3.45 3.60

ANALOG SUPPLY CURRENT

vs. ANALOG SUPPLY VOLTAGE

MAX1181 toc22

VDD (V)

IVDD (mA)

100

-40 10-15 35 60 85

ANALOG SUPPLY CURRENT vs. TEMPERATURE

MAX11811 toc23

TEMPERATURE (°C)

IVDD (mA)

0.4

1.2

0.8

1.6

2.0

2.70 3.002.85 3.15 3.30 3.45 3.60

ANALOG POWER-DOWN CURRENT

vs. ANALOG POWER SUPPLY

MAX1181 toc24

VDD (V)

IVDD (μA)

OE = PD = OVDD

35 45 5040 55 60 65

SNR/SINAD, -THD/SFDR

vs. CLOCK DUTY CYCLE

MAX1181 toc25

CLOCK DUTY CYCLE (%)

SNR/SINAD, -THD/SFDR (dB, dBc)

SFDR

fINA = 24.9123MHz

-THD

SINAD

SNR

2.025

2.035

2.055

2.045

2.065

2.075

2.70 3.002.85 3.15 3.30 3.45 3.60

INTERNAL REFERENCE VOLTAGE

vs. ANALOG SUPPLY VOLTAGE

MAX1181 toc26

VDD (V)

VREFOUT (V)

2.00

2.02

2.06

2.04

2.08

2.10

-40 10-15 35 60 85

INTERNAL REFERENCE VOLTAGE

vs. TEMPERATURE

MAX11811 toc27

TEMPERATURE (°C)

VREFOUT (V)

40000

20000

80000

60000

120000

100000

140000

N - 1N - 2

0965 730 0

129377

NN + 1 N + 2

OUTPUT NOISE HISTOGRAM (DC INPUT)

MAX1181 toc28

DIGITAL OUTPUT NOISE

COUNTS

Typical Operating Characteristics (continued)

(VDD = 3V, OVDD = 2.5V, internal reference, differential input at -0.5dBFS, fCLK = 80.0006MHz, CL≈10pF. TA= +25°C, unless other-

wise noted.)

MAX1181

Dual 10-Bit, 80Msps, 3V, Low-Power ADC

with Internal Reference and Parallel Outputs

_______________________________________________________________________________________ 9

Pin Description

PIN NAME FUNCTION

1 COM Common-Mode Voltage Input/Output. Bypass to GND with a ≥ 0.1µF capacitor.

2, 6, 11, 14, 15

VDD

Analog Supply Voltage. Bypass each supply pin to GND with a 0.1µF capacitor. The analog

supply voltage accepts a 2.7V to 3.6V input range.

3, 7, 10, 13, 16

GND Analog Ground

4 INA+ Channel ‘A’ Positive Analog Input. For single-ended operation, connect signal source to INA+.

5 INA- Channel ‘A’ Negative Analog Input. For single-ended operation, connect INA- to COM.

8 INB- Channel ‘B’ Negative Analog Input. For single-ended operation, connect INB- to COM.

9 INB+ Channel ‘B’ Positive Analog Input. For single-ended operation, connect signal source to INB+.

12 CLK Converter Clock Input

17 T/B

T/B selects the ADC digital output format.

High: Two’s complement.

Low: Straight offset binary.

18 SLEEP

Sleep Mode Input.

High: Deactivates the two ADCs, but leaves the reference bias circuit active.

Low: Normal operation.

19 PD

Power-Down Input.

High: Power-down mode.

Low: Normal operation.

20 OE

Output Enable Input.

High: Digital outputs disabled.

Low: Digital outputs enabled.

21 D9B Three-State Digital Output, Bit 9 (MSB), Channel B

22 D8B Three-State Digital Output, Bit 8, Channel B

23 D7B Three-State Digital Output, Bit 7, Channel B

24 D6B Three-State Digital Output, Bit 6, Channel B

25 D5B Three-State Digital Output, Bit 5, Channel B

26 D4B Three-State Digital Output, Bit 4, Channel B

27 D3B Three-State Digital Output, Bit 3, Channel B

28 D2B Three-State Digital Output, Bit 2, Channel B

29 D1B Three-State Digital Output, Bit 1, Channel B

30 D0B Three-State Digital Output, Bit 0 (LSB), Channel B

31, 34 OGND Output Driver Ground

32, 33 OVDD

Output Driver Supply Voltage. Bypass each supply pin to OGND with a 0.1µF capacitor. The

digital supply voltage accepts a 1.7V to 3.6V input range.

35 D0A Three-State Digital Output, Bit 0 (LSB), Channel A

36 D1A Three-State Digital Output, Bit 1, Channel A

37 D2A Three-State Digital Output, Bit 2, Channel A

38 D3A Three-State Digital Output, Bit 3, Channel A

39 D4A Three-State Digital Output, Bit 4, Channel A

MAX1181

Detailed Description

The MAX1181 uses a nine-stage, fully-differential

pipelined architecture (Figure 1), that allows for high-

speed conversion while minimizing power consump-

tion. Samples taken at the inputs move progressively

through the pipeline stages every half clock cycle.

Counting the delay through the output latch, the clock-

cycle latency is five clock cycles.

1.5-bit (two-comparator) flash ADCs convert the held-

input voltages into a digital code. The digital-to-analog

converters (DACs) convert the digitized results back

into analog voltages, which are then subtracted from

the original held-input signals. The resulting error sig-

nals are then multiplied by two, and the residues are

passed along to the next pipeline stages where the

process is repeated until the signals have been

processed by all nine stages. Digital error correction

compensates for ADC comparator offsets in each of

these pipeline stages and ensures no missing codes.

Input Track-and-Hold (T/H) Circuits

Figure 2 displays a simplified functional diagram of the

input track-and-hold (T/H) circuits in both track-and-

hold mode. In track mode, switches S1, S2a, S2b, S4a,

S4b, S5a and S5b are closed. The fully-differential cir-

cuits sample the input signals onto the two capacitors

(C2a and C2b) through switches S4a and S4b. S2a and

S2b set the common mode for the amplifier input, and

open simultaneously with S1, sampling the input wave-

form. Switches S4a and S4b are then opened before

switches S3a and S3b connect capacitors C1a and

C1b to the output of the amplifier and switch S4c is

closed. The resulting differential voltages are held on

capacitors C2a and C2b. The amplifiers are used to

charge capacitors C1a and C1b to the same values

originally held on C2a and C2b. These values are then

presented to the first-stage quantizers and isolate the

pipelines from the fast-changing inputs. The wide input

bandwidth T/H amplifiers allow the MAX1181 to track

and sample/hold analog inputs of high frequencies

(> Nyquist). Both ADC inputs (INA+, INB+, INA-, and

INB-) can be driven either differentially or single-ended.

Match the impedance of INA+ and INA-, as well as

INB+ and INB-, and set the common-mode voltage to

midsupply (VDD / 2) for optimum performance.

Analog Inputs and Reference

Configurations

The full-scale range of the MAX1181 is determined by

the internally generated voltage difference between

REFP (VDD / 2 + VREFIN / 4) and REFN (VDD / 2 -

VREFIN / 4). The full-scale range for both on-chip ADCs is

adjustable through the REFIN pin, which is provided for

this purpose.

REFOUT, REFP, COM (VDD / 2) and REFN are internally

buffered low-impedance outputs.

The MAX1181 provides three modes of reference

operation:

• Internal reference mode

• Buffered external reference mode

• Unbuffered external reference mode

In the internal reference mode, connect the internal ref-

erence output REFOUT to REFIN through a resistor

(e.g., 10kΩ) or resistor divider, if an application

requires a reduced full-scale range.

Dual 10-Bit, 80Msps, 3V, Low-Power ADC

with Internal Reference and Parallel Outputs

10 ______________________________________________________________________________________

Pin Description (continued)

PIN NAME FUNCTION

40 D5A Three-State Digital Output, Bit 5, Channel A

41 D6A Three-State Digital Output, Bit 6, Channel A

42 D7A Three-State Digital Output, Bit 7, Channel A

43 D8A Three-State Digital Output, Bit 8, Channel A

44 D9A Three-State Digital Output, Bit 9 (MSB), Channel A

REFOUT

Internal Reference Voltage Output. May be connected to REFIN through a resistor or a resistor

divider.

46 REFIN Reference Input. VREFIN = 2 x (VREFP - VREFN). Bypass to GND with a > 1nF capacitor.

47 REFP Positive Reference Input/Output. Conversion range is ±(VREFP - VREFN). Bypass to GND

with a > 0.1µF capacitor.

48 REFN Negative Reference Input/Output. Conversion range is ±(VREFP - VREFN). Bypass to GND

with a > 0.1µF capacitor.

— EP Exposed Paddle. Connect to analog ground.

For stability and noise filtering purposes, bypass REFIN

with a > 10nF capacitor to GND. In internal reference

mode, REFOUT, COM, REFP, and REFN become low-

impedance outputs.

In the buffered external reference mode, adjust the ref-

erence voltage levels externally by applying a stable

and accurate voltage at REFIN. In this mode, COM,

REFP, and REFN become outputs. REFOUT may be left

open or connected to REFIN through a > 10kΩresistor.

In the unbuffered external reference mode, connect

REFIN to GND. This deactivates the on-chip reference

buffers for REFP, COM, and REFN. With their buffers

shut down, these nodes become high impedance and

may be driven through separate external reference

sources.

Clock Input (CLK)

The MAX1181’s CLK input accepts CMOS-compatible

clock signals. Since the interstage conversion of the

device depends on the repeatability of the rising and

falling edges of the external clock, use a clock with low

jitter and fast rise and fall times (< 2ns). In particular,

sampling occurs on the rising edge of the clock signal,

requiring this edge to provide lowest possible jitter. Any

significant aperture jitter would limit the SNR perfor-

mance of the on-chip ADCs as follows:

SNR = 20 ✕log10 (1 / [2πx fIN ✕tAJ]),

where fIN represents the analog input frequency and

tAJ is the time of the aperture jitter.

Clock jitter is especially critical for undersampling

applications. The clock input should always be consid-

ered as an analog input and routed away from any ana-

log input or other digital signal lines.

The MAX1181 clock input operates with a voltage thresh-

old set to VDD / 2. Clock inputs with a duty cycle other

than 50% must meet the specifications for high and low

periods as stated in the Electrical Characteristics table.

System Timing Requirements

Figure 3 depicts the relationship between the clock

input, analog input, and data output. The MAX1181

samples at the rising edge of the input clock. Output

data for channels A and B is valid on the next rising

edge of the input clock. The output data has an internal

latency of five clock cycles. Figure 4 also determines

the relationship between the input clock parameters

and the valid output data on channels A and B.

Digital Output Data, Output Data Format

Selection (T/B), Output Enable (

)

All digital outputs, D0A–D9A (Channel A) and D0B–D9B

(Channel B), are TTL/CMOS logic-compatible. There is a

MAX1181

Dual 10-Bit, 80Msps, 3V, Low-Power ADC

with Internal Reference and Parallel Outputs

______________________________________________________________________________________ 11

T/H VOUT

FLASH

ADC DAC

1.5 BITS

VINA

VIN

STAGE 1 STAGE 2

D9A–D0A

VINA = INPUT VOLTAGE BETWEEN INA+ AND INA- (DIFFERENTIAL OR SINGLE-ENDED)

VINB = INPUT VOLTAGE BETWEEN INB+ AND INB- (DIFFERENTIAL OR SINGLE-ENDED)

DIGITAL CORRECTION LOGIC

STAGE 8 STAGE 9

2-BIT FLASH

ADC

T/H

T/H VOUT

FLASH

ADC DAC

1.5 BITS

VINB

VIN

STAGE 1 STAGE 2

D9B–D0B

DIGITAL CORRECTION LOGIC

STAGE 8 STAGE 9

2-BIT FLASH

ADC

T/H

Figure 1. Pipelined Architecture––Stage Blocks

MAX1181

five clock cycle latency between any particular sample

and its corresponding output data. The output coding

can be chosen to be either straight offset binary or two’s

complement (Table 1) controlled by a single pin (T/B).

Pull T/B low to select offset binary and high to activate

two’s complement output coding. The capacitive load

on the digital outputs D0A–D9A and D0B–D9B should

be kept as low as possible (< 15pF), to avoid large digi-

tal currents that could feed back into the analog portion

of the MAX1181, thereby degrading its dynamic perfor-

mance. Using buffers on the digital outputs of the ADCs

can further isolate the digital outputs from heavy capaci-

tive loads. To further improve the dynamic performance

Dual 10-Bit, 80Msps, 3V, Low-Power ADC

with Internal Reference and Parallel Outputs

12 ______________________________________________________________________________________

S3b

S3a

COM

S5b

S5a

INB+

INB-

OUT

C2a

C2b

S4c

S4a

S4b

C1b

C1a

INTERNAL

BIAS

INTERNAL

BIAS

COM

HOLD HOLD CLK

INTERNAL

NONOVERLAPPING

CLOCK SIGNALS

TRACK TRACK

S2a

S2b

S3b

S3a

COM

S5b

S5a

INA+

INA-

OUT

C2a

C2b

S4c

S4a

S4b

C1b

C1a

INTERNAL

BIAS

INTERNAL

BIAS

COM

S2a

S2b

MAX1181

Figure 2. MAX1181 T/H Amplifiers

______________________________________________________________________________________________________ 13

of the MAX1181 small-series resistors (e.g., 100Ω), add

to the digital output paths, close to the MAX1181.

Figure 4 displays the timing relationship between out-

put enable and data output valid, as well as power-

down/wake-up and data output valid.

Power-Down (PD) and Sleep

(SLEEP) Modes

The MAX1181 offers two power-save modes; sleep and

full power-down mode. In sleep mode (SLEEP = 1),

only the reference bias circuit is active (both ADCs are

disabled) and current consumption is reduced to

2.8mA.

To enter full power-down mode, pull PD high. With OE

simultaneously low, all outputs are latched at the last

value prior to the power-down. Pulling OE high, forces

the digital outputs into a high-impedance state.

Applications Information

Figure 5 depicts a typical application circuit containing

two single-ended to differential converters. The internal

reference provides a VDD / 2 output voltage for level-

shifting purposes. The input is buffered and then split

to a voltage follower and inverter. One lowpass filter per

ADC suppresses some of the wideband noise associat-

ed with high-speed operational amplifiers. The user

may select the RISO and CIN values to optimize the fil-

ter performance to suit a particular application. For the

application in Figure 5, a RISO of 50Ωis placed before

the capacitive load to prevent ringing and oscillation.

MAX1181

Dual 10-Bit, 80Msps, 3V, Low-Power ADC

with Internal Reference and Parallel Outputs

DIFFERENTIAL INPUT

VOLTAGE* DIFFERENTIAL INPUT

STRAIGHT OFFSET

BINARY

T/B = 0

TWO’S COMPLEMENT

T/B = 1

VREF ✕ 511/512 +FULL SCALE - 1LSB 11 1111 1111 01 1111 1111

VREF ✕ 1/512 + 1 LSB 10 0000 0001 00 0000 0001

0 Bipolar Zero 10 0000 0000 00 0000 0000

-VREF ✕ 1/512 - 1 LSB 01 1111 1111 11 1111 1111

-VREF ✕ 511/512 - FULL SCALE + 1 LSB 00 0000 0001 10 0000 0001

-VREF ✕ 512/512 - FULL SCALE 00 0000 0000 10 0000 0000

Table 1. MAX1181 Output Codes For Differential Inputs

N - 6

N - 5

N + 1

N - 4

N + 2

N - 3

N + 3

N - 2

N + 4

N - 1

N + 5

N + 6

N + 1

5 CLOCK-CYCLE LATENCY

ANALOG INPUT

CLOCK INPUT

DATA OUTPUT

D9A–D0A

tD0 tCH tCL

N - 6 N - 5 N - 4 N - 3 N - 2 N - 1 N N + 1

DATA OUTPUT

D9B–D0B

tCLK

Figure 3. System Timing Diagram

*VREF = VREFP - VREFN

MAX1181

Dual 10-Bit, 80Msps, 3V, Low-Power ADC

with Internal Reference and Parallel Outputs

14 ______________________________________________________________________________________

The 22pF CIN capacitor acts as a small bypassing

capacitor.

Using Transformer Coupling

An RF transformer (Figure 6) provides an excellent

solution to convert a single-ended source signal to a

fully-differential signal, required by the MAX1181 for

optimum performance. Connecting the center tap of the

transformer to COM provides a VDD / 2 DC level shift to

the input. Although a 1:1 transformer is shown, a step-

up transformer may be selected to reduce the drive

requirements. A reduced signal swing from the input

driver, such as an op amp, may also improve the over-

all distortion.

In general, the MAX1181 provides better SFDR and

THD with fully-differential input signals, than a single-

ended drive, especially for high input frequencies. In

differential input mode, even-order harmonics are lower

as both inputs (INA+, INA- and/or INB+, INB-) are bal-

anced, and each of the ADC inputs only require half the

signal swing compared to single-ended mode.

Single-Ended AC-Coupled Input Signal

Figure 7 shows an AC-coupled, single-ended applica-

tion. Amplifiers, like the MAX4108, provide high-speed,

high bandwidth, low-noise, and low distortion to main-

tain the integrity of the input signal.

Typical QAM Demodulation Application

The most frequently used modulation technique for digi-

tal communications application is the Quadrature

Amplitude Modulation (QAM). QAMs are typically found

in spread-spectrum based systems. A QAM signal rep-

resents a carrier frequency modulated in both amplitude

and phase. At the transmitter, modulating the baseband

signal with quadrature outputs, a local oscillator fol-

lowed by subsequent up-conversion can generate the

QAM signal. The result is an in-phase (I) and a quadra-

ture (Q) carrier component, where the Q component is

90 degrees phase-shifted with respect to the in-phase

component. At the receiver, the QAM signal is divided

down into its I and Q components, essentially represent-

ing the modulation process reversed. Figure 8 displays

the demodulation process performed in the analog

domain, using the dual-matched, 3V, 10-bit ADCs,

MAX1181 and the MAX2451 quadrature demodulators,

to recover and digitize the I and Q baseband signals.

Before being digitized by the MAX1181, the mixed-down

signal components may be filtered by matched analog

filters, such as Nyquist or pulse-shaping filters which

remove any unwanted images from the mixing process,

enhances the overall signal-to-noise (SNR) perfor-

mance, and minimizes intersymbol interference.

Grounding, Bypassing,

and Board Layout

The MAX1181 requires high-speed board layout design

techniques. Locate all bypass capacitors as close to

the device as possible, preferably on the same side as

the ADC, using surface-mount devices for minimum

inductance. Bypass VDD, REFP, REFN, and COM with

two parallel 0.1µF ceramic capacitors and a 2.2µF

bipolar capacitor to GND. Follow the same rules to

bypass the digital supply (OVDD) to OGND. Multilayer

boards with separate ground and power planes, pro-

duce the highest level of signal integrity. Consider the

use of a split ground plane arranged to match the phys-

ical location of the analog ground (GND) and the digital

output driver ground (OGND) on the ADCs package.

The two ground planes should be joined at a single

point, such that the noisy digital ground currents do not

interfere with the analog ground plane. The ideal loca-

tion of this connection can be determined experimental-

ly at a point along the gap between the two ground

planes, which produces optimum results. Make this

connection with a low-value, surface-mount resistor (1Ω

to 5Ω), a ferrite bead, or a direct short. Alternatively, all

ground pins could share the same ground plane, if the

ground plane is sufficiently isolated from any noisy, dig-

ital systems ground plane (e.g., downstream output

buffer or DSP ground plane). Route high-speed digital

signal traces away from the sensitive analog traces of

either channel. Make sure to isolate the analog input

lines to each respective converter to minimize channel-

to-channel crosstalk. Keep all signal lines short and

free of 90 degree turns.

OUTPUT

D9A–D0A

tDISABLE

tENABLE

HIGH IMPEDANCEHIGH IMPEDANCE VALID DATA

OUTPUT

D9B–D0B

HIGH IMPEDANCEHIGH IMPEDANCE VALID DATA

Figure 4. Output Timing Diagram

MAX1181

Dual 10-Bit, 80Msps, 3V, Low-Power ADC

with Internal Reference and Parallel Outputs

______________________________________________________________________________________ 15

INPUT

300Ω

-5V

+5V

0.1μF

-5V

600Ω

300Ω

INA+

INA-

LOWPASS FILTER

COM

600Ω

+5V

-5V

0.1μF

600Ω

300Ω

600Ω

300Ω

0.1μF

+5V

0.1μF

300Ω

MAX4108

MAX1181

INB+

INB-

MAX4108

LOWPASS FILTER

INPUT

300Ω

-5V

+5V

0.1μF

CIN

22pF

-5V

600Ω

300Ω

LOWPASS FILTER

600Ω

+5V

-5V

0.1μF

600Ω

300Ω

600Ω

300Ω

0.1μF

+5V

0.1μF

300Ω

MAX4108

LOWPASS FILTER

RISO

50ΩCIN

22pF

RISO

50ΩCIN

22pF

RISO

50ΩCIN

22pF

RISO

50Ω

Figure 5. Typical Application for Single-Ended-to-Differential Conversion

MAX1181

Dual 10-Bit, 80Msps, 3V, Low-Power ADC

with Internal Reference and Parallel Outputs

16 ______________________________________________________________________________________

Static Parameter Definitions

Integral Nonlinearity (INL)

Integral nonlinearity is the deviation of the values on an

actual transfer function from a straight line. This straight

line can be either a best straight-line fit or a line drawn

between the endpoints of the transfer function, once

offset and gain errors have been nullified. The static lin-

earity parameters for the MAX1181 are measured using

the best straight-line fit method.

Differential Nonlinearity (DNL)

Differential nonlinearity is the difference between an

actual step-width and the ideal value of 1LSB. A DNL

error specification of less than 1LSB guarantees no

missing codes and a monotonic transfer function.

Dynamic Parameter Definitions

Aperture Jitter

Figure 9 depicts the aperture jitter (tAJ), which is the

sample-to-sample variation in the aperture delay.

Aperture Delay

Aperture delay (tAD) is the time defined between the

falling edge of the sampling clock and the instant when

an actual sample is taken (Figure 9).

Signal-to-Noise Ratio (SNR)

For a waveform perfectly reconstructed from digital

samples, the theoretical maximum SNR is the ratio of

the full-scale analog input (RMS value) to the RMS

quantization error (residual error).

The ideal, theoretical minimum analog-to-digital noise is

caused by quantization error only and results directly

from the ADC’s resolution (N-Bits):

SNR[max] = 6.02 ✕N + 1.76

In reality, there are other noise sources besides quanti-

zation noise; thermal noise, reference noise, clock jitter,

etc. SNR is computed by taking the ratio of the RMS

signal to the RMS noise, which includes all spectral

components minus the fundamental, the first five har-

monics, and the DC offset.

Signal-to-Noise Plus Distortion (SINAD)

SINAD is computed by taking the ratio of the RMS sig-

nal to all spectral components minus the fundamental

and the DC offset.

Effective Number of Bits (ENOB)

ENOB specifies the dynamic performance of an ADC at

a specific input frequency and sampling rate. An ideal

ADC’s error consists of quantization noise only. ENOB

is computed from:

Total Harmonic Distortion (THD)

THD is typically the ratio of the RMS sum of the first four

harmonics of the input signal to the fundamental itself.

This is expressed as:

THD VVVV

=× +++

⎛

⎝

⎜

⎞

⎠

⎟

20 10

2222

2345

log

ENOB SINAD

=−176

602

MAX1181

N.C.

VIN 6

22pF

0.1μF

2.2μF

25Ω

MINI-CIRCUITS

TT1–6

N.C.

VIN 6

22pF

0.1μF

2.2μF

25Ω

MINI-CIRCUITS

TT1–6

INA-

INA+

INB-

INB+

COM

Figure 6. Transformer-Coupled Input Drive

MAX1181

Dual 10-Bit, 80Msps, 3V, Low-Power ADC

with Internal Reference and Parallel Outputs

______________________________________________________________________________________ 17

MAX1181

0.1μF

1kΩ

100Ω

CIN

22pF

CIN

22pF

INB+

INB-

COM

INA+

INA-

0.1μFRISO

50Ω

RISO

50Ω

REFP

REFN

VIN

MAX4108

0.1μF

1kΩ

100Ω

CIN

22pF

CIN

22pF

0.1μFRISO

50Ω

RISO

50Ω

REFP

REFN

VIN

MAX4108

Figure 7. Using an Op Amp for Single-Ended, AC-Coupled Input Drive

0°

90°

÷8

DOWNCONVERTER

MAX2451 INA+

MAX1181

INA-

INB+

INB-

DSP POST

PROCESSING

Figure 8. Typical QAM Application, Using the MAX1181

MAX1181

Dual 10-Bit, 80Msps, 3V, Low-Power ADC

with Internal Reference and Parallel Outputs

18 ______________________________________________________________________________________

GND

REFERENCE

OUTPUT

DRIVERS

CONTROL

T/H

T/H PIPELINE

ADC DEC OUTPUT

DRIVERS

REFOUT

REFN COM REFP REFIN

INA+

INA-

CLK

INB+

INB-

VDD

DEC

PIPELINE

ADC

OGND

OVDD

D9A–D0A

D9B–D0B

T/B

SLEEP

MAX1181

10 10

Functional Diagram

where V1is the fundamental amplitude, and V2through

V5are the amplitudes of the 2nd- through 5th-order

harmonics.

Spurious-Free Dynamic Range (SFDR)

SFDR is the ratio expressed in decibels of the RMS

amplitude of the fundamental (maximum signal compo-

nent) to the RMS value of the next largest spurious

component, excluding DC offset.

Intermodulation Distortion (IMD)

The two-tone IMD is the ratio expressed in decibels of

either input tone to the worst 3rd-order (or higher) inter-

modulation products. The individual input tone levels

are at -6.5dB full scale.

HOLD

ANALOG

INPUT

SAMPLED

DATA (T/H)

T/H

tAD

tAJ

TRACK TRACK

CLK

Figure 9. T/H Aperture Timing

MAX1181

Dual 10-Bit, 80Msps, 3V, Low-Power ADC

with Internal Reference and Parallel Outputs

______________________________________________________________________________________ 19

Package Information

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,

go to www.maxim-ic.com/packages.)

48L,TQFP.EPS

21-0065

PACKAGE OUTLINE,

48L TQFP, 7x7x1.0mm EP OPTION

MAX1181

Dual 10-Bit, 80Msps, 3V, Low-Power ADC

with Internal Reference and Parallel Outputs

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

G22

21-0065

PACKAGE OUTLINE,

48L TQFP, 7x7x1.0mm EP OPTION

Package Information (continued)

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,

go to www.maxim-ic.com/packages.)

Revision History

Pages changed at Rev 1: 1–19