NM27C010Q120 - National Semiconductor

TL/D/10798

NM27C010 1,048,576-Bit (128K x 8) High Performance CMOS EPROM

January 1994

NM27C010

1,048,576-Bit (128K x 8) High Performance CMOS EPROM

General Description

The NM27C010 is a high performance, 1,048,576-bit Electri-

cally Programmable UV Erasable Read Only Memory. It is

organized as 128K-words of 8 bits each. Its pin-compatibility

with byte-wide JEDEC EPROMs enables upgrades through

8 Mbit EPROMs. The ‘‘Don’t Care’’ feature during read op-

erations allows memory expansions from 1M to 8M bits with

no printed circuit board changes.

The NM27C010 can directly replace lower density 28-pin

EPROMs by adding an A16 address line and VCC jumper.

During the normal read operation PGM and VPP are in a

‘‘Don’t Care’’ state which allows higher order addresses,

such as A17, A18, and A19 to be connected without affect-

ing the normal read operation. This allows memory up-

grades to 8M bits without hardware changes. The

NM27C010 is also offered in a 32-pin plastic DIP with the

same upgrade path.

The NM27C010 provides microprocessor-based systems

extensive storage capacity for large portions of operating

system and application software. Its 90 ns access time pro-

vides no-wait-state operation with high-performance CPUs.

The NM27C010 offers a single chip solution for the code

storage requirements of 100% firmware-based equipment.

Frequently-used software routines are quickly executed

from EPROM storage, greatly enhancing system utility.

The NM27C010 is manufactured using National’s advanced

CMOS AMGTM EPROM technology.

The NM27C010 is one member of a high density EPROM

Family which range in densities up to 4 Megabit.

Features

YHigh performance CMOS

Ð 90 ns access time

YFast turn-off for microprocessor compatibility

YSimplified upgrade path

ÐV

PP and PGM are ‘‘Don’t Care’’ during normal read

operation

YManufacturers identification code

YFast programming

YJEDEC standard pin configurations

Ð 32-pin DIP package

Ð 32-pin PLCC package

Ð 32-pin TSOP package

Block Diagram

TL/D/10798–1

TRI-STATEÉis a registered trademark of National Semiconductor Corporation.

AMGTM is a trademark of WSI, Inc.

C1995 National Semiconductor Corporation RRD-B30M65/Printed in U. S. A.

Connection Diagrams

DIP PIN CONFIGURATIONS

27C080 27C040 27C020 27C512 27C256

A19 XX/VPP XX/VPP

A16 A16 A16

A15 A15 A15 A15 VPP

A12 A12 A12 A12 A12

A7 A7 A7 A7 A7

A6 A6 A6 A6 A6

A5 A5 A5 A5 A5

A4 A4 A4 A4 A4

A3 A3 A3 A3 A3

A2 A2 A2 A2 A2

A1 A1 A1 A1 A1

A0 A0 A0 A0 A0

O0O0O0O0O0

O1O1O1O1O1

O2O2O2O2O2

GND GND GND GND GND

DIP

NM27C010

TL/D/10798–2

27C256 27C512 27C020 27C040 27C080

VCC VCC VCC

XX/PGM A18 A18

VCC VCC A17 A17 A17

A14 A14 A14 A14 A14

A13 A13 A13 A13 A13

A8 A8 A8 A8 A8

A9 A9 A9 A9 A9

A11 A11 A11 A11 A11

OE OE/VPP OE OE OE/VPP

A10 A10 A10 A10 A10

CE/PGM CE/PGM CE CE/PGM CE/PGM

O7O7O7O7O7

O6O6O6O6O6

O5O5O5O5O5

O4O4O4O4O4

O3O3O3O3O3

Note: Compatible EPROM pin configurations are shown in the blocks adjacent to the NM27C010 pins.

Commercial Temperature Range (0§Ctoa

70§C)

VCC e5V g10%

Parameter/Order Number Access Time (ns)

NM27C010 Q, V, N, T 90 90

NM27C010 Q, V, N, T 120 120

NM27C010 Q, V, N, T 150 150

NM27C010 Q, V, N, T 200 200

Extended Temperature Range (b40§Ctoa

85§C)

VCC e5V g10%

Parameter/Order Number Access Time (ns)

NM27C010 QE, VE, NE 100 100

NM27C010 QE, VE, NE 120 120

NM27C010 QE, VE, NE 150 150

NM27C010 QE, VE, NE 200 200

Military Temperature Range (b55§Ctoa

125§C)

VCC e5V g10%

Parameter/Order Number Access Time (ns)

NM27C010 QM 150 150

NM27C010 QM 200 200

Note: Surface mount PLCC package available for commercial and extended

temperature ranges only.

Package Types: NM27C010 Q, N, V XXX

QeQuartz-Windowed Ceramic DIP package

VePLCC package

NePlastic DIP package

TeTSOP package

#All packages conform to JEDEC standard.

#All versions are guaranteed to function at slower speeds.

Pin Names

A0– A16 Addresses

CE Chip Enable

OE Output Enable

O0– O7 Outputs

PGM Program

XX Don’t Care (During Read)

TSOP Pin Configuration

TL/D/10798–9

PLCC Pin Configuration

TL/D/10798–3

Top View

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales

Office/Distributors for availability and specifications.

Storage Temperature b65§Ctoa

150§C

All Input Voltages Except A9with

Respect to Ground (Note 10) b0.6V to a7V

VPP and A9with Respect to Ground b0.6V to a14V

VCC Supply Voltage with

Respect to Ground b0.6V to a7V

ESD Protection l2000V

All Output Voltages with

Respect to Ground (Note 10) VCC a1.0V to GND b0.6V

Operating Range

Range Temperature VCC Tolerance

Commercial 0§Ctoa

70§Ca5V g10%

Industrial b40§Ctoa

85§Ca5V g10%

Military b55§Ctoa

125§Ca5V g10%

DC Read Characteristics Over Operating Range with VPP eVCC

Symbol Parameter Test Conditions Min Max Units

VIL Input Low Level b0.5 0.8 V

VIH Input High Level 2.0 VCC a1V

OL Output Low Voltage IOL e2.1 mA 0.4 V

VOH Output High Voltage IOH eb

2.5 mA 3.5 V

ISB1 VCC Standby Current CE eVCC g0.3V 100 mA

(CMOS)

ISB2 VCC Standby Current (TTL) CE eVIH 1mA

CC VCC Active Current CE eOE eVIL fe5 MHz 30 mA

I/O e0mA

PP VPP Supply Current VPP eVCC 10 mA

VPP VPP Read Voltage VCC b0.7 VCC V

ILI Input Load Current VIN e5.5 or GND b11mA

LO Output Leakage Current VOUT e5.5V or GND b10 10 mA

AC Read Characteristics Over Operating Range with VPP eVCC

Symbol Parameter 90 120 150 200 Units

Min Max Min Max Min Max Min Max

tACC Address to Output Delay 90 120 150 200

tCE CE to Output Delay 90 120 150 200

tOE OE to Output Delay 40 50 50 50

tDF Output Disable to Output Float 35 35 45 55 ns

(Note 2)

tOH Output Hold from Addresses,

(Note 2) CE or OE, Whichever 0 0 0 0

Occurred First

Capacitance TAea

25§C, f e1 MHz (Note 2)

Symbol Parameter Conditions Typ Max Units

CIN Input Capacitance VIN e0V 6 15 pF

COUT Output Capacitance VOUT e0V 10 15 pF

AC Test Conditions

Output Load 1 TTL Gate and

CLe100 pF (Note 8)

Input Rise and Fall Times s5ns

Input Pulse Levels 0.45V to 2.4V

Timing Measurement Reference Level

Inputs 0.8V and 2V

Outputs 0.8V and 2V

AC Waveforms (Notes 6, 7, & 9)

TL/D/10798–4

Note 1: Stresses above those listed under ‘‘Absolute Maximum Ratings’’ may cause permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

Note 2: This parameter is only sampled and is not 100% tested.

Note 3: OE may be delayed up to tACC btOE after the falling edge of CE without impacting tACC.

Note 4: The tDF and tCF compare level is determined as follows:

High to TRI-STATEÉ, the measured VOH1 (DC) b0.10V;

Low to TRI-STATE, the measured VOL1 (DC) a0.10V.

Note 5: TRI-STATE may be attained using OE or CE.

Note 6: The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.1 mF ceramic capacitor be used on

every device between VCC and GND.

Note 7: The outputs must be restricted to VCC a1.0V to avoid latch-up and device damage.

Note 8: 1 TTL Gate: IOL e1.6 mA, IOH eb

400 mA.

CL: 100 pF includes fixture capacitance.

Note 9: VPP may be connected to VCC except during programming.

Note 10: Inputs and outputs can undershoot to b2.0V for 20 ns Max.

Programming Characteristics (Notes 1, 2, 3, 4, & 5)

Symbol Parameter Conditions Min Typ Max Units

tAS Address Setup Time 1 ms

tOES OE Setup Time 1 ms

tCES CE Setup Time OE eVIH 1ms

tDS Data Setup Time 1 ms

tVPS VPP Setup Time 1 ms

tVCS VCC Setup Time 1 ms

tAH Address Hold Time 0 ms

tDH Data Hold Time 1 ms

tDF Output Enable to Output Float Delay CE eVIL 060ns

PW Program Pulse Width 95 100 105 ms

tOE Data Valid from OE CE eVIL 100 ms

IPP VPP Supply Current during CE eVIL 15 mA

Programming Pulse PGM eVIL

ICC VCC Supply Current 20 mA

TATemperature Ambient 20 25 30 §C

VCC Power Supply Voltage 6.0 6.25 6.5 V

VPP Programming Supply Voltage 12.5 12.75 13.0 V

tFR Input Rise, Fall Time 5 ns

VIL Input Low Voltage 0.0 0.45 V

VIH Input High Voltage 2.4 4.0 V

tIN Input Timing Reference Voltage 0.8 2.0 V

tOUT Output Timing Reference Voltage 0.8 2.0 V

Programming Waveforms (Note 3)

TL/D/10798–5

Note 1: National’s standard product warranty applies only to devices programmed to specifications described herein.

Note 2: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. The EPROM must not be inserted into or removed from a

board with voltage applied to VPP or VCC.

Note 3: The maximum absolute allowable voltage which may be applied to the VPP pin during programming is 14V. Care must be taken when switching the VPP

supply to prevent any overshoot from exceeding this 14V maximum specification. At least a 0.1 mF capacitor is required across VPP,V

CC to GND to suppress

spurious voltage transients which may damage the device.

Note 4: Programming and program verify are tested with the fast Program Algorithm, at typical power supply voltages and timings.

Note 5: During power up the PGM pin must be brought high (tVIH) either coincident with or before power is applied to VPP.

Fast Programming Algorithm Flow Chart (Same as NMC27C010)

TL/D/10798–6

FIGURE 1

Functional Description

DEVICE OPERATION

The six modes of operation of the EPROM are listed in Ta-

ble I. It should be noted that all inputs for the six modes are

at TTL levels. The power supplies required are VCC and

VPP. The VPP power supply must be at 12.75V during the

three programming modes, and must be at 5V in the other

three modes. The VCC power supply must be at 6.25V dur-

ing the three programming modes, and at 5V in the other

three modes.

Read Mode

The EPROM has two control functions, both of which must

be logically active in order to obtain data at the outputs.

Chip Enable (CE) is the power control and should be used

for device selection. Output Enable (OE) is the output con-

trol and should be used to gate data to the output pins,

independent of device selection. Assuming that the ad-

dresses are stable, address access time (tACC) is equal to

the delay from CE to output (tCE). Data is available at the

outputs tOE after the falling edge of OE, assuming that CE

has been low and addresses have been stable for at least

tACC–tOE.

Standby Mode

The EPROM has a standby mode which reduces the active

power dissipation by over 99%, from 165 mW to 0.55 mW.

The EPROM is placed in the standby mode by applying a

CMOS high signal to the CE input. When in standby mode,

the outputs are in a high impedance state, independent of

the OE input.

Output Disable

The EPROM is placed in output disable by applying a TTL

high signal to the OE input. When in output disable all cir-

cuitry is enabled, except the outputs are in a high imped-

ance state (TRI-STATE).

Output OR-Tying

Because the EPROM is usually used in larger memory ar-

rays, National has provided a 2-line control function that

accommodates this use of multiple memory connections.

The 2-line control function allows for:

a) the lowest possible memory power dissipation, and

b) complete assurance that output bus contention will not

occur.

To most efficiently use these two control lines, it is recom-

mended that CE be decoded and used as the primary de-

vice selecting function, while OE be made a common con-

nection to all devices in the array and connected to the

READ line from the system control bus. This assures that all

deselected memory devices are in their low power standby

modes and that the output pins are active only when data is

desired from a particular memory device.

Programming

CAUTION: Exceeding 14V on the VPP or A9 pin will damage

the EPROM.

Initially, and after each erasure, all bits of the EPROM are in

the ‘‘1’s’’ state. Data is introduced by selectively program-

ming ‘‘0’s’’ into the desired bit locations. Although only

‘‘0’s’’ will be programmed, both ‘‘1’s’’ and ‘‘0’s’’ can be pre-

sented in the data word. The only way to change a ‘‘0’’ to a

‘‘1’’ is by ultraviolet light erasure.

The EPROM is in the programming mode when the VPP

power supply is at 12.75V and OE is at VIH. It is required

that at least a 0.1 mF capacitor be placed across VPP,V

to ground to suppress spurious voltage transients which

may damage the device. The data to be programmed is

applied 8 bits in parallel to the data output pins. The levels

required for the address and data inputs are TTL.

When the address and data are stable, an active low, TTL

program pulse is applied to the PGM input. A program pulse

must be applied at each address location to be pro-

grammed. The EPROM is programmed with the Fast Pro-

gramming Algorithm shown in

Figure 1

. Each Address is

programmed with a series of 100 ms pulses until it verifies

good, up to a maximum of 25 pulses. Most memory cells will

program with a single 100 ms pulse.

The EPROM must not be programmed with a DC signal ap-

plied to the PGM input.

Programming multiple EPROM in parallel with the same

data can be easily accomplished due to the simplicity of the

programming requirements. Like inputs of the parallel

EPROM may be connected together when they are pro-

grammed with the same data. A low level TTL pulse applied

to the PGM input programs the paralleled EPROM.

Program Inhibit

Programming multiple EPROM’s in parallel with different

data is also easily accomplished. Except for CE all like in-

puts (including OE and PGM) of the parallel EPROM may be

common. A TTL low level program pulse applied to an

EPROM’s PGM input with CE at VIL and VPP at 12.75V will

program that EPROM. A TTL high level CE input inhibits the

other EPROM’s from being programmed.

Program Verify

A verify should be performed on the programmed bits to

determine whether they were correctly programmed. The

verify may be performed with VPP at 12.75V. VPP must be at

VCC, except during programming and program verify.

AFTER PROGRAMMING

Opaque labels should be placed over the EPROM window

to prevent unintentional erasure. Covering the window will

also prevent temporary functional failure due to the genera-

tion of photo currents.

MANUFACTURER’S IDENTIFICATION CODE

The EPROM has a manufacturer’s indentification code to

aid in programming. When the device is inserted in an

EPROM programmer socket, the programmer reads the

code and then automatically calls up the specific program-

ming algorithm for the part. This automatic programming

control is only possible with programmers which have the

capability of reading the code.

The Manufacturer’s Identification code, shown in Table II,

specifically identifies the manufacturer and device type. The

code for the NM27C010 is ‘‘8F86’’, where ‘‘8F’’ designates

that it is made by National Semiconductor, and ‘‘86’’ desig-

nates a 1 Megabit (128K c8) part.

The code is accessed by applying 12V g0.5V to address

pin A9. Addresses A1– A8, A10– A16, and all control pins

are held at VIL. Address pin A0 is held at VIL for the manu-

facturer’s code, and held at VIH for the device code. The

code is read on the eight data pins, O0– 07. Proper code

access is only guaranteed at 25§Cg5§C.

Functional Description (Continued)

ERASURE CHARACTERISTICS

The erasure characteristics of the device are such that era-

sure begins to occur when exposed to light with wave-

lengths shorter than approximately 4000 Angstroms (Ð). It

should be noted that sunlight and certain types of fluores-

cent lamps have wavelengths in the 3000Ð–4000Ðrange.

The recommended erasure procedure for the EPROM is ex-

posure to short wave ultraviolet light which has a wave-

length of 2537Ð. The integrated dose (i.e., UV intensity X

exposure time) for erasure should be a minimum of 15W-

sec/cm2.

The EPROM should be placed within 1 inch of the lamp

tubes during erasure. Some lamps have a filter on their

tubes which should be removed before erasure.

An erasure system should be calibrated periodically. The

distance from lamp to device should be maintained at one

inch. The erasure time increases as the square of the dis-

tance from the lamp. (if distance is doubled the erasure time

increases by factor of 4). Lamps lose intensity as they age.

When a lamp is changed, the distance has changed, or the

lamp has aged, the system should be checked to make cer-

tain full erasure is occurring. Incomplete erasure will cause

symptoms that can be misleading. Programmers, compo-

nents and even system designs have been erroneously sus-

pected when incomplete erasure was the problem.

SYSTEM CONSIDERATION

The power switching characteristics of EPROMs require

careful decoupling of the devices. The supply current, ICC,

has three segments that are of interest to the system de-

signer: the standby current level, the active current level,

and the transient current peaks that are produced by volt-

age transitions on input pins. The magnitude of these tran-

sient current peaks is dependent on the output capacitance

loading of the device. The associated VCC transient voltage

peaks can be suppressed by properly selected decoupling

capacitors. It is recommended that at least a 0.1 mF ceramic

capacitor be used on every device between VCC and GND.

This should be a high frequency capacitor of low inherent

inductance. In addition, at least a 4.7 mF bulk electrolytic

capacitor should be used between VCC and GND for each

eight devices. The bulk capacitor should be located near

where the power supply is connected to the array. The pur-

pose of the bulk capacitor is to overcome the voltage drop

caused by the inductive effects of the PC board traces.

MODE SELECTION

The modes of operation of the NM27C010 are listed in Table I. A single 5V power supply is required in the read mode. All inputs

are TTL levels except for VPP and A9 for device signature.

TABLE I. Modes Selection

Pins CE OE PGM VPP VCC Outputs

Mode

Read VIL VIL

XX 5.0V DOUT

(Note 1)

Output Disable X VIH X X 5.0V High Z

Standby VIH X X X 5.0V High Z

Programming VIL VIH VIL 12.75V 6.25V DIN

Program Verify VIL VIL VIH 12.75V 6.25V DOUT

Program Inhibit VIH X X 12.75V 6.25V High Z

Note 1: X can be VIL or VIH.

TABLE II. Manufacturer’s Identification Code

Pins A0 A9 O7O6O5O4O3O2O1O0Hex

(12) (26) (21) (20) (19) (18) (17) (15) (14) (13) Data

Manufacturer Code VIL 12V100011118F

Device Code VIH 12V1000011086

Physical Dimensions inches (millimeters)

32-Lead EPROM Ceramic Dual-In-Line Package (Q)

Order Number NM27C010QXXX

NS Package Number J32AQ

Physical Dimensions millimeters (Continued)

32-Lead TSOP, EIAJ Type I (T)

Order Number NM27C010TXXX

NS Package Number MBH32A

NM27C010 1,048,576-Bit (128K x 8) High Performance CMOS EPROM

Physical Dimensions inches (millimeters) (Continued)

32-Lead PLCC Package

Order Number NM27C010VXXX

NS Package Number VA32A

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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL

SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or 2. A critical component is any component of a life

systems which, (a) are intended for surgical implant support device or system whose failure to perform can

into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life

failure to perform, when properly used in accordance support device or system, or to affect its safety or

with instructions for use provided in the labeling, can effectiveness.

be reasonably expected to result in a significant injury

to the user.

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