© Semiconductor Components Industries, LLC, 2011
June, 2011 − Rev. 12
1Publication Order Number:
MC14541B/D
MC14541B
Programmable Timer
The MC14541B programmable timer consists of a 16−stage binary
counter, an integrated oscillator for use with an external capacitor and
two resistors, an automatic power−on reset circuit, and output control
logic.
Timing is initialized by turning on power, whereupon the power−on
reset is enabled and initializes the counter, within the specified VDD
range. With the power already on, an external reset pulse can be
applied. Upon release of the initial reset command, the oscillator will
oscillate with a frequency determined by the external RC network. The
16−stage counter divides the oscillator frequency (fosc) with the nth
stage frequency being fosc/2n.
Features
•Available Outputs 28, 210, 213 or 216
•Increments on Positive Edge Clock Transitions
•Built−in Low Power RC Oscillator (± 2% accuracy over temperature
range and ± 20% supply and ± 3% over processing at < 10 kHz)
•Oscillator May Be Bypassed if External Clock Is Available
(Apply external clock to Pin 3)
•External Master Reset Totally Independent of Automatic Reset
Operation
•Operates as 2n Frequency Divider or Single Transition Timer
•Q/Q Select Provides Output Logic Level Flexibility
•Reset (auto or master) Disables Oscillator During Resetting to
Provide No Active Power Dissipation
•Clock Conditioning Circuit Permits Operation with Very Slow Clock
Rise and Fall Times
•Automatic Reset Initializes All Counters On Power Up
•Supply Voltage Range = 3.0 Vdc to 18 Vdc with Auto Reset
Supply Voltage Range = Disabled (Pin 5 = VDD)
Supply Voltage Range = 8.5 Vdc to 18 Vdc with Auto Reset
Supply Voltage Range = Enabled (Pin 5 = VSS)
•These Devices are Pb−Free and are RoHS Compliant
PIN ASSIGNMENT
NC = NO CONNECTION
11
12
13
14
8
9
105
4
3
2
1
7
6
MODE
NC
A
B
VDD
Q
Q/Q SEL
NC
RS
Ctc
Rtc
VSS
MR
AR
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MARKING
DIAGRAMS
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G= Pb−Free Package
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
ORDERING INFORMATION
1
14
PDIP−14
P SUFFIX
CASE 646
MC14541BCP
AWLYYWWG
SOIC−14
D SUFFIX
CASE 751A
TSSOP−14
DT SUFFIX
CASE 948G
1
14
14541BG
AWLYWW
14
541B
ALYWG
G
1
14
SOEIAJ−14
F SUFFIX
CASE 965
1
14
MC14541B
ALYWG
(Note: Microdot may be in either location)
MC14541B
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2
MAXIMUM RATINGS (Voltages Referenced to VSS)
Symbol Parameter Value Unit
VDD DC Supply Voltage Range −0.5 to +18.0 V
Vin, Vout Input or Output Voltage Range, (DC or Transient) −0.5 to VDD + 0.5 V
Iin Input Current (DC or Transient) ±10 (per Pin) mA
Iout Output Current (DC or Transient) ±45 (per Pin) mA
PDPower Dissipation, per Package (Note 1) 500 mW
TAAmbient Temperature Range −55 to +125 °C
Tstg Storage Temperature Range −65 to +150 °C
TLLead Temperature, (8−Second Soldering) 260 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
ORDERING INFORMATION
Device Package Shipping†
MC14541BCPG PDIP−14
(Pb−Free) 500 Units / Rail
MC14541BDG SOIC−14
(Pb−Free) 55 Units / Rail
MC14541BDR2G SOIC−14
(Pb−Free) 2500 / Tape & Reel
MC14541BDTR2G TSSOP−14*
MC14541BFG SOEIAJ−14
(Pb−Free) 50 Units / Rail
MC14541BFELG SOEIAJ−14
(Pb−Free) 2000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
MC14541B
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3
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Characteristic Symbol VDD
Vdc
− 55_C 25_C 125_C
Unit
Min Max Min Typ
(Note 2)
Max Min Max
Output Voltage “0” Level
Vin = VDD or 0
VOL 5.0
10
15
−
−
−
0.05
0.05
0.05
−
−
−
0
0
0
0.05
0.05
0.05
−
−
−
0.05
0.05
0.05
Vdc
“1” Level
Vin = 0 or VDD
VOH 5.0
10
15
4.95
9.95
14.95
−
−
−
4.95
9.95
14.95
5.0
10
15
−
−
−
4.95
9.95
14.95
−
−
−
Vdc
Input Voltage “0” Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
5.0
10
15
−
−
−
1.5
3.0
4.0
−
−
−
2.25
4.50
6.75
1.5
3.0
4.0
−
−
−
1.5
3.0
4.0
Vdc
“1” Level
(VO = 0.5 or 4.5 Vdc)
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
VIH
5.0
10
15
3.5
7.0
11
−
−
−
3.5
7.0
11
2.75
5.50
8.25
−
−
−
3.5
7.0
11
−
−
−
Vdc
Output Drive Current
(VOH = 2.5 Vdc) Source
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
IOH
5.0
10
15
– 4.19
– 7.96
– 16.3
−
−
−
– 3.38
– 6.42
– 13.2
– 6.75
– 12.83
– 26.33
−
−
−
– 2.37
– 4.49
− 9.24
−
−
−
mAdc
(VOL = 0.4 Vdc) Sink
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
IOL 5.0
10
15
1.93
4.96
19.3
−
−
−
1.56
4.0
15.6
3.12
8.0
31.2
−
−
−
1.09
2.8
10.9
−
−
−
mAdc
Input Current Iin 15 −± 0.1 −±0.00001 ± 0.1 −± 1.0 mAdc
Input Capacitance
(Vin = 0)
Cin − − − − 5.0 7.5 − − pF
Quiescent Current
(Pin 5 is High)
Auto Reset Disabled
IDD 5.0
10
15
−
−
−
5.0
10
20
−
−
−
0.005
0.010
0.015
5.0
10
20
−
−
−
150
300
600
mAdc
Auto Reset Quiescent Current
(Pin 5 is low)
IDDR 10
15
−
−
250
500
−
−
30
82
250
500
−
−
1500
2000
mAdc
Supply Current (Notes 3 & 4)
(Dynamic plus Quiescent)
ID5.0
10
15
ID = (0.4 mA/kHz) f + IDD
ID = (0.8 mA/kHz) f + IDD
ID = (1.2 mA/kHz) f + IDD
mAdc
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
3. The formulas given are for the typical characteristics only at 25_C.
4. When using the on chip oscillator the total supply current (in mAdc) becomes: IT = ID + 2 Ctc VDD f x 10–3 where ID is in mA, Ctc is in pF,
VDD in Volts DC, and f in kHz. (see Fig. 3) Dissipation during power−on with automatic reset enabled is typically 50 mA @ VDD = 10 Vdc.
MC14541B
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4
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS (Note 5) (CL = 50 pF, TA = 25_C)
Characteristic Symbol VDD Min Typ
(Note 6)
Max Unit
Output Rise and Fall Time
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns
tTLH,
tTHL 5.0
10
15
−
−
−
100
50
40
200
100
80
ns
Propagation Delay, Clock to Q (28 Output)
tPLH, tPHL = (1.7 ns/pF) CL + 3415 ns
tPLH, tPHL = (0.66 ns/pF) CL + 1217 ns
tPLH, tPHL = (0.5 ns/pF) CL + 875 ns
tPLH
tPHL 5.0
10
15
−
−
−
3.5
1.25
0.9
10.5
3.8
2.9
ms
Propagation Delay, Clock to Q (216 Output)
tPHL, tPLH = (1.7 ns/pF) CL + 5915 ns
tPHL, tPLH = (0.66 ns/pF) CL + 3467 ns
tPHL, tPLH = (0.5 ns/pF) CL + 2475 ns
tPHL
tPLH 5.0
10
15
−
−
−
6.0
3.5
2.5
18
10
7.5
ms
Clock Pulse Width tWH(cl) 5.0
10
15
900
300
225
300
100
85
−
−
−
ns
Clock Pulse Frequency (50% Duty Cycle) fcl 5.0
10
15
−
−
−
1.5
4.0
6.0
0.75
2.0
3.0
MHz
MR Pulse Width tWH(R) 5.0
10
15
900
300
225
300
100
85
−
−
−
ns
Master Reset Removal Time trem 5.0
10
15
420
200
200
210
100
100
−
−
−
ns
5. The formulas given are for the typical characteristics only at 25_C.
6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
Figure 1. Power Dissipation Test Circuit
and Waveform
Figure 2. Switching Time Test Circuit
and Waveforms
PULSE
GENERATOR
VDD
CL
Q
RS
AR
Q/Q SELECT
MODE
A
B
MR
VSS
20 ns 20 ns
90% 50%
10%
50%
DUTY CYCLE
(Rtc AND Ctc OUTPUTS ARE LEFT OPEN)
PULSE
GENERATOR
VDD
RS
AR
Q/Q SELECT
MODE
A
B
MR
VSS
CL
Q
20 ns
90% 50%
20 ns
10%
RS
Q
tPLH
50% 90%
50%
10% 50%
tTLH tTHL
tPHL
MC14541B
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5
EXPANDED BLOCK DIAGRAM
A12
B13
Rtc1
Ctc2
RS3
5
AUTO RESET
OSC
RESET
C28
8-STAGE
COUNTER
RESET
POWER-ON
RESET
6
MASTER RESET
210 213 216
C8-STAGE
COUNTER
RESET
1 OF 4
MUX
10
MODE
9
Q/Q
SELECT
8Q
VDD = PIN 14
VSS = PIN 7
FREQUENCY SELECTION TABLE
A B
Number of
Counter Stages
n
Count
2n
0 0 13 8192
0 1 10 1024
1 0 8 256
1 1 16 65536
TRUTH TABLE
Pin
State
0 1
Auto Reset, 5 Auto Reset
Operating
Auto Reset Disabled
Master Reset, 6 Timer Operational Master Reset On
Q/Q,9Output Initially Low
After Reset
Output Initially High
After Reset
Mode, 10 Single Cycle Mode Recycle Mode
Figure 3. Oscillator Circuit Using RC Configuration
3
RSRTC
Ctc
21
TO CLOCK
CIRCUIT
INTERNAL
RESET
MC14541B
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6
TYPICAL RC OSCILLATOR CHARACTERISTICS
Figure 4. RC Oscillator Stability
Figure 5. RC Oscillator Frequency as a
Function of Rtc and Ctc
8.0
4.0
0
-4.0
-8.0
-12
-16 1251007550250-25-55
TA, AMBIENT TEMPERATURE (°C)
FREQUENCY DEVIATION (%)
VDD = 15 V
10 V
5.0 V
RS = 0, f = 10.15 kHz @ VDD = 10 V, TA = 25°C
RS = 120 kW, f = 7.8 kHz @ VDD = 10 V, TA = 25°C
RTC = 56 kW,
C = 1000 pF
100
0.1
0.2
0.5
1.0
2.0
5.0
10
20
50
1.0 k 10 k 100 k 1.0 m
f, OSCILLATOR FREQUENCY (kHz)
RTC, RESISTANCE (OHMS)
0.0001 0.001 0.01 0.1
C, CAPACITANCE (mF)
VDD = 10 V
f AS A FUNCTION
OF RTC
(C = 1000 pF)
(RS ≈ 2RTC)
f AS A FUNCTION
OF C
(RTC = 56 kW)
(RS = 120 kW)
OPERATING CHARACTERISTICS
With Auto Reset pin set to a “0” the counter circuit is
initialized by turning on power. Or with power already on,
the counter circuit is reset when the Master Reset pin is set
to a “1”. Both types of reset will result in synchronously
resetting all counter stages independent of counter state.
Auto Reset pin when set to a “1” provides a low power
operation.
The RC oscillator as shown in Figure 3 will oscillate with
a frequency determined by the external RC network i.e.,
if (1 kHz v f v 100 kHz)
2.3 RtcCtc
1
f =
and RS ≈ 2 Rtc where RS ≥ 10 kW
The time select inputs (A and B) provide a two−bit address
to output any one of four counter stages (28, 210, 213 and
216). The 2n counts as shown in the Frequency Selection
Table represents the Q output of the Nth stage of the counter.
When A is “1”, 216 is selected for both states of B. However,
when B is “0”, normal counting is interrupted and the 9th
counter stage receives its clock directly from the oscillator
(i.e., effectively outputting 28).
The Q/Q select output control pin provides for a choice of
output level. When the counter is in a reset condition and
Q/Q select pin is set to a “0” the Q output is a “0”,
correspondingly when Q/Q select pin is set to a “1” the Q
output is a “1”.
When the mode control pin is set to a “1”, the selected
count is continually transmitted to the output. But, with
mode pin “0” and after a reset condition the RS flip−flop (see
Expanded Block Diagram) resets, counting commences,
and after 2n−1 counts the RS flip−flop sets which causes the
output to change state. Hence, after another 2n−1 counts the
output will not change. Thus, a Master Reset pulse must be
applied or a change in the mode pin level is required to reset
the single cycle operation.
DIGITAL TIMER APPLICATION
Rtc
Ctc
NC
RS
AR
MR
INPUT
tMR
VDD
B
A
N.C.
OUTPUT
VDD
MODE
Q/Q
t + tMR
1
2
3
4
5
6
78
9
10
11
12
13
14
When Master Reset (MR) receives a positive pulse, the
internal counters and latch are reset. The Q output goes high
and remains high until the selected (via A and B) number of
clock pulses are counted, the Q output then goes low and
remains low until another input pulse is received.
This “one shot” is fully retriggerable and as accurate as the
input frequency. An external clock can be used (pin 3 is the
clock input, pins 1 and 2 are outputs) if additional accuracy
is needed.
Notice that a setup time equal to the desired pulse width
output is required immediately following initial power up,
during which time Q output will be high.
MC14541B
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7
PACKAGE DIMENSIONS
PDIP−14
CASE 646−06
ISSUE P
17
14 8
B
ADIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.715 0.770 18.16 19.56
B0.240 0.260 6.10 6.60
C0.145 0.185 3.69 4.69
D0.015 0.021 0.38 0.53
F0.040 0.070 1.02 1.78
G0.100 BSC 2.54 BSC
H0.052 0.095 1.32 2.41
J0.008 0.015 0.20 0.38
K0.115 0.135 2.92 3.43
L
M−−− 10 −−− 10
N0.015 0.039 0.38 1.01
__
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
F
HG D
K
C
SEATING
PLANE
N
−T−
14 PL
M
0.13 (0.005)
L
M
J
0.290 0.310 7.37 7.87
MC14541B
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8
PACKAGE DIMENSIONS
SOIC−14
CASE 751A−03
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
−A−
−B−
G
P7 PL
14 8
7
1
M
0.25 (0.010) B M
S
B
M
0.25 (0.010) A S
T
−T−
F
RX 45
SEATING
PLANE D14 PL K
C
J
M
_DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A8.55 8.75 0.337 0.344
B3.80 4.00 0.150 0.157
C1.35 1.75 0.054 0.068
D0.35 0.49 0.014 0.019
F0.40 1.25 0.016 0.049
G1.27 BSC 0.050 BSC
J0.19 0.25 0.008 0.009
K0.10 0.25 0.004 0.009
M0 7 0 7
P5.80 6.20 0.228 0.244
R0.25 0.50 0.010 0.019
__ __
7.04
14X
0.58
14X
1.52
1.27
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT*
7X
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
MC14541B
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9
PACKAGE DIMENSIONS
TSSOP−14
CASE 948G−01
ISSUE B
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A4.90 5.10 0.193 0.200
B4.30 4.50 0.169 0.177
C−−− 1.20 −−− 0.047
D0.05 0.15 0.002 0.006
F0.50 0.75 0.020 0.030
G0.65 BSC 0.026 BSC
H0.50 0.60 0.020 0.024
J0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L6.40 BSC 0.252 BSC
M0 8 0 8
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
____
S
U0.15 (0.006) T
2X L/2
S
U
M
0.10 (0.004) V S
T
L−U−
SEATING
PLANE
0.10 (0.004)
−T−
ÇÇÇ
ÇÇÇ
ÇÇÇ
SECTION N−N
DETAIL E
JJ1
K
K1
ÉÉÉ
ÉÉÉ
DETAIL E
F
M
−W−
0.25 (0.010)
8
14
7
1
PIN 1
IDENT.
H
G
A
D
C
B
S
U0.15 (0.006) T
−V−
14X REFK
N
N
7.06
14X
0.36 14X
1.26
0.65
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT*
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
MC14541B
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10
PACKAGE DIMENSIONS
SOEIAJ−14
CASE 965−01
ISSUE B
HE
A1
DIM MIN MAX MIN MAX
INCHES
--- 2.05 --- 0.081
MILLIMETERS
0.05 0.20 0.002 0.008
0.35 0.50 0.014 0.020
0.10 0.20 0.004 0.008
9.90 10.50 0.390 0.413
5.10 5.45 0.201 0.215
1.27 BSC 0.050 BSC
7.40 8.20 0.291 0.323
0.50 0.85 0.020 0.033
1.10 1.50 0.043 0.059
0
0.70 0.90 0.028 0.035
--- 1.42 --- 0.056
A1
HE
Q1
LE
_10 _0
_10 _
LE
Q1
_
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
0.13 (0.005) M0.10 (0.004)
D
Z
E
1
14 8
7
eA
b
VIEW P
c
L
DETAIL P
M
A
b
c
D
E
e
L
M
Z
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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