44 - Pin Plastic 7mm x 7mm
Chip-Scale Package (QFN)
FEATURES
·
·
·
·
·
·
·
·
·
·
·
·
ARINC specification 429 compliant
3.3V or 5.0V logic supply operation
directly to ARINC 429 bus
Programmable label recognition for 256 labels
32 x 32 Receive FIFO and 32 x 32 Transmit FIFO
High-speed, four-wire Serial Peripheral Interface
Label bit-order control
32nd transmit bit can be data or parity
Self test mode
Low power
Industrial & extended temperature ranges
On-chip analog line driver and receiver connect
Independent data rates for Transmit and Receive
GENERAL DESCRIPTION
The HI-3585 from Holt Integrated Circuits is a silicon gate
CMOS device for interfacing a Serial Peripheral Interface
(SPI) enabled microcontroller to the ARINC 429 serial bus.
The device provides one receiver with user-programmable
label recognition for any combination of 256 possible
labels, 32 x 32 Receive FIFO and analog line receiver.
The independent transmitter has a 32 x 32 Transmit FIFO
and built-in line driver. The status of the transmit and
receive FIFOs can be monitored using the programmable
external interrupt pin, or by polling the HI-3585 Status
Register. Other features include a programmable option
of data or parity in the 32nd bit, and the ability to switch the
bit-signifiance of ARINC 429 labels. Pins are available
with different input resistance and output resistance
values which provides flexibility when using external
lightning protection circuitry.
The Serial Peripheral Interface minimizes the number of
host interface signals resulting in a small footprint device
that can be interfaced to a wide range of industry-standard
microcontrollers supporting SPI. Alternatively, the SPI
signals may be controlled using just four general purpose
I/O port pins from a microcontroller or custom FPGA. The
SPI and all control signals are CMOS and TTL compatible
and support 3.3V or 5V operation.
The HI-3585 applies the ARINC 429 protocol to the
receiver and transmitter. ARINC 429 databus timing
comes from a 1 MHz clock input, or an internal counter can
derive it from higher clock frequencies having certain fixed
values, possibly the external host processor clock.
The HI-3586 is functionally identical to the HI-3585 except
it includes digital transmitter output pins 429D1 and 429D0
instead of a built-in line driver. This allows the designer to
take advantage of Holt’s single supply rail line drivers,
such as the 5V HI-8592 or 3.3V HI-8596.
PIN CONFIGURATIONS (Top View)
ARINC 429
Terminal IC with SPI Interface
November 2015
HI-3585, HI-3586
(DS3585 Rev. N) 11/15
44 - N/C
43 - RINA
42 - RINA-40
41 - N/C
40 - VDD
39 - N/C
38 - V+
37 - N/C
36 - AOUT27
35 - AOUT37
34 - N/C
N/C - 1
RINB-40 - 2
RINB - 3
N/C - 4
N/C - 5
N/C - 6
MR - 7
SI - 8
-9
N/C - 10
N/C - 11
CS
33 - BOUT27
32 - BOUT37
31 - N/C
30 - V-
29 - N/C
28 - TFLAG
27 - N/C
26 - N/C
25 - RFLAG
24 - N/C
23 - N/C
N/C - 12
N/C - 13
N/C - 14
SCK - 15
N/C - 16
GND - 17
N/C - 18
ACLK - 19
SO - 20
N/C - 21
N/C - 22
HI-3585PCI
HI-3585PCT
HOLT INTEGRATED CIRCUITS
www.holtic.com
429D0 (HI-3586 only)
429D1(HI-3586 only)
SIGNAL FUNCTION DESCRIPTION NOTE
RINB INPUT ARINC receiver negative input. Direct connection to ARINC 429 bus
RINB-40 INPUT Alternate ARINC receiver negative input. Requires external 40K ohm resistor
MR INPUT Master Reset. A positive pulse clears Receive and Transmit data FIFOs and flags 10K ohm pull-down*
SI INPUT SPI interface serial data input 10K ohm pull-down*
INPUT Chip select. Data is shifted into SI and out of SO when is low. 10K ohm pull-up*
SCK INPUT SPI Clock. Data is shifted into or out of the SPI interface using SCK 10K ohm pull-down*
GND POWER Chip 0V supply
ACLK INPUT Master timing source for the ARINC 429 receiver and transmitter 10K ohm pull-down*
SO OUTPUT SPI interface serial data output
RFLAG OUTPUT Goes high when ARINC 429 Receive FIFO is empty (CR15=0), or full (CR15=1)
TFLAG OUTPUT Goes high when ARINC 429 Transmit FIFO is empty (CR14=0), or full (CR14=1)
V- POWER Minus 5V power supply to ARINC 429 Line Driver (HI-3585 only)
BOUT37 OUTPUT ARINC line driver negative output. Direct connection to ARINC 429 bus (HI-3585 only)
BOUT27 OUTPUT Alternate ARINC line driver negative output. Requires external 10 ohm resistor (HI-3585 only)
AOUT27 OUTPUT Alternate ARINC line driver positive output. Requires external 10 ohm resistor (HI-3585 only)
AOUT37 OUTPUT ARINC line driver positive output. Direct connection to ARINC 429 bus (HI-3585 only)
V+ POWER Positive 5V power supply to ARINC 429 Line Driver (HI-3585 only)
VDD POWER 3.3V or 5.0V logic power
RINA-40 INPUT Alternate ARINC receiver positive input. Requires external 40K ohm resistor
RINA INPUT ARINC receiver positive input. Direct connection to ARINC 429 bus
429D1 OUTPUT Digital positive output to external line driver (HI-3586 only)
429D0 OUTPUT Digital negative output to external line driver (HI-3586 only)
* Internal Pull-up or Pull-down
CS CS
PIN DESCRIPTIONS
VDD
AOUT27
BOUT27
SPI
Interface
AOUT37
BOUT37
Control Register Status Register
ARINC 429
Transmit
Data FIFO
ARINC 429
Transmit
Formatter
ARINC 429
Line Driver
(HI-3585 only)
ARINC 429
Received
Data FIFO
Label
Filter
ARINC 429
Valid word
Checker
ARINC 429
Line Receiver
Label
Filter
Bit Map
Memory
RINA-40
RINA
RINB
RINB-40
SCK
CS
SI
SO
V-
RFLAG
ACLK
GND
TFLAG
V+
40 Kohm
40 Kohm
27 Ohm
10 Ohm
10 Ohm
27 Ohm
ARINC
Clock
Divider
BLOCK DIAGRAM
HI-3585, HI-3586
HOLT INTEGRATED CIRCUITS
2
Example:
one SPI Instruction
op code 07hex data field 02hex
MSB LSB MSB LSB
CS
SCK
SI
INSTRUCTIONS
Instruction op codes are used to read, write and configure the HI-
3585. When goes low, the next 8 clocks at the SCK pin shift an
instruction op code into the decoder, starting with the first positive
edge. The op code is fed into the SI pin most significant bit first.
For write instructions, the most significant bit of the data word must
immediately follow the instruction op code and is clocked into its
register on the next rising SCK edge. Data word length varies
depending on word type written: 16-bit writes to Control Register,
32-bit ARINC word writes to transmit FIFO or 256-bit writes to the
label-matching enable/disable table.
CS
For read instructions, the most significant bit of the requested data
word appears at the SO pin after the last op code bit is clocked into
the decoder, at the next falling SCK edge. As with write
instructions, data field bit-length varies with read instruction type.
Table 1 lists all instructions. Instructions that perform a reset or set,
or enable transmission are executed after the last SI bit is received
while is still low.CS
OP CODE
Hex
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
DATA FIELD
None
None
None
None
8 bits
8 bits
256 bits
8 bits
32 bits
None
8 bits
16 bits
8 bits
256 bits
N x 32 Bits
None
16 bits
None
None
DESCRIPTION
No instruction implemented
After the 8th op code bit is received, perform Master Reset (MR)
, reset all label selections
, set all the label selections
Reset the label at the address specified in the data field
Set
Starting with label FF hex, consecutively set or reset each label in descending order
For example, a Data Field pattern starting with 1011 will set labels FF, FD, and FC
hex and reset label FE hex
Programs a division of the ACLK input. If the divided ACLK frequency is 1 MHz and Control
Register bit CR1 is set, the ARINC receiver and transmitter operate from the divided ACLK clock.
Allowable values for division rate are X1, X2, X4, X8, or XA hex. Any other programmed value
results in no clock. Note: ACLK input frequency and division ratio must yield 1 MHz clock.
Read the next word in the Receive FIFO. If the FIFO is empty, it will read zeros
No Instruction Implemented
Read the Status Register
Read the Control Register
Read the ACLK divide value programmed previously using op code 07 hex
Read the Label look-up memory table consecutively starting with address FF hex.
Write up to 32 words into the next empty positions of the Transmit FIFO
No instruction implemented
Write the Control Register
Reset the Transmit FIFO. , the transmit FIFO will be empty
Transmission enabled by this instruction only if Control Register bit 13 is zero
After the 8th op code bit is received
After the 8th op code bit is received
the label at the address specified in the data field
After the 8th op code bit is received
TABLE 1. DEFINED INSTRUCTION OP CODES
HI-3585, HI-3586
HOLT INTEGRATED CIRCUITS
3
CONTROL WORD REGISTER
The HI-3585 contains a 16-bit Control Register which is used to
configure the device. Control Register bits CR15 - CR0 are loaded
from a 16-bit data value appended to SPI instruction 10 hex. The
Control Register contents may be read using SPI instruction 0B
hex. Each bit of the Control Register has the following function:
STATUS REGISTER
The HI-3585 contains an 8-bit Status Register which can be
interrogated to determine the status of the ARINC receiver, data
FIFOs and transmitter. The contents of the Status Register are
output using SPI instruction 0A hex. Unused bits are output as
Zeros. The following table defines the Status Register bits.
SR
Bit FUNCTION STATE DESCRIPTION
SR0 Receive FIFO 0
1 Receiver FIFO is empty
Receiver FIFO contains valid data
(LSB) Empty Sets to One when all data has
been read. RFLAG pin reflects the
state of this bit when CR15=0
SR1 Receive FIFO 0 Receiver FIFO holds less than 16
Half Full words
1 Receiver FIFO holds at least 16
words
SR2 Receive FIFO 0 Receiver FIFO not full. RFLAG pin
Full reflects the state of this bit when
CR15=1
1 Receiver FIFO full. To avoid data
loss, the FIFO must be read within
one ARINC word period
SR3 Transmit FIFO 0 Transmit FIFO not empty.
Empty Sets to One when all data has
been sent. TFLAG pin reflects the
state of this bit when CR14=0
1 Transmit FIFO is empty.
SR4 Transmit FIFO 0 Transmit FIFO contains less than 16
Half Full words
1 Transmit FIFO contains at least 16
words
SR5 Transmit FIFO 0 Transmit FIFO not full. TFLAG pin
Full reflects the state of this bit when
CR14=1
1 Transmit FIFO full.
SR6 Not used 0 Always “0”
SR7 Not used 0 Always “0”
(MSB)
CR
Bit FUNCTION STATE DESCRIPTION
Cr0 Receiver 0 Data rate = CLK/10
1 Data rate = CLK/80
(ARINC 429 High-Speed)
(LSB) Data Rate
Select (ARINC 429 Low-Speed)
CR1 ARINC Clock 0 ARINC CLK = ACLK input frequency
Source Select
1 ARINC CLK = ACLK divided by the value
programmed with SPI Instruction 07 hex
CR2 Enable Label 0 Label recognition disabled
Recognition
1 Label recognition enabled
CR3 Transmitter 0 Transmitter 32nd bit is data
Parity Bit
Enable 1 Transmitter 32nd bit is parity
CR4 Receiver 0 Receiver parity check disabled
Parity Check
Enable 1 Receiver odd parity check enabled
CR5 Self Test 0 The transmitter’s digital outputs are internally
connected to the receiver logic inputs
1 Normal operation
CR6 Receiver 0 Receiver decoder disabled
Decoder
1 ARINC bits 10 and 9 must match CR7 and CR8
CR7 - - If receiver decoder is enabled,
the ARINC bit 10 must match this bit
CR8 - - If receiver decoder is enabled,
the ARINC bit 9 must match this bit
CR9 Transmitter 0 Transmitter 32nd bit is Odd parity
Parity
Select 1 Transmitter 32nd bit is Even parity
CR10 Transmitter 0 Data rate = CLK/10, O/P slope = 1.5us
Data Rate
1 Data rate = CLK/80, O/P slope = 10us
CR11 ARINC Label 0 Label bit order reversed (See Table 2)
Bit Order
1 Label bit order same as transmitted /
received (See Table 2)
CR12 Disable 0 Line Driver enabled
Line Driver
1 Line Driver disabled (force outputs to Null state)
CR13 Transmission 0 Start transmission by SPI
Enable Mode instruction12 hex
1 Transmit whenever data is available
in the Transmit FIFO
CR14 TFLAG 0 TFLAG goes high when transmit FIFO is empty
Definition
1 TFLAG goes high when transmit FIFO is full
CR15 RFLAG 0 RFLAG goes high when receive FIFO is empty
(MSB) Definition
1 RFLAG goes high when receive FIFO is full
FUNCTIONAL DESCRIPTION
HI-3585, HI-3586
HOLT INTEGRATED CIRCUITS
4
1. An accurate 1MHz clock source is required to validate the
receive signal timing. Less than 1% error is recommended.
2. The receiver uses three separate 10-bit sampling shift reg-
isters for Ones detection, Zeros detection and Null detection.
When the input signal is within the differential voltage range
for any shift register’s state (One Zero or Null) sampling
clocks a high bit into that register. When the receive signal is
outside the differential voltage range defined for any shift reg-
ister, a low bit is clocked. Only one shift register can clock a
high bit for any given sample. All three registers clock low
bits if the differential input voltage is between defined state
voltage bands.
Valid data bits require at least three consecutive One or Zero
samples (three high bits) in the upper half of the Ones or
Zeros sampling shift register, and at least three consecutive
Null samples (three high bits) in the lower half of the Null sam-
pling shift register within the data bit interval.
A word gap Null requires at least three consecutive Null sam-
ples (three high bits) in the upper half of the Null sampling
shift register and at least three consecutive Null samples
(three high bits) in the lower half of the Null sampling shift reg-
ister. This guarantees the minimum pulse width.
RECEIVER LOGIC OPERATION
BIT TIMING
BIT RATE
PULSE RISE TIME
PULSE FALL TIME
PULSE WIDTH
Figure 2 is a block diagram showing receiver logic.
The ARINC 429 specification defines the following timing toler-
ances for received data:
100K BPS ± 1% 12K -14.5K BPS
1.5 ± 0.5 µsec 10 ± 5 µsec
1.5 ± 0.5 µsec 10 ± 5 µsec
5 µsec ± 5% 34.5 to 41.7 µsec
The HI-3585 accepts signals within these tolerances and rejects
signals outside these tolerances. Receiver logic achieves this as
described below:
HIGH SPEED LOW SPEED
3. To validate the receive data bit rate, each bit must follow
its preceding bit by not less than 8 samples and not more
than 12 samples. With exactly 1MHz input clock frequency,
the acceptable data bit rates are:
83K BPS 10.4K BPS
125K BPS 15.6K BPS
4. Following the last data bit of a valid reception, the Word
Gap timer samples the Null shift register every 10 input
clocks (every 80 clocks for low speed). If a Null is present,
the Word Gap counter is incremented. A Word Gap count of
3 enables the next reception.
HIGH SPEED LOW SPEED
DATA BIT RATE MIN
DATA BIT RATE MAX
FUNCTIONAL DESCRIPTION (cont.)
ARINC 429 RECEIVER
ARINC BUS INTERFACE
Figure 1 shows the input circuit for the on-chip ARINC 429 line
receiver. The ARINC 429 specification requires the following
detection levels:
ONE +6.5 Volts to +13 Volts
NULL +2.5 Volts to -2.5 Volts
ZERO -6.5 Volts to -13 Volts
STATE DIFFERENTIAL VOLTAGE
DIFFERENTIAL
AMPLIFIERS
COMPARATORS
FIGURE 1. ARINC RECEIVER INPUT
RINA-40
RINA
RINB
RINB-40
VDD
GND
VDD
GND
ONE
NULL
ZERO
The HI-3585 guarantees recognition of these levels with a common
mode voltage with respect to GND less than ±30V for the worst case
condition (3.15V supply and 13V signal level).
Design tolerances guarantee detection of the above levels, so the
actual acceptance ranges are slightly larger. If the ARINC signal
(including nulls) is outside the differential voltage ranges, the HI-
3585 receiver rejects the data.
HI-3585, HI-3586
Parity
SDI
Label
Label (LSB)
Label (MSB)
Label
Label
Label
Label
Label
SDI
Parity
SDI
Label
Label (MSB)
Label (LSB)
Label
Label
Label
Label
Label
SDI
ARINC 429 DATA FORMAT
Control Register bit CR11 controls how individual bits in the
received or transmitted ARINC word are mapped to the HI-3585 SPI
data word bits during data read or write operations. The following
table describes this mapping:
Table 2. SPI / ARINC bit-mapping
SPI 1 2-22 23242526272829303132
Order
. ARINC bit 32 31 - 11 10 912345678
CR11=0 Data
ARINC bit 32 31 - 11 10 987654321
CR11=1 Data
HOLT INTEGRATED CIRCUITS
5
FIFO
LOAD
CONTROL
CONTROL BITS
CR2, CR6-8 /
SPI INTERFACE
32 BIT SHIFT REGISTER
CONTROLBITS
CR0, CR1
CLOCK
OPTION
CLOCK
ACLK
BIT
COUNTER
AND
END OF
SEQUENCE
PARITY
CHECK
32ND
BIT
DATA
BIT CLOCK
WORD GAP
WORD GAP
TIMER
BIT CLOCK
END
START
SEQUENCE
CONTROL
ERROR
CLOCK
ERROR
DETECTION
SHIFT REGISTER
SHIFT REGISTER
NULL
ZEROS
SHIFT REGISTER
ONES
EOS
FIGURE 2. RECEIVER BLOCK DIAGRAM
LABEL /
DECODE
COMPARE
256-BIT
LABEL
LOOK-UP
TABLE
32X32
FIFO
RFLAG
SCK
CS
SI
SO
FUNCTIONAL DESCRIPTION (cont.)
HI-3585, HI-3586
HOLT INTEGRATED CIRCUITS
6
0 X 0 X Load FIFO
1 No 0 X Ignore data
1 Yes 0 X Load FIFO
0 X 1 No Ignore data
0 X 1 Yes Load FIFO
1 Yes 1 No Ignore data
1 No 1 Yes Ignore data
1 No 1 No Ignore data
1 Yes 1 Yes Load FIFO
CR2 ARINC word CR6 ARINC word FIFO
matches bits 10, 9
Enabled match
CR7, 8label
RETRIEVING DATA
Once 32 valid bits are recognized, the receiver logic generates an
End of Sequence (EOS). Depending on the state of Control
Register bits CR2, CR6, CR7 and CR8, the received 32-bit ARINC
word is then checked for correct decoding and label match before
it is loaded into the 32 x 32 Receive FIFO. ARINC words that do
not match required 9th and 10th ARINC bit and do not have a label
match are ignored and are not loaded into the Receive FIFO. The
adjacent table describes this operation.
Once a valid ARINC word is loaded into the FIFO, the EOS signal
clocks the Data Ready flip-flop to a "1" and Status Register bit 0
(SR0) to a “0”. The SR0 bit remains low until the Receive FIFO is
empty. Each received ARINC word is retrieved via the SPI
interface using SPI instruction 08 hex to read a single word.
Up to 32 ARINC words may be held in the Receive FIFO. Status
register bit 2 (SR2) goes high when the Receive FIFO is full.
Failure to unload the Receive FIFO when full causes additional
received validARINC words to overwrite Receive FIFO location 32.
A FIFO half-full flag (SR1) is high when the Receive FIFO contains
16 or more ARINC words. SR1 may be interrogated by the
system’s external microprocessor, allowing a 16 word data
retrieval routine to be performed.
FUNCTIONAL DESCRIPTION (cont.)
TABLE 3. FIFO LOADING CONTROL
HI-3585, HI-3586
HOLT INTEGRATED CIRCUITS
7
RECEIVER PARITY
The Receiver Parity Check Enable bit (Control Register bit 4,
CR4) controls how the 32nd bit of the received ARINC word is
interpreted by the HI-3585 receiver.
, the 32nd bit is treated as data and
transferred as received from the ARINC bus to the receive FIFO.
, the 32nd bit is treated as a parity
error bit.
The receiver expects the 32nd bit of the received word to
indicate odd parity. If this is the case, the parity bit is reset to
indicate correct parity was received and resulting word is
written to the receive FIFO.
If the received word is even parity, the receiver sets the 32nd
bit to a “1”, indicating a parity error. The resulting word is then
written to the receive FIFO.
Therefore, when CR4 is set to “1”, the 32nd bit retrieved from the
receiver FIFO will always be “0” when valid (odd parity) ARINC 429
words are received.
When CR4 is set to a “0”
When CR4 is set to a “1”
Odd Parity Received
Even Parity Received
0 data data
1 parity bit
0 = odd parity
1= odd parity error (even parity)
CR4 ARINC BUS FIFO
32nd bit 32nd bit
Error Bit:
LABEL RECOGNITION
The user loads the 256-bit label look-up table to specify which 8-bit
incoming ARINC labels are captured by the receiver, and which are
discarded. Setting a “1” in the look-up table enables processing of
received ARINC words containing the corresponding label. A “0”
in the look-up table causes discard of received ARINC words
containing the label. The 256-bit look-up table is loaded using SPI
op codes 02 hex, 03 hex or 06 hex, as described in Table 1. After
the look-up table is initialized, set Control Register bit CR2 to
enable label recognition.
If label recognition is enabled, the receiver compares the label in
each new ARINC word against the stored look-up table. If a label
match is found, the received word is processed. If no match
occurs, the new ARINC word is discarded and no indicators of
receivedARINC data are presented.
The contents of the Label Look-up table may be read via the SPI
interface using instruction 0D hex as described in Table 1.
READING THE LABEL LOOK-UP TABLE
The HI-3586 is functionally identical to the HI-3585 except
it does not include an on-chip ARINC 429 Line Driver.
Instead, digital output pins 429D1 and 429D0 may be used
to drive an external ARINC 429 line driver. This
configuration is useful if the desiger wishes to take
advantage of Holt’s single supply rail line drivers, such as
the 5V Hi-8592 or 3.3V HI-8596.
HI-3586 OPTION
ARINC 429 Bus
HI-3586
HI-3586 / HI-8596 3.3V-only Design Example
GND
3.3V
32.5 Ohm
32.5 Ohm
429D1
429D0 HI-8596
TX1IN
TX0IN
TXAOUT
TXBOUT
FUNCTIONAL DESCRIPTION (cont.)
TRANSMITTER
FIFO OPERATION
The Transmit FIFO is loaded with ARINC 429 words awaiting
transmission. SPI op code 0E hex writes up to 32 ARINC words
into the FIFO, starting at the next available FIFO location. If Status
Register bit SR3 equals “1” (FIFO empty), then up to 32 words (32
bits each) may be loaded. If Status Register bit SR3 equals “0”
then only the available positions may be loaded. If all 32 positions
are full, Status Register bit SR5 is asserted. Further attempts to
load the Transmit FIFO are ignored until at least one ARINC word is
transmitted.
The Transmit FIFO half-full flag (Status Register bit SR4) equals “0”
when the Transmit FIFO contains less than 16 words. When SR4
equals “0”, the system microprocessor can safely initiate a 16-word
ARINC block-write sequence.
In normal operation (Control Register bit CR3 = ”1”), the 32nd bit
transmitted is a word parity bit. Odd or even parity is selected by
programming Control Register bit CR9 to a “0” or “1” respectively. If
Control Register bit CR3 equals “0”, all 32 bits loaded into the
Transmit FIFO are treated as data and are transmitted.
SPI op code 11 hex asynchronously clears all data in the Transmit
FIFO. The Transmit FIFO should be cleared after a self-test before
starting normal operation to avoid inadvertent transmission of test
data.
CR3, CR9
FIGURE 3. TRANSMITTER BLOCK DIAGRAM
DATA
CLOCK
CR10, CR1
ACLK
PARITY
GENERATOR
DATA AND
NULL TIMER
SEQUENCER
LINE DRIVER
BIT
AND
WORD GAP
COUNTER
START
SEQUENCE
WORD COUNTER
AND
FIFO CONTROL
INCREMENT
WORD COUNT
DATA CLOCK
DIVIDER
FIFO
LOADING
SEQUENCER
AOUT
BOUT
32 x 32 FIFO
32 BIT PARALLEL
LOAD SHIFT REGISTER BIT CLOCK
WORD CLOCK
ADDRESS
LOAD
SR3
CR12
SR4
SR5
SPI INTERFACE
SCK
CS
SI
SO
SPI COMMANDS
SPI COMMANDS
HI-3585, HI-3586
HOLT INTEGRATED CIRCUITS
8
FUNCTIONAL DESCRIPTION (cont.)
DATA TRANSMISSION
TRANSMITTER PARITY
SELF TEST
SYSTEM OPERATION
LINE DRIVER OPERATION
LINE DRIVER OUTPUT PINS
LINE RECEIVER INPUT PINS
POWER SUPPLY SEQUENCING
MASTER RESET (MR)
If Control Register bit CR13 equals “1”, ARINC 429 data is
transmitted immediately following the rising edge of the SPI
instruction that loaded data into the Transmit FIFO. Loading
Control Register bit CR13 to “0” allows the software to control
transmission timing; each time an SPI op code 12 hex is executed,
all loaded Transmit FIFO words are transmitted. If new words are
loaded into the Transmit FIFO before transmission stops, the new
words will also be output. Once the Transmit FIFO is empty and
transmission of the last word is complete, the FIFO can be loaded
with new data which is held until the next SPI 12 hex instruction is
executed. Once transmission is enabled, the FIFO positions are
incremented with the top register loading into the data transmission
shift register. Within 2.5 data clocks the first data bit appears at
AOUT and BOUT. The 31 or 32 bits in the data transmission shift
register are presented sequentially to the outputs in the ARINC 429
format with the following timing:
The word counter detects when all loaded positions have been
transmitted and sets the transmitter ready flag, SR3, high.
The parity generator counts the Ones in the 31-bit word. If control
register bit CR9 is set to a “0”, the 32nd bit transmitted will make
parity odd. If the control bit is a “1”, the parity is even. Setting CR3
to “0” bypasses the parity generator, and allows 32 bits of data to be
transmitted.
If Control Register bits CR5 and CR12 equal ”0”, the transmitter
serial output data is internally looped-back into the receiver. Data
passes unmodified from transmitter to receiver. Setting Control
register bit CR12 to ”1” forces AOUT and BOUT to the Null state
regardless of CR5 state.
The receiver is independent of the transmitter. Therefore, control
of data exchanges is strictly at the option of the user. The only
restrictions are:
1. The received data will be overwritten if the Receive FIFO is
full and at least one location is not retrieved before the next
complete ARINC word is received.
2. The Transmit FIFO can store 32 words maximum and
ignores attempts to load additional data when full.
The line driver in the HI-3585 directly drives the ARINC 429 bus.
The two ARINC outputs (AOUT37 and BOUT37) provide a
differential voltage to produce a +10V One, a -10V Zero, and a
0 Volt Null. Control Register bit CR10 controls both the transmitter
data rate and the slope of the differential output signal. No
additional hardware is required to control the slope.
Transmit timing is derived from a 1 MHZ reference clock. Control
Register bit CR1 determines the reference clock source. If CR1
equals ”0,” a 50% duty cycle 1 MHZ clock should be applied to the
ACLK input pin. If CR1 equals ”1,” the ACLK input is divided to
generate the 1 MHZ ARINC clock. SPI op code 07 hex provides
the HI-3585 with the correct division ratio to generate a 1 MHZ
reference from ACLK.
Loading Control Register bit CR10 to “0” causes a 100 Kbit/s data
rate and a slope of 1.5 µs on the ARINC outputs. Loading CR10 to
“1” causes a 12.5 Kbit/s data rate and a slope of 10 µs. Timing is
set by an on-chip resistor and capacitor and tested to be within
ARINC 429 requirements.
The HI-3585 AOUT37 and BOUT37 pins have 37.5 Ohms in
series with each line driver output, and may be directly connected
to an ARINC 429 bus. The alternate AOUT27 and BOUT27 pins
have 27 ohms of internal series resistance and require external 10
ohm resistors at each pin. AOUT27 and BOUT27 are for
applications where external series resistance is applied, typically
for lightning protection devices.
Please refer to the Holt AN-300 Application Note for additional
information and recommendations on lightning protection of Holt
line drivers and line receivers.
Power supply sequencing should be controlled to prevent large
currents during supply turn-on and turn-off. The recommended
sequence is V+ followed by V , always ensuring that V+ is the
most positive supply. The V- supply is not critical and can be
applied at any time.
Application of a Master Reset causes immediate termination of
data transmission and data reception. The transmit and receive
FIFOs are cleared. Status Register FIFO flags and FIFO status
output signals RFLAG and TFLAG are also cleared. The Control
Register is not affected by a Master Reset.
CS
ARINC DATA BIT TIME 10 Clocks 80 Clocks
DATA BIT TIME 5 Clocks 40 Clocks
NULL BIT TIME 5 Clocks 40 Clocks
WORD GAP TIME 40 Clocks 320 Clocks
HIGH SPEED LOW SPEED
The HI-3585 has two sets of Line Receiver input pins, RINA/B
and RINA/B-40. Only one pair may be used to connect to the
ARINC 429 bus. The unused pair must be left floating. The
RINA/B pins may be connected directly to the ARINC 429 bus.
The RINA/B-40 pins require external 40K ohm resistors in series
with each ARINC input. These do not affect the ARINC receiver
thresholds. By keeping excessive voltage outside the device, this
option is helpful in applications where lightning protection is re-
quired.
When using the RINA/B-40 pins, each side of the ARINC bus
must be connected through a 40K ohm series resistor in order for
the chip to detect the correct ARINC levels. The typical 10 Volt dif-
ferential signal is translated and input to a window comparator
and latch. The comparator levels are set so that with the external
40K ohm resistors, they are just below the standard 6.5 volt mini-
mum ARINC data threshold and just above the standard 2.5 volt
maximum ARINC null threshold.
DD
HI-3585, HI-3586
HOLT INTEGRATED CIRCUITS
9
MSB LSB
MSB LSB High Z
High Z
CS
SO
SI
01234567
SCK (SPI Mode 0)
Figure 4. Generalized Single-Byte Transfer Using SPI Protocol Mode 0
SERIAL PERIPHERAL INTERFACE (SPI) BASICS
The HI-3585 uses an SPI synchronous serial interface for host
access to internal registers and data FIFOs. Host serial
communication is enabled through the Chip Select ( ) pin, and
is accessed via a three-wire interface consisting of Serial Data
Input (SI) from the host, Serial Data Output (SO) to the host and
Serial Clock (SCK). All read / write cycles are completely self-
timed.
The SPI (Serial Peripheral Interface) protocol specifies master
and slave operation; the HI-3585 operates as an SPI slave.
The SPI protocol defines two parameters, CPOL (clock polarity)
and CPHA (clock phase). The possible CPOL-CPHA
combinations define four possible "SPI Modes". Without
describing details of the SPI modes, the HI-3585 operates in
mode 0 where input data for each device (master and slave) is
clocked on the rising edge of SCK, and output data for each
device changes on the falling edge (CPHA = 0, CPOL = 0). Be
sure to set the host SPI logic for mode 0.
As seen in Figure 4, SPI Mode 0 holds SCK in the low state when
idle. The SPI protocol transfers serial data as 8-bit bytes. Once
chip select is asserted, the next 8 rising edges on SCK latch
input data into the master and slave devices, starting with each
byte’s most-significant bit.
Multiple bytes may be transferred when the host holds low
after the first byte transferred, and continues to clock SCK in
multiples of 8 clocks. A rising edge on chip select terminates
the serial transfer and reinitializes the HI-3585 SPI for the next
transfer. If goes high before a full byte is clocked by SCK, the
incomplete byte clocked into the device SI pin is discarded.
In the general case, both master and slave simultaneously send
and receive serial data (full duplex), per Figure 4 below. However
the HI-3585 operates half duplex, maintaining high impedance
on the SO output, except when actually transmitting serial data.
When the HI-3110 is sending data on SO during read operations,
activity on its SI input is ignored. Figures 5 and 6 show actual
behavior for the HI-3585 SO output.
CS
CS
CS
CS
CS
SERIAL PERIPHERAL INTERFACE
HOLT INTEGRATED CIRCUITS
10
HI-3585, HI-3586
Figure 6. 2-Byte Write example
CS
SO
SI
SCK
SPI Mode 0
MSB LSB
01234567
High Z
0123456701234567
MSB LSB MSB LSB
Data Byte 0 Data Byte 1
Op-Code Byte
Host may continue to assert
here to write sequential byte(s)
when allowed by the SPI instruction.
Each byte needs 8 SCK clocks.
CS
Figure 5. Single-Byte Read From a Register
CS
SO
SI
SCK
MSB LSB
01234567
High Z High Z
01234567
MSB LSB MSB
LSB
Data Byte
Op-Code Byte
Host may continue to assert
here to read sequential word(s)
when allowed by the instruction.
Each word needs 8 SCK clocks.
CS
HI-3585 SPI COMMANDS
For the HI-3585, each SPI read or write operation begins with an
8-bit command byte transferred from the host to the device after
assertion of . Since HI-3585 command byte reception is half-
duplex, the host discards the dummy byte it receives while
serially transmitting the command byte.
Figures 5 and 6 show read and write timing as it appears for a
single-byte and dual-byte register operation. The command byte
is immediately followed by a data byte comprising the 8-bit data
word read or written. For a single register read or write, is
negated after the data byte is transferred.
Multiple byte read or write cycles may be performed by
transferring more than one byte before is negated. Table 1
defines the required number of bytes for each instruction.
Note: SPI Instruction op-codes not shown in Tables 1 are
“reserved” and must not be used. Further, these op-codes will
not provide meaningful data in response to read commands.
; must be
negated after the command, then reasserted for the following
Read or Write command.
CS
CS
CS
CSTwo instruction bytes cannot be “chained”
HOST SERIAL PERIPHERAL INTERFACE (cont.)
HOLT INTEGRATED CIRCUITS
11
HI-3585, HI-3586
SERIAL OUTPUT TIMING DIAGRAM
CS
SCK
SO
CHZ
t
Hi Impedance
SCKH
t
tDV
LSB
CPH
t
tSCKL
MSB Hi Impedance
RECEIVER OPERATION
RFLAG
ARINC DATA
CS
SI
BIT 31 BIT 32
RFLG
t
ARINC
BIT 32
SPIF
t
SO
SPI INSTRUCTION 08h
ARINC
BIT 31
ARINC
BIT 30
RXR
t
DATA RATE - EXAMPLE PATTERN
TXAOUT
ARINC BIT
TXBOUT
NULL
DATA DATA DATA
NULL NULL
WORD GAP BIT 1
NEXT WORD
BIT 32
BIT 31
BIT 30
SERIAL INPUT TIMING DIAGRAM
CS
SCK
SI
CHH
t
CEH
t
MSB
CES
t
DS
tt
DH
LSB
CPH
t
SCKR
t
SCKF
t
TIMING DIAGRAMS
HI-3585, HI-3586
ARINC
BIT 1
HOLT INTEGRATED CIRCUITS
12
CES
t
CYC
t
Supply Voltages V ......................................... -0.3V to +7.0V
V+ ......................................................... +7.0V
V- ......................................................... -7.0V
Voltage at pins RINA, RINB ............................... -120V to +120V
Voltage at ARINC pins AOUT, BOUT ... (V-) 0.3V to (V+) 0.3V
Voltage at any other pin ............................... -0.3V to V +0.3V
Solder temperature (Reflow) ........................................... 260
DD
DD
–+
°C
Power Dissipation at 25°C
Plastic Quad Flat Pack ..................1.5 W, derate 10mW/ C
DC Current Drain per pin .............................................. ±10mA
Operating Temperature Range (Industrial): ..... -40°C to +85°C
(Hi-Temp): ..... -55°C to +125°C
°
Storage Temperature Range ........................ -65°C to +150°C
NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only.
Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS
TRANSMITTING DATA
ARINC BIT ARINC BIT ARINC BIT
CS
TFLAG (CR14=0)
AOUT
BOUT
DIFF
V
(AOUT - BOUT)
+5V +5V
+5V
+10V +10V
-10V
-5V -5V
-5V
SI
DATT
t
DATA
BIT 1
DATA
BIT 2 DATA
BIT 32
one level zero level null level
90%
90%
10%
10%
tfx
trx
tfx
trx
SDAT
t
TFLG
t
SPI INSTRUCTION 0Eh, (or 12h)
TIMING DIAGRAMS (cont.)
HI-3585, HI-3586
HOLT INTEGRATED CIRCUITS
13
ARINC OUTPUTS - Pins AOUT37, BOUT37, (or AOUT27, BOUT27 with external 10 Ohms)
LOGIC OUTPUTS
Operating Voltage Range
Operating Supply Current
Output Voltage: Logic "1" Output Voltage V I = -100 A V
Logic "0" Output Voltage V I = 1.0mA V
Output Current: Output Sink I V = 0.4V 1.6 mA
Output Source I V = V - 0.4V -1.0 mA
Output Capacitance: C 15 pF
VDD 3.15 5.25 V
V+ 4.75 5.5 V
V- -4.75 -5.5 V
VDD I 2.5 7 mA
ARINC output voltage (Ref. To GND) One or zero V No load and magnitude at pin, 4.50 5.00 5.50 V
Null V -0.25 0.25 V
ARINC output voltage (Differential) One or zero V No load and magnitude at pin, 9.0 10.0 11.0 V
Null V -0.5 0.5 V
ARINC output current I Momentary current 80 mA
µ
V+ I 4 14 mA
V- I 4 12 mA
DOUT
NOUT
DDIF
NDIF
OUT
DD2
EE1
OH OH
OL OL
OL OUT
OH OUT DD
O
DD1
90%VDD
10% VDD
LIMITS
PARAMETER CONDITIONS UNIT
SYMBOL
Differential Input Voltage: ONE V Common mode voltages 6.5 10.0 13.0 V
(RINA to RINB) ZERO V less than ±30V with -13.0 -10.0 -6.5 V
NULL V respect to GND -2.5 0 2.5 V
Input Resistance: Differential R - 140 - K
To GND R - 140 - K
To V R - 100 - K
Input Current: Input Sink I 200 µA
Input Source I -450 µA
Input Capacitance: Differential C 20 pF
(Guaranteed but not tested) To GND C 20 pF
To V C 20 pF
Input Voltage: Input Voltage HI V V
Input Voltage LO V V
Input Current: Input Sink I 1.5 µA
Input Source I -1.5 A
MIN TYP MAX
ARINC INPUTS - Pins RINA, RINB, RINA-40 (with external 40KOhms), RINB-40 (with external 40KOhms)
LOGIC INPUTS
IH
IL
NUL
I
G
DD H
IH
IL
I
G
DD H
IH
IL
IH
IL
W
W
W
(RINA to RINB)
µ
Pull-down Current (MR, SI, SCK, ACLK pins) I 250 600 µA
Pull-up current (CS pin) I -600 -300 µA
80% VDD
20% VDD
PD
PU
V = 3.3V or 5.0V , GND = 0V, TA = Operating Temperature Range (unless otherwise specified).DD V+ = +5V, V- = -5V,
DC ELECTRICAL CHARACTERISTICS
HI-3585, HI-3586
HOLT INTEGRATED CIRCUITS
14
AC ELECTRICAL CHARACTERISTICS
VDD = 3.3V or 5.0V, V+=+5V, V-=-5V, GND = 0V, TA = Operating Temperature Range and fclk=1MHz 0.1% with 50/50 duty cycle+
LIMITS
PARAMETER SYMBOL UNITS
MIN TYP MAX
SPI INTERFACE TIMING - 5.0V
RECEIVER TIMING
SCK clock period
active after last SCK rising edge t 10 ns
setup time to first SCK rising edge t 10 ns
hold time after last SCK falling edge t 40 ns
inactive between SPI instructions t
Delay - Last bit of received ARINC word to RFLAG(Full or Empty) - Hi Speed t 16 µs
Received data available to SPI interface. RFLAG to active
SPI receiver read or clear FIFO instruction to RFLAG t
SPI transmit data write or FIFO clear instruction to TFLAG (Empty or Full) t
SPI instruction to ARINC 429 data output - Hi Speed t
Delay TFLAG high after enable transmit - Hi Speed
Line driver transition differential times:
high to low t 1.0 1.5 2.0
t 250 ns
20 ns
SPI SI Data set-up time to SCK rising edge t 25 ns
SPI SI Data hold time after SCK rising edge t 15 ns
SCK rise time t 10 ns
SCK fall ime t 10 ns
SO valid after SCK falling edge t 125 ns
SO high-impedance after inactive t 100 ns
Master Reset pulse width t 150 ns
SCK clock period t 390 ns
active after last SCK rising edge t 10 ns
setup time to first SCK rising edge t 10 ns
hold time after last SCK falling edge t 40 ns
inactive between SPI instructions t 35 ns
SPI SI Data set-up time to SCK rising edge t 30 ns
SPI SI Data hold time after SCK rising edge t 30 ns
SCK rise time t 10 ns
SCK fall ime t 10 ns
SO valid after SCK falling edge t 195 ns
SO high-impedance after t 100 ns
Master Reset pulse width t 150 ns
Delay - Last bit of received ARINC word to RFLAG(Full or Empty) - Lo Speed t 126 µs
t0 ns
155 ns
120 ns
17 µs
SPI instruction to ARINC 429 data output - Lo Speed t 118 µs
t14µs
Delay TFLAG high after enable transmit - Lo Speed t 114 µs
(High Speed, control register CR10 = Logic 0) µs
low to high t 1.0 1.5 2.0 µs
(Low Speed, control register CR10 = Logic 1) high to low t 5.0 10 15 µs
low to high t 5.0 10 15 µs
CYC
CPH
DS
DH
SCKR
SCKF
DV
CHZ
CYC
CHH
CES
CEH
CPH
DS
DH
SCKR
SCKF
DV
CHZ
RFLG
RXR
SDAT
DATT
DATT
rx
fx
rx
CS
CS
CS
CS
CS
CHH
CES
CEH
RFLG
SPIF
TFLG
SDAT
fx
CS
CS
CS
CS
CS
MR
MR
SPI INTERFACE TIMING - 3.3V
TRANSMITTER TIMING
inactiveCS
HI-3585, HI-3586
HOLT INTEGRATED CIRCUITS
15
HOLT INTEGRATED CIRCUITS
16
HI-3585, HI-3586
44 - Pin Plastic 7mm x 7mm
Chip-Scale Package (QFN)
ADDITIONAL HI-3585 & HI-3586 PIN CONFIGURATIONS (Top View)
44 - Pin Plastic Quad Flat Pack (PQFP)
44 - N/C
43 - RINA
42 - RINA-40
41 - N/C
40 - VDD
39 - 429D1
38 - 429D0
37 - VDD
36 - N/C
35 - N/C
34 - N/C
N/C - 1
RINB-40 - 2
RINB - 3
N/C - 4
N/C - 5
N/C - 6
MR - 7
SI - 8
-9
N/C - 10
N/C - 11
CS
33 - N/C
32 - N/C
31 - N/C
30 - GND
29 - N/C
28 - TFLAG
27 - N/C
26 - N/C
25 - RFLAG
24 - N/C
23 - N/C
N/C - 12
N/C - 13
N/C - 14
SCK - 15
N/C - 16
GND - 17
N/C - 18
ACLK - 19
SO - 20
N/C - 21
N/C - 22
HI-3586PCI
HI-3586PCT
44 - N/C
43 - RINA
42 - RINA-40
41 - N/C
40 - VDD
39 - 429D1
38 - 429D0
37 - VDD
36 - N/C
35 - N/C
34 - N/C
33 - N/C
32 - N/C
31 - N/C
30 - GND
29 - N/C
28 - TFLAG
27 - N/C
26 - N/C
25 - RFLAG
24 - N/C
23 - N/C
N/C-12
N/C-13
N/C-14
SCK-15
N/C-16
GND-17
N/C-18
ACLK - 19
SO-20
N/C-21
N/C-22
N/C - 1
RINB-40 - 2
RINB - 3
N/C - 4
N/C - 5
N/C - 6
MR - 7
SI - 8
-9
N/C-10
N/C-11
CS
HI-3586PQI
HI-3586PQT
HI-3586PQM
44 - Pin Plastic Quad Flat Pack (PQFP)
44 - N/C
43 - RINA
42 - RINA-40
41 - N/C
40 - VDD
39 - N/C
38 - V+
37 - N/C
36 - AOUT27
35 - AOUT37
34 - N/C
33 - BOUT27
32 - BOUT37
31 - N/C
30-V-
29 - N/C
28 - TFLAG
27 - N/C
26 - N/C
25 - RFLAG
24 - N/C
23 - N/C
N/C-12
N/C-13
N/C-14
SCK-15
N/C-16
GND-17
N/C-18
ACLK - 19
SO-20
N/C-21
N/C-22
N/C - 1
RINB-40 - 2
RINB - 3
N/C - 4
N/C - 5
N/C - 6
MR - 7
SI - 8
-9
N/C-10
N/C-11
CS
HI-3585PQI
HI-3585PQT
HI-3585PQM
ORDERING INFORMATION
HI - 358x xx x x
PACKAGE
DESCRIPTION
44 PIN PLASTIC CHIP-SCALE, QFN (44PCS) Not Avaiable in “M” Flow
PART
NUMBER
PC
44 PIN PLASTIC QUAD FLAT PACK, PQFP (44PMQS)
PQ
LEAD
FINISH
PART
NUMBER
100% Matte Tin (Pb-free, RoHS compliant)
F
Tin / Lead (Sn / Pb) Solder
Blank
TEMPERATURE
RANGE
-40°C TO +85°C No
-55°C TO +125°C No
T
PART
NUMBER
T
I
FLOW
I
HOLT INTEGRATED CIRCUITS
17
HI-3585, HI-3586
PACKAGE
DESCRIPTION
On-chip ARINC 429 Line Driver
PART
NUMBER
3585
External ARINC 429 Line Driver
3586
-55°C TO +125°C YES
M
M
HI-3585, HI-3586
REVISION HISTORY
P/N Rev Date Description of Change
DS3585 NEW 05/08/08 Initial Release
A 10/10/08 Revised AC Electrical Characteristics table and description of “T” process.
B 05/22/09 Clarified relationship between SPI bit order and the ARINC 429 bit order.
C 02/03/10 Clarified op code 09 hex description.
D 04/20/10 Removed op code 09 hex.
E 05/19/10 Corrected ARINC receiver nomenclature.
F 09/03/10 Added HI-3586 digital-only product option
G 11/02/10 Enhanced description of HI-3586 digital-only product option, added basics of SPI
communications and added M flow for QFP package.
H 06/04/12 Clarified the description of receiver parity. Updated PQFP package drawing. Corrected typo
in clock source tolerance on p. 5 from 0.1% to 1%.
I 07/02/12 Update SPI Interface Timing at 5.0V and 3.3V
J 07/25/13 Update QFN package drawing. Remove note on heat sink connection for QFN package.
M 10/23/15 Update SPI Output timing diagram. Update AC Characteristics for tCHZ.
K 06/23/14 Update solder reflow temperature. Correct typo in ordering information. Update package
drawings.
L 07/18/14 Clarify absolute maximum voltage at ARINC bus pins AOUT, BOUT.
N 11/11/15 Update AC Characteristics for tCHZ parameter at 3.3V.
HOLT INTEGRATED CIRCUITS
18
44-PIN PLASTIC CHIP-SCALE PACKAGE (QFN)
Package Type: 44PCS
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
5.50 ± 0.050
(0.217 ± 0.002)
0.400 ± 0.050
(0.016 ± 0.002)
0.25 ± 0.050
(0.010 )± 0.002
0.50
(0.0197)
0.200
(0.008)
1.00
(0.039)
7.00
(0.276)
BSC
5.50 ± 0.050
(0.217 ± 0.002)
typ
Bottom
View
Top View
BSC
7.00
(0.276)BSC
max
millimeters (inches)
Electrically isolated heat
sink pad on bottom of
package
Connect to any ground or
power plane for optimum
thermal dissipation
Package Type:
0° £ Q £ 7°
Detail A
See Detail A
SQ.
44PMQS
44-PIN PLASTIC QUAD FLAT PACK (PQFP)
0.230
(0.009)
13.200
(0.520)
10.000
(0.394)
SQ.
MAX.
0.370 ± 0.080
(0.015 ± 0.003)
0.880 .150±0
(0.035 ± 0.006)
0.13
(0.005)R MIN.
0.30
(0.012)R MAX.
2.00 .20±0
(0.079 .008)±0
2.70
(0.106)MAX.
0.80
(0.031)
millimeters (inches)
BSC
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
BSC BSC
0.20
(0.008)min
1.60
(0.063)
typ
HI-3585, HI-3586 PACKAGE DIMENSIONS
HOLT INTEGRATED CIRCUITS
19
