HN29V128A1A (3.3 V/x x8) HN29V128A0A (3.3 V/x x16) HN29A128A1A (1.8 V/x x8) HN29A128A0A (1.8 V/x x16) 128M superAND Flash Memory (with internal sector management) REJ03C0031-0003Z (Previous ADE-203-1344B (Z) Rev.0.2) Preliminary Rev. 0.03 Jun. 06, 2003 Description The HN29V128A1A, HN29V128A0A, HN29A128A1A, and HN29A128A0A Series is a CMOS flash memory, which uses cost effective and high performance AND type multi-level memory cell technology. Current AND flash memory requires us to support complicated operations such as sector management for defect sector and error check correction. But this series doesn't need such operations. Beside it supports wear leveling function, which is sector replacement function in case of that certain sector, reaches certain erase/write times. And power-on-auto-read function is available. It enables to read the data of the lowest sector(2k byte) without command and address data input when power is on. Note: This product is authorized for using consumer application such as cellular phone, Therefore, please contact Renesas Technology's sales office before using other applications. Preliminary: The specifications of this device are subject to change without notice. Please contact your nearest Renesas Technology's Sales Dept. regarding specifications. Rev.0.03, Jun.06.2003, page 1 of 50 HN29V128A1A/A0A, HN29A128A1A/A0A Series Features * On-board single power supply (VCC): VCC = 2.7 V to 3.6 V (HN29V128A1A/HN29V128A0A) : VCC = 1.70 V to 1.95 V (HN29A128A1A/HN29A128A0A) * Operating temperature range: Ta = 0 to +70 C * Program/erase, rewrite endurance 10 times 5 * Access time First access 80 s (typ) (3.3 V, x8/x16) 150 s (typ) (1.8 V, x8/x16) Serial read cycle 50 ns (min) (3.3 V, x8/x16) 100 ns (min) (1.8 V, x8/x16) maximum transfer rate (sequential read) 20.0 Mbyte/s (3.3 V, x8) 40.0 Mbyte/s (3.3 V, x16) 10.0 Mbyte/s (1.8 V, x8) 20.0 Mbyte/s (1.8 V, x16) * Program time 1.2 ms (typ) /sector (2048 byte) (3.3 V, x8/x16) 2.0 ms (typ) /sector (2048 byte) (1.8 V, x8/x16) * Erase time 2.2 ms (typ) /sector (2048 byte) (3.3 V, x8/x16) 3.5 ms (typ) /sector (2048 byte) (1.8 V, x8/x16) * Rewrite time 2.2 ms (typ) /sector (2048 byte) (3.3 V, x8/x16) 3.5 ms (typ) /sector (2048 byte) (1.8 V, x8/x16) Rev.0.03, Jun.06.2003, page 2 of 50 HN29V128A1A/A0A, HN29A128A1A/A0A Series * Low power dissipation (3.3 V and 1.8 V) Standby current ICCS1 = 1 mA (max) ICCS2 = 50 A (max) (CMOS level) ICCS3 = 10 A (max) (3.3 V), 15A (max) (1.8 V) (deep standby) Serial read operation current ICC1 = 30 mA (max) Program/erase/rewrite operation current ICC2/3/4 = 60 mA (max) (program/erase/rewrite) * Sector management Following functions are build-in flash memory component. Sector management: If certain sector had been damaged, it would be replaced by the spare sector automatically. 5 Always 100% of sector number are available up to 10 erase/write cycles per device. Error check and correction: ECC code is generated at the time of programming, and data error is checked at the time of read operation. If data error occurs, the data will be corrected automatically. (ECC: 1-byte error correction, 2-byte error detection per 512byte page) Wear leveling: To avoid erase/program/rewrite operation converge on the particular physical sector, The number of erase/program/rewrite operation will be leveled automatically by changing internal logical sector address. * Package line up CSP: CSP 95-bump (TBP-95V) Ordering Information Type No. Operating voltage (VCC) Organization HN29V128A1ABP-5E 3.3 V x8 10.0 x 11.50 mm , 95-bump HN29V128A0ABP-5E 3.3 V x16 0.8 mm ball pitch CSP (TBP-95V) HN29A128A1ABP-8E 1.8 V x8 Lead free HN29A128A0ABP-8E 1.8 V x16 Rev.0.03, Jun.06.2003, page 3 of 50 Package 2 HN29V128A1A/A0A, HN29A128A1A/A0A Series Pin Arrangement 95-bump CSP 95-bump CSP 1 2 A DU B DU 3 4 5 6 7 8 9 10 11 12 DU DU DU DU DU DU C DU DU DU DU DU DU DU VSS DU DU D DU DU DU DU DU I/O15 MRES I/O8 I/O7 DU E DU WE R/B DU DU I/O13 I/O6 I/O14 I/O16 DU VSS DSE DU PRE I/O5 DU F DU VCC DU G DU WP DU DU I/O3 DU I/O11 I/O4 I/O12 DU H DU DU DU DU DU I/O1 I/O9 I/O2 I/O10 DU J DU CLE DU DU DU DU DU DU DU DU K DU ALE DU DU DU DU VSS RE CE DU L DU DU DU DU M DU DU DU DU (TOP View) Rev.0.03, Jun.06.2003, page 4 of 50 HN29V128A1A/A0A, HN29A128A1A/A0A Series Pin Description Name Description I/O1 to I/O8 Command, address, data input/output I/O9 to I/O16 Data input/output (x8 device: DU) CLE Command latch enable ALE Address latch enable CE Chip enable RE Read enable WE Write enable WP Write protect R/B Ready/busy PRE Power on auto read enable MRES Master reset output DSE Deep standby enable VCC Power supply VSS Ground DU Don't use Note: 1. All VSS pins should be connected respectively. Rev.0.03, Jun.06.2003, page 5 of 50 HN29V128A1A/A0A, HN29A128A1A/A0A Series Pin Function Chip enable :CE CE CE is for selecting a chip and making the device in the active state. During command waiting state, CE=H makes the device standby state. During command execution such as erase, program and rewrite, CE=H can't stop command operation itself. Read enable :RE RE RE is output enable pin and also controls read timing. Clocking RE increments the internal address and reads out each data. Write enable :WE WE Commands, address, and program data are latched into the device at the rising edge of WE. Command latch enable :CLE CLE specifies the command data. When CLE=H, data on I/O bus will be recognized as the command data. The command data is latched on the rising edge of WE with CLE=H. Address latch enable :ALE ALE specifies the address data. When ALE=H, data on I/O bus will be recognized as the address data. The address data is latched on the rising edge of WE with ALE=H. Write protect :WP WP WP=L disables erase, program and rewrite operation. Ready/busy busy :R/B B R/B is the output signal. It shows the internal status of the device to be ready or busy. It is an open-drain signal and should be pulled up to VCC via suitable resistance. Power on auto read enable :PRE PRE is control pin with active high signal. PRE active Power on auto read mode and Auto read mode. If Power on auto read mode and Auto read mode are unnecessary, PRE pin should be connected to VSS or open. Master reset output :MRES MRES MRES is the output signal and for providing a reset signal to CPU when Power on auto read mode and auto read mode are activated. MRES going from low to high indicates that the data is ready for reading. If Power on auto read mode and Auto read mode are not activated, MRES going from low to high indicates that the device initialization is completed after power is on. Deep standby enable :DSE DSE DSE must be low when power is on. The device is initialized by DSE signal low to high after power is on. During command waiting state or standby state, DSE = L makes the device deep standby state. When DSE goes to high, the device returns from the deep standby state. During command execution, DSE = L stops command operation and makes the device deep standby state. Input/output pins :I/O1 to I/O16 The I/O pins are used as input/output data and also as command and address. I/O pins are tri-state pins and transit to the high impedance state when disabled by CE and RE. I/O9 to 16 are effective for x16 product, but they are applied for data only. Only I/O1 to 8 pins are used as command and address inputs for x16 product. Rev.0.03, Jun.06.2003, page 6 of 50 HN29V128A1A/A0A, HN29A128A1A/A0A Series Block Diagram VCC VSS Data output buffer Multiplexer Data input buffer signal buffer control PRE DSE Rev.0.03, Jun.06.2003, page 7 of 50 X-decoder Read/Program/Erase ........................... Control Sector address buffer WE RE WP Y-gating Data register 2,048 Byte MRES CE CLE ALE Y-decoder Input data control ..... I/O1 to 8 I/O8 I/O9 to 16 I/O16 R/B ..... Y-address counter Memory matrix 8,192 2,048 8 8,192 1,024 16 HN29V128A1A/A0A, HN29A128A1A/A0A Series Memory Map and Address 8,192 8,192 0002 0001 0000 Sector address 1FFF 1FFE 1FFD Sector address 1FFF 1FFE 1FFD 0002 0001 0000 512 bytes 256 words 2,048 bytes (8 device) (1) 8 device Page size : (512) bytes Sector size : (2,048) bytes Total device capacity : 2,048 bytes 8,192 sectors 1,024 words (16 device) (2) 16 device Page size : (256) words Sector size : (1,024) words Total device capacity : 1,024 words 8,192 sectors Address Input Case of HN29V128A1A/HN29A128A1A (x x8 device) Clock Cycle I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 First cycle (CA1) A7 A6 A5 A4 A3 A2 A1 A0 Second cycle (CA2) L* L* L* L* L* A10 A9 A8 Third cycle (SA1) A18 A17 A16 A15 A14 A13 A12 A11 Fourth cycle (SA2) L* L* L* A23 A22 A21 A20 A19 I/O3 I/O2 I/O1 Notes: 1. A0 to A8: Column address A11 to A23: Sector address 2. I/O9 to I/O16: VIH or VIL 3. L* must be set to "Low". A9 to A10: Page address Case of HN29V128A0A/HN29A128A0A (x x16 device) Clock Cycle I/O8 I/O7 I/O6 I/O5 I/O4 First cycle (CA1) A7 A6 A5 A4 A3 A2 A1 A0 Second cycle (CA2) L* L* L* L* L* L* A9 A8 Third cycle (SA1) A17 A16 A15 A14 A13 A12 A11 A10 Fourth cycle (SA2) L* L* L* A22 A21 A20 A19 A18 Notes: 1. A0 to A7: Column address A10 to A22: Sector address 2. I/O9 to I/O16: VIH or VIL 3. L* must be set to "Low". Rev.0.03, Jun.06.2003, page 8 of 50 A8 to A9: Page address HN29V128A1A/A0A, HN29A128A1A/A0A Series Mode Selection The address input, command input and data input/output operations of the device are controlled by CLE, ALE, CE, WE, RE WP and DSE signals. The following table shows the operation logic table. Mode CLE ALE CE Command input H L Address input L Data input WE RE WP DSE I/O Power L H x H Input Active H L H x H Input Active L L L H x H Input Active Data output L L L H x H Output Active Output deselect L L L H H x H High-Z Active During rewriting/erasing x x x x x H H Input/ output Active Write protect x x x x x L H Input/ output Active/ standby Standby x x H x x x H High-Z Standby* Deep standby x x x x x x L High-Z Deep 3 standby* 2 Notes: 1. H: VIH, L: VIL, x: VIH or VIL 2. When setting CE = H during the read operation, even if it is in ready state, the device becomes the following data output waiting state and doesn't become standby mode. It becomes standby mode to set CE = H in ready state after read stop command execution. 3. The device can transfer only from command waiting state or standby state to deep standby state. Command Definition Mode First cycle Second cycle Data input 80H Read mode 00H Sequential read mode 0FH Read stop F0H Program 10H Erase 60H D0H Rewrite 1FH Status read 70H ID read 90H Deep standby (release) C1H Deep standby (setup) C0H Rev.0.03, Jun.06.2003, page 9 of 50 Acceptance in the busy state Acceptance (in Read busy state only) Acceptance HN29V128A1A/A0A, HN29A128A1A/A0A Series State transition diagram Power off VCC, DSE VCC, DSE Deep standby (ICCS3) DSE DSE CE DSE CE C0H C1H, Ready DSE PRE Standby (ICCS1/2) PRE Command deep standby (ICCS3) Auto read *SRD setup Ready RE Sector read-(Auto read) PRE W A I T I N G Data output RE F0H F0H Status read Ready,00H PRE C O M M A N D RE 70H PRE RE Read Data output RE Ready Ready, 00H CA SA 00H Read setup CA input 0FH Sequential CA read setup CA input 70H SA input SA SRD setup 70H SA input SRD setup RE Status read RE Status read Sector End Ready, 00H F0H Sequential read PRE SA 60H Erase setup D0H SA input Erase start 70H Erase finish 80H Data input setup SA CA CA input SA input Data input 10H Program start Program finish Rewrite finish 70H *SRD setup Ready RE ID read setup Address input Rewrite start 70H *SRD setup RE Status read RE 90H 1FH 70H Status read RE ID read Note: SRD = Status read data Rev.0.03, Jun.06.2003, page 10 of 50 HN29V128A1A/A0A, HN29A128A1A/A0A Series Absolute Maximum Ratings If exceeded the following specification, the device may be damaged. HN29V128A1A (3.3 V) HN29A128A1A (1.8 V) HN29V128A0A (3.3 V) HN29A128A0A (1.8 V) Parameter Symbol Value Value Unit Notes 1 VCC voltage VCC -0.6 to +4.6 -0.6 to +2.45 V VSS voltage VSS 0 0 V Input voltage VIN -0.6 to +4.6 -0.6 to +2.45 V Input/output voltage VI/O -0.6 to VCC + 0.3 ( 4.6) -0.6 to VCC + 0.3 ( 2.45) V Operating temperature range Topr 0 to +70 0 to +70 C Storage temperature range -55 to +125 -55 to +125 C Tstg 1, 2 3 Notes: 1. Relative to VSS. 2. VIN, VOUT = -2.0 V for pulse width 20 ns 3. Device storage temperature range before programming. Capacitance (Ta = +25C, f = 1 MHz) Parameter Symbol Min Typ Max Unit Test conditions Input capacitance CIN 10 pF VIN = 0 V Output capacitance COUT 10 pF VOUT = 0 V Rev.0.03, Jun.06.2003, page 11 of 50 HN29V128A1A/A0A, HN29A128A1A/A0A Series DC Characteristics DC Characteristics (1) HN29V128A1A (3.3 V) HN29V128A0A (3.3 V) Parameter HN29A128A1A (1.8 V) HN29A128A0A (1.8 V) Test Symbol Min Typ Max Min Typ Max Unit conditions Power supply voltage VCC 2.7 1.95 V High input voltage VIH VCC x 0.8 VCC + VCC x 0.3 0.8 VCC + V 0.3 Low input voltage VIL -0.3 VCC x -0.3 0.2 VCC x V 0.2 High input voltage (DSE, PRE pin) VIHP VCC x 0.9 VCC + VCC x 0.3 0.9 VCC + V 0.3 Low input voltage (DSE, PRE pin) VILP -0.3 VCC x -0.3 0.1 VCC x V 0.1 Input leakage current ILI 2 2 A VIN = 0 V to VCC Output leakage current ILO 2 2 A VOUT = 0 V to VCC Operating current (Serial read) ICC1 30 30 mA CE = VIL RE = VIH (Program) ICC2 60 60 mA (Erase) ICC3 60 60 mA (Rewrite) ICC4 60 60 mA Rev.0.03, Jun.06.2003, page 12 of 50 3.3 3.6 1.70 1.8 HN29V128A1A/A0A, HN29A128A1A/A0A Series DC Characteristics (2) HN29V128A1A (3.3 V) HN29V128A0A (3.3 V) Parameter Symbol Min Standby current (Standby state) ICCS1 HN29A128A1A (1.8 V) HN29A128A0A (1.8 V) Test Typ Max Min Typ Max Unit conditions 1 1 mA CE = VIH, WP = VIH or VIL, PRE = VIHP or VILP or open, DSE = VIHP ICCS2 50 50 A CE = VCC - 0.2 V, WP = VCC 0.2 V or VSS 0.2 V, PRE = VCC 0.2 V or VSS 0.2 V or open, DSE = VCC 0.2 V (Deep standby) ICCS3 Deep standby command 10 15 A CE = VCC 0.2 V, PRE = VCC 0.2 V or VSS 0.2 V or open, DSE = VCC 0.2 V, WP = VCC 0.2 V or VSS 0.2 V (Deep standby) DSE control ICCS3 10 15 A CE = VCC 0.2 V, PRE = VCC 0.2 V or VSS 0.2 V or open, DSE = VSS 0.2 V, WP = VCC 0.2 V or VSS 0.2 V High-level output voltage VOH VCC - 0.2 VCC - 0.2 V IOH = -100 A Low-level output voltage VOL 0.2 0.2 V IOL = 100 A Rev.0.03, Jun.06.2003, page 13 of 50 HN29V128A1A/A0A, HN29A128A1A/A0A Series AC Characteristics (Ta = 0 to +70C) Test Conditions * VCC : 2.7 V to 3.6 V (HN29V128A1A(x8)/HN29V128A0A(x16)) : 1.70 V to 1.95 V (HN29A128A1A(x8)/HN29A128A0A(x16)) * Input pulse levels: 0 V, VCC * Input rise and fall time: 3 ns * Input and Output reference levels: 1/2 VCC / 1/2 VCC * Output load : VCC R1 = 3k Dout 50 pF Rev.0.03, Jun.06.2003, page 14 of 50 R2 = 3k HN29V128A1A/A0A, HN29A128A1A/A0A Series AC Characteristics (1) HN29V128A1A (3.3 V) HN29A128A1A (1.8 V) HN29V128A0A (3.3 V) HN29A128A0A (1.8 V) Parameter Symbol Min Typ Max Min Typ Max Unit CLE setup time tCLS 0 0 ns CLE hold time tCLH 10 20 ns CE setup time tCS 0 0 ns CE hold time tCH 10 20 ns CE high hold time tCEH 15 25 ns Write pulse width tWP 25 65 ns ALE setup time tALS 0 0 ns ALE hold time tALH 10 20 ns Data setup time tDS 20 50 ns Data hold time tDH 10 20 ns Write cycle time tWC 50 100 ns WE high hold time tWH 15 35 ns RE high to WE low time tRHW 50 100 ns RE high to WE low time in Sequential read cycle tRHWS 200 250 ns Ready to WP low time tRW 0 0 ns Ready to RE fall time tRR 20 20 ns Read pulse time tRP 35 80 ns Read cycle time tRC 50 100 ns RE access time (serial data access) tREA 35 80 ns RE access time (ID read) tREAID 35 80 ns RE access time (Status read) tRSTO 35 80 ns Output data hold time tOH 10 10 ns RE high to output high-Z time tRHZ 30 80 ns CE high to output high-Z time tCHZ 30 80 ns RE high hold time tREH 15 20 ns CE access time tCEA 45 100 ns CE access time (status read) tCSTO 45 100 ns WE high to CE low time tWHC 30 50 ns Note: 1. tRHWS applies to Sequential read cycle only. Rev.0.03, Jun.06.2003, page 15 of 50 Note 1 HN29V128A1A/A0A, HN29A128A1A/A0A Series AC Characteristics (2) HN29V128A1A (3.3 V) HN29A128A1A (1.8 V) HN29V128A0A (3.3 V) HN29A128A0A (1.8 V) Parameter Symbol Min Typ Max Min Typ Max Unit WE high to RE low time tWHR 30 100 ns ALE low to RE low time (ID read) tAR1 100 100 ns ALE low to RE low time (read cycle) tAR2 50 100 ns CE low to RE low time (ID read) tCR 100 100 ns Start address access from memory cell array tR 80 250 150 400 s WE high to busy output time tWB 200 200 ns Power on to DSE High time tDSE 0 0 ns DSE high to PRE high delay tPD 50 100 ns DSE high to busy time tDB 5 5 ms Power on busy time tBSY 5 30 5 50 ms Ready to MRES high time tRMRES 50 100 ns Deep standby busy tDBSY 300 500 s Auto read busy time tARBSY 1 1 ms PRE pulse width tPRE 50 100 ns PRE low to busy time tARAS 300 500 s WP setup time tWPS 100 100 ns WP hold time tWPH 100 100 ns Read stop time tRSTP 0 250 0 400 s CE high to WE low setup time tCHWS 5 5 ns WE high to CE low hold time tWHCH 5 5 ns CE high to RE low setup time tCHRS 5 5 ns RE high to CE low hold time tRHCH 5 5 ns Rev.0.03, Jun.06.2003, page 16 of 50 Note HN29V128A1A/A0A, HN29A128A1A/A0A Series Program/Erase/Rewrite Characteristics (HN29V128A1A, HN29V128A0A: 2.7 V to 3.6 V, HN29A128A1A, HN29A128A0A: 1.70 V to 1.95 V, Ta = 0 to +70 C) HN29V128A1A (3.3 V) HN29V128A0A (3.3 V) Parameter Symbol Min Rewrite time tREWRITE Erase time HN29A128A1A (1.8 V) HN29A128A0A (1.8 V) Typ Max Min Typ Max Unit 2.2 100 3.5 150 ms tERS 2.2 100 3.5 150 ms Program time tPROG 1.2 30 2.0 45 ms Number of partial program cycles in the same sector NPPS 4 4 cycles Number of partial program cycles in the same page NPPP 1 1 cycles Note: 1. The data transfer time is not included. Rev.0.03, Jun.06.2003, page 17 of 50 Note HN29V128A1A/A0A, HN29A128A1A/A0A Series Timing Waveforms Power on and off VCC min VCC CE, WE, RE, WP, 0V 0V Don't care Don't care CLE, ALE tDSE DSE VIHP VILP VILP tDB tBSY R/B Operation Invalid Basic timing for command, address and data latch CLE ALE RE CE tCEH tCEH Setup time Hold time WE tDS tDH I/O1 to I/O8 I/O9 to I/O16 (x16) VIH or VIL Rev.0.03, Jun.06.2003, page 18 of 50 HN29V128A1A/A0A, HN29A128A1A/A0A Series Command input cycle CLE tCLH tCLS tCH tCS tWP tALS tALH ALE tDS tDH I/O1 to I/O8 I/O9 to I/O16 ( 16) VIH or VIL Rev.0.03, Jun.06.2003, page 19 of 50 HN29V128A1A/A0A, HN29A128A1A/A0A Series Command input cycle after data output cycle CLE tCLH tCLS tCS tCH CE tWP WE tALS tALH ALE tRHW, tRHWS RE tDS tDH I/O1 to I/O8 I/O9 to I/O16 (16) VIH or VIL Rev.0.03, Jun.06.2003, page 20 of 50 HN29V128A1A/A0A, HN29A128A1A/A0A Series Address input cycle tCLS tCS tCH CLE tCS tWC tWP tCH tWH tALH tALS tALH ALE tDS tDH I/O1 to I/O8 CA(1) CA(2) SA(1) SA(2) I/O9 to I/O16 ( 16) VIH or VIL Data input cycle tCS tCS tCH tCLH CLE tWC tWP tCH tWH tALS ALE tDS tDH I/O1 to I/O8 DIN0 DIN1 DIN2 DIN M DIN1 DIN2 DIN M tDS tDH I/O9 to I/O16 ( 16) DIN0 VIH or VIL Rev.0.03, Jun.06.2003, page 21 of 50 HN29V128A1A/A0A, HN29A128A1A/A0A Series Serial read cycle tCHZ tCEA tCEA CE tRP RE tREH tRHZ tOH I/O1 to I/O8 I/O9 to I/O16 (16) tREA tREA tRR R/B tRC VIH or VIL Rev.0.03, Jun.06.2003, page 22 of 50 HN29V128A1A/A0A, HN29A128A1A/A0A Series Invalid input cycle CE tCHWS tWHCH ALE CLE WE I/O1 to I/O8 I/O9 to I/O16 (x16) VIH or VIL Invalid output cycle CE tCHRS tRHCH ALE CLE RE I/O1 to I/O8 I/O9 to I/O16 (x16) VIH or VIL Rev.0.03, Jun.06.2003, page 23 of 50 HN29V128A1A/A0A, HN29A128A1A/A0A Series Status read This device automatically performs rewriting, programming, erasing, and verification after the operation. This device provides the status read function to indicate the device status and the execution result. The device status is output through the I/O pins by issuing command 70H then inputting the RE clock. The following timing shows the status as the output through the I/O pins. Status read cycle tCLS CLE tCLS tCHZ tCLH tCS tCSTO tCH CE tWP WE tWHC RE tRSTO tWHR tDS I/O1 to I/O8 tRHZ tOH tDH Status output 70H I/O9 to I/O16 (16) 00H VIH or VIL Pin Status Output I/O1 Passed or failed Passed: 0, failed: 1 I/O2 Not used. Reserved for future use 0 I/O3 Not used. Reserved for future use 0 I/O4 Not used. Reserved for future use 0 I/O5 Not used. Reserved for future use 0 I/O6 Not used. Reserved for future use 0 I/O7 Ready or busy Ready: 1, busy: 0 I/O8 Write protection Protected: 0, not protected: 1 I/O9 to I/O16 Not used 00H Note: 1. The passed or failed status indicated through the I/O1 is only valid while the device is in the ready state. Rev.0.03, Jun.06.2003, page 24 of 50 HN29V128A1A/A0A, HN29A128A1A/A0A Series ID read This device holds the ID code which indicates the manufacturer and device information to the application system. The ID code can be read in the following timing. ID read cycle tCLS CLE tCLS tCLH tCS tCH tCH tCS tCR CE WE tALH tALS tALH tAR1 ALE RE tDS I/O1 to I/O8 tREAID tDH 90H tREAID Manufacturer code 00H Device code 07H I/O9 to I/O16 00H 00H VIH or VIL I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 Hexadecimal Manufacturer code 0 0 0 0 0 1 1 1 07H Device code I/O (x8) 3.3 V device 0 1 0 1 0 0 0 1 51H I/O (x8) 1.8 V device 0 1 0 1 0 0 1 0 52H I/O (x16) 3.3 V device 0 1 0 1 0 0 1 1 53H I/O (x16) 1.8 V device 0 1 0 1 0 1 0 0 54H Note: 1. Output of I/O9 to I/O16 at manufacture code and device code is "00H". Rev.0.03, Jun.06.2003, page 25 of 50 HN29V128A1A/A0A, HN29A128A1A/A0A Series Read mode The device enters into the read mode by command 00H. Read command operation is performed per every page. Start address in the page can be specified in a CA (Column address). The operating timing is shown below. CLE CE WE ALE RE R/B Busy N I/O 00H Read mode command CA1 Sector address CA2 SA1 SA2 N N+1 N+2 N+3 Address input Note : Read mode: When start address N is specified serial read is 512-N cycles in case of 8 or 256-N cycles in case of 16. Rev.0.03, Jun.06.2003, page 26 of 50 HN29V128A1A/A0A, HN29A128A1A/A0A Series Read cycle CLE CE WE tALH tALH tAR2 tRC tRHZ ALE tWB tALS RE tRR N I/O1 to I/O8 00H CA1 CA2 Sector address SA1 SA2 I/O9 to I/O16 (16) DOUT N DOUT N+1 DOUT N+2 DOUT M DOUT N DOUT N+1 DOUT N+2 DOUT M tR R/B Note : M is end of page. Rev.0.03, Jun.06.2003, page 27 of 50 VIH or VIL HN29V128A1A/A0A, HN29A128A1A/A0A Series Status read during the read operation The device status can be read out by inputting the status read command 70H in the read mode. Once the device has been set to the status read mode by 70H command, the device will not return to the read mode automatically. However, when the read command 00H is input after ready, the status read mode is reset and the device returns to the read mode. Status read during read mode Ready 00H Input address 70H 00H R/B RE Output data DOUT Status read mode Rev.0.03, Jun.06.2003, page 28 of 50 DOUT DOUT DOUT Normal read mode HN29V128A1A/A0A, HN29A128A1A/A0A Series Read stop cycle Read stop command F0H enables to finish read mode. Read stop command F0H can be accepted in the busy state. Read stop cycle Read cycle Standby mode CLE CE WE ALE RE N I/O1 to I/O8 Read Stop command Sector address 00H CA1 CA2 SA1 SA2 I/O9 to I/O16 (16) DOUT DOUT N N+1 DOUT M DOUT DOUT N N+1 DOUT M F0H tWB tRSTP R/B Note: M is end of page. Rev.0.03, Jun.06.2003, page 29 of 50 VIH or VIL HN29V128A1A/A0A, HN29A128A1A/A0A Series Sequential read mode The device enters into the sequential read mode by command 0FH. This mode performs continuously reading through the pages and the sectors without additional command/address inputs. Start address in the page can be specified in a CA. The operating timing and block diagram are shown below. CLE CE WE ALE RE R/B Busy N I/O 0FH CA1 Sequential read command Sector address CA2 SA1 SA2 N N+1 M 0 1 Address input Note : M is end of sector. Column address N Sector address End of sector address (1FFFH) Rev.0.03, Jun.06.2003, page 30 of 50 Start address Stop sequential read M HN29V128A1A/A0A, HN29A128A1A/A0A Series Sequential read cycle CLE CE WE tALH tALH tAR2 tRC tRHZ ALE tWB tALS RE N I/O1 to I/O8 0FH tRR Sector address CA1 CA2 SA1 SA2 I/O9 to I/O16 (16) DOUT N DOUT N+1 DOUT M DOUT N DOUT N+1 DOUT M tWB tR tR R/B VIH or VIL Note : M is end of sector. Status read during the sequential read operation The device status can be read out by inputting the status read command 70H in the sequential read mode. Once the device has been set to the status read mode by 70H command, the device will not return to the sequential read mode automatically. However, when the read command 00H is input after ready state, the status read mode is reset and the device returns to the sequential read mode. Ready 0FH Input address 70H Ready 00H 70H 00H R/B RE Output data DOUT Status read mode Rev.0.03, Jun.06.2003, page 31 of 50 DOUT DOUT DOUT Sequential read mode (Start sector data) DOUT Status read mode DOUT DOUT DOUT Sequential read mode (Next sector data) HN29V128A1A/A0A, HN29A128A1A/A0A Series Sequential read stop cycle Read stop command F0H enables to finish sequential read mode. After inputting read stop command F0H, the device becomes busy state. And then, the sequential read mode ends and becomes command waiting state when the status returns to ready. Read stop command F0H can be accepted in the busy state. Stop in Ready state Read stop cycle Sequential read cycle Standby mode CLE CE WE tRHWS ALE RE Sequential read command I/O1 to I/O8 N Middle of sector data Sector address 0FH CA1 CA2 SA1 SA2 I/O9 to I/O16 (16) DOUT DOUT N N+1 DOUT M-x DOUT DOUT N N+1 DOUT M-x Read Stop command F0H tWB tRSTP R/B Note: M is end of sector Rev.0.03, Jun.06.2003, page 32 of 50 VIH or VIL HN29V128A1A/A0A, HN29A128A1A/A0A Series Stop in Busy state Read stop cycle Sequential read cycle Standby mode CLE CE WE tRHWS ALE RE Sequential read command I/O1 to I/O8 N Read Stop command Sector address 0FH CA1 CA2 SA1 SA2 I/O9 to I/O16 (16) DOUT DOUT N N+1 DOUT M DOUT DOUT N N+1 DOUT M tWB F0H tRSTP R/B Note: M is end of sector Rev.0.03, Jun.06.2003, page 33 of 50 VIH or VIL HN29V128A1A/A0A, HN29A128A1A/A0A Series Power on auto read / Auto read Power on auto read mode enables to read the data of the lowest sector(2k byte) without command and address data input when power is on. Auto read mode enables to read the data of the lowest sector (2k byte) without command and address data input in the normal operation. Power on auto read and Auto read are activated when power is on. Power on auto read is available and Auto read operates until power is off when these are activated. These are activated after PRE high signal right after DSE goes high. (DSE must be low until Power reaches VCCmin). MRES going low to high indicates that the data is ready for reading. The data of the lowest sector (2k byte) can be output by RE clock without command and address input. After power on read operation, PRE should be kept high. During the normal operation, keeping PRE low for 50 ns or more makes the device transfer to the auto read mode and the data of the lowest sector (2k byte) can be output by RE clock without command and address input. If power on auto read and auto read operation is unnecessary, PRE pin should be connected to VSS or open. Power on auto read VCC VCC min CLE CE WE ALE tDSE DSE VIHP VILP tPD VIHP PRE RE I/O1 to I/O8 I/O9 to I/O16 (16) tDB tBSY DOUT 0 DOUT 1 DOUT 2 DOUT M DOUT 0 DOUT 1 DOUT 2 DOUT M R/B tRMRES MRES Note : M 2047 (8 device) M 1023 (16 device) Rev.0.03, Jun.06.2003, page 34 of 50 HN29V128A1A/A0A, HN29A128A1A/A0A Series Auto read Case of tPRE < tARBSY VCC DSE VIHP CE WE VIH ALE VIL CLE VIL tPRE PRE RE I/O1 to I/O8 I/O9 to I/O16 (16) R/B tWB tARBSY DOUT 0 DOUT 1 DOUT M DOUT 0 DOUT 1 DOUT M tRMRES MRES Note : M 2047 (8 device) M 1023 (16 device) Rev.0.03, Jun.06.2003, page 35 of 50 VIH or VIL HN29V128A1A/A0A, HN29A128A1A/A0A Series Case of tPRE tARBSY VCC DSE VIHP CE WE VIH ALE VIL CLE VIL tPRE PRE RE I/O1 to I/O8 I/O9 to I/O16 (16) R/B tWB tARBSY DOUT 0 DOUT 1 DOUT M DOUT 0 DOUT 1 DOUT M tRMRES MRES Note : M 2047 (8 device) M 1023 (16 device) Note: VIH or VIL 1. When PRE is turned low during busy, after the operation performed now is completed, this device transfer to the auto read mode. Rev.0.03, Jun.06.2003, page 36 of 50 HN29V128A1A/A0A, HN29A128A1A/A0A Series Auto read (Deep standby mode which transferred by the command) Case of tPRE < tARBSY VCC DSE VIHP CE WE ALE CLE tPRE PRE RE I/O1 to I/O8 I/O9 to I/O16 (16) R/B tWB tARBSY DOUT 0 DOUT 1 DOUT M DOUT 0 DOUT 1 DOUT M tRMRES MRES Note : M 2047 (8 device) M 1023 (16 device) Rev.0.03, Jun.06.2003, page 37 of 50 VIH or VIL HN29V128A1A/A0A, HN29A128A1A/A0A Series Case of tPRE tARBSY VCC DSE VIHP CE WE ALE CLE tPRE PRE RE I/O1 to I/O8 I/O9 to I/O16 (16) R/B tWB tARBSY DOUT 0 DOUT 1 DOUT M DOUT 0 DOUT 1 DOUT M tRMRES MRES Note : M 2047 (8 device) M 1023 (16 device) Rev.0.03, Jun.06.2003, page 38 of 50 VIH or VIL HN29V128A1A/A0A, HN29A128A1A/A0A Series Auto read stop cycle Read stop command F0H enables to finish power on auto read mode and auto read mode. Read stop cycle Power on auto read mode or Auto read mode Standby mode CLE CE WE ALE VIL RE Read Stop command I/O1 to I/O8 DOUT DOUT 0 1 DOUT M I/O9 to I/O16 (16) DOUT DOUT 0 1 DOUT M F0H tWB tRSTP R/B PRE VIHP Note : M 2047 (8 device) M 1023 (16 device) Rev.0.03, Jun.06.2003, page 39 of 50 VIH or VIL HN29V128A1A/A0A, HN29A128A1A/A0A Series Program mode The program mode is organized by the data input and the program. Data input command 80H is for the input address and the program data. And program command 10H makes the device start the program (Please refer to the next page). The maximum data size is 2 kbyte (1 kword for x16 device). One sector is divided by 4 pages. The size of page is 512byte. Each page is programmable just one time as well as the normal 2 kbyte programming (Please refer to the figure below). The data at applied sector for program must be erased. The data of erased sector is [FF]. The programmed bits in the sector goes "1" to "0"when they are programmed. 0 to 2047 (8 device) 0 to 1023 (16 device) 0 0 Original data pattern in a sector 511 255 512 256 1023 1024 511 512 1535 1536 767 768 2047 1023 FF pattern FF pattern FF pattern FF pattern FF pattern Data1 FF pattern FF pattern Data2 Data1 FF pattern FF pattern Input data1 Data1 Pattern after program Input data2 Data2 Pattern after program Note: Input only program data. It is not necessary to mask of the previous programmed data. Rev.0.03, Jun.06.2003, page 40 of 50 (8) (16) HN29V128A1A/A0A, HN29A128A1A/A0A Series Program cycle CLE CE WE tWB ALE RE I/O1 to I/O8 I/O9 to I/O16 (16) tPROG 80H CA CA SA SA (1) (2) (1) (2) Column address DIN DIN N N+1 DIN DIN 10H M-1 M DIN DIN N N+1 DIN DIN M-1 M 70H Output status data Sector address R/B Note : N M 2047 (8 device) N M 1023 (16 device) Rev.0.03, Jun.06.2003, page 41 of 50 VIH or VIL 00H HN29V128A1A/A0A, HN29A128A1A/A0A Series Erase mode The erase mode is entered by command 60H. After inputting sector address, command D0H erases the sector data. The erase size is always 2 kbyte and the erase operation must be done in the sector. Erase cycle CLE CE WE tERS ALE tWB RE I/O1 to I/O8 60H SA (1) SA (2) D0H Status read command 70H Status output I/O9 to I/O15 R/B VIH or VIL Rev.0.03, Jun.06.2003, page 42 of 50 HN29V128A1A/A0A, HN29A128A1A/A0A Series Rewrite mode The rewrite mode is organized by the data input and the rewrite. Data input command 80H is for the input address and the rewrite data to be changed. And rewrite command 1FH makes the device start the rewrite (Please refer to the next page). The maximum data size is 2 kbyte (1 kword in case of x16 device). By using rewrite, erase is automatically executed before programming, and the data can be rewritten for the sector. So the data before the programming operation can be either "1" or "0" (Please refer to the figure below). N M Pass I/O 80H CA1 Data input command CA2 SA1 SA2 DIN DIN 1FH Automatic Data input 0 to 2047 (8 device/sector) Rewriting 0 to 1023 (16 device/sector) command Address 70H Status read command Fail R/B 0 to 2047 (8 device) 0 to 1023 (16 device) 0 Original Data Pattern Input Data Pattern Data Pattern after rewrite Rev.0.03, Jun.06.2003, page 43 of 50 N I/O HN29V128A1A/A0A, HN29A128A1A/A0A Series Rewrite cycle CLE CE WE tWB ALE RE I/O1 to I/O8 I/O9 to I/O16 (16) tREWRITE 80H CA CA SA SA (1) (2) (1) (2) Column address DIN DIN N N+1 DIN DIN 1FH M-1 M DIN DIN N N+1 DIN DIN M-1 M 70H Output status data Sector address R/B Note : N M 2047 (8 device) N M 1023 (16 device) Rev.0.03, Jun.06.2003, page 44 of 50 VIH or VIL 00H HN29V128A1A/A0A, HN29A128A1A/A0A Series Notes on usage 1. Prohibition of undefined command input The commands listed in the command definition can only be used in this device. It is prohibited to issue a command that is not defined in the list. If an undefined command is issued, the data held in the device may be lost. 2. Limitation of command input in the busy state In the busy state, following two commands are acceptable. Do not issue any other command except below two commands. * Status read 70H * Read stop F0H (during read option) 3. Commands that can be issued after the serial input command (80H) After the serial input command (80H) is issued, the rewriting and programming command (1FH, 10H) can be issued; do not issue any other command except 1FH and 10H after 80H. 4. R/B B(Ready/busy busy) busy pin handing R/B is an open-drain output pin, and it should be pulled up to VCC with a resistance(more than 2k). 5. Notes on turning power on and off The input signal levels may be unstable after power is on or off. In order to prevent unexpected operation, use DSE as shown below. VCC min VCC CE, WE, RE, WP, 0V 0V Don't care Don't care CLE, ALE tDSE DSE VIHP VILP VILP tDB R/B Invalid Rev.0.03, Jun.06.2003, page 45 of 50 tBSY Operation HN29V128A1A/A0A, HN29A128A1A/A0A Series 6. Notes on WP signal When WP is at the low level, the rewriting operation is disabled. When using WP to control the operation, satisfy the timing shown below. Operation enable WE 1st com D IN 2nd com WP R/B tRW tWPS Operation disable WE 1st com D IN 2nd com WP tWPH R/B tWPS 1st com 2nd com Erase 60H D0H Program 80H 10H Rewrite 80H 1FH 7. Notes on RE signal If the RE clock is sent before the address is input, the internal read operation may start unintentionally. Be sure to send the RE clock after the address is input. Rev.0.03, Jun.06.2003, page 46 of 50 HN29V128A1A/A0A, HN29A128A1A/A0A Series 8. Deep standby mode During command waiting or standby state, when DSE pin goes to low, the device transfers to deep standby state. When DSE goes to high, the device returns from the deep standby state. During command execution, going DSE low stops command operation. If DSE goes to low during erase/program/rewrite operation, the command operation is forced to terminate and the applied sector data is not guaranteed. Standby state Deep standby state tDBSY Standby state DSE R/B When CE becomes high after the C0H command input, the state of this device transfers to the deep standby state. When CE becomes high after the C1H command input, the state of this device transfers from the deep standby state to the standby state. Deep standby release command Deep standby setup command DIN tDBSY Deep standby state Standby state C0H CE, WE R/B Rev.0.03, Jun.06.2003, page 47 of 50 C1H Standby state HN29V128A1A/A0A, HN29A128A1A/A0A Series 9. Notes on the power supply down Please do not turn off a power supply in busy status. It is recommended to take either of following (1) or (2) measures on system side for unexpected power down. (1) Please set DSE=L when detecting the power down. And erase any sector after the power supply is on. The other sectors data is protected though applied sector data is invalid by doing this. VCC 2.4V (3.3V device) 1.6V (1.8V device) 1ms min DSE (2) Please store the operation record for back up. When the power down is recognized to have occurred during erase/program/rewrite operation, erase applied sector after the power on. The other sectors data is protected though applied sector data is invalid by doing this. Rev.0.03, Jun.06.2003, page 48 of 50 HN29V128A1A/A0A, HN29A128A1A/A0A Series Package Dimensions HN29V128A1ABP, HN29V128A0ABP, HN29A128A1ABP, HN29A128A0ABP Series (TBP-95V) Unit: mm B 10.00 0.80 0.60 12 0.80 0.20 S B 11 10 9 11.50 A 8 7 6 A 5 4 3 INDEX 2 4x 1.35 0.20 S A 1 0.15 0.20 S M L K J H G F E D C B A 95 x 0.40 0.05 0.08 M S A B 1.2 Max 0.10 S 0.20 0.05 S Details of the part A Note: DatumA, B are defined as center line of terminal matrix. Package CODE JEDEC JEITA Mass (reference value) Rev.0.03, Jun.06.2003, page 49 of 50 TBP-95V - - 0.25 g HN29V128A1A/A0A, HN29A128A1A/A0A Series Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corporation or a third party. 2. Renesas Technology Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corporation by various means, including the Renesas Technology Corporation Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corporation for further details on these materials or the products contained therein. http://www.renesas.com Copyright (c) 2003. Renesas Technology Corporation, All rights reserved. Printed in Japan. Colophon 0.0 Rev.0.03, Jun.06.2003, page 50 of 50