Rev.0.03, Jun.06.2003, page 1 of 50
HN29V128A1A (3.3 V/×
××
×8)
HN29V128A0A (3.3 V/×
××
×16)
HN29A128A1A (1.8 V/×
××
×8)
HN29A128A0A (1.8 V/×
××
×16)
128M superAND Flash Memory
(with internal sector management) REJ03C0031-0003Z
(Previous ADE-203-1344B (Z) Rev.0.2)
Preliminary
Rev. 0.03
Jun. 06, 2003
Description
The HN29V128A1A, HN29V128A0A, HN29A128A1A, and HN29A128A0A Series is a CMOS flash
memory, which uses cost effective and high performance AND type multi-level memory cell technology.
Current AND flash memory requires us to support complicated operations such as sector management for
defect sector and error check correction. But this series doesn’t need such operations. Beside it supports
wear leveling function, which is sector replacement function in case of that certain sector, reaches certain
erase/write times. And power-on-auto-read function is available. It enables to read the data of the lowest
sector(2k byte) without command and address data input when power is on.
Note: This product is authorized for using consumer application such as cellular phone,
Therefore, please contact Renesas Technology’s sales office before using other applications.
Preliminary: The specifications of this device are subject to change without notice. Please contact your
nearest Renesas Technology’s Sales Dept. regarding specifications.
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Rev.0.03, Jun.06.2003, page 2 of 50
Features
• On-board single power supply (VCC): VCC = 2.7 V to 3.6 V (HN29V128A1A/HN29V128A0A)
: VCC = 1.70 V to 1.95 V (HN29A128A1A/HN29A128A0A)
• Operating temperature range: Ta = 0 to +70 °C
• Program/erase, rewrite endurance
105 times
• Access time
First access
80 µs (typ) (3.3 V, ×8/×16)
150 µs (typ) (1.8 V, ×8/×16)
Serial read cycle
50 ns (min) (3.3 V, ×8/×16)
100 ns (min) (1.8 V, ×8/×16)
maximum transfer rate (sequential read)
20.0 Mbyte/s (3.3 V, ×8)
40.0 Mbyte/s (3.3 V, ×16)
10.0 Mbyte/s (1.8 V, ×8)
20.0 Mbyte/s (1.8 V, ×16)
• Program time
1.2 ms (typ) /sector (2048 byte) (3.3 V, ×8/×16)
2.0 ms (typ) /sector (2048 byte) (1.8 V, ×8/×16)
• Erase time
2.2 ms (typ) /sector (2048 byte) (3.3 V, ×8/×16)
3.5 ms (typ) /sector (2048 byte) (1.8 V, ×8/×16)
• Rewrite time
2.2 ms (typ) /sector (2048 byte) (3.3 V, ×8/×16)
3.5 ms (typ) /sector (2048 byte) (1.8 V, ×8/×16)
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Rev.0.03, Jun.06.2003, page 3 of 50
• Low power dissipation (3.3 V and 1.8 V)
Standby current
ICCS1 = 1 mA (max)
ICCS2 = 50 µA (max) (CMOS level)
ICCS3 = 10 µA (max) (3.3 V), 15µA (max) (1.8 V) (deep standby)
Serial read operation current
ICC1 = 30 mA (max)
Program/erase/rewrite operation current
ICC2/3/4 = 60 mA (max) (program/erase/rewrite)
• Sector management
Following functions are build-in flash memory component.
Sector management:
If certain sector had been damaged, it would be replaced by the spare sector automatically.
Always 100% of sector number are available up to 105 erase/write cycles per device.
Error check and correction:
ECC code is generated at the time of programming, and data error is checked at the time of read
operation. I f data error occu r s, the data will be corrected automatically.
(ECC: 1-byte error correction, 2-byte error detection per 512byte page)
Wear leveling:
To avoid erase/program/rewrite operation converge on the particular physical sector, The number of
erase/progr am/rewrite opera tion will be leveled automatically by changing internal logical sector
address.
• Package line up
CSP: CSP 95-bump (TBP-95V)
Ordering Information
Type No. Operating voltage (VCC) Organization Package
HN29V128A1ABP-5E 3.3 V ×8 10.0 × 11.50 mm2, 95-bump
HN29V128A0ABP-5E 3.3 V ×16 0.8 mm ball pitch CSP (TBP-95V)
HN29A128A1ABP-8E 1.8 V ×8 Lead free
HN29A128A0ABP-8E 1.8 V ×16
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Rev.0.03, Jun.06.2003, page 4 of 50
Pin Arrangement 95-bump CSP
1
DU DU
DU DU
DU
DU
DU
DU
DU
DU
DU
DU
DU
WE
V
SS
WP
DU
CLE
ALE
DU
DU
R/
B
DSE
DU
DU
DU
DU
DU
DU
DU
DU
DU
DU
DU
DU
(TOP View)
95-bump CSP
DU
DU
DU
PRE
I/O3
DU
DU
DU
DU
I/O15
I/O13
I/O5
DU
I/O1
DU
DU
DU
I/O6
DU
I/O11 I/O4
I/O9
DU
V
SS
DU
DU
I/O2
DU
RE
MRES
I/O7I/O8
I/O14 I/O16
V
CC
V
SS
I/O12
I/O10
DU
CE
DU
DU
DU
DU
DU
DU
DU
DU
DU
DU
DU
DU
DU
DU
DU
DU
DU
DU
DU
DU
A
B
C
D
E
F
G
H
J
K
L
M
23456789101112
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Rev.0.03, Jun.06.2003, page 5 of 50
Pin Description
Name Description
I/O1 to I/O8 Command, address, data input/output
I/O9 to I/O16 Data input/output (×8 device: DU)
CLE Command latch enable
ALE Address latch enable
CE Chip enable
RE Read enable
WE Write enable
WP Write protect
R/B Ready/busy
PRE Power on auto read enable
MRES Master reset output
DSE Deep standby enable
VCC Power supply
VSS Ground
DU Don’t use
Note: 1. All VSS pins should be connected respectively.
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Rev.0.03, Jun.06.2003, page 6 of 50
Pin Function
Chip enable :CE
CECE
CE
CE is for selecting a chip and making the device in the active state.
During command waiting state, CE=H makes the device standby state.
During command execution such as erase, program and rewrite, CE=H can’t stop command operation
itself.
Read enable :RE
RERE
RE
RE is output enable pin and also controls read timing. Clocking RE increments the internal address and
reads out each data.
Write enable :WE
WEWE
WE
Commands, address, and program data are latched into the device at the rising edge of WE.
Command lat ch enable :CLE
CLE specifies the command data. When CLE=H, data on I/O bus will be recognized as the command data.
The command data is latched on the rising edge of WE with CLE=H.
Address latch enable :ALE
ALE specifies the address data. When ALE=H, data on I/O bus will be recognized as the address data.
The address data is latched on the rising edge of WE with ALE=H.
Write protect :WP
WPWP
WP
WP=L disables erase, program and rewrite operation.
Ready/busy
busybusy
busy :R/B
BB
B
R/B is the output signal. It shows the internal status of the device to be ready or busy.
It is an open-drain signal and should be pulled up to VCC via suitable resistance.
Power on auto read enable :PRE
PRE is control pin with active high signal. PRE active Power on auto read mode and Auto read mode. If
Power on auto read mode and Auto read mode are unnecessary, PRE pin should be connected to VSS or
open.
Master reset output :MRES
MRESMRES
MRES
MRES is the output signal and for providing a reset signal to CPU when Power on auto read mode and auto
read mode are activated. MRES going from low to high indicates that the data is ready for reading.
If Power on auto read mode and Auto read mode are not activated, MRES going from low to high indicates
that the device in itialization is completed after power is on.
Deep standby enable :DSE
DSEDSE
DSE
DSE must be low when power is on. The device is initialized b y DSE signal low to high after power is on.
During command waiting state or standby state, DSE = L makes the device deep standby state. When DSE
goes to high, the device returns from the deep standby state. During command execution, DSE = L stops
command operation and makes the device deep standby state.
Input/output pins :I/O1 to I/O 16
The I/O pins are used as input/output data and also as command and address.
I/O pins are tri-state pins and transit to the high impedance state when disabled by CE and RE.
I/O9 to 16 are effective for ×16 product, but they are applied for data only.
Only I/O1 to 8 pins are used as command and address inputs for ×16 product.
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Rev.0.03, Jun.06.2003, page 7 of 50
Block Diagram
Multiplexer
I/O1
´
8
´
16
I/O8
I/O9
I/O16
R/
B
MRES
CE
WE
RE
WP
DSE
CLE
ALE
PRE
to
to
VCC VSS
Read/Program/Erase
control
Control
signal buffer
Y-address counter
Y-decoder
Y-gating
Sector address buffer
X-decoder
...........................
Memory matrix
8,192
´
2,048
´
8
8,192
´
1,024
´
16
Data register 2,048 Byte
Input data
control
Data input
buffer
Data output
buffer
..........
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Rev.0.03, Jun.06.2003, page 8 of 50
Memory Map and Address
1FFF
1FFE
1FFD
Sector address
8,192
0002
0001
0000
512 bytes
2,048 bytes
(1)
´
8 device
Page size : (512) bytes
Sector size : (2,048) bytes
Total device capacity : 2,048 bytes
´
8,192 sectors
(2)
´
16 device
Page size : (256) words
Sector size : (1,024) words
Total device capacity : 1,024 words
´
8,192 sectors
(
´
8 device)
1FFF
1FFE
1FFD
Sector address
8,192
0002
0001
0000
256 words
1,024 words
(
´
16 device)
Address Input
Case of HN29V128A1A/HN29A128A1A (×
××
×8 device)
Clock Cycle I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1
First cycle (CA1) A7 A6 A5 A4 A3 A2 A1 A0
Second cycle (CA2) L* L* L* L* L* A10 A9 A8
Third cycle (SA1) A18 A17 A16 A15 A14 A13 A12 A11
Fourth cycle (SA2) L* L* L* A23 A22 A21 A20 A19
Notes: 1. A0 to A8: Column address A9 to A10: Page address
A11 to A23: Sector address
2. I/O9 to I/O16: VIH or VIL
3. L* must be set to “Low”.
Case of HN29V128A0A/HN29A128A0A (×
××
×16 device)
Clock Cycle I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1
First cycle (CA1) A7 A6 A5 A4 A3 A2 A1 A0
Second cycle (CA2) L* L* L* L* L* L* A9 A8
Third cycle (SA1) A17 A16 A15 A14 A13 A12 A11 A10
Fourth cycle (SA2) L* L* L* A22 A21 A20 A19 A18
Notes: 1. A0 to A7: Column address A8 to A9: Page address
A10 to A22: Sector address
2. I/O9 to I/O16: VIH or VIL
3. L* must be set to “Low”.
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Rev.0.03, Jun.06.2003, page 9 of 50
Mode Selection
The address input, command input and data input/output operations of the device are controlled by CLE,
ALE, CE, WE, RE WP and DSE signals. The following table shows the operation logic table.
Mode CLE ALE CE
CECE
CE
WE
WEWE
WE
RE
RERE
RE
WP
WPWP
WP
DSE
DSEDSE
DSE
I/O Power
Command input H L L H × H Input Active
Address input L H L H × H Input Active
Data input L L L H × H Input Active
Data output L L L H × H Output Active
Output deselect L L L H H × H High-Z Active
During
rewriting/erasing × × × × × H H Input/
output Active
Write protect × × × × × L H Input/
output Active/
standby
Standby × × H × × × H High-Z Standby*2
Deep standby × × × × × × L High-Z Deep
standby*3
Notes: 1. H: VIH, L: VIL, ×: VIH or VIL
2. When setting CE = H during the read operation, even if it is in ready state, the device becomes
the following data output waiting state and doesn’t become standby mode. It becomes standby
mode to set CE = H in ready state after read stop command execution.
3. The device can transfer only from command waiting state or standby state to deep standby state.
Command Definition
Mode First cycle Second cycle Acceptance in the busy state
Data input 80H
Read mode 00H
Sequential read mode 0FH
Read stop F0H Acceptance (in Read busy state only)
Program 10H
Erase 60H D0H
Rewrite 1FH
Status read 70H Acceptance
ID read 90H
Deep standby (release) C1H
Deep standby (setup) C0H
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Rev.0.03, Jun.06.2003, page 10 of 50
State transition diagram
Deep standby (I
CCS3
)
Standby
(I
CCS1/2
)
Auto read
Sector read-(Auto read)
Read
*SRD setup
Data output
Data output
Ready, 00H
Ready,00H
70H
RE
RE
CE
CE
DSE
DSE
RE
RE
RE
RE
RE
Ready
Ready
Sector End
D0H 70H
70H
70H
10H
1FH
Erase finish
Program finish
Rewrite finish
Ready
Ready, 00H
Status
read
Status readSRD setupSA inputCA inputRead setup
Status read
Sequential read
SRD setupSA inputCA input
Sequential
read setup
SA input
Erase setup
CA input SA input Data input
Status
read
ID read
Status
read
*SRD setup
*SRD setup
ID read setup
Note: SRD = Status read data
Address input
Program start
Rewrite start
Data input
setup
Erase start
Command
deep standby
(I
CCS3
)
Power off
F0H
F0H
C1H, Ready
PRE
PRE
C0H
PRE
PRE
PRE
V
CC,
DSE
00H
CA
CA
SA 70H
70HSA
F0H
60H
80H
70H
90H
SA
CA SA
0FH
RE
RE
RE
RE
C
O
M
M
A
N
D
W
A
I
T
I
N
G
DSE
PRE
V
CC,
DSE
DSE
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Rev.0.03, Jun.06.2003, page 11 of 50
Absolute Maximum Ratings
If exceeded the following specification, the device may be damaged.
HN29V128A1A (3.3 V)
HN29V128A0A (3.3 V) HN29A128A1A (1.8 V)
HN29A128A0A (1.8 V)
Parameter Symbol Value Value Unit Notes
VCC voltage VCC −0.6 to +4.6 −0.6 to +2.45 V 1
VSS voltage VSS 0 0 V
Input voltage VIN −0.6 to +4.6 −0.6 to +2.45 V 1, 2
Input/output voltage VI/O −0.6 to VCC + 0.3
(≤ 4.6) −0.6 to VCC + 0.3
(≤ 2.45) V
Operating temperature range Topr 0 to +70 0 to +70 °C
Storage temperature range Tstg −55 to +125 −55 to +125 °C 3
Notes: 1. Relative to VSS.
2. VIN, VOUT = −2.0 V for pulse width ≤ 20 ns
3. Device storage temperature range before programming.
Capacitance (Ta = +25°
°°
°C, f = 1 MHz)
Parameter Symbol Min Typ Max Unit Test conditions
Input capacitance CIN 10 pF VIN = 0 V
Output capacitance COUT 10 pF VOUT = 0 V
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Rev.0.03, Jun.06.2003, page 12 of 50
DC Characteristics
DC Characteristics (1)
HN29V128A1A
(3.3 V)
HN29V128A0A
(3.3 V)
HN29A128A1A
(1.8 V)
HN29A128A0A
(1.8 V)
Test
Parameter Symbol Min Typ Max Min Typ Max Unit conditions
Power supply voltage VCC 2.7 3.3 3.6 1.70 1.8 1.95 V
High input voltage VIH VCC ×
0.8 VCC +
0.3 VCC ×
0.8 VCC +
0.3 V
Low input voltage VIL −0.3 VCC ×
0.2 −0.3 VCC ×
0.2 V
High input voltage
(DSE, PRE pin) VIHP V
CC ×
0.9 VCC +
0.3 VCC ×
0.9 VCC +
0.3 V
Low input voltage
(DSE, PRE pin) VILP −0.3 VCC ×
0.1 −0.3 VCC ×
0.1 V
Input leakage current ILI ±2 ±2 µA VIN = 0 V to VCC
Output leakage current ILO ±2 ±2 µA VOUT = 0 V to VCC
Operating current
(Serial read) ICC1 30 30 mA CE = VIL
RE = VIH
(Program) ICC2 60 60 mA
(Erase) ICC3 60 60 mA
(Rewrite) ICC4 60 60 mA
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Rev.0.03, Jun.06.2003, page 13 of 50
DC Characteristics (2)
HN29V128A1A
(3.3 V)
HN29V128A0A
(3.3 V)
HN29A128A1A
(1.8 V)
HN29A128A0A
(1.8 V)
Test
Parameter Symbol Min Typ Max Min Typ Max Unit conditions
Standby current
(Standby state) ICCS1 1 1 mA CE = VIH, WP = VIH or VIL,
PRE = VIHP or VILP or open,
DSE = VIHP
I
CCS2 50 50 µA CE = VCC − 0.2 V,
WP = VCC ± 0.2 V or VSS ±
0.2 V, PRE = VCC ± 0.2 V or
VSS ± 0.2 V or open, DSE =
VCC ± 0.2 V
(Deep standby)
Deep standby command ICCS3 10 15 µA CE = VCC ± 0.2 V,
PRE = VCC ± 0.2 V or VSS ±
0.2 V or open, DSE = VCC ±
0.2 V, WP = VCC ± 0.2 V or
VSS ± 0.2 V
(Deep standby)
DSE control ICCS3 10 15 µA CE = VCC ± 0.2 V,
PRE = VCC ± 0.2 V or VSS ±
0.2 V or open, DSE = VSS ±
0.2 V, WP = VCC ± 0.2 V or
VSS ± 0.2 V
High-level output voltage VOH V
CC −
0.2 V
CC −
0.2 V IOH = −100 µA
Low-level output voltage VOL 0.2 0.2 V IOL = 100 µA
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Rev.0.03, Jun.06.2003, page 14 of 50
AC Characteristics (Ta = 0 to +70°C)
Test Condit ions
• VCC : 2.7 V to 3.6 V (HN29V128A1A(×8)/HN29V128A0A(×16))
: 1.70 V to 1.95 V (HN29A128A1A(×8)/HN29A128A0A(×16))
• Input pulse levels: 0 V, VCC
• Input rise and fall time: 3 ns
• Input and Output reference levels: 1/2 VCC / 1/2 VCC
• Output load :
Dout R1 = 3kΩ
V
CC
R2 = 3kΩ
50 pF
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Rev.0.03, Jun.06.2003, page 15 of 50
AC Characteristics (1)
HN29V128A1A (3.3 V)
HN29V128A0A (3.3 V) HN29A128A1A (1.8 V)
HN29A128A0A (1.8 V)
Parameter Symbol Min Typ Max Min Typ Max Unit Note
CLE setup time tCLS 0 0 ns
CLE hold time tCLH 10 20 ns
CE setup time tCS 0 0 ns
CE hold time tCH 10 20 ns
CE high hold time tCEH 15 25 ns
Write pulse width tWP 25 65 ns
ALE setup time tALS 0 0 ns
ALE hold time tALH 10 20 ns
Data setup time tDS 20 50 ns
Data hold time tDH 10 20 ns
Write cycle time tWC 50 100 ns
WE high hold time tWH 15 35 ns
RE high to WE low time tRHW 50 100 ns
RE high to WE low time in
Sequential read cycle tRHWS 200 250 ns 1
Ready to WP low time tRW 0 0 ns
Ready to RE fall time tRR 20 20 ns
Read pulse time tRP 35 80 ns
Read cycle time tRC 50 100 ns
RE access time
(serial data access) tREA 35 80 ns
RE access time
(ID read) tREAID 35 80 ns
RE access time
(Status read) tRSTO 35 80 ns
Output data hold time tOH 10 10 ns
RE high to output high-Z time tRHZ 30 80 ns
CE high to output high-Z time tCHZ 30 80 ns
RE high hold time tREH 15 20 ns
CE access time tCEA 45 100 ns
CE access time
(status read) tCSTO 45 100 ns
WE high to CE low time tWHC 30 50 ns
Note: 1. tRHWS applies to Sequential read cycle only.
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Rev.0.03, Jun.06.2003, page 16 of 50
AC Characteristics (2)
HN29V128A1A (3.3 V)
HN29V128A0A (3.3 V) HN29A128A1A (1.8 V)
HN29A128A0A (1.8 V)
Parameter Symbol Min Typ Max Min Typ Max Unit Note
WE high to RE low time tWHR 30 100 ns
ALE low to RE low time
(ID read) tAR1 100 100 ns
ALE low to RE low time
(read cycle) tAR2 50 100 ns
CE low to RE low time
(ID read) tCR 100 100 ns
Start address access from
memory cell array tR 80 250 150 400 µs
WE high to busy output time tWB 200 200 ns
Power on to DSE High time tDSE 0 0 ns
DSE high to PRE high delay tPD 50 100 ns
DSE high to busy time tDB 5 5 ms
Power on busy time tBSY 5 30 5 50 ms
Ready to MRES high time tRMRES 50 100 ns
Deep standby busy tDBSY 300 500 µs
Auto read busy time tARBSY 1 1 ms
PRE pulse width tPRE 50 100 ns
PRE low to busy time tARAS 300 500 µs
WP setup time tWPS 100 100 ns
WP hold time tWPH 100 100 ns
Read stop time tRSTP 0 250 0 400 µs
CE high to WE low setup time tCHWS 5 5 ns
WE high to CE low hold time tWHCH 5 5 ns
CE high to RE low setup time tCHRS 5 5 ns
RE high to CE low hold time tRHCH 5 5 ns
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Rev.0.03, Jun.06.2003, page 17 of 50
Program/Erase/Rewrite Characteristics
(HN29V128A1A, HN29V128A0A: 2.7 V to 3.6 V,
HN29A128A1A, HN29A128A0A: 1.70 V to 1.95 V,
Ta = 0 to +70 °C)
HN29V128A1A (3.3 V)
HN29V128A0A (3.3 V) HN29A128A1A (1.8 V)
HN29A128A0A (1.8 V)
Parameter Symbol Min Typ Max Min Typ Max Unit Note
Rewrite ti me t REWRITE 2.2 100 3.5 150 ms
Erase time tERS 2.2 100 3.5 150 ms
Program time tPROG 1.2 30 2.0 45 ms
Number of partial
program cycles in the
same sector
NPPS 4 4 cycles
Number of partial
program cycles in the
same page
NPPP 1 1 cycles
Note: 1. The data transfer time is not included.
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Rev.0.03, Jun.06.2003, page 18 of 50
Timing Waveforms
Power on and off
Don't care
Don't care
Invalid
Operation
t
DB
V
CC
R/
B
CE
,
WE
,
RE
,
WP
,
CLE, ALE
0V
V
CC
min
V
ILP
V
ILP
DSE
V
IHP
t
BSY
t
DSE
0V
Basic timing for command, address and data la t c h
CLE
ALE
I/O1 to
I/O8
I/O9 to
I/O16
VIH or VIL
Setup time
tDS tDH
Hold time
tCEH tCEH
(×16)
CE
WE
RE
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Rev.0.03, Jun.06.2003, page 19 of 50
Command input cycle
I/O1 to
I/O8
I/O9 to
I/O16
(16)
VIH or VIL
tDS
tALS
ALE
CLE
tWP
tCS
tALH
tDH
tCH
tCLH
tCLS
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Rev.0.03, Jun.06.2003, page 20 of 50
Command input cycle a fter data o ut put cycle
WE
CE
I/O1 to
I/O8
I/O9 to
I/O16
(
´
16)
V
IH
or V
IL
t
DS
CLE
t
WP
t
DH
t
CLS
ALE
t
CLH
t
CS
t
CH
t
ALS
t
ALH
RE
t
RHW,
t
RHWS
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Rev.0.03, Jun.06.2003, page 21 of 50
Address input cycle
I/O1 to
I/O8
I/O9 to
I/O16
(16)
VIH or VIL
ALE
CLE tCLS tCS tCH
tCS tWC tCH
tWP
tALS tALH
tWH tALH
tDS tDH
CA(1) CA(2) SA(1) SA(2)
Data input cycle
I/O1 to
I/O8
I/O9 to
I/O16
(16)
V
IH
or V
IL
ALE
CLE
t
CS
t
CS
t
CH
t
WC
t
CH
t
CLH
t
WP
t
ALS
t
WH
t
DS
t
DH
DIN0 DIN1 DIN2 DIN M
t
DS
t
DH
DIN0 DIN1 DIN2 DIN M
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Rev.0.03, Jun.06.2003, page 22 of 50
Serial read cycle
RE
CE
I/O1 to
I/O8
I/O9 to
I/O16
(
´
16)
V
IH
or V
IL
R/
B
t
CEA
t
CEA
t
RP
t
REH
t
OH
t
REA
t
REA
t
RR
t
RC
t
CHZ
t
RHZ
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Rev.0.03, Jun.06.2003, page 23 of 50
Invalid input cycle
I/O1 to
I/O8
I/O9 to
I/O16
V
IH
or V
IL
t
WHCH
t
CHWS
ALE
CE
WE
CLE
(×16)
Invalid output cycle
V
IH
or V
IL
t
RHCH
t
CHRS
I/O1 to
I/O8
I/O9 to
I/O16
ALE
CE
RE
CLE
(×16)
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Rev.0.03, Jun.06.2003, page 24 of 50
Status read
This device automatically performs rewriting, programming, erasing, and verification after the operation.
This device provides the status read function to indicate the device status and the execution result. The
device status is output through the I/O pins by issuing command 70H then inputting the RE clock. The
following timing shows the status as the output through the I/O pins.
Status read cycle
RE
WE
CE
CLE
I/O1 to
I/O8
I/O9 to
I/O16
(
´
16)
V
IH
or V
IL
t
CLS
t
CLS
t
CLH
t
CS
t
CH
t
WP
t
WHC
t
WHR
t
DH
Status
output
70H
00H
t
RHZ
t
OH
t
RSTO
t
DS
t
CSTO
t
CHZ
Pin Status Output
I/O1 Passed or failed Passed: 0, failed: 1
I/O2 Not used. Reserved for future use 0
I/O3 Not used. Reserved for future use 0
I/O4 Not used. Reserved for future use 0
I/O5 Not used. Reserved for future use 0
I/O6 Not used. Reserved for future use 0
I/O7 Ready or busy Ready: 1, busy: 0
I/O8 Write protection Protected: 0, not protected: 1
I/O9 to I/O16 Not used 00H
Note: 1. The passed or failed status indicated through the I/O1 is only valid while the device is in the
ready state.
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Rev.0.03, Jun.06.2003, page 25 of 50
ID read
This device holds the ID code which indicates the manufacturer and device information to the application
system. The ID code can be read in the following timing.
ID read cycle
WE
RE
CE
CLE
ALE
I/O1 to
I/O8
I/O9 to
I/O16
90H 00H 07H
00H 00H
Device
code
Manufacturer
code
V
IH
or V
IL
t
CLS
t
CLH
t
CS
t
CH
t
CR
t
AR1
t
ALH
t
ALS
t
ALH
t
DH
t
REAID
t
REAID
t
DS
t
CLS
t
CH
t
CS
I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 Hexadecimal
Manufacturer code 0 0 0 0 0 1 1 1 07H
Device code
I/O (×8) 3.3 V device
0
1
0
1
0
0
0
1
51H
I/O (×8) 1.8 V device 0 1 0 1 0 0 1 0 52H
I/O (×16) 3.3 V device 0 1 0 1 0 0 1 1 53H
I/O (×16) 1.8 V device 0 1 0 1 0 1 0 0 54H
Note: 1. Output of I/O9 to I/O16 at manufacture code and device code is “00H”.
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Rev.0.03, Jun.06.2003, page 26 of 50
Read mode
The device enters into the read mode by command 00H. Read command operation is performed per every
page. Start address in the page can be specified in a CA (Column address). The operating timing is shown
below.
00H
Read mode
command Address input
CA1 CA2 SA1 SA2
Busy
N
N Sector address
N+1 N+2 N+3
WE
RE
CE
CLE
ALE
I/O
Note : Read mode: When start address N is specified serial read is 512-N cycles in case of
´
8 or 256-N cycles in case of
´
16.
R/
B
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Rev.0.03, Jun.06.2003, page 27 of 50
Read cycle
RE
R/
B
ALE
CLE
I/O1 to
I/O8
I/O9 to
I/O16
(
´
16)
WE
CE
Note : M is end of page.
t
RHZ
t
RC
t
AR2
t
ALH
t
WB
t
R
t
ALS
t
RR
t
ALH
N Sector address
DOUT
M
D
OUT
N
D
OUT
N
D
OUT
N+2
D
OUT
N+1
D
OUT
N+1 D
OUT
N+2
SA2SA1CA2CA100H
DOUT
M
V
IH
or V
IL
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Rev.0.03, Jun.06.2003, page 28 of 50
Status read during t he read operation
The device status can be read out by inputting the status read command 70H in the read mode. Once the
device has been set to the status read mode by 70H co mmand, the d e vice will not return to the read mode
automatically. However, when the read command 00H is input after ready, the status read mode is reset and
the device returns to the read mode.
Status read during read mode
DOUT DOUT DOUT DOUT
70H
Status read mode
Ready
Output data
RE
R/
B
Normal read mode
00H00H Input address
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Rev.0.03, Jun.06.2003, page 29 of 50
Read stop cycle
Read stop command F0H enables to finish read mode.
Read stop command F0H can be accepted in the busy state.
WE
RE
CE
CLE
Read cycle Read stop
cycle Standby
mode
ALE
I/O1 to
I/O8
I/O9 to
I/O16
(
´
16)
R/
B
NSector address Read Stop
command
F0HSA2SA1CA2CA100H D
OUT
M
D
OUT
N+1
D
OUT
N
V
IH
or V
IL
Note: M is end of page.
D
OUT
M
tWB tRSTP
D
OUT
N+1
D
OUT
N
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Rev.0.03, Jun.06.2003, page 30 of 50
Sequential read mode
The device enters into the sequential read mode by command 0FH. This mode performs continuously
reading through the pages and the sectors without additional command/address inputs. Start address in the
page can be specified in a CA. The operating timing and block diagram are shown below.
0FH
Sequential
read command Address input
CA1 CA2 SA1 SA2
Busy
N
N Sector address
N+1 M 0 1 M
WE
RE
CE
CLE
ALE
I/O
Note : M is end of sector.
R/
B
Column address
Sector address
Stop sequential read
End of sector address
(1FFFH)
Start
address
N
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Rev.0.03, Jun.06.2003, page 31 of 50
Sequential read cycle
RE
R/
B
ALE
CLE
I/O1 to
I/O8
I/O9 to
I/O16
(
´
16)
WE
CE
t
WB
t
RHZ
t
R
t
AR2
t
RC
t
ALH
t
WB
t
R
t
ALS
t
RR
t
ALH
D
OUT
M
V
IH
or V
IL
D
OUT
M
D
OUT
ND
OUT
N+1
D
OUT
N+1
D
OUT
N
N Sector address
SA2SA1CA2CA10FH
Note : M is end of sector.
Status read during the sequential read opera t ion
The device status can be read out by inputting the status read command 70H in the sequential read mode.
Once the device h as been set to the status read m ode by 70H command , th e device will not return to the
sequential read mode automatically. However, when the read command 00H is input after ready state, the
status read mode is reset and the device returns to the sequential read mode.
0FH
R/
B
RE
70H 00H 00H70H
Ready
Input address
Ready
Sequential read mode
(Next sector data)
Sequential read mode
(Start sector data)
Status read
mode
Status read
mode
D
OUT
D
OUT
D
OUT
D
OUT
D
OUT
D
OUT
D
OUT
D
OUT
Output data
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Rev.0.03, Jun.06.2003, page 32 of 50
Sequential read sto p cycle
Read stop command F0H enables to finish sequential read mode.
After inputting read stop command F0H, the device becomes busy state. And then, the sequential read
mode ends and becomes command waiting state when the status returns to ready.
Read stop command F0H can be accepted in the busy state.
Stop in Ready state
WE
RE
CE
CLE
Sequential read cycle Read stop
cycle Standby
mode
ALE
I/O1 to
I/O8
I/O9 to
I/O16
(
´
16)
R/
B
NSector address Read Stop
command
Middle of
sector
data
Sequential
read
command
F0H
SA2SA1CA2CA10FH
D
OUT
M-x
D
OUT
N+1
D
OUT
N
V
IH
or V
IL
Note: M is end of sector
D
OUT
M-x t
WB
t
RSTP
D
OUT
N+1
D
OUT
N
t
RHWS
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Rev.0.03, Jun.06.2003, page 33 of 50
Stop in Busy state
WE
RE
CE
CLE
Sequential read cycle Read stop
cycle Standby
mode
ALE
I/O1 to
I/O8
I/O9 to
I/O16
(
´
16)
R/
B
NSector address Read Stop
command
Sequential
read
command
F0H
SA2SA1CA2CA10FH DOUT
M
DOUT
N+1
DOUT
N
V
IH
or V
IL
Note: M is end of sector
DOUT
MtWB tRSTP
DOUT
N+1
DOUT
N
tRHWS
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Rev.0.03, Jun.06.2003, page 34 of 50
Power on auto read / Auto read
Power on auto read mode enables to read the data of the lowest sector(2k byte) without command and
address data input when power is on.
Auto read mode enables to read the data of the lowest sector (2k byte) without command and address data
input in the normal operation.
Power on auto read and Auto read are activated when power is on.
Power on auto read is available and Auto read operates until po wer is off when these ar e activated.
These are activated after PRE high signal right after DSE goes high. (DSE must be lo w until Power
reaches VCCmin).
MRES going low to high indicates that the data is ready for reading.
The data of the lowest sector (2k byte) can be output by RE clock without command and address input.
After power on read operation, PRE should be kept high.
During the normal operation, keeping PRE low for 50 ns or more makes the device transfer to the auto read
mode and the data of the lowest sector (2k byte) can be output by RE clock without command and address
input.
If power on auto read and auto read operation is unnecessary, PRE pin should be connected to VSS or open.
Power on auto read
V
CC
RE
R/
B
DSE
MRES
ALE
CLE
PRE
I/O1 to
I/O8
I/O9 to
I/O16
(
´
16)
WE
CE
DOUT
0DOUT
1DOUT
2DOUT
M
DOUT
0
t
BSY
t
RMRES
V
CC
min
DOUT
1DOUT
2DOUT
M
t
PD
V
ILP
t
DB
V
IHP
V
IHP
t
DSE
Note : M ≤ 2047 (
´
8 device)
M ≤ 1023 (
´
16 device)
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Rev.0.03, Jun.06.2003, page 35 of 50
Auto read
Case of tPRE <
<<
< tARBSY
D
OUT
M
D
OUT
M
D
OUT
0
D
OUT
0
D
OUT
1
D
OUT
1
t
ARBSY
tPRE
tWB
tRMRES
Note : M ≤ 2047 (
´
8 device)
M ≤ 1023 (
´
16 device)
V
CC
RE
R/
B
MRES
ALE
CLE
PRE
I/O1 to
I/O8
I/O9 to
I/O16
(
´
16)
WE
DSE
CE
V
IH
or V
IL
V
IHP
V
IH
V
IL
V
IL
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Rev.0.03, Jun.06.2003, page 36 of 50
Case of tPRE ≥
≥≥
≥ tARBSY
D
OUT
M
D
OUT
M
D
OUT
0
D
OUT
0
D
OUT
1
D
OUT
1
t
ARBSY
tPRE
tWB
tRMRES
V
CC
RE
R/
B
MRES
ALE
CLE
PRE
I/O1 to
I/O8
I/O9 to
I/O16
(
´
16)
WE
DSE
CE
V
IH
or V
IL
V
IHP
V
IL
V
IL
V
IH
Note : M ≤ 2047 (
´
8 device)
M ≤ 1023 (
´
16 device)
Note: 1. When PRE is turned low during busy, after the operation performed now is completed, this device
transfer to the auto read mode.
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Rev.0.03, Jun.06.2003, page 37 of 50
Auto read (Deep standby mode which transferred by the command)
Case of tPRE <
<<
< tARBSY
D
OUT
M
D
OUT
M
D
OUT
0
D
OUT
0
D
OUT
1
D
OUT
1
t
ARBSY
tPRE
tWB
tRMRES
V
CC
RE
R/
B
MRES
ALE
CLE
PRE
I/O1 to
I/O8
I/O9 to
I/O16
(
´
16)
WE
DSE
CE
V
IH
or V
IL
V
IHP
Note : M ≤ 2047 (
´
8 device)
M ≤ 1023 (
´
16 device)
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Rev.0.03, Jun.06.2003, page 38 of 50
Case of tPRE ≥
≥≥
≥ tARBSY
D
OUT
M
D
OUT
M
D
OUT
0
D
OUT
0
D
OUT
1
D
OUT
1
t
ARBSY
tPRE
tWB
tRMRES
V
CC
RE
R/
B
MRES
ALE
CLE
PRE
I/O1 to
I/O8
I/O9 to
I/O16
(
´
16)
WE
DSE
CE
V
IH
or V
IL
V
IHP
Note : M ≤ 2047 (
´
8 device)
M ≤ 1023 (
´
16 device)
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Rev.0.03, Jun.06.2003, page 39 of 50
Auto read stop cycle
Read stop command F0H enables to finish power on auto read mode and auto read mode.
WE
RE
CE
CLE
Power on auto read mode
or Auto read mode Read stop
cycle Standby
mode
ALE
PRE
VIL
VIHP
I/O1 to
I/O8
I/O9 to
I/O16
(
´
16)
R/
B
Read Stop
command
F0H
DOUT
M
DOUT
1
DOUT
0
VIH or VIL
DOUT
M
tWB tRSTP
DOUT
1
DOUT
0
Note : M ≤ 2047 (
´
8 device)
M ≤ 1023 (
´
16 device)
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Rev.0.03, Jun.06.2003, page 40 of 50
Program mode
The program mode is organized by the data input and the program. Data input command 80H is for the
input address and the program data. And program command 10H makes the device start the program
(Please refer to the next page). The maximum data size is 2 kbyte (1 kword for ×16 device).
One sector is divided by 4 pages. The size of page is 512byte. Each page is programmable just one time as
well as the normal 2 kbyte programming (Please refer to the figure below).
The data at applied sector for program must be erased.
The data of erased sector is [FF]. The programmed bits in the sector goes “1” to “0”when they are
programmed.
Data2
Note: Input only program data. It is not necessary to mask of the previous programmed data.
Data2 Pattern
after program
Input data2
Data1 Pattern
after program
Input data1
Original data pattern
in a sector
0 (
´
8)511 512 1023 1024 1535 1536 2047
0 (
´
16)255 256 511 512 767 768 1023
0 to 2047 (
´
8 device)
0 to 1023 (
´
16 device)
Data1
Data1
FF pattern FF pattern FF pattern
FF pattern
FF pattern
FF pattern
FF pattern
FF pattern
FF pattern
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Rev.0.03, Jun.06.2003, page 41 of 50
Program cycle
RE
R/
B
ALE
CLE
I/O1 to
I/O8
I/O9 to
I/O16
(
´
16)
WE
CE
Note : N ≤ M ≤ 2047 (
´
8 device)
N ≤ M ≤ 1023 (
´
16 device)
00H
D
IN
M-1 D
IN
M
D
IN
ND
IN
N+1
Output
status
data
D
IN
M-1 D
IN
M
D
IN
ND
IN
N+1
SA
(1) SA
(2)
CA
(1) CA
(2) 70H
10H
80H
t
WB
t
PROG
Sector
address
Column
address
V
IH
or V
IL
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Rev.0.03, Jun.06.2003, page 42 of 50
Erase mode
The erase mode is entered by command 60H. After inputting sector address, command D0H erases the
sector data. The erase size is always 2 kbyte and the erase operation must be done in the sector.
Erase cycle
Status
read
command
70H
Status
output
D0H60H SA
(2)
SA
(1)
RE
R/
B
ALE
CLE
I/O1 to
I/O8
I/O9 to
I/O15
WE
CE
t
WB
t
ERS
V
IH
or V
IL
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Rev.0.03, Jun.06.2003, page 43 of 50
Rewrite mode
The rewrite mode is organized by the data input and the rewrite. Data input command 80H is for the input
address and the rewrite data to be changed. And rewrite command 1FH makes the device start the rewrite
(Please refer to the next page). The maximum data size is 2 kbyte (1 kword in case of ×16 device). By
using rewrite, erase is au tomatically executed b e f ore progr am ming, and th e d a ta can be rewritten for the
sector. So the data before the programming operation can be either “1” or “0” (Please refer to the figure
below).
Data Pattern
after rewrite
Input
Data Pattern
Original
Data Pattern
R/
B
I/O
0
N
0 to 2047 (
´
8 device)
0 to 1023 (
´
16 device)
80H
N
CA1 CA2 SA1 SA2 D
IN 1FH 70H Pass
Status read
command
Automatic
Rewriting
command
Data inputData input
command Address
Fail
M
0 to 2047 (
´
8 device/sector)
0 to 1023 (
´
16 device/sector)
I/O
D
IN
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Rev.0.03, Jun.06.2003, page 44 of 50
Rewrite cycle
Note : N ≤ M ≤ 2047 (
´
8 device)
N ≤ M ≤ 1023 (
´
16 device)
00H
DIN
M-1 DIN
M
DIN
NDIN
N+1
Output
status
data
DIN
M-1 DIN
M
DIN
NDIN
N+1
SA
(1) SA
(2)
CA
(1) CA
(2) 70H
1FH
80H
tWB
tREWRITE
Sector
address
Column
address
RE
R/
B
ALE
CLE
I/O1 to
I/O8
I/O9 to
I/O16
(
´
16)
WE
VIH or VIL
CE
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Rev.0.03, Jun.06.2003, page 45 of 50
Notes on usage
1. Prohibition of undefined command input
The commands listed in the command definition can only be used in this device. It is prohibited to issue a
command that is not defined in the list. If an undefined command is issued, the data held in the device may
be lost.
2. Limitat ion of command input in the busy stat e
In the busy state, following two commands are acceptable. Do not issue any other command except below
two commands.
• Status read 70H
• Read stop F0H (during read option)
3. Commands t ha t can be issued after t he seria l input command (80H)
After the serial input command (80H) is issued, the rewriting and programming command (1FH, 10H) can
be issued; do not issue any other command except 1FH and 10H after 80H.
4. R/B
BB
B(Ready/busy
busybusy
busy) pin handing
R/B is an open-drain output pin, and it should be pulled up to VCC with a resistance(more than 2kΩ).
5. Notes on turning power on and off
The input signal levels may be unstable after power is on or off.
In order to prevent unexpected operation, use DSE as shown below.
Don't care
Don't care
Invalid
Operation
t
DB
V
CC
R/
B
CE
,
WE
,
RE
,
WP
,
CLE, ALE
0V
V
CC
min
V
ILP
V
ILP
DSE
V
IHP
t
BSY
t
DSE
0V
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Rev.0.03, Jun.06.2003, page 46 of 50
6. Notes on WP
WPWP
WP signal
When WP is at the low level, the rewriting o peration is disab led.
When using WP to control the operation, satisfy the timing shown below.
Operation enable
WE
D
IN
D
IN
WP
R/
B
Operation disable
WE
WP
R/
B
t
WPS
t
WPS
1st com
Erase Program Rewrite
1st com 60H 80H 80H
2nd com D0H 10H 1FH
2nd com
1st com
2nd com
t
RW
t
WPH
7. Notes on RE
RERE
RE signal
If the RE clock is sent before the address is input, the internal read operation may start unintentionally.
Be sure to send the RE clock after the address is input.
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Rev.0.03, Jun.06.2003, page 47 of 50
8. Deep standby mode
During command waiting or standby state, when DSE pin goes to low, the device transfers to deep standby
state.
When DSE goes to high, the device returns from the deep standby state.
During command execution, going DSE low stops command operation. If DSE goes to low during
erase/program/rewrite operation, the command operation is forced to terminate and the applied sector data
is not guaranteed.
Standby state
Deep standby stateStandby state
DSE
R/
B
tDBSY
When CE becomes high after the C0H command input, the state of this device transfers to the deep standby
state.
When CE becomes high after the C1H command input, the state of this device transfers from the deep
standby state to the standby state.
Standby state
Deep standby state
Deep standby
setup command Deep standby
release command
Standby state
CE
,
WE
R/
B
DIN C1HC0H
tDBSY
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Rev.0.03, Jun.06.2003, page 48 of 50
9. Notes on the power supply down
Please do not turn off a power supply in busy status.
It is recommended to take either of following (1) or (2) measures on system side for unexpected power
down.
(1) Please set DSE=L when detecting the power down.
And erase any sector after the power supply is on.
The other sectors data is protected though applied sector data is invalid by doing this.
2.4V (3.3V device)
1.6V (1.8V device)
1ms min
V
CC
DSE
(2) Please store the operation record for back up.
When the power down is recognized to have occurred during erase/program/rewrite operation,
erase applied sector after the power on.
The other sectors data is protected though applied sector data is invalid by doing this.
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Rev.0.03, Jun.06.2003, page 49 of 50
Package Dimensions
HN29V128A1ABP, HN29V128A0ABP, HN29A128A1ABP, HN29A128A0ABP Series (TBP-95V)
10.00
11.50
0.20 SB
0.20 SA
0.80 0.60
0.80
1.35
0.15
4×
S
φ0.08 AB
95 × φ0.40 ± 0.05
Details of the part A
Note: DatumA, B are defined as center line of terminal matrix.
M
0.20 ± 0.05
0.20
0.10
S
S
1.2 Max
S
INDEX
B
A
A
ABCDEFGHJKLM
12
11
10
9
8
7
6
5
4
3
2
1
Package CODE
JEDEC
JEITA
Mass
(reference value)
TBP-95V
–
–
0.25 g
Unit: mm
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Rev.0.03, Jun.06.2003, page 50 of 50
Keep safety first in your circuit designs!
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