Hifn Confidential
7955
Security Accelerator
Data Sheet
750 University Ave. ● Los Gatos, CA 95032 ● E:info@hifn.com ● P:408.399.3500 ● F: 408.399.3501
Hifn Confidential
DS-0114-08, © 2004, Hi/fn®, Inc. All rights reserved. 8/08
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May include one or more of the following United States patents: 4,701,745; 5,003,307; 5,016,009; 5,126,739; 5,146,221;
5,414,425; 5,463,390; 5,506,580; and 5,5532,694. Other patents pending.
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Contents
List of Figures ............................................................................................................................. 5
List of Tables ............................................................................................................................... 6
Preface ......................................................................................................................................... 7
About This Document ............................................................................................ 7
Customer Support ................................................................................................. 7
Web Site .............................................................................................................. 7
1 Product Description .............................................................................................................. 8
2 Features ................................................................................................................................. 9
2.1 High Performance ......................................................................................... 9
2.2 Major Security and Compression Protocol Support ............................................. 9
2.3 Multiple Host Bus Interface Modes ................................................................... 9
2.4 Low Host Overhead ...................................................................................... 10
2.5 Advanced Cryptographic Engines .................................................................... 10
2.6 Software Support ......................................................................................... 10
2.7 Other Features ............................................................................................ 10
3 Performance Summary ....................................................................................................... 11
3.1 Symmetric Key Processing Units..................................................................... 11
3.2 Protocol Performance .................................................................................... 12
3.3 Public Key ................................................................................................... 12
4 Block Diagram ..................................................................................................................... 14
4.1 Operation ................................................................................................... 14
4.2 Security Processing ...................................................................................... 16
4.2.1 Muting Table ........................................................................................ 16
4.2.2 Public Key Processing ............................................................................ 16
5 Configuration Options ........................................................................................................ 17
5.1 Core Clock Configuration ............................................................................... 17
5.2 EEPROM and Hardware Configuration .............................................................. 17
5.2.1 EEPROM Memory Map ........................................................................... 19
5.2.2 Configuration without EEPROM ............................................................... 20
5.3 Endianness Configuration .............................................................................. 21
5.3.1 Device Endianness Configuration ............................................................ 21
5.3.2 Device Endianness Configuration Examples .............................................. 24
6 Signal Description ............................................................................................................... 25
6.1 Signal Overview ........................................................................................... 25
6.1.1 PCI Signal Overview .............................................................................. 25
6.1.2 PowerQuicc II Signal Overview ............................................................... 26
6.1.3 PowerQuicc I Signal Overview ................................................................ 27
6.2 Detailed Signal Description ............................................................................ 28
6.2.1 PCI Signal Description ........................................................................... 28
6.2.2 PowerQuicc II Signal Description ............................................................. 29
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6.2.3 PowerQuicc I Signal Description .............................................................. 31
6.2.4 EEPROM Signal Description .................................................................... 32
6.2.5 Clock and Test Signal Description ........................................................... 32
6.2.6 Power and Ground Signal Description ...................................................... 34
7 Timing Specifications ......................................................................................................... 35
7.1 AC Operating Conditions ............................................................................... 35
7.2 Host Bus Interface Clock ............................................................................... 35
7.3 PCI Timing .................................................................................................. 37
7.4 PowerQuicc I Timing ..................................................................................... 38
7.5 PowerQuicc II Timing .................................................................................... 39
7.6 EEPROM ..................................................................................................... 41
8 DC Specifications ................................................................................................................ 42
8.1 Absolute Maximum Ratings ............................................................................ 42
8.2 Power Sequencing ........................................................................................ 42
8.3 Recommended Operating Conditions ............................................................... 43
8.4 DC Characteristics ........................................................................................ 43
9 Thermal Specifications ....................................................................................................... 45
9.1 Heat Sink Requirements ................................................................................ 45
9.2 Junction Temperature Specifications ............................................................... 45
10 Pin List ................................................................................................................................. 46
10.1 LQFP PCI-Mode Pin List .............................................................................. 46
10.2 LQFP PCI Mode Pinout ................................................................................ 48
10.3 LQFP PQI Mode Pin List .............................................................................. 49
10.4 LQFP PQI Mode Pinout ................................................................................ 51
10.5 LQFP PQII Mode Pin List ............................................................................. 52
10.6 LQFP PQII Mode Pinout .............................................................................. 54
11 Physical Specifications ...................................................................................................... 55
11.1 LQFP 144-pin Plastic Quad Flatpack ............................................................. 55
Document Changes/Revisions ................................................................................................ 56
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List of Figures
Figure 1 Example System Concept, MPC versus PCI Interface Mode ............................... 8
Figure 2 Block Diagram ......................................................................................... 14
Figure 3 Hardware Configuration Options ................................................................. 18
Figure 4 Endianness Transfer Modes ........................................................................ 23
Figure 5 PCI Host Bus Interface Signals ................................................................... 25
Figure 6 PowerQuicc II Host Bus Interface Signals ..................................................... 26
Figure 7 PowerQuicc I Host Bus Interface Signals ...................................................... 27
Figure 8 Input Bus Clock Timing ............................................................................. 35
Figure 9 PQI bus Read/Write Timing ........................................................................ 39
Figure 10 PQII bus Read/Write Timing .................................................................... 40
Figure 11 EEPROM Timing ..................................................................................... 41
Figure 12 Power Sequence Specifications ................................................................ 43
Figure 13 LQFP PCI Mode Pinout Drawing ................................................................ 48
Figure 14 LQFP PQI Mode Pinout Drawing ................................................................ 51
Figure 15 LQFP PQII Mode Pinout Drawing .............................................................. 54
Figure 16 144 LQFP Package ................................................................................. 55
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List of Tables
Table 1 Ordering Information ................................................................................ 10
Table 2 Processing Unit Performance ...................................................................... 11
Table 3 Protocol Processing Performance ................................................................ 12
Table 4 IKE Performance ...................................................................................... 12
Table 5 Public Key Performance (133 MHz Operation) ............................................... 13
Table 6 Description of the functional units ............................................................... 15
Table 7 EEPROM Memory Map ............................................................................... 19
Table 8 PowerQuicc I and PowerQuicc II Chip Select Methods .................................... 20
Table 9 Host Bus Mode Configuration without EEPROM .............................................. 20
Table 10 Host Bus Endian Configuration without EEPROM ............................................ 20
Table 11 PCI Register Configuration without EEPROM ................................................. 20
Table 12 7955 Endianness Configuration .................................................................. 21
Table 13 Endianness Mapping of System Data ........................................................... 22
Table 14 64-bit Host Data Endianness Control ........................................................... 24
Table 15 PCI Signals .............................................................................................. 28
Table 16 PowerQuicc II Signals ............................................................................... 29
Table 17 PowerQuicc I Signals ................................................................................ 31
Table 18 EEPROM Signals ....................................................................................... 32
Table 19 PLL Signals .............................................................................................. 33
Table 20 Test and JTAG signals ............................................................................... 33
Table 21 Power and Ground signals ......................................................................... 34
Table 22 AC Operating Conditions ............................................................................ 35
Table 23 PCI_CLK Timing ....................................................................................... 35
Table 24 PQI_CLK Timing ....................................................................................... 36
Table 25 PQII_CLK Timing ...................................................................................... 36
Table 26 PLL_REF Clock ......................................................................................... 36
Table 27 PCI Timing Parameters .............................................................................. 37
Table 28 Read/Write Timing (PQI bus) ..................................................................... 38
Table 29 Read/Write Timing (PQII bus) .................................................................... 39
Table 30 EEPROM Timing ....................................................................................... 41
Table 31 Absolute Maximum Ratings ........................................................................ 42
Table 32 Recommended Operating Conditions ........................................................... 43
Table 33 DC Electrical Characteristics ....................................................................... 43
Table 34 Thermal Specifications .............................................................................. 45
Table 35 LQFP Thermal Resistance........................................................................... 45
Table 36 LQFP PCI-Mode Pin List (Numerically) .......................................................... 46
Table 37 LQFP PCI-Mode Pin List (Alphabetically) ....................................................... 47
Table 38 LQFP PQI Mode Pin List (Numerically) .......................................................... 49
Table 39 LQFP PQI Mode Pin List (Alphabetically) ....................................................... 50
Table 40 LQFP PQII Mode Pin List (Numerically) ......................................................... 52
Table 41 LQFP PQII Mode Pin List (Alphabetically) ...................................................... 53
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Preface
Welcome to the Data Sheet for the Hifn 7955 network security processors family. This
document provides feature, performance, and interface information and specifications for
the 7955 Security Accelerator.
The reader is assumed to have a general knowledge of Hifn 795x architecture. The 7955 is
the newest members of the 795x family of algorithm accelerators, which began with the
Hifn 7951. For register descriptions, definitions of data structures, and general usage
information, refer to the 7954/7955/7956 Hardware Users Guide (UG-0034).
About This Document
This document assumes you are already familiar with the chip technology and terminology.
This document is intended for integrators and application developers responsible for and
familiar with software and hardware architecture of a target system.
Customer Support
For technical support about this product, please contact your local Hifn sales office,
representative, or distributor.
Web Site
For general information about Hifn and Hifn products refer to: www.hifn.com.
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1 Product Description
High Performance- The Hifn TM 7955 Security Accelerator supports multi-protocol
algorithm processing. Optimized for OC3/T3 Applications, 7955 Security Accelerator
achieves over 250 Mbps full-duplex sustained performance with simultaneous encryption,
compression, and authentication of large packets (1500 Bytes).
Highly Integrated- All major security/compression protocols are supported. The 7955 is
an ideal security solution for VPN enabled routers, remote access concentrators, VPN
gateways, firewalls, and WAN switches. The 7955’s integrated high-speed compression
engines also make it ideal for wireless applications. IPSec algorithms include AES-128,
AES-192, AES-256, DES, 3DES, and ARC4 encryption. The 7955 supports SHA-1 and MD5
authentication, LZS and MPPC compression.
AES Support- The 7955 fully supports the new Advanced Encryption Standard, AES, with
key lengths of 128, 192 & 256-bits. It also supports AES counter-mode.
Integrated Public-Key Processing- The 7955 contains an on-chip public-key subsystem.
SSL, TLS, and IKE algorithms include RSA, DSA, and Diffie-Hellman operations.
Host Bus Interface- The 7955 is equipped with a configurable PCI-2.2 compliant interface,
enabling direct connection to any PCI host system. The 7955 also offers a glueless interface
to the MPC860 or MPC8260 bus.
Compatibility- The 7955 is software-compatible with the Hifn 79xx family.
7955
MPC CPU
(860/8260)PowerQuicc I/II Bus (32-bit @ 66 MHz )
WAN/LAN
Ports
System
Memory
CPU
7955
System
Controller
System
Memory
PCI Host Bus (32/64-bit @ 66 MHz )
WAN Ports LAN Ports
Figure 1 Example System Concept, MPC versus PCI Interface Mode
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2 Features
2.1 High Performance
Supports IPSec processing at OC3 and higher data rates (for 1500-byte packets)
Processes entire packet (compression, encryption, and authentication) in a single
pass
Supports concurrent Public-Key and Symmetric Key processing
Integrated Public Key processor
IPSec performance; 75 Diffie-Hellmann quick-mode connections/s (1024-bit)
SSL performance; 40 RSA signatures/s (1024-bit)
Compression engine runs at over 250 Mbps and increases effective throughput
Supports 128 Security Associations (SA) on-chip, and unlimited in host memory.
2.2 Major Security and Compression Protocol
Support
128/192/256-bit AES (Advanced Encryption Standard), DES, 3DES, and ARC4
encryption (ARC4 is fully compatible with RSA’s RC4TM algorithm)
SHA-1 and MD5 hashing and authentication
LZS and MPPC compression
Public-key support includes RSA, DSA, SSL, IKE, and Diffie-Hellman
Supports up to 3072-bit modular arithmetic and exponentiation
True Hardware Random Number Generator
2.3 Multiple Host Bus Interface Modes
Bus mastering PCI-2.2 Interface at 33 or 66 MHz
Efficient scatter/gather DMA engines handle fragmented host memory
Programmable bus arbitration/utilization for PCI bandwidth control
64-byte FIFO input and output buffers support high-speed burst transfers
Optional external serial EEPROM enables customized PCI configurations
Direct MPC860/850 PowerQuicc bus (32-bit GPCM) interface, up to 4 word burst
Direct MPC8260 PowerQuicc II bus (32-bit UPM) interface, up to 4 double word
burst
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2.4 Low Host Overhead
Security context (encryption keys and other stateful parameters) may be stored in
on-chip memory to reduce host overhead
Descriptor Based DMA engine (supports data scatter / gather) in PCI mode
On-chip memory used to buffer control data packets
2.5 Advanced Cryptographic Engines
Support for ECB, CBC, and CTR block-cipher modes of operation
Multi-mode automatic padding
Programmable mutable field MAC support for handling AH, IPv4, IPv6, and others
2.6 Software Support
Supported by standard 79xx Hifn API
API supports the full feature set of Hifn 79xx products
API works with a wide variety of host architectures
2.7 Other Features
Architecture compatibility with other Hifn 79xx Security Accelerators
Supports low-cost implementation with 144-pin LQFP package
JTAG support
Reference hardware design
1.5V core with 3.3V I/O
Typical dissipation = 0.64 W
Table 1 Ordering Information
Part Number
Speed
Description
7956PT6/2-G
66 MHz
144-pin LQFP 7955 Network Security Accelerator
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3 Performance Summary
The figures in this section summarize the performance of the 7955 Security Accelerator
functional units. Performance of the 7955 Security Accelerator when multiple engines are
used (for example, the compression, MAC and encryption engines are all engaged) can be
approximated by using throughput of the slowest engine.
The MAC and encryption engine speeds are accelerated (effectively multiplied) by the actual
compression ratio achieved by the compression engine. For example, if the achieved
compression ratio is 2:1, then the MAC and encryption engine speeds are effectively
doubled and the compression engine would be the slowest engine. This performance data
reflects the following conditions:
66 MHz maximum internal core frequency
1500-byte packets.
Single session or security association.
Encoded text throughput
3.1 Symmetric Key Processing Units
Table 2 Processing Unit Performance
Protocol
Performance @ 66 MHz
(Mbps)
AES-128, 192, 256
365, 420, 460
3DES
340
ARC4
210
SHA-1
325
MD5
360
LZS Compression
Stateless
Stateful
510
450
LZS Decompression
455
395
MPPC Compression
505
460
MPPC Decompression
420
425
Note:
All performance numbers are based on simulation
results. Text from the United States Constitution was
arbitrarily selected for the compression and
decompression simulations. The compression ratio is
approximately 2:1.
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3.2 Protocol Performance
Table 3 Protocol Processing Performance
Protocol
Performance @ 66 MHz
Throughput
(Mbps)
Packets/Sec
IPSec (Tunnel; 3DES-CBC, SHA-1
HMAC)
325
27K
IPSec (Tunnel; AES-256, SHA-1
HMAC)
330
27K
IPSec (AH Tunnel; SHA-1 HMAC)
320
27K
3-DES, SHA-1, Stateless LZS
370
31K
PPTP (RC4, MPPC)
360
30K
Note:
All performance numbers are based on simulation results. Text
from the United States Constitution was arbitrarily selected for
the compression and decompression simulations. The
compression ratio is approximately 2:1.
3.3 Public Key
Table 4 IKE Performance
IKE Handshake
Connections/Sec
@ 133 MHz
Two 1024-bit Diffie-Hellman operations (Quick Mode)
70
Two 1024-bit Diffie-Hellman operations, 1 RSA sign,
2 RSA verifies (Main Mode)
24
Four 1024-bit Diffie-Hellman operations, 1 RSA sign, 2
RSA verifies (Main Mode + Quick Mode)
38
Note:
180-bit exponent. The number of connections/sec is based on
simulation results.
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Table 5 Public Key Performance (133 MHz Operation)
Operation @ 66 MHz
Completion Time (ms) vs. Key Length (bits)
2048
1024
768
512
RSA private key
82.75
11.88
4.69
1.75
RSA public key (3-bit exponent)
.45
.12
.07
.03
Diffie-Hellman (180-bit exponent)
27.13
7.25
4.81
2.06
Diffie-Hellman (exponent = key
size)
308
41.25
20.50
5.88
DSA sign
12.94
7.78
3.75
DSA verify
19.41
11.66
5.63
Note:
Performance numbers assume a uniform distribution of ones and zeros in the exponent.
Actual performance varies with the Hamming weight of the exponent. Performance
numbers assume that the public key module has unrestricted access to memory. Actual
performance varies with the memory usage of other system components. These
numbers are only estimates and have not been experimentally verified.
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4 Block Diagram
4.1 Operation
The 7955 Security Accelerator contains several processing units - Public Key encryption,
symmetric key encryption, compression, padding, authentication, and Random Number
Generator,. The symmetric key encryption, compression, padding, and authentication units
are combined into a single functional block called the Packet Engine. The 7955 Security
Accelerator also contains two programmable DMA engines with time-multiplex capability to
transfer control and traffic data, two source and destination FIFOs, a PCI interface, and a
PowerQuicc I/II Host Interface.
PCI Rev 2.2 64/32-bits 66/33MHz Master
MPC PowerQuicc I Slave
MPC PowerQuicc II Slave
Engines
Packet
Engine
EncryptionEncryption
PK Engine
RNG
Fetch FIFOs
Post FIFOs
CompressionCompression
Authentication
PK Operand
RAM (4KB)
JTAG
PLL
Interrupt
and Control
Registers
Host Bus Interface (PCI, PQI, or PQII)
Local
RAM (32KB)
EEPROM
Interface
Data Path
DMA (PCI)
Memory Ctrl Pipeline
uControl
EEPROM
Optional
PLL_REF
Figure 2 Block Diagram
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Table 6 Description of the functional units
Block
Description
Packet Engine
The packet engine consist of the encryption, compression and
authentification processors. The packet engine contains
pipelined compression, encryption, padding and
authentication units, along with hardware for computing
checksums, CRCs, and LCBs. The packet engine is configured
by a command message prior to the start of each packet or
task.
Public-Key Processor
The public-key processor incorporates enhanced features,
providing hardware acceleration of public-key or symmetric
key calculations on keys of up to 3,072 bits. The public-key
processor also contains a hardware true-random number
generator. It is accessible from both the PCI or MPC
interfaces.
Local RAM
The 32KB local memory is used for the storage of information
such as descriptor, command, or per-session security context
data. It may also contain I/O packet buffers.
Inbound/Outbound
DMA Units
When the 7955 Security Accelerator is operating in PCI-bus
mode, the inbound and outbound DMA units are special-
purpose block-transfer engines controlled by the 7955
Security Accelerator. The inbound DMA unit transfers
commands and unprocessed packets from PCI to the 7955
Security Accelerator’s security processing core, while the
outbound DMA unit transfers processed packets and status
information from security core to PCI. Fragmented buffers are
supported through scatter/gather features in the DMA
hardware. Internal FIFOs provide buffering to allow high-
speed burst transfers. When the 7955 Security Accelerator is
operating in slave-bus MPC mode, the PCI portion of the
inbound/outbound DMA unit is disabled, and the
PowerQuicc_I&II logic is enabled.
PCI Interface
The PCI interface is both an efficient bus master and an
efficient bus target. It becomes a bus master for either the
inbound DMA unit, or the outbound DMA unit. As a PCI slave,
it services requests by the PCI host to access 7955 Security
Accelerator registers and private memory.
PowerQuicc I&II
The PowerQuicc I&I interface is an alternate I/O interface
supporting direct host interface to MPC860/850 and
MPC8260. The MPC interface shares pins with the PCI
interface, so both cannot be active in the same design.
7955 Security
Accelerator Registers
The 7955 Security Accelerator registers control the operation
of the subsystem. They are memory-mapped to both the MPC
and PCI.
EEPROM /
Hardware Configuration
Interface
This interface supports an optional serial EEPROM used to
configure the device registers at reset. If no EEPROM is used,
the interface can be used to select default configuration,
including host bus interface mode.
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4.2 Security Processing
The 7955 DMA channels and associated controller are designed to off-load the host from
having to move numerous copies of data and associated context for each iteration of
security processing. Locally accessible descriptor, command and context further relieve the
host from having to move multiple control data packets between the host and target to
perform necessary security related processing.
4.2.1 Muting Table
An on-board muting table memory provides the mask that controls the input to the MAC
processor. The mask nulls specific segments of the data packet prior to being submitted to
the MAC processor. The masks are programmable through the host bus & are selected by
the MAC descriptor.
4.2.2 Public Key Processing
7955 uses an enhanced Public Key (PK) processor. To further optimize the PK acceleration,
7955 PK processor is equipped with a 16 Opcode FIFO. The PK processor operates on a
batch of modular arithmetic instructions (up to 16) and issues an interrupt once the operand
FIFO is empty. Since each modular arithmetic instruction (nano instruction) execution is
host independent, the host is only expected to setup the PK engine and retrieve the result
upon reception of PK interrupt.
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5 Configuration Options
The 7955 Security Accelerator supports a five-pin configuration interface that is used during
hardware reset to select the host bus mode and to set up critical register values. This
configuration information may be contained in a serial EEPROM attached to the interface.
Otherwise, a default configuration can be selected by the applying a value to the interface
during hardware reset.
5.1 Core Clock Configuration
When the 7955 comes out of reset the core logic is directly driven by the host bus interface
clock, HBI_CLK (PCI_CLK, PQI_CLK or PQII_CLK depending on the bus mode selected).
During register initialization, the on-chip PLL is enabled and programmed appropriately if a
multiple of one of the input clocks (host bus interface or PLL_REF) is needed to maximize
the 7955’s performance. The clock configuration circuit provides maximum flexibility
allowing the 7955 to be clocked synchronously or asynchronously to its host bus interface.
Refer to the PLL Configuration Register section in the 7954/7955/7956 Hardware Users Guide
(UG-0034) for details on configuring the clock circuit.
Note
The PLL_REF input signal may not be required in some systems to achieve maximum
performance (see 6.2.5 for more information on use of this input signal). Care must be
exercised in configuring the clock circuit to prevent the core logic from being over-
clocked.
5.2 EEPROM and Hardware Configuration
This section describes how the 5-pin serial EEPROM interface is used to configure the 7955
as it comes out of reset. The 7955 is designed so that the use of an external serial EEPROM
is optional. When the 7955 comes out of reset (rising edge of the RST# signal), the
EEPROM_EN signal is sampled to determine if an external EEPROM is present or not. If
EEPROM_EN is tied high, the 7955 will determine that an EEPROM is present and begin
loading configuration register values from it. Aside from internal register logic, the
remainder of the 7955, including the host interface, is held in a reset state for 20K clock
cycles (the time it takes to load register values from EEPROM).
If EEPROM_EN is tied low, the 7955 will determine that there is no external EEPROM present
as the device comes out of reset. However, in non-EEPROM configurations, the remaining 4
EEPROM signals are designed to be individually tied high and low (see section 5.2.2) on the
PCB to enable additional 7955 configuration options.
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7955
Security
Accelerator
Hardware
Configuration
Option Flag
EEPROM_EN
EEPROM_CS
EEPROM_SK
EEPROM_DO
EEPROM_DI
7955
Security
Accelerator EEPROM
Local Configuration
Memory
EEPROM_EN
EEPROM_CS
EEPROM_SK
EEPROM_DO
EEPROM_DI
Figure 3 Hardware Configuration Options
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5.2.1 EEPROM Memory Map
Table 7 EEPROM Memory Map
EEPROM
Address
(H)
Bit
Field
Name
Description
Default
Value
(H)
0x00
1:0
HBI Select
Host Bus Interface Select
0x0
0x00
3:2
RESERVED
0x0
0x00
4
HBI_SWAP8*
Endian Byte Swap
0x0
0x00
5
HBI_SWAP32*
Endian Double-Word Swap
0x0
0x00
15:6
RESERVED
0x0
0x01
15:0
PCI Vendor ID
0x13A3
0x02
15:0
PCI Device ID
0x0020
0x03
15:0
PCI Class Code [23:8]
0x0B40
0x04
15:8
PCI Class Code [7:0]
0x00
0x04
7:0
RESERVED
0x00
0x05
15:8
PCI Revision ID
0x00
0x05
7:0
RESERVED
0x00
0x06
15:8
PCI BIST
0x00
0x06
7:0
RESERVED
0x00
0x07
15:8
PCI Header Type
0x00
0x07
7:0
RESERVED
0x00
0x08
15:0
PCI Subsystem ID
0x0000
0x09
15:0
PCI Subsystem Vendor ID
0x0A
15:8
PCI Max_Lat
0x00
0x0A
7:0
PCI Min_Gnt
0x00
0x0B
15:8
PCI Interrupt Pin
0x01
0x0B
7:0
RESERVED
0x00
0x0C
15:0
RESERVED
0x00
0x0D
15:0
RESERVED
0x00
0x0E
15:0
RESERVED
0x00
0x0F
15:0
RESERVED
0x00
0x10
0
PQ_ADD_DECODE_EN
Address decode enable
0x0
0x10
1
PQII_PIPELINE_EN
MPC8260 bus pipeline enabled
0x0
0x10
15:2
RESERVED
0x0000
0x11
15:0
PQ_BASE_ADD
Base address
0x0000
0x12 -
0x1F
15:0
RESERVED
0x0000
0x20 -
0x2F
15:0
RESERVED
0x0000
0x30 -
0x3F
15:0
RESERVED
0x0000
Notes:
* Refer to Section 5.3 for endianness control.
When using the 7955 in the PowerQuick I and PowerQuick II modes, the 7955 device
supports two chip select methods. The PQ_ADD_DECODE_EN bit from EEPROM (address
0x010 bit 0) selects which method is used as shown in Table 8. For sake of this discussion,
PQ_signalname will represent signals from both PowerQuicc I and PowerQuicc II.
7955 - Data Sheet, DS-0114-08 20
Hifn Confidential
If the PQ_ADD_DECODE_EN bit is zero, the device is selected solely by the PQ_CS# pin,
qualified by PQ_TS#. This method is used for configurations without an EEPROM, for
configurations with an EEPROM when PQ_ADD_DECODE_EN is zero, and as the default.
If the PQ_ADD_DECODE_EN bit is a one, the device is selected using a combination of chip
select and address comparison. When PQ_CS# and PQ_TS# are asserted and the 16 most
significant bits of the host address PQ_A[0:15] matches the PQ_BASE_ADD field in the
EEPROM, address 0x011 bits [15:0], the device is selected. In a typical application of this
method the PQ_CS# pin would be tied low.
Table 8 PowerQuicc I and PowerQuicc II Chip Select Methods
PQ_ADD_DECODE_EN
EEPROM
Chip Select Method
0
Yes
PQ_TS# and PQ_CS# active
1
PQ_TS# and PQ_CS# active, and
PQ_A[0:15] = PQ_BASE_ADD[15:0]
0 (default value)
No
PQ_TS# and PQ_CS# active
5.2.2 Configuration without EEPROM
If the EEPROM_EN input is tied low, the EEPROM interface signals are used as simple
configuration inputs. EEPROM_CS and EEPROM_SK select the Host Bus mode, while
EEPROM_DI and EEPROM_DO select the endian settings.
Table 9 Host Bus Mode Configuration without EEPROM
EEPROM_CS
EEPROM_SK
Host Bus Mode
0
0
PCI Bus Mode
0
1
PowerQuicc-II Bus Mode
1
0
PowerQuicc-I Bus Mode
1
1
Asynchronous SRAM Bus Mode
Table 10 Host Bus Endian Configuration without EEPROM
EEPROM_DI
EEPROM_DO
Host Bus Endian Mode
0
0
SWAP[32,8] = 00
0
1
SWAP[32,8] = 01
1
0
SWAP[32,8] = 10
1
1
SWAP[32,8] = 11
Table 11 PCI Register Configuration without EEPROM
PCI
Configuration
Space Field
Default Value
(H)
Read/Write
Access
PCI
Configuration
Address (H)
EEPROM
Loadable?
Device ID
0x0020 or
0x001D (1)
Read only
0x02-03
Yes
Vendor ID
0x13A3
Read only
0x00-01
Yes
Status
0x0280
Read only
0x06-07
No
Command
0x0000
Read/Write
0x04-05
No
Class Code
0x0B4000
Read only
0x09-0B
Yes
7955 - Data Sheet, DS-0114-08 21
Hifn Confidential
Revision ID
0x0000
Read only
0x08
Yes
BIST
0x00
Read only
0x0F
No
Header Type
0x00
Read only
0x0E
Yes
Master Lat
Timer
0x00
Read/Write
0x0D
No
Cacheline Size
0x00 (2)
Read/Write
0x0C
No
BAR0
0x00000000
Read/Write
0x10-13
No
BAR1
0x00000000
Read/Write
0x14-17
No
BAR2
0x00000000
Read/Write
0x18-1B
No
Subsystem ID
0x0000
Read only
0x2E-2F
Yes
Subsystem
Vendor ID
0x0000
Read only
0x2C-2D
Yes
Max_Lat
0x00
Read only
0x3F
Yes
Min_Gnt
0x00
Read only
0x3E
Yes
Interrupt Line
0x00
Read/Write
0x3C
No
Note
(1) The two different Device_IDs are to be used for the 7955 and 7956,
respectively.
(2) The Cacheline size may be set to 0x08 for better performance.
5.3 Endianness Configuration
The internal data endianness format of the 7955 is 64-bit Little-Endian. However, the 7955
is capable of functioning with four different host interface modes; 64-bit PCI-2.2 , 32-bit
PowerQuicc I and 32-bit PowerQuicc II.
Endianness configuration is controlled for the following data paths:
Target access to Registers (EEPROM Memory Map)
Target access to Local-RAM (DMA Configuration Register #1)
Target access to PKRAM (DMA Configuration Register #2)
Initiator access to external descriptors (DMA Configuration Register #1)
Initiator access to external data (Descriptor Structures)
Initiator access to Local-RAM for internal descriptors and data is always in Little-Endian
format. Target access to Local-RAM must be configured appropriately to preserve internal
Little-Endian format.
5.3.1 Device Endianness Configuration
Independent 2-bit fields will determine the endianness of each of these 5 data paths. The
2-bit field comprise of SWAP8 bit, which controls byte transposition of a 32-bit entity, and
SWAP32 bit that controls swapping within a 64-bit entity. To the extent possible, these two
bits are adjacent and the SWAP32 bit is the significant bit position.
Table 12 7955 Endianness Configuration
Endianness Configuration
System Data Format
HBI_SWAP32
HBI_SWAP8
32-bit
64-bit
0
0
Little-Endian
Little-Endian
7955 - Data Sheet, DS-0114-08 22
Hifn Confidential
0
1
Big-Endian
Big-Endian (Double-Word
Swapped)
1
0
RESERVED
Little-Endian (Double-Word
Swapped)
1
1
Big-Endian
Table 13 Endianness Mapping of System Data
System
Endianness
Mode
System Data Format
Byte[7]
Byte[6]
Byte[5]
Byte[4]
Byte[3]
Byte[2]
Byte[1]
Byte[0]
32-bit Little-
Endian
RESERVED
Byte[3]
Byte[2]
Byte[1]
Byte[0]
32-bit Big-
Endian
Byte[0]
Byte[1]
Byte[2]
Byte[3]
64-bit Little-
Endian
Byte[7]
Byte[6]
Byte[5]
Byte[4]
Byte[3]
Byte[2]
Byte[1]
Byte[0]
64-bit Little-
Endian (DW
swapped)
Byte[3]
Byte[2]
Byte[1]
Byte[0]
Byte[7]
Byte[6]
Byte[5]
Byte[4]
64-bit Big-
Endian
Byte[0]
Byte[1]
Byte[2]
Byte[3]
Byte[4]
Byte[5]
Byte[6]
Byte[7]
64-bit Big-
Endian (DW
swapped)
Byte[4]
Byte[5]
Byte[6]
Byte[7]
Byte[0]
Byte[1]
Byte[2]
Byte[3]
7955 - Data Sheet, DS-0114-08 23
Hifn Confidential
B3 B2 B0
B0 B2 B3
B1
32-bit Big-Endian
B3 B2 B0
B1
B3 B2 B0
32-bit Little-Endian
B7B6B4 B3B2B0
B7 B6 B4 B3 B2 B0
64-bit Big-Endian (Double-Word Swapped)
B7B6B4B3B2B0
B7 B6 B4 B3 B2 B0
64-bit Big-Endian
B7 B6 B4 B3 B2 B0
B7 B6 B4 B3 B2 B0
64-bit Little-Endian
B7 B6 B4 B3 B2 B0
B7 B6 B5
B3 B2 B0B1
64-bit Little-Endian (Double-Word Swapped)
B5 B1 B1 B5
B5 B5
B5 B1
B5 B1B5 B1
B4
B5 B1
B1B1
Figure 4 Endianness Transfer Modes
7955 - Data Sheet, DS-0114-08 24
Hifn Confidential
5.3.2 Device Endianness Configuration Examples
Table 14 64-bit Host Data Endianness Control
Endianness Configuration
System Data Format
HBI_SWAP32
HBI_SWAP8
32-bit Mode Transferred Data
64-bit Mode Transferred Data
0
0
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
1
6
7
4
5
2
3
0
1
8
9
A
B
C
D
E
F
6
7
4
5
2
3
0
1
1
0
RESERVED
E
F
C
D
A
B
8
9
6
7
4
5
2
3
0
1
1
1
6
7
4
5
2
3
0
1
E
F
C
D
A
B
8
9
7955 - Data Sheet, DS-0114-08 25
Hifn Confidential
6 Signal Description
The 7955 Security Accelerator supports three different Host Bus Interface modes; PCI 2.2,
PowerQuicc I and PowerQuicc II. All other signals are used for configuration and testing.
6.1 Signal Overview
6.1.1 PCI Signal Overview
7955
Security
Accelerator
(PCI mode) PLL_REF
AVS
AVD
PCI_RST#
PCI_CLK
PCI_AD[31:0]
32
PCI_CBE#[7:0]
8
PCI_REQ#
PCI_GNT#
PCI_REQ64#
PCI_ACK64#
PCI_IDSEL
PCI_FRAME#
PCI_TRDY#
PCI_DEVSEL#
PCI_STOP#
PCI_INTA#
PCI_PAR
PCI_PAR64
PCI_PERR#
PCI_SERR#
PCI_IRDY#
PCI_AD[63:32]
32
JTRST#
JTMS
JTDO
JTDI
JTCK
TEST_EN
EEPROM_EN
EEPROM_CS
EEPROM_SK
EEPROM_DO
EEPROM_DI
Core
Clock
PLL
EEPROM
Config
Interface
PCI 2.2
Host Bus
Interface
JTAG
Test
Interface
Tied Low
Figure 5 PCI Host Bus Interface Signals
7955 - Data Sheet, DS-0114-08 26
Hifn Confidential
6.1.2 PowerQuicc II Signal Overview
7955
Security
Accelerator
(PowerQuicc_II Mode) PLL_REF
AVS
AVD
JTRST#
JTMS
JTDO
JTDI
JTCK
TEST_EN
EEPROM_EN
EEPROM_CS
EEPROM_SK
EEPROM_DO
EEPROM_DI
PQII_RST#
PQII_CLK
PQII_A[0:31]
32
PQII_TA#
PQII_PSDVAL#
PQII_DBB#
PQII_TEA#
PQII_TS#
PQII_D[0:31]
32
PQII_TSIZ[0:3]
4
PQII_INT#
PQII_CS#
PQII_AACK#
PQII_TBST#
PQII_TT[0:4]
5
Figure 6 PowerQuicc II Host Bus Interface Signals
7955 - Data Sheet, DS-0114-08 27
Hifn Confidential
6.1.3 PowerQuicc I Signal Overview
7955
Security
Accelerator
(PowerQuicc_I mode) PLL_REF
AVS
AVD
JTRST#
JTMS
JTDO
JTDI
JTCK
TEST_EN
EEPROM_EN
EEPROM_CS
EEPROM_SK
EEPROM_DO
EEPROM_DI
PQI_RST#
PQI_CLK
PQI_A[0:31]
32
PQI_TA#
PQI_RD/WR#
PQI_BURST#
PQI_TEA#
PQI_TS#
PQI_D[0:31]
32
PQI_TSIZ[0:1]
2
PQI_INT#
PQI_CS#
Figure 7 PowerQuicc I Host Bus Interface Signals
7955 - Data Sheet, DS-0114-08 28
Hifn Confidential
6.2 Detailed Signal Description
6.2.1 PCI Signal Description
The 7955 provides a PCI 2.2 compliant interface mode. The following PCI signals are
supported.
Table 15 PCI Signals
PCI Signals
I/O (Buffer type)
Description
PCI_CLK
Input (I-PCI)
PCI clock
PCI_RST#
Input (I-PCI)
PCI reset. Master reset for 7955.
PCI_IDSEL
Input (I-PCI)
PCI initialization device select.
PCI_REQ#
Output (TS-PCI)
PCI bus request.
PCI_GNT#
Input (I-PCI)
PCI bus grant.
PCI_AD[63:0]
I/O (I/O-PCI)
PCI address/data bus.
PCI_PAR
I/O (I/O-PCI)
PCI Parity signal; even parity across PCI_AD[31:0] and
PCI_CBE#[3:0]
PCI_PAR64
I/O (I/O-PCI)
PCI Parity Upper DWORD signal for PCI_AD[63:32] and
PCI_CBE#[7:4]. The PCI_PAR64 port is used only when
the interface is configured with a 64-bit AD bus.
PCI_CBE#[7:0]
I/O (I/O-PCI)
PCI bus command/byte-enable bits.
PCI_FRAME#
I/O (I/O-PCI)
PCI cycle frame.
PCI_TRDY#
I/O (I/O-PCI)
PCI target ready.
PCI_IRDY#
I/O (I/O-PCI)
PCI initiator ready.
PCI_DEVSEL#
I/O (I/O-PCI)
PCI device select.
PCI_STOP#
I/O (I/O-PCI)
PCI stop.
PCI_PERR#
I/O (I/O-PCI)
PCI parity error.
PCI_SERR#
Output (TS-PCI)
PCI system error.
PCI_ACK64#
I/O (I/O-PCI)
PCI Acknowledge 64-Bit Transfer signal. The
PCI_ACK64# is used only when the interface is
configured with a 64-bit AD bus.
PCI_REQ64#
I/O (I/O-PCI)
PCI Request 64-Bit Transfer signal. The PCI_REQ64# is
used only when the interface is configured with a 64-bit
AD bus.
PCI_INTA#
Output (TS-PCI)
PCI interrupt request.
Notes:
Buffer Type: I-PCI=PCI input, I/O-PCI=PCI Bidirectional, TS-PCI=PCI Tri-State output
7955 - Data Sheet, DS-0114-08 29
Hifn Confidential
6.2.2 PowerQuicc II Signal Description
The 7955 provides a MPC8260 PowerQuicc II compliant interface mode. The following
PowerQuicc II signals are supported. It is important to note that bus transactions have
certain restrictions for the transfer type, alignment, and size that must be adhered to for
proper operation.
Only word, double word and burst type bus accesses are supported by the 7955.
Table 16 specifies the supported encodings of PQII_TSIZ[0:3].
All transferred data must be naturally aligned. All word bus transfers must be
aligned on a 32-bit word boundary, all double word bus transfers must be aligned
on a double word boundary.
Local memory, address range 0x8000 – 0xFFFC, can be accessed using word,
double word, or burst transfers. The remaining address space, address range
0x0000 – 0x33FC, can only be accessed using word transfers.
Should a bus transaction violate the restrictions mentioned above, the device will
immediately terminate the transaction with the transfer error acknowledge signal
PQII_TEA# asserted.
Only the specified transfer types encodings of PQII_TT[0:4] are supported. The device
ignores all unsupported transfer types.
Table 16 PowerQuicc II Signals
PowerQuicc II
Signal
I/O (Buffer
type)
Description
PQII_CLK
Input (I-PQ)
Clock input, for the PowerQuicc I&II interface bus clock
PQII_RST#
Input (I-PQ)
Chip reset. Master reset for 7955.
PQII_CS#
Input (I-PQ)
The device chip select. Active low.
PQII_AACK#
Tri-state Output
(I/O-PQ)
PowerQuicc II address acknowledge
PQII_A[0:31]
Input (I/O-PQ)
PowerQuicc II address bus
PQII_DBB#
Input (I/O-PQ)
PowerQuicc II data bus busy
PQII_D[0:31]
I/O (I/O-PQ)
PowerQuicc II data bus
PQII_TA#
Tri-state Output
(I/O-PQ)
PowerQuicc II transfer acknowledge
PQII_PSDVAL#
Tri-state Output
(I/O-PQ)
PowerQuicc II partial data valid indication
PQII_TBST#
Input (I/O-PQ)
PowerQuicc II transfer burst
PQII_TEA#
Tri-state Output
(TS-PQ)
PowerQuicc II transfer error acknowledge
PQII_TS#
Input (I-PQ)
PowerQuicc II transfer start
PQII_TSIZ[0:3]
Input (I/O-PQ)
PowerQuicc II transfer size
PQII_TSIZ[0:3]
PQII_TBST#
Transfer
Size
Access
0000
1
8 bytes
Local
Memory
only
0010
0
32
bytes
Local
Memory
7955 - Data Sheet, DS-0114-08 30
Hifn Confidential
PowerQuicc II
Signal
I/O (Buffer
type)
Description
only
0100
1
4 bytes
All address
space
PQII_TT[0:4]
Input (I/O-PQ)
PowerQuicc II transfer type
PQII_TT[0:4]
Transfer Type
01010
Read – Single Beat
01110
Read with intent to write
11010
Read atomic
11110
Read with intent to modify atomic
01011
Read with no intent to cache
00010
Write with flush
00110
Write with kill
10010
Write with flush automatic
PQII_INT#
Open-Drain
Output (TS-PQ)
PowerQuicc II interrupt request
Notes:
Buffer Type: I-PQ=PQ input, I/O-PQ=PQ Bi-directional, TS-PQ=PQ Tri-State output
7955 - Data Sheet, DS-0114-08 31
Hifn Confidential
6.2.3 PowerQuicc I Signal Description
The 7955 provides a MPC860/850 PowerQuicc I compliant interface mode. The following
PowerQuicc I signals are supported. It is important to note that bus transactions have
certain restrictions for the transfer type, alignment, and size that must be adhered to for
proper operation.
Only word and burst type bus accesses are supported by the 7955. Table 17
specifies the supported encodings of PQI_TSIZ[0:1].
All word bus transfers must be aligned on a 32-bit word boundary.
Local memory, address range 0x8000 – 0xFFFC, can be accessed using word, or
burst transfers. The remaining address space, address range 0x0000 – 0x33FC,
can only be accessed using word transfers.
Should a bus transaction violate the restrictions, the device will immediately terminate the
transaction with the transfer error acknowledge signal PQI_TEA# asserted.
Table 17 PowerQuicc I Signals
PowerQuicc I
Signal
I/O (Buffer
type)
Description
PQI_CLK
Input (I-PQ)
Clock input, for the PowerQuicc I interface bus clock
PQI_RST#
Input (I-PQ)
Chip reset. Master reset for 7955.
PQI_CS#
Input (I-PQ)
The device chip select. Active low.
PQI_A[0:31]
Input (I/O-PQ)
PowerQuicc I address bus.
PQI_BURST#
Input (I/O-PQ)
PowerQuicc I transfer burst
PQI_D[0:31]
I/O (I/O-PQ)
PowerQuicc I data bus
PQI_RD/WR#
Input (I/O-PQ)
PowerQuicc I read/write enable
PQI_TA#
Tri-state
Output (I/O-
PQ)
PowerQuicc I transfer acknowledge
PQI_TEA#
Tri-state
Output (TS-
PQ)
PowerQuicc I transfer error acknowledge
PQI_TS#
Input (I-PQ)
PowerQuicc I transfer start
PQI_TSIZ[0:1]
Input (I/O-PQ)
PowerQuicc I transfer size
PQI_TSIZ[0:1]
PQI_BURST#
Transfer
Size
Access
00
1
4 bytes
All
address
space
00
0
16
bytes
Local
Memory
only
PQI_INT#
Open-Drain
Output (TS-
PQ)
PowerQuicc I interrupt request
Notes:
Buffer Type: I-PQ=PQ input, I/O-PQ=PQ Bi-directional, TS-PQ=PQ Tri-State output
7955 - Data Sheet, DS-0114-08 32
Hifn Confidential
6.2.4 EEPROM Signal Description
The 7955 has an EEPROM 5 pin serial interface. The following signals are used in this
interface.
Table 18 EEPROM Signals
EEPROM Signal
I/O (Buffer type)
Description
EEPROM_EN
Input (I)
When high, an EEPROM device is used to configure the
7955. When low, an EEPROM device is not used and
the EEPROM device pins are used as Hardware
Configuration inputs. See Section 5.2 for more details.
EEPROM_CS
I/O (I/O-O4)
EEPROM chip select /
HW Configuration Address bit[0]
EEPROM_DI
I/O (I)
EEPROM serial data in /
HW Configuration Address bit[1]
EEPROM_DO
I/O (I/O-O4)
EEPROM serial data out /
HW Configuration Address bit[2]
EEPROM_SK
I/O (I/O-O4)
EEPROM clock /
HW Configuration Address bit[3]
Notes:
Buffer Type: I=Input, I/O-O4=I/O with 4mA output driver
6.2.5 Clock and Test Signal Description
The 7955 has a phase locked loop reference signal that must be connected to a clock source
in all configurations. Bypassing the PLL is not a supported mode of operation for the 7955.
7955 - Data Sheet, DS-0114-08 33
Hifn Confidential
Table 19 PLL Signals
PLL Signal
I/O
Description
PLL_REF
Input (CI)
PLL reference clock input or system clock (7955
Security Accelerator). This signal is completely
asynchronous to the host bus interface, HBI_CLK,
(PQI_CLK, PQII_CLK and PCI_CLK). On 7955 Security
Accelerator, this signal is the input to a clock-
multiplier PLL, which provides the clock for the packet
engine and PK processor subsystems.
Notes:
The 7955 requires a clock source to drive the PLL_REF input pin in all configurations.
This clock input pin must not be grounded when register to a 0b0 to select the HBI_CLK
as the PLL source will fail unless PLL the HBI_CLK (PQI_CLK or PCI_CLK) is used to
drive the internal PLL.
Programming bit 0 (PLL_REF_SEL) of the PLL Configuration _REF is driven by a clock
source. Once the PLL Configuration register has been programmed, the PLL_REF input
requires four rising edges to complete the PLL clock source reconfiguration. Once the
four clocks have been completed, the PLL lock time, as specified in the Timing
Specifications shown in Table 24 for PLL_REF, will begin.
When using PLL_REF as the clock source to the PLL, all timing requirements as stated in
Table 24 must be met. When using PLL_REF to reconfigure the PLL source to the
HBI_CLK, the clock frequency still must not exceed the values specified in Table 24 but
the minimum frequency doesn’t apply. Any source that will provide the required four
clocks can be used.
One solution for customers that use an EEPROM (EEPROM_EN=0b1) to configure the
device is to connect the EEPROM_SK signal to the PLL_REF input pin as well as to the
EEPROM. In this case, the PLL clock source is guaranteed to be configured to the
HBI_CLK within 2050 PCI clock periods after writing to the PLL Configuration register.
Note:
Buffer Type: CI=clock input
The following signals are used for testing the 7955.
Table 20 Test and JTAG signals
Test Signal
I/O (Buffer type)
Description
TEST_EN
Input (I)
Test mode enable. It is normally tied low at all times
JTDI
Input (PI)
JTAG test data in
JTDO
Output (TS-O4)
JTAG test data out
JTMS
Input (PI)
JTAG test mode select
JTCK
Input (PI)
JTAG test clock
JTRST#
Input (PI)
JTAG test mode reset. This should not be tied to the
system reset signal. It is normally tied low at all times
except JTAG testing.
Note:
Buffer Type: PI-Input with pull-up resistor, TS-O4=Tri-State with 4mA output driver
7955 - Data Sheet, DS-0114-08 34
Hifn Confidential
6.2.6 Power and Ground Signal Description
The following power and ground signals must be connected as shown below for proper
device operation.
Table 21 Power and Ground signals
Misc. Signal
I/O
Description
VSS
Ground
Digital ground for output buffers
VSS2
Ground
Digital ground for input buffers, internal arrays & pre-
buffers
VDDC
Power
Power for 1.5 V internal logic
VDDS
Power
Power for 3.3 V output buffers
Tie these
together
VDDS2
Power
Power for 3.3 V input buffers & pre-
buffers
VDDS12
Power
Power for 3.3 V input & output buffers
& pre-buffers
AVS
Ground
PLL Analog ground
AVD
Power
PLL 1.5 V Analog supply
RESERVED_VSS
Input
Must be tied to VSS (series resistor is optional)
RESERVED_NC
Output
Must not be connected
7955 - Data Sheet, DS-0114-08 35
Hifn Confidential
7 Timing Specifications
7.1 AC Operating Conditions
Table 22 AC Operating Conditions
Symbol
Parameter
Conditions*
VDDC
Supply voltage - Core
1.5V ± 5%
VDDS
Supply voltage – I/O
3.3V ± 10%
VSS
Ground potential
0V
TA
Ambient operating temperature
0°C to +70°C
Note:
(*) See de-rating information below for other load conditions.
7.2 Host Bus Interface Clock
1
32
4 5
Figure 8 Input Bus Clock Timing
Table 23 PCI_CLK Timing
Number
Description
Min
Max
Units
1
Clock frequency
DC
66
MHz
Clock period
Infinite
15
ns
2
Clock width high
6
ns
3
Clock width low
6
ns
4
Clock rise time from VIL to VIH
2
ns
5
Clock fall time from VIH to VIL
2
ns
7955 - Data Sheet, DS-0114-08 36
Hifn Confidential
Table 24 PQI_CLK Timing
Number
Description
Min
Max
Units
1
Clock frequency
DC
40
MHz
Clock period
Infinite
25
ns
2
Clock width high
6
ns
3
Clock width low
6
ns
4
Clock rise time from VIL to VIH
2
ns
5
Clock fall time from VIH to VIL
2
ns
Table 25 PQII_CLK Timing
Number
Description
Min
Max
Units
1
Clock frequency
DC
66
MHz
Clock period
Infinite
15
ns
2
Clock width high
6
ns
3
Clock width low
6
ns
4
Clock rise time from VIL to VIH
2
ns
5
Clock fall time from VIH to VIL
2
ns
Table 26 PLL_REF Clock
Number
Description
Min
Max
Units
1
Clock frequency
20
100
MHz
Clock Period
50
10
ns
2
Clock width high
4.5
ns
3
Clock width low
4.5
ns
4
Clock rise time from VIL to VIH
2
ns
5
Clock fall time from VIH to VIL
2
ns
n/a
Duty cycle
45
55
%
n/a
Jitter (peak to peak)
100
ps
n/a
PLL lock time
100*n
usec
Note:
n = (PLL_ND+1)*2 (see the PLL Configuration Register description in the
7954/7955/7956 Hardware Users Guide (UG-0034) for more information on
the PLL_ND setting).
7955 - Data Sheet, DS-0114-08 37
Hifn Confidential
7.3 PCI Timing
Table 27 PCI Timing Parameters
Symbol
Parameter
Min
Max
Units
Tval
PCI_CLK to Signal Valid Delay
– bused signals
2
6
ns
Tval (ptp)
PCI_CLK to Signal Valid Delay
– point to point signals
2
6
ns
Ton
Float to Active Delay
2
ns
Toff
Active to Float Delay
14
ns
Tsu
Input setup time to PCI_CLK –
bused signals
3
ns
Tsu
(ptp)
Input setup time to PCI_CLK –
point to point signals
5
ns
Th
Input Hold time from PCI_CLK
0
ns
Trst
Reset Active Time after power
stable
1
ms
Trst-clk
Reset Active Time after
PCI_CLK stable
100
ms
Trst-off
Reset Active to output float
delay
40
ns
Trrsu
PCI_REQ64# to PCI_RST#
setup time
10Tcyc
ns
trrh
PCI_RST# to PCI_REQ# hold
time
0
50
ns
Trhfa
PCI_RST# high to first
Configuration access
2
clocks
Trhff
PCI_RST# high to first
PCI_FRAME# assertion
5
clock
Notes:
These specifications are taken from the PCI 2.2 Standard, section 7.6.4.2. PCI_REQ#
and PCI_GNT# are point to point signals and have different input setup times than do
bused signals.
7955 - Data Sheet, DS-0114-08 38
Hifn Confidential
7.4 PowerQuicc I Timing
Table 28 Read/Write Timing (PQI bus)
Number
Description
Min
Max
Units
1
PQI_A[0:31], PQI_TSIZ[0:1] input setup time
3
ns
2
PQI_CS#, PQI_TS#, PQI_BURST#, PQI_RD/WR#,
PQI_D[0:31] input setup time
5
ns
3
PQI_A[0:31], PQI_TS#, PQI_CS#, PQI_TSIZ[0:1],
PQI_BURST#, PQI_RD/WR#, PQI_D[0:31] input
hold time
0
ns
4
PQI_D[0:31],PQI_TA#, PQI_TEA# valid delay
2
7
ns
5
PQI_D[0:31],PQI_TA#, PQI_TEA# active to float
delay
14
ns
6
PQI_D[0:31],PQI_TA#, PQI_TEA# float to active
delay
2
ns
Notes
All signals are synchronous to PQI_CLK. Max values for output signals are for a 50 pF
load and Min values are for a 10 pF load. PQI_TEA# is not shown in the timing
diagram.
7955 - Data Sheet, DS-0114-08 39
Hifn Confidential
PQI_TS#
PQI_CS#
PQI_A[0:31]
PQI_TSIZ[0:1] 1
3
3
3
3
Write Operation
Read Operation
PQI_RD/WR#
PQI_D[0:31]
PQI_D[0:31]
PQI_RD/WR#
4,5
3
PQI_TA# 5
PQI_CLK
6
PQI_BURST#
3
3
4
4
4,6
2
2
2
2
2
2
Figure 9 PQI bus Read/Write Timing
7.5 PowerQuicc II Timing
Table 29 Read/Write Timing (PQII bus)
Number
Description
Min
Max
Units
1
PQII_A[0:31], PQII_TSIZ[0:3], PQII_TT[0:4] input
setup time
3
ns
2
PQII_CS#, PQII_TS#, PQII_TBST#, PQII_D[0:31],
PQII_DBB# input setup time
5
ns
3
PQII_A[0:31], PQII_TS#, PQII_CS#,
PQII_TSIZ[0:3], PQII_TBST#, PQII_TT[0:4],
PQII_D[0:31] , PQII_DBB# input hold time
0
ns
4
PQII_D[0:31], PQII_TA#, PQII_AACK#,
PQII_PSDVAL#, PQII_TEA# valid delay
2
7
ns
5
PQII_D[0:31], PQII_TA#, PQII_AACK#,
PQII_PSDVAL#, PQII_TEA# active to float delay
14
ns
6
PQII_D[0:31], PQII_TA#, PQII_AACK#,
PQII_PSDVAL#, PQII_TEA# float to active delay
2
ns
Notes
7955 - Data Sheet, DS-0114-08 40
Hifn Confidential
All signals are synchronous to PQII_CLK. Max values for output signals are for a 50
pF load and Min values are for a 10 pF load. PQII_TEA# is not shown in the timing
diagram.
PQII_TS#
PQII_AACK#
PQII_A[0:31]
PQII_TSIZ[0:3]
PQII_TT[0:4]
PQII_TBST
1
3
3
3
Write Operation
Read Operation
PQII_PSDVAL#
PQII_D[0:31]
PQII_D[0:31]
4,5
PQII_TA#
PQII_CLK
PQII_PSDVAL#
4,6
4,6
PQII_DBB#
PQII_CS#
3
5
5
5
4
4
4
4
4,6 5
4,6
6
4
3
3
2
2
2
2
2
Figure 10 PQII bus Read/Write Timing
7955 - Data Sheet, DS-0114-08 41
Hifn Confidential
7.6 EEPROM
The EEPROM interface signal timing is derived from the PCI_CLK divided by 256.
Table 30 EEPROM Timing
Number
Symbol
Min
Max
Units
1
Fsk
256 tPCI_CLK
ns
2
Tskh
128 tPCI_CLK – 5
ns
3
Tskl
128 tPCI_CLK – 5
ns
4
Tsks
128 tPCI_CLK – 5
ns
5
Tcs
256 tPCI_CLK – 5
ns
6
Tcss
128 tPCI_CLK – 10
ns
7
Tdh
0
ns
8
Tdis
128 tPCI_CLK – 10
ns
9
Tcsh
0
ns
10
Tdih
127 tPCI_CLK – 10
ns
11
Tpd0
127 tPCI_CLK – 10
ns
12
Tpd1
127 tPCI_CLK – 10
ns
Synchronous Data Timing
VIH
EEPROM_CS
EEPROM_SK
EEPROM_DO
EEPROM_DI
VIL
VIH
VIL
VIH
VIL
VOH
VOL
4
810
77
12
9
1
62 3
11
5
Figure 11 EEPROM Timing
7955 - Data Sheet, DS-0114-08 42
Hifn Confidential
8 DC Specifications
8.1 Absolute Maximum Ratings
Table 31 Absolute Maximum Ratings
DC Supply Voltage (VDDS, VDDS2, VDDS12)
–0.3V to +5.0V
DC Supply Voltage (VDDC, AVD)
-0.3V to +3.3V
DC Input Voltage (Signals)
–0.3V to VDDS+0.3
Storage Temperature
–40°C to +125°C
8.2 Power Sequencing
The +1.5V and +3.3V power supply voltages must be asserted at the same time. Otherwise,
the device may be damaged by reverse currents. To prevent damage to the device, these
voltages must be enabled within the time given in the recommended operating conditions.
The power supply should be designed to assert power within the time limits given under the
recommended operating conditions.
Warning
Stresses above those listed under Absolute Maximum Ratings may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions may affect device reliability.
7955 - Data Sheet, DS-0114-08 43
Hifn Confidential
8.3 Recommended Operating Conditions
Table 32 Recommended Operating Conditions
DC Supply Voltage (VDDS, VDDS2, VDDS12)
+3.0V to +3.6V
DC Supply Voltage (VDDC, AVD)
+1.425V to +1.575V
Delay from 1.5V (VDDC, PLL_AVD) power supply reaching
80% of its final value to 3.3V power supply (VDDS, VDDS2,
VDDS12) reaching 80% of its final value.
0 – 100ms
Delay from 3.3V power supply (VDDS, VDDS2, VDDS12)
falling below 80% of its initial value to 1.5V (VDDC,
PLL_AVD) power supply falling below 80% of its initial value.
0 – 100ms
Operating Temperature
0°C to +70°C
100 ms max 100 ms max
Turn On Turn Off
GND
Core Voltage* 80%
I/O Voltage* 80%
0 ms min0 ms min
Figure 12 Power Sequence Specifications
8.4 DC Characteristics
Table 33 DC Electrical Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Units
VIL
Low level input voltage (I, PI, I/O-
O4)
0.8
V
I-PCI, I/O-PCI, I-PQ, I/O-PQ
-0.5
1.17
Clock Input (CI)
0.72
VIH
High level input voltage (I, PI,
I/O-O4)
2.0
V
I-PCI, I/O-PCI, I-PQ, I/O-PQ
1.425
4.1
Clock Input (CI)
2.4
IIL
Low level input current (I, I/O-O4)
VIN = VSS
VDDS = 3.6V
-10
10
A
With pull-up (PI)
10
200
I-PCI, I/O-PCI, I-PQ, I/O-PQ
-10
10
IIH
High level input current (I, I/O-
O4)
VIN = VDDS
VDDS = 3.6V
-10
10
µA
I-PCI, I/O-PCI, I-PQ, I/O-PQ
-10
10
7955 - Data Sheet, DS-0114-08 44
Hifn Confidential
Symbol
Parameter
Conditions
Min
Typ
Max
Units
VOL
Low level output voltage
VDDS = 3.0V
V
(O4)
IOL = 4mA
0.4
I/O-PCI, TS-PCI, I/O-PQ, TS-
PQ
0.36
VOH
High level output voltage
VDDS = 3.0V
V
(O4)
IOH = -4mA
2.4
I/O-PCI, TS-PCI, I/O-PQ, TS-
PQ
2.7
IOZ
High impedance output leakage
current
VO = VSS or
VDDS
VDDS = 3.6V
-10
µA
IDD
Quiescent supply current
300
µA
CIN
Input capacitance (I, PI)
VDDS = 3.3V
2.4
pF
I-PCI, I/O-PCI, I-PQ, I/O-PQ
10
PCI_IDSEL
8
PCI_CLK, PQI_CLK, PQII_CLK
5
12
COUT
Output capacitance (TS-O4)
VDDS = 3.3V
5.6
pF
CI/O
I/O capacitance (I/O-O4)
VDDS = 3.3V
6.6
pF
IDD core
Active Supply Current (VDDC)
VDDC=1.575V
166
178
mA
IDD I/O
Active Supply Current (VDDS)
VDDS = 3.6V
115
165
mA
IAVD
PLL analog power supply current
AVD =
1.575V
6
mA
Notes:
Host Bus pins are shared between 32-bit PowerQuicc I & II and the 64-bit PCI.
Buffer Type: I=input, I/O-O4=Bi-directional with 4mA output driver, CI=Clock input, PI-Input with
pull-up resistor, TS-O4=Tri-State with 4mA output driver, I-PCI=PCI input, I/O-PCI=PCI
Input/Output, TS-PCI=PCI Tri-State output, I-PQ=PQ input, I/O-PQ=PQ Input/Output, TS-PQ=PQ
Tri-State output
7955 - Data Sheet, DS-0114-08 45
Hifn Confidential
9 Thermal Specifications
Table 34 Thermal Specifications
Parameter
Min
Typ
Max
Units
Junction Temperature (Tj)
0
100*
125*
ºC
Ambient Operating Temperature (Ta)
0
70
ºC
Storage Temperature
-40
125
ºC
Power Dissipation (P) @ VDDS = 3.6V
0.64
0.89
W
* For proper operation, the maximum junction temperature must not exceed 125 ºC.
However, the life of the part may be shortened if the average operating junction
temperature is allowed to exceed 100 ºC.
Table 35 LQFP Thermal Resistance
Parameter
Max
Units
Thermal Resistance, Junction to Ambient ( ja)
44.4
ºC/W
Thermal Resistance, Junction to Ambient ( jma at 1 m/s)
38.5
ºC/W
Internal Thermal Resistance ( jc)
12
ºC/W
Temperature Correlation, Center Top of Pkg to Junction (Ψjt)
0.4
ºC/W
9.1 Heat Sink Requirements
Refer to the 7954/7955/7956 Thermal Characteristics Application Note for additional
information to help determine the heat sink requirements.
9.2 Junction Temperature Specifications
The maximum operating junction temperature is 125 ºC. Above this temperature, operating
the part is not guaranteed. For maximum operating life the junction temperature in the
device should be no more than 100 ºC. Worst case device dissipation should be used when
performing thermal calculations. Refer to Thermal Management Application Note, AN-0038
for additional information to help determine application specific junction temperatures and
heat sink requirements.
7955 - Data Sheet, DS-0114-08 46
Hifn Confidential
10 Pin List
10.1 LQFP PCI-Mode Pin List
Table 36 LQFP PCI-Mode Pin List (Numerically)
Pin
Name
Pin
Name
Pin
Name
Pin
Name
1
TEST_EN
37
PCI_AD21
73
VSS2
109
PCI_AD51
2
JTDO
38
PCI_AD20
74
PCI_AD5
110
PCI_AD50
3
JTCK
39
PCI_AD19
75
PCI_AD4
111
PCI_AD49
4
JTRST#
40
VDDS
76
VSS
112
PCI_AD48
5
EEPROM_EN
41
PCI_AD18
77
PCI_AD3
113
VSS2
6
VDDS2
42
PCI_AD17
78
VDDS
114
VDDS
7
EEPROM_DO
43
PCI_AD16
79
VDDS2
115
PCI_AD47
8
EEPROM_CS
44
VSS
80
PCI_AD2
116
VSS
9
EEPROM_SK
45
PCI_CBE#2
81
PCI_AD1
117
PCI_AD46
10
EEPROM_DI
46
PCI_FRAME#
82
PCI_AD0
118
PCI_AD45
11
VSS2
47
PCI_IRDY#
83
PCI_ACK64#
119
PCI_AD44
12
VDDC
48
PCI_TRDY#
84
PCI_REQ64#
120
PCI_AD43
13
PCI_INTA#
49
PCI_DEVSEL#
85
PCI_CBE#7
121
PCI_AD42
14
PCI_RST#
50
PCI_STOP#
86
PCI_CBE#6
122
PCI_AD41
15
VDDS
51
VDDS
87
PCI_CBE#5
123
VDDC
16
PCI_CLK
52
PCI_PERR#
88
VSS
124
PCI_AD40
17
PCI_GNT#
53
VSS
89
PCI_CBE#4
125
VDDS2
18
VDDC
54
VSS2
90
VDDS12
126
VDDS
19
PCI_REQ#
55
VDDS2
91
PCI_PAR64
127
PCI_AD39
20
PCI_AD31
56
PCI_SERR#
92
VDDC
128
VSS
21
PCI_AD30
57
PCI_PAR
93
PCI_AD63
129
PCI_AD38
22
PCI_AD29
58
VDDC
94
VSS2
130
PCI_AD37
23
VSS
59
PCI_CBE#1
95
PCI_AD62
131
PCI_AD36
24
PCI_AD28
60
PCI_AD15
96
PCI_AD61
132
PCI_AD35
25
PCI_AD27
61
PCI_AD14
97
PCI_AD60
133
PCI_AD34
26
PCI_AD26
62
PCI_AD13
98
PCI_AD59
134
PCI_AD33
27
VDDS
63
PCI_AD12
99
PCI_AD58
135
PCI_AD32
28
PCI_AD25
64
VSS
100
PCI_AD57
136
VSS2
29
PCI_AD24
65
PCI_AD11
101
VDDS2
137
RESERVED_NC
30
VDDS2
66
VDDS
102
VSS
138
VDDS
31
PCI_CBE#3
67
PCI_AD10
103
PCI_AD56
139
AVS
32
PCI_IDSEL
68
PCI_AD9
104
VDDS
140
AVD
33
PCI_AD23
69
PCI_AD8
105
PCI_AD55
141
VSS
34
VSS2
70
PCI_CBE#0
106
PCI_AD54
142
JTMS
35
VDDC
71
PCI_AD7
107
PCI_AD53
143
JTDI
36
PCI_AD22
72
PCI_AD6
108
PCI_AD52
144
PLL_REF
7955 - Data Sheet, DS-0114-08 47
Hifn Confidential
Table 37 LQFP PCI-Mode Pin List (Alphabetically)
Pin
Name
Pin
Name
Pin
Name
Pin
Name
140
AVD
33
PCI_AD23
98
PCI_AD59
92
VDDC
139
AVS
29
PCI_AD24
97
PCI_AD60
123
VDDC
8
EEPROM_CS
28
PCI_AD25
96
PCI_AD61
15
VDDS
10
EEPROM_DI
26
PCI_AD26
95
PCI_AD62
27
VDDS
7
EEPROM_DO
25
PCI_AD27
93
PCI_AD63
40
VDDS
5
EEPROM_EN
24
PCI_AD28
70
PCI_CBE#0
51
VDDS
9
EEPROM_SK
22
PCI_AD29
59
PCI_CBE#1
66
VDDS
3
JTCK
21
PCI_AD30
45
PCI_CBE#2
78
VDDS
143
JTDI
20
PCI_AD31
31
PCI_CBE#3
104
VDDS
2
JTDO
135
PCI_AD32
89
PCI_CBE#4
114
VDDS
142
JTMS
134
PCI_AD33
87
PCI_CBE#5
126
VDDS
4
JTRST#
133
PCI_AD34
86
PCI_CBE#6
138
VDDS
83
PCI_ACK64#
132
PCI_AD35
85
PCI_CBE#7
90
VDDS12
82
PCI_AD0
131
PCI_AD36
16
PCI_CLK
6
VDDS2
81
PCI_AD1
130
PCI_AD37
49
PCI_DEVSEL#
30
VDDS2
80
PCI_AD2
129
PCI_AD38
46
PCI_FRAME#
55
VDDS2
77
PCI_AD3
127
PCI_AD39
17
PCI_GNT#
79
VDDS2
75
PCI_AD4
124
PCI_AD40
32
PCI_IDSEL
101
VDDS2
74
PCI_AD5
122
PCI_AD41
13
PCI_INTA#
125
VDDS2
72
PCI_AD6
121
PCI_AD42
47
PCI_IRDY#
23
VSS
71
PCI_AD7
120
PCI_AD43
57
PCI_PAR
44
VSS
69
PCI_AD8
119
PCI_AD44
91
PCI_PAR64
53
VSS
68
PCI_AD9
118
PCI_AD45
52
PCI_PERR#
64
VSS
67
PCI_AD10
117
PCI_AD46
19
PCI_REQ#
76
VSS
65
PCI_AD11
115
PCI_AD47
84
PCI_REQ64#
88
VSS
63
PCI_AD12
112
PCI_AD48
14
PCI_RST#
102
VSS
62
PCI_AD13
111
PCI_AD49
56
PCI_SERR#
116
VSS
61
PCI_AD14
110
PCI_AD50
50
PCI_STOP#
128
VSS
60
PCI_AD15
109
PCI_AD51
48
PCI_TRDY#
141
VSS
43
PCI_AD16
108
PCI_AD52
144
PLL_REF
11
VSS2
42
PCI_AD17
107
PCI_AD53
137
RESERVED_NC
34
VSS2
41
PCI_AD18
106
PCI_AD54
1
TEST_EN
54
VSS2
39
PCI_AD19
105
PCI_AD55
12
VDDC
73
VSS2
38
PCI_AD20
103
PCI_AD56
18
VDDC
94
VSS2
37
PCI_AD21
100
PCI_AD57
35
VDDC
113
VSS2
36
PCI_AD22
99
PCI_AD58
58
VDDC
136
VSS2
7955 - Data Sheet, DS-0114-08 48
Hifn Confidential
10.2 LQFP PCI Mode Pinout
TEST_EN
JTDO
JTCK
EEPROM_EN
VDDS2
EEPROM_DO
EEPROM_CS
EEPROM_SK
EEPROM_DI
VSS2
VDDC
PCI_RST#
VDDS
PCI_CLK
PCI_GNT#
PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD26
VDDS2
PCI_CBE#3
PCI_IDSEL
PCI_AD25
PCI_AD17
PCI_AD16
VSS
VSS2
VDDS2
PCI_SERR#
PCI_PAR
VSS
PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_DEVSEL#
PCI_STOP#
VDDS
PCI_PERR#
PCI_CBE#1
PCI_AD43
PCI_AD42
PCI_AD41
VDDC
PCI_AD40
VDDS
VSS
PCI_AD38
PCI_AD37
PCI_AD36
PCI_AD35
PCI_AD34
PCI_AD33
RESERVED_NC
AVS
AVD
VSS
JTMS
JTDI 37
38
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
VDDS
PCI_AD10
PCI_AD9
PCI_AD8
PCI_CBE#0
PCI_AD7
PCI_AD51
PCI_AD50
PCI_AD49
PCI_AD48
VSS2
PCI_AD23
VSS2
VDDC
PCI_AD22
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
VDDC
PCI_REQ#
VSS
PCI_AD27
VDDS
PCI_AD24
PCI_AD15
VDDS
PCI_AD47
VSS
PCI_AD46
PCI_AD45
PCI_AD44
VSS2
VDDS
VDDS2
PCI_AD39
PCI_AD32
PLL_REF
PCI_AD6
VSS
VDDC
PCI_AD21
PCI_AD20
PCI_AD19
VDDS
PCI_AD18
PCI_CBE#2
PCI_INTA#
JTRST#
PCI_REQ64#
PCI_CBE#7
PCI_CBE#6
PCI_CBE#5
VSS
PCI_CBE#4
PCI_PAR64
PCI_AD63
VSS2
PCI_AD62
PCI_AD61
PCI_AD59
PCI_AD58
PCI_AD57
VDDS2
VSS
PCI_AD56
VDDS
PCI_AD55
PCI_AD54
PCI_AD53
VDDS
VSS2
PCI_AD5
PCI_AD4
VSS
PCI_AD3
PCI_ACK64#
VDDS2
PCI_AD2
PCI_AD1
PCI_AD0
VDDS12
PCI_AD60
PCI_AD52
VDDC
Figure 13 LQFP PCI Mode Pinout Drawing
7955 - Data Sheet, DS-0114-08 49
Hifn Confidential
10.3 LQFP PQI Mode Pin List
Table 38 LQFP PQI Mode Pin List (Numerically)
Pin
Name
Pin
Name
Pin
Name
Pin
Name
1
TEST_EN
37
PQI_A10
73
VSS2
109
PQI_D12
2
JTDO
38
PQI_A11
74
PQI_A26
110
PQI_D13
3
JTCK
39
PQI_A12
75
PQI_A27
111
PQI_D14
4
JTRST#
40
VDDS
76
VSS
112
PQI_D15
5
EEPROM_EN
41
PQI_A13
77
PQI_A28
113
VSS2
6
VDDS2
42
PQI_A14
78
VDDS
114
VDDS
7
EEPROM_DO
43
PQI_A15
79
VDDS2
115
PQI_D16
8
EEPROM_CS
44
VSS
80
PQI_A29
116
VSS
9
EEPROM_SK
45
PQI_TSIZ0
81
PQI_A30
117
PQI_D17
10
EEPROM_DI
46
RESERVED_VDD
82
PQI_A31
118
PQI_D18
11
VSS2
47
PQI_BURST#
83
RESERVED_VSS
119
PQI_D19
12
VDDC
48
RESERVED_VSS
84
RESERVED_VSS
120
PQI_D20
13
PQI_INT#
49
RESERVED_VSS
85
RESERVED_VSS
121
PQI_D21
14
PQI_RST#
50
RESERVED_VSS
86
RESERVED_VSS
122
PQI_D22
15
VDDS
51
VDDS
87
RESERVED_VSS
123
VDDC
16
PQI_CLK
52
PQI_TA#
88
VSS
124
PQI_D23
17
PQI_TS#
53
VSS
89
PQI_RW#
125
VDDS2
18
VDDC
54
VSS2
90
VDDS12
126
VDDS
19
RESERVED_NC
55
VDDS2
91
RESERVED_VSS
127
PQI_D24
20
PQI_A0
56
PQI_TEA#
92
VDDC
128
VSS
21
PQI_A1
57
RESERVED_VSS
93
PQI_D0
129
PQI_D25
22
PQI_A2
58
VDDC
94
VSS2
130
PQI_D26
23
VSS
59
RESERVED_VSS
95
PQI_D1
131
PQI_D27
24
PQI_A3
60
PQI_A16
96
PQI_D2
132
PQI_D28
25
PQI_A4
61
PQI_A17
97
PQI_D3
133
PQI_D29
26
PQI_A5
62
PQI_A18
98
PQI_D4
134
PQI_D30
27
VDDS
63
PQI_A19
99
PQI_D5
135
PQI_D31
28
PQI_A6
64
VSS
100
PQI_D6
136
VSS2
29
PQI_A7
65
PQI_A20
101
VDDS2
137
RESERVED_NC
30
VDDS2
66
VDDS
102
VSS
138
VDDS
31
PQI_TSIZ1
67
PQI_A21
103
PQI_D7
139
AVS
32
PQI_CS#
68
PQI_A22
104
VDDS
140
AVD
33
PQI_A8
69
PQI_A23
105
PQI_D8
141
VSS
34
VSS2
70
RESERVED_VSS
106
PQI_D9
142
JTMS
35
VDDC
71
PQI_A24
107
PQI_D10
143
JTDI
36
PQI_A9
72
PQI_A25
108
PQI_D11
144
PLL_REF
7955 - Data Sheet, DS-0114-08 50
Hifn Confidential
Table 39 LQFP PQI Mode Pin List (Alphabetically)
Pin
Name
Pin
Name
Pin
Name
Pin
Name
140
AVD
69
PQI_A23
127
PQI_D24
92
VDDC
139
AVS
71
PQI_A24
129
PQI_D25
123
VDDC
8
EEPROM_CS
72
PQI_A25
130
PQI_D26
15
VDDS
10
EEPROM_DI
74
PQI_A26
131
PQI_D27
27
VDDS
7
EEPROM_DO
75
PQI_A27
132
PQI_D28
40
VDDS
5
EEPROM_EN
77
PQI_A28
133
PQI_D29
51
VDDS
9
EEPROM_SK
80
PQI_A29
134
PQI_D30
66
VDDS
3
JTCK
81
PQI_A30
135
PQI_D31
78
VDDS
143
JTDI
82
PQI_A31
13
PQI_INT#
104
VDDS
2
JTDO
47
PQI_burst#
14
PQI_RST#
114
VDDS
142
JTMS
16
PQI_CLK
89
PQI_rw#
126
VDDS
4
JTRST#
32
PQI_CS#
52
PQI_TA#
138
VDDS
144
PLL_REF
93
PQI_D0
56
PQI_tea#
90
VDDS12
20
PQI_A0
95
PQI_D1
17
PQI_Ts#
6
VDDS2
21
PQI_A1
96
PQI_D2
45
PQI_tsiz0
30
VDDS2
22
PQI_A2
97
PQI_D3
31
PQI_tsiz1
55
VDDS2
24
PQI_A3
98
PQI_D4
19
RESERVED_NC
79
VDDS2
25
PQI_A4
99
PQI_D5
46
RESERVED_VDD
101
VDDS2
26
PQI_A5
100
PQI_D6
85
RESERVED_VSS
125
VDDS2
28
PQI_A6
103
PQI_D7
86
RESERVED_VSS
23
VSS
29
PQI_A7
105
PQI_D8
87
RESERVED_VSS
44
VSS
33
PQI_A8
106
PQI_D9
59
RESERVED_VSS
53
VSS
36
PQI_A9
107
PQI_D10
70
RESERVED_VSS
64
VSS
37
PQI_A10
108
PQI_D11
48
RESERVED_VSS
76
VSS
38
PQI_A11
109
PQI_D12
49
RESERVED_VSS
88
VSS
39
PQI_A12
110
PQI_D13
50
RESERVED_VSS
102
VSS
41
PQI_A13
111
PQI_D14
57
RESERVED_VSS
116
VSS
42
PQI_A14
112
PQI_D15
83
RESERVED_VSS
128
VSS
43
PQI_A15
115
PQI_D16
84
RESERVED_VSS
141
VSS
60
PQI_A16
117
PQI_D17
91
RESERVED_VSS
11
VSS2
61
PQI_A17
118
PQI_D18
137
RESERVED_NC
34
VSS2
62
PQI_A18
119
PQI_D19
1
TEST_EN
54
VSS2
63
PQI_A19
120
PQI_D20
12
VDDC
73
VSS2
65
PQI_A20
121
PQI_D21
18
VDDC
94
VSS2
67
PQI_A21
122
PQI_D22
35
VDDC
113
VSS2
68
PQI_A22
124
PQI_D23
58
VDDC
136
VSS2
7955 - Data Sheet, DS-0114-08 51
Hifn Confidential
10.4 LQFP PQI Mode Pinout
TEST_EN
JTDO
JTCK
EEPROM_EN
VDDS2
EEPROM_DO
EEPROM_CS
EEPROM_SK
EEPROM_DI
VSS2
VDDC
PQI_RST#
VDDS
PQI_CLK
PQI_TS#
PQI_A0
PQI_A1
PQI_A2
PQI_A3
PQI_A5
VDDS2
PQI_TSIZ1
PQI_CS#
PQI_A6
PQI_A14
PQI_A15
VSS
VSS2
VDDS2
PQI_TEA#
RESERVED_VSS
VSS
RESERVED_VDD
PQI_BURST#
RESERVED_VSS
RESERVED_VSS
RESERVED_VSS
VDDS
PQI_TA#
RESERVED_VSS
PQI_D20
PQI_D21
PQI_D22
VDDC
PQI_D23
VDDS
VSS
PQI_D25
PQI_D26
PQI_D27
PQI_D28
PQI_D29
PQI_D30
RESERVED_NC
AVS
AVD
VSS
JTMS
JTDI 37
38
PQI_A17
PQI_A18
PQI_A19
PQI_A20
VDDS
PQI_A21
PQI_A22
PQI_A23
RESERVED_VSS
PQI_A24
PQI_D12
PQI_D13
PQI_D14
PQI_D15
VSS2
PQI_A8
VSS2
VDDC
PQI_A9
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
VDDC
RESERVED_NC
VSS
PQI_A4
VDDS
PQI_A7
PQI_A16
VDDS
PQI_D16
VSS
PQI_D17
PQI_D18
PQI_D19
VSS2
VDDS
VDDS2
PQI_D24
PQI_D31
PLL_REF
PQI_A25
VSS
VDDC
PQI_A10
PQI_A11
PQI_A12
VDDS
PQI_A13
PQI_TSIZ0
PQI_INT#
JTRST#
RESERVED_VSS
RESERVED_VSS
RESERVED_VSS
RESERVED_VSS
VSS
PQI_RW#
RESERVED_VSS
PQI_D0
VSS2
PQI_D1
PQI_D2
PQI_D4
PQI_D5
PQI_D6
VDDS2
VSS
PQI_D7
VDDS
PQI_D8
PQI_D9
PQI_D10
VDDS
VSS2
PQI_A26
PQI_A27
VSS
PQI_A28
RESERVED_VSS
VDDS2
PQI_A29
PQI_A30
PQI_A31
VDDS12
PQI_D3
PQI_D11
VDDC
Figure 14 LQFP PQI Mode Pinout Drawing
7955 - Data Sheet, DS-0114-08 52
Hifn Confidential
10.5 LQFP PQII Mode Pin List
Table 40 LQFP PQII Mode Pin List (Numerically)
Pin
Name
Pin
Name
Pin
Name
Pin
Name
1
TEST_EN
37
PQII_A10
73
VSS2
109
PQII_D12
2
JTDO
38
PQII_A11
74
PQII_A26
110
PQII_D13
3
JTCK
39
PQII_A12
75
PQII_A27
111
PQII_D14
4
JTRST#
40
VDDS
76
VSS
112
PQII_D15
5
EEPROM_EN
41
PQII_A13
77
PQII_A28
113
VSS2
6
VDDS2
42
PQII_A14
78
VDDS
114
VDDS
7
EEPROM_DO
43
PQII_A15
79
VDDS2
115
PQII_D16
8
EEPROM_CS
44
VSS
80
PQII_A29
116
VSS
9
EEPROM_SK
45
PQII_TSIZ2
81
PQII_A30
117
PQII_D17
10
EEPROM_DI
46
RESERVED_VDD
82
PQII_A31
118
PQII_D18
11
VSS2
47
PQII_TBST#
83
PQII_PSDVAL#
119
PQII_D19
12
VDDC
48
PQII_DBB#
84
PQII_AACK#
120
PQII_D20
13
PQII_INT#
49
RESERVED_VSS
85
PQII_TT4
121
PQII_D21
14
PQII_RST#
50
RESERVED_VSS
86
PQII_TT3
122
PQII_D22
15
VDDS
51
VDDS
87
PQII_TT2
123
VDDC
16
PQII_CLK
52
PQII_TA#
88
VSS
124
PQII_D23
17
PQII_TS#
53
VSS
89
PQII_TT1
125
VDDS2
18
VDDC
54
VSS2
90
VDDS12
126
VDDS
19
RESERVED_NC
55
VDDS2
91
PQII_TT0
127
PQII_D24
20
PQII_A0
56
PQII_TEA#
92
VDDC
128
VSS
21
PQII_A1
57
RESERVED_VSS
93
PQII_D0
129
PQII_D25
22
PQII_A2
58
VDDC
94
VSS2
130
PQII_D26
23
VSS
59
PQII_TSIZ1
95
PQII_D1
131
PQII_D27
24
PQII_A3
60
PQII_A16
96
PQII_D2
132
PQII_D28
25
PQII_A4
61
PQII_A17
97
PQII_D3
133
PQII_D29
26
PQII_A5
62
PQII_A18
98
PQII_D4
134
PQII_D30
27
VDDS
63
PQII_A19
99
PQII_D5
135
PQII_D31
28
PQII_A6
64
VSS
100
PQII_D6
136
VSS2
29
PQII_A7
65
PQII_A20
101
VDDS2
137
RESERVED_NC
30
VDDS2
66
VDDS
102
VSS
138
VDDS
31
PQII_TSIZ3
67
PQII_A21
103
PQII_D7
139
AVS
32
PQII_CS#
68
PQII_A22
104
VDDS
140
AVD
33
PQII_A8
69
PQII_A23
105
PQII_D8
141
VSS
34
VSS2
70
PQII_TSIZ0
106
PQII_D9
142
JTMS
35
VDDC
71
PQII_A24
107
PQII_D10
143
JTDI
36
PQII_A9
72
PQII_A25
108
PQII_D11
144
PLL_REF
7955 - Data Sheet, DS-0114-08 53
Hifn Confidential
Table 41 LQFP PQII Mode Pin List (Alphabetically)
Pin
Name
Pin
Name
Pin
Name
Pin
Name
140
AVD
69
PQII_A23
127
PQII_D24
92
VDDC
139
AVS
71
PQII_A24
129
PQII_D25
123
VDDC
8
EEPROM_CS
72
PQII_A25
130
PQII_D26
15
VDDS
10
EEPROM_DI
74
PQII_A26
131
PQII_D27
27
VDDS
7
EEPROM_DO
75
PQII_A27
132
PQII_D28
40
VDDS
5
EEPROM_EN
77
PQII_A28
133
PQII_D29
51
VDDS
9
EEPROM_SK
80
PQII_A29
134
PQII_D30
66
VDDS
3
JTCK
81
PQII_A30
135
PQII_D31
78
VDDS
143
JTDI
82
PQII_A31
48
PQII_DBB#
104
VDDS
2
JTDO
84
PQII_AACK#
13
PQII_INT#
114
VDDS
142
JTMS
16
PQII_CLK
83
PQII_PSDVAL#
126
VDDS
4
JTRST#
32
PQII_CS#
14
PQII_RST#
138
VDDS
144
PLL_REF
93
PQII_D0
52
PQII_TA#
90
VDDS12
20
PQII_A0
95
PQII_D1
47
PQII_TBST#
6
VDDS2
21
PQII_A1
96
PQII_D2
56
PQII_TEA#
30
VDDS2
22
PQII_A2
97
PQII_D3
17
PQII_TS#
55
VDDS2
24
PQII_A3
98
PQII_D4
70
PQII_TSIZ0
79
VDDS2
25
PQII_A4
99
PQII_D5
59
PQII_TSIZ1
101
VDDS2
26
PQII_A5
100
PQII_D6
45
PQII_TSIZ2
125
VDDS2
28
PQII_A6
103
PQII_D7
31
PQII_TSIZ3
23
VSS
29
PQII_A7
105
PQII_D8
91
PQII_TT0
44
VSS
33
PQII_A8
106
PQII_D9
89
PQII_TT1
53
VSS
36
PQII_A9
107
PQII_D10
87
PQII_TT2
64
VSS
37
PQII_A10
108
PQII_D11
86
PQII_TT3
76
VSS
38
PQII_A11
109
PQII_D12
85
PQII_TT4
88
VSS
39
PQII_A12
110
PQII_D13
19
RESERVED_NC
102
VSS
41
PQII_A13
111
PQII_D14
46
RESERVED_VDD
116
VSS
42
PQII_A14
112
PQII_D15
49
RESERVED_VSS
128
VSS
43
PQII_A15
115
PQII_D16
50
RESERVED_VSS
141
VSS
60
PQII_A16
117
PQII_D17
57
RESERVED_VSS
11
VSS2
61
PQII_A17
118
PQII_D18
137
RESERVED_NC
34
VSS2
62
PQII_A18
119
PQII_D19
1
TEST_EN
54
VSS2
63
PQII_A19
120
PQII_D20
12
VDDC
73
VSS2
65
PQII_A20
121
PQII_D21
18
VDDC
94
VSS2
67
PQII_A21
122
PQII_D22
35
VDDC
113
VSS2
68
PQII_A22
124
PQII_D23
58
VDDC
136
VSS2
7955 - Data Sheet, DS-0114-08 54
Hifn Confidential
10.6 LQFP PQII Mode Pinout
TEST_EN
JTDO
JTCK
EEPROM_EN
VDDS2
EEPROM_DO
EEPROM_CS
EEPROM_SK
EEPROM_DI
VSS2
VDDC
PQII_RST#
VDDS
PQII_CLK
PQII_TS#
PQII_A0
PQII_A1
PQII_A2
PQII_A3
PQII_A5
VDDS2
PQII_TSIZ3
PQII_CS#
PQII_A6
PQII_A14
PQII_A15
VSS
VSS2
VDDS2
PQI_TEA#
RESERVED_VSS
VSS
RESERVED_VDD
PQII_TBST#
PQII_DBB#
RESERVED_VSS
RESERVED_VSS
VDDS
PQII_TA#
PQII_TSIZ1
PQII_D20
PQII_D21
PQII_D22
VDDC
PQII_D23
VDDS
VSS
PQII_D25
PQII_D26
PQII_D27
PQII_D28
PQII_D29
PQII_D30
RESERVED_NC
AVS
AVD
VSS
JTMS
JTDI 37
38
PQII_A17
PQII_A18
PQII_A19
PQII_A20
VDDS
PQII_A21
PQII_A22
PQII_A23
PQII_TSIZ0
PQII_A24
PQII_D12
PQII_D13
PQII_D14
PQII_D15
VSS2
PQII_A8
VSS2
VDDC
PQII_A9
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
VDDC
RESERVED_NC
VSS
PQII_A4
VDDS
PQII_A7
PQII_A16
VDDS
PQII_D16
VSS
PQII_D17
PQII_D18
PQII_D19
VSS2
VDDS
VDDS2
PQII_D24
PQII_D31
PLL_REF
PQII_A25
VSS
VDDC
PQII_A10
PQII_A11
PQII_A12
VDDS
PQII_A13
PQII_TSIZ2
PQII_INT#
JTRST#
PQII_AACK#
PQII_TT4
PQII_TT3
PQII_TT2
VSS
PQII_TT1
PQII_TT0
PQII_D0
VSS2
PQII_D1
PQII_D2
PQII_D4
PQII_D5
PQII_D6
VDDS2
VSS
PQII_D7
VDDS
PQII_D8
PQII_D9
PQII_D10
VDDS
VSS2
PQII_A26
PQII_A27
VSS
PQII_A28
PQII_PSDVAL#
VDDS2
PQII_A29
PQII_A30
PQII_A31
VDDS12
PQII_D3
PQII_D11
VDDC
Figure 15 LQFP PQII Mode Pinout Drawing
7955 - Data Sheet, DS-0114-08 55
Hifn Confidential
11 Physical Specifications
11.1 LQFP 144-pin Plastic Quad Flatpack
20.0±0.1
22.0±0.2
20.0±0.1
22.0±0.2
1.25
TYP 0.5 M
0.08
1.4±0.05
1.7 MAX
0.1±0.05
0~10°
0.22
0.08
0.145 +0.055
–0.04
5
All units in millimeters
0.45min,
0.75max
-0.04
+0.05
Figure 16 144 LQFP Package
7955 - Data Sheet, DS-0114-08 56
Hifn Confidential
Document Changes/Revisions
Documentation Changes include additions, deletions, and modifications made to this
document. This section identifies the changes made in each release of the document.
Document Revision 01
Update 1. Added PCI Mode and PQI Mode Pinout drawings.
Section 10.
Document Revision 02
Update 1. Added MPC8260 PowerQuicc II Mode throughout document.
Corrected PCI Register Configuration without EEPROM Device ID from to
0x0020 to 0x001D.
Section 5.2.2, Table 10, page 16.
Update 2. Added PowerQuicc II timing diagrams to new section 7.5.
Section 7.5, Table 27 and Figure 10, pages 34-35.
Update 3. Added access type to transfer size description.
Section 6.2.2, Table 15, page 25. Section 6.2.3, Table 16, page 26.
Update 4. Added definition of transfer type for PowerQuicc II access.
Section 6.2.2, Table 15, page 25.
Update 5. Clearly stated that PLL bypass mode is not supported.
Section 6.2.5, page 28.
Document Revision 03
Update 1. Removed 33 MHz and 66 MHz speeds on PCI timing specifications.
Section 7.3, Table 27.
Update 2. Added EEPROM chip select methods for PowerQuiccI and PowerQuicc II.
Section 5.2.1, Table 8 (new).
Update 3. Added bus transaction restrictions for PowerQuiccI and PowerQuicc II.
Sections 6.2.2 and 6.2.3.
Update 4. Added PQII_TBST#, PQII_CS# signals to the timing diagrams and timing
specifications for PowerQuicc II.
Section 7.5, Table 29, Figure 10.
7955 - Data Sheet, DS-0114-08 57
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Update 5. Changed transfer size access types allowed for the bus transactions in
PowerQuiccI and PowerQuicc II.
Section 6.2.2, Table 16 and Section 6.2.3, Table 17.
Update 6. Modified the timing parameters for PowerQuiccI and PowerQuicc II read and
write bus transactions and the timing diagrams accordingly.
Section 7.5, Table 29 and Figure 10. Section 7.4, Table 28 and Figure 9.
Update 7. Changed all references to “Context” memory to “Local” memory.
Section 4.1, Table 6, Figure 2
Document Revision 04
Update 1. Changed Device ID default value to 0x0020.
Section 5.2.2, Table 11
Document Revision 05
Update 1. Updated PCI Configuration space table.
Section 5.2.2, Table 11
Update 2. Changed text for EEPROM_EN signal. EEPROM configuration is selected when
the EEPROM_EN input is high.
Section 6.2.4, Table 18
Update 3. Corrected RESERVED_VSS input connection to high instead of VSS.
Section 6.2.6, Table 21
Update 4. Removed power down sequence deassertion delay to the Absolute maximum
ratings.
Section 8.1, Table 31
Update 5. Added power down sequence deassertion delay to the Recommended
Operating conditions and added new Figure 12, Power Sequence
Specifications.
Section 8.3, Table 32 and Figure 12
Update 6. Corrected EEPROM address 0x0B reset value to 0x01.
Section 5.2.1, Table 7.
Document Revision 06
Update 1. Updated template. All sections.
Update 2. Updated power dissipation in section 9 Thermal Specifications, Table 34.
Document Revision 07
Update 1. Internal change.
7955 - Data Sheet, DS-0114-08 58
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Document Revision 08
Update 1. Internal change.
