AGLN020V2-UCG81 - Actel Corporation

January 2010 I

IGLOO nano Low-Power Flash FPGAs

with Flash*Freeze Technology

Features and Benefits

Low Power

• nanoPower Consumption—Industry’s Lowest Power

• 1.2 V to 1.5 V Core Voltage Support for Low Power

• Supports Single-Voltage System Operation

• Low-Power Active FPGA Operation

• Flash*Freeze Technology Enables Ultra-Low Power

Consumption while Maintaining FPGA Content

• Easy Entry to / Exit from Ultra-Low-Power Flash*Freeze

Mode

Small Footprint Packages

• As Small as 3x3 mm in Size

Wide Range of Features

• 10 k to 250 k System Gates

• Up to 36 kbits of True Dual-Port SRAM

• Up to 71 User I/Os

Reprogrammable Flash Technology

• 130-nm, 7-Layer Metal, Flash-Based CMOS Process

• Live-at-Power-Up (LAPU) Level 0 Support

• Single-Chip Solution

• Retains Programmed Design When Powered Off

• 250 MHz (1.5 V systems) and 160 MHz (1.2 V systems) System

Performance

In-System Programming (ISP) and Security

• Secure ISP Using On-Chip 128-Bit Advanced Encryption

Standard (AES) Decryption via JTAG (IEEE 1532–compliant)

•FlashLock

® to Secure FPGA Contents

High-Performance Routing Hierarchy

• Segmented, Hierarchical Routing and Clock Structure

Advanced I/Os

• 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation

• Bank-Selectable I/O Voltages—up to 4 Banks per Chip

• Single-Ended I/O Standards: LVTTL, LVCMOS

3.3 V / 2.5 V / 1.8 V / 1.5 V / 1.2 V

• Wide Range Power Supply Voltage Support per JESD8-B,

Allowing I/Os to Operate from 2.7 V to 3.6 V

• Wide Range Power Supply Voltage Support per JESD8-12,

Allowing I/Os to Operate from 1.14 V to 1.575 V

• I/O Registers on Input, Output, and Enable Paths

• Selectable Schmitt Trigger Inputs

• Hot-Swappable and Cold-Sparing I/Os

• Programmable Output Slew Rate and Drive Strength

• Weak Pull-Up/-Down

• IEEE 1149.1 (JTAG) Boundary Scan Test

• Pin-Compatible Packages across the IGLOO Family

Clock Conditioning Circuit (CCC) and PLL†

• Up to Six CCC Blocks, One with an Integrated PLL

• Configurable Phase Shift, Multiply/Divide, Delay

Capabilities, and External Feedback

• Wide Input Frequency Range (1.5 MHz up to 250 MHz)

Embedded Memory

• 1 kbit of FlashROM User Nonvolatile Memory

• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM

Blocks (×1, ×2, ×4, ×9, and ×18 organizations)†

• True Dual-Port SRAM (except × 18 organization)†

Enhanced Commercial Temperature Range

• –20°C to +70°C

† AGLN030 and smaller devices do not support this feature.

Table 1 • IGLOO nano Devices

IGLOO nano Devices AGLN010 AGLN015 AGLN020 AGLN030 1AGLN060 AGLN125 AGLN250

System Gates 10 k 15 k 20 k 30 k 60 k 125 k 250 k

Typical Equivalent Macrocells 86 128 172 256 512 1,024 2,048

VersaTiles (D-flip-flops) 260 384 520 768 1,536 3,072 6,144

Flash*Freeze Mode (typical, µW) 2 4 4 5 10 16 24

RAM kbits (1,024 bits) 2– – – – 18 36 36

4,608-Bit Blocks 2––– – 4 8 8

FlashROM Bits 1 k 1 k 1 k 1 k 1 k 1 k 1 k

Secure (AES) ISP 2––– –YesYesYes

Integrated PLL in CCCs 2,3 ––– – 1 1 1

VersaNet Globals 4 4 4 6 18 18 18

I/O Banks 233 2 2 2 4

Maximum User I/Os (packaged device) 34 49 52 77 71 71 68

Maximum User I/Os (Known Good Die) 34 – 52 83 71 71 68

Package Pins

UC/CS

QFN

VQFP

UC36

QN48 QN68

UC81, CS81

QN68

UC81, CS81

QN48, QN68

VQ100

CS81

VQ100

CS81

VQ100

CS81

VQ100

Notes:

1. AGLN030 is available in the Z feature grade only.

2. AGLN030 and smaller devices do not support this feature.

3. AGLN060, AGLN125, and AGLN250 in the CS81 package do not support PLLs.

4. For higher densities and support of additional features, refer to the IGLOO and IGLOOe handbooks.

Advance v0.8

IGLOO nano Low-Power Flash FPGAs

II Advance v0.8

I/Os Per Package

IGLOO nano Devices AGLN010 AGLN015 AGLN020 AGLN030 1AGLN060 AGLN125 AGLN250

Known Good Die 34 – 52 83 71 71 68

UC36 23

QN48 34 34

QN68 49 49 49

UC81 52 66

CS81 52 66 60 60 60

VQ100 77 71 71 68

Notes:

1. AGLN030 is available in the Z feature grade only and offers package compatibility with the lower density nano devices. Refer

to "IGLOO nano Ordering Information" on page III.

2. When considering migrating your design to a lower- or higher-density device, refer to the IGLOO Handbook to ensure

compliance with design and board migration requirements.

3. When the Flash*Freeze pin is used to directly enable Flash*Freeze mode and not used as a regular I/O, the number of single-

ended user I/Os available is reduced by one.

4. "G" indicates RoHS-compliant packages. Refer to "IGLOO nano Ordering Information" on page III for the location of the "G"

in the part number. For nano devices, the VQ100 package is offered in both leaded and RoHS-compliant versions. All other

packages are RoHS-compliant only.

Table 2 • IGLOO FPGAs Package Sizes Dimensions

Packages UC36 UC81 CS81 QN48 QN68 VQ100

Length × Width (mm\mm) 3 x 3 4 x 4 5 x 5 6 x 6 8 x 8 14 x 14

Nominal Area (mm2)916363664196

Pitch (mm) 0.4 0.4 0.5 0.4 0.4 0.5

Height (mm) 0.80 0.80 0.80 0.90 0.90 1.20

IGLOO nano Low-Power Flash FPGAs

Advance v0.8 III

IGLOO nano Ordering Information

Device Marking

Actel normally topside marks the full ordering part number on each device. There are some exceptions to this, such as some

of the Z feature grade nano devices, the V2 designator for IGLOO devices, and packages where space is physically limited.

Packages that have limited characters available are UC36, UC81, CS81, QN48, QN68, and QFN132. On these specific packages,

a subset of the device marking will be used that includes the required legal information and as much of the part number as

allowed by character limitation of the device. In this case, devices will have a truncated device marking and may exclude the

applications markings, such as the I designator for Industrial Devices or the ES designator for Engineering Samples.

Notes:

1. For the AGLN060, AGLN125, and AGLN250, the Z feature grade does not support the enhanced nano features of Schmitt trigger

input, bus hold, cold-sparing, and hot-swap I/O capability. The AGLN030 Z feature grade does not support Schmitt trigger input

and bus hold. For the VQ100, CS81, UC81, QN68, and QN48 packages, the Z feature grade and the N part number are not marked

on the device.

2. Marking Information: IGLOO nano V2 devices do not have V2 marking, but IGLOO nano V5 devices are marked with a V5

designator.

AGLN010 = 10,000 System Gates

AGLN015 = 15,000 System Gates

AGLN020 = 20,000 System Gates

AGLN030 = 30,000 System Gates

AGLN060 = 60,000 System Gates

AGLN125 = 125,000 System Gates

AGLN250 = 250,000 System Gates

Blank = Standard

Z = nano devices without enhanced features1

Supply Voltage

2 = 1.2 V to 1.5 V

5 = 1.5 V only

AGLN250 V2 Z VQ

Part Number

IGLOO nano Devices

Package Type

VQ =Very Thin Quad Flat Pack (0.5 mm pitch)

DIELOT =Known Good Die

QN =Quad Flat Pack No Leads (0.4 mm and 0.5 mm pitches)

100 I

Package Lead Count

Lead-Free Packaging

Application (Temperature Range)

Blank = Commercial (–20°C to +70°C Ambient Temperature)

I= Industrial (–40°C to +85°C Ambient Temperature)

Blank = Standard Packaging

G= RoHS-Compliant Packaging

PP = Pre-Production

ES=Engineering Sample (Room Temperature Only)

CS =Chip Scale Package (0.5 mm pitch)

UC=Micro Chip Scale Package (0.4 mm pitch)

IGLOO nano Low-Power Flash FPGAs

IV Advance v0.8

Figure 1 shows an example of device marking based on the AGL030V5-UCG81. The actual mark will vary by the

device/package combination ordered.

IGLOO nano Product Available in the Z Feature Grade

Temperature Grade Offerings

Contact your local Actel representative for device availability: http://www.actel.com/contact/default.aspx.

Figure 1 • Example of Device Marking for Small Form Factor Packages

Devices AGLN030 AGLN060 AGLN125 AGLN250

Packages QN48 – – –

QN68 – – –

UC81 – – –

CS81 CS81 CS81 CS81

VQ100 VQ100 VQ100 VQ100

Package AGLN010 AGLN015 AGLN020 AGLN030 AGLN060 AGLN125 AGLN250

UC36 C, I––––––

QN48 C, I – – C, I – – –

QN68 – C, I C, I C, I – – –

UC81 ––C, IC, I–––

CS81 – – C, IC, IC, IC, IC, I

VQ100 – – – C, IC, IC, IC, I

Notes:

1. C = Commercial temperature range: –20°C to 70°C ambient temperature.

2. I = Industrial temperature range: –40°C to 85°C ambient temperature.

ACTELXXX

AGL030YWW

UCG81XXXX

XXXXXXXX

Country of Origin

Date Code

Customer Mark

(if applicable)

Device Name

(six characters)

Package

Wafer Lot #

Advance v0.8 1-1

1 – IGLOO nano Device Overview

General Description

The IGLOO family of flash FPGAs, based on a 130-nm flash process, offers the lowest power FPGA, a

single-chip solution, small footprint packages, reprogrammability, and an abundance of advanced

features.

The Flash*Freeze technology used in IGLOO nano devices enables entering and exiting an ultra-

low-power mode that consumes nanoPower while retaining SRAM and register data. Flash*Freeze

technology simplifies power management through I/O and clock management with rapid recovery

to operation mode.

The Low Power Active capability (static idle) allows for ultra-low-power consumption while the

IGLOO nano device is completely functional in the system. This allows the IGLOO nano device to

control system power management based on external inputs (e.g., scanning for keyboard stimulus)

while consuming minimal power.

Nonvolatile flash technology gives IGLOO nano devices the advantage of being a secure, low-

power, single-chip solution that is live at power-up (LAPU). The IGLOO nano device is

reprogrammable and offers time-to-market benefits at an ASIC-level unit cost.

These features enable designers to create high-density systems using existing ASIC or FPGA design

flows and tools.

IGLOO nano devices offer 1 kbit of on-chip, reprogrammable, nonvolatile FlashROM storage as well

as clock conditioning circuitry based on an integrated phase-locked loop (PLL). The AGLN030 and

smaller devices have no PLL or RAM support. IGLOO nano devices have up to 250 k system gates,

supported with up to 36 kbits of true dual-port SRAM and up to 71 user I/Os.

IGLOO nano devices increase the breadth of the IGLOO product line by adding new features and

packages for greater customer value in high volume consumer, portable, and battery-backed

markets. Features such as smaller footprint packages designed with two-layer PCBs in mind, power

consumption measured in nanoPower, Schmitt trigger, and bus hold functionality make these

devices ideal for deployment in applications that require high levels of flexibility and low cost.

Flash*Freeze Technology

The IGLOO nano device offers unique Flash*Freeze technology, allowing the device to enter and

exit ultra-low-power Flash*Freeze mode. IGLOO nano devices do not need additional components

to turn off I/Os or clocks while retaining the design information, SRAM content, and registers.

Flash*Freeze technology is combined with in-system programmability, which enables users to

quickly and easily upgrade and update their designs in the final stages of manufacturing or in the

field. The ability of IGLOO nano V2 devices to support a wide range of core voltage (1.2 V to 1.5 V)

allows further reduction in power consumption, thus achieving the lowest total system power.

During Flash*Freeze mode, each I/O can be set to the following configurations: hold previous state,

tristate, HIGH, or LOW.

The availability of low-power modes, combined with reprogrammability, a single-chip and single-

voltage solution, and small-footprint packages make IGLOO nano devices the best fit for portable

electronics.

IGLOO nano Device Overview

1-2 Advance v0.8

Flash Advantages

Low Power

Flash-based IGLOO nano devices exhibit power characteristics similar to those of an ASIC, making

them an ideal choice for power-sensitive applications. IGLOO nano devices have only a very limited

power-on current surge and no high-current transition period, both of which occur on many

FPGAs.

IGLOO nano devices also have low dynamic power consumption to further maximize power

savings; power is reduced even further by the use of a 1.2 V core voltage.

Low dynamic power consumption, combined with low static power consumption and Flash*Freeze

technology, gives the IGLOO nano device the lowest total system power offered by any FPGA.

Security

Nonvolatile, flash-based IGLOO nano devices do not require a boot PROM, so there is no vulnerable

external bitstream that can be easily copied. IGLOO nano devices incorporate FlashLock, which

provides a unique combination of reprogrammability and design security without external

overhead, advantages that only an FPGA with nonvolatile flash programming can offer.

IGLOO nano devices utilize a 128-bit flash-based lock and a separate AES key to secure

programmed intellectual property and configuration data. In addition, all FlashROM data in IGLOO

nano devices can be encrypted prior to loading, using the industry-leading AES-128 (FIPS192) bit

block cipher encryption standard. AES was adopted by the National Institute of Standards and

Technology (NIST) in 2000 and replaces the 1977 DES standard. IGLOO nano devices have a built-in

AES decryption engine and a flash-based AES key that make them the most comprehensive

programmable logic device security solution available today. IGLOO nano devices with AES-based

security allow for secure, remote field updates over public networks such as the Internet, and

ensure that valuable IP remains out of the hands of system overbuilders, system cloners, and IP

thieves. The contents of a programmed IGLOO nano device cannot be read back, although secure

design verification is possible.

Security, built into the FPGA fabric, is an inherent component of IGLOO nano devices. The flash cells

are located beneath seven metal layers, and many device design and layout techniques have been

used to make invasive attacks extremely difficult. IGLOO nano devices, with FlashLock and AES

security, are unique in being highly resistant to both invasive and noninvasive attacks. Your

valuable IP is protected and secure, making remote ISP possible. An IGLOO nano device provides

the most impenetrable security for programmable logic designs.

Single Chip

Flash-based FPGAs store their configuration information in on-chip flash cells. Once programmed,

the configuration data is an inherent part of the FPGA structure, and no external configuration

data needs to be loaded at system power-up (unlike SRAM-based FPGAs). Therefore, flash-based

IGLOO nano FPGAs do not require system configuration components such as EEPROMs or

microcontrollers to load device configuration data. This reduces bill-of-materials costs and PCB

area, and increases security and system reliability.

Live at Power-Up

Actel flash-based IGLOO nano devices support Level 0 of the LAPU classification standard. This

feature helps in system component initialization, execution of critical tasks before the processor

wakes up, setup and configuration of memory blocks, clock generation, and bus activity

management. The LAPU feature of flash-based IGLOO nano devices greatly simplifies total system

design and reduces total system cost, often eliminating the need for CPLDs and clock generation

PLLs. In addition, glitches and brownouts in system power will not corrupt the IGLOO nano device's

flash configuration, and unlike SRAM-based FPGAs, the device will not have to be reloaded when

system power is restored. This enables the reduction or complete removal of the configuration

PROM, expensive voltage monitor, brownout detection, and clock generator devices from the PCB

design. Flash-based IGLOO nano devices simplify total system design and reduce cost and design

risk while increasing system reliability and improving system initialization time.

IGLOO nano flash FPGAs enable the user to quickly enter and exit Flash*Freeze mode. This is done

almost instantly (within 1 µs) and the device retains configuration and data in registers and RAM.

IGLOO nano Device Overview

Advance v0.8 1-3

Unlike SRAM-based FPGAs, the device does not need to reload configuration and design state from

external memory components; instead it retains all necessary information to resume operation

immediately.

Reduced Cost of Ownership

Advantages to the designer extend beyond low unit cost, performance, and ease of use. Unlike

SRAM-based FPGAs, flash-based IGLOO nano devices allow all functionality to be live at power-up;

no external boot PROM is required. On-board security mechanisms prevent access to all the

programming information and enable secure remote updates of the FPGA logic. Designers can

perform secure remote in-system reprogramming to support future design iterations and field

upgrades with confidence that valuable intellectual property cannot be compromised or copied.

Secure ISP can be performed using the industry-standard AES algorithm. The IGLOO nano device

architecture mitigates the need for ASIC migration at higher user volumes. This makes IGLOO nano

devices cost-effective ASIC replacement solutions, especially for applications in the consumer,

networking/communications, computing, and avionics markets.

With a variety of devices under $1, Actel IGLOO nano FPGAs enable cost-effective implementation

of programmable logic and quick time to market.

Firm-Error Immunity

Firm errors occur most commonly when high-energy neutrons, generated in the upper atmosphere,

strike a configuration cell of an SRAM FPGA. The energy of the collision can change the state of the

configuration cell and thus change the logic, routing, or I/O behavior in an unpredictable way.

These errors are impossible to prevent in SRAM FPGAs. The consequence of this type of error can be

a complete system failure. Firm errors do not exist in the configuration memory of IGLOO nano

flash-based FPGAs. Once it is programmed, the flash cell configuration element of IGLOO nano

FPGAs cannot be altered by high-energy neutrons and is therefore immune to them. Recoverable

(or soft) errors occur in the user data SRAM of all FPGA devices. These can easily be mitigated by

using error detection and correction (EDAC) circuitry built into the FPGA fabric.

Advanced Flash Technology

The IGLOO nano device offers many benefits, including nonvolatility and reprogrammability,

through an advanced flash-based, 130-nm LVCMOS process with seven layers of metal. Standard

CMOS design techniques are used to implement logic and control functions. The combination of

fine granularity, enhanced flexible routing resources, and abundant flash switches allows for very

high logic utilization without compromising device routability or performance. Logic functions

within the device are interconnected through a four-level routing hierarchy.

IGLOO nano FPGAs utilize design and process techniques to minimize power consumption in all

modes of operation.

Advanced Architecture

The proprietary IGLOO nano architecture provides granularity comparable to standard-cell ASICs.

The IGLOO nano device consists of five distinct and programmable architectural features

(Figure 1-3 on page 1-5 to Figure 1-4 on page 1-5):

• Flash*Freeze technology

• FPGA VersaTiles

• Dedicated FlashROM

• Dedicated SRAM/FIFO memory†

• Extensive CCCs and PLLs†

• Advanced I/O structure

The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input

logic function, a D-flip-flop (with or without enable), or a latch by programming the appropriate

flash switch interconnections. The versatility of the IGLOO nano core tile as either a three-input

lookup table (LUT) equivalent or a D-flip-flop/latch with enable allows for efficient use of the FPGA

fabric. The VersaTile capability is unique to the Actel ProASIC® family of third-generation-

† The AGLN030 and smaller devices do not support PLL or SRAM.

IGLOO nano Device Overview

1-4 Advance v0.8

architecture flash FPGAs. VersaTiles are connected with any of the four levels of routing hierarchy.

Flash switches are distributed throughout the device to provide nonvolatile, reconfigurable

interconnect programming. Maximum core utilization is possible for virtually any design.

In addition, extensive on-chip programming circuitry enables rapid, single-voltage (3.3 V)

programming of IGLOO nano devices via an IEEE 1532 JTAG interface.

Note: *Bank 0 for the AGLN030 device

Figure 1-1 • IGLOO Device Architecture Overview with Two I/O Banks and No RAM (AGLN010 and AGLN030)

Figure 1-2 • IGLOO Device Architecture Overview with Three I/O Banks and No RAM (AGLN015 and AGLN020)

VersaTile

I/Os

User Nonvolatile

FlashROM

Flash*Freeze

Technology

Charge

Pumps

Bank 1*

Bank 1

Bank 0

Bank 1

CCC-GL

VersaTile

I/Os

User Nonvolatile

FlashRom

Flash*Freeze

Technology

Charge

Pumps

Bank 1

Bank 2

Bank 0

Bank 1

IGLOO nano Device Overview

Advance v0.8 1-5

Figure 1-3 • IGLOO Device Architecture Overview with Two I/O Banks (AGLN060, AGLN125)

Figure 1-4 • IGLOO Device Architecture Overview with Four I/O Banks (AGLN250)

RAM Block

4,608-Bit Dual-Port

SRAM or FIFO Block

VersaTile

CCC

I/Os

ISP AES

Decryption

User Nonvolatile

FlashRom

Flash*Freeze

Technology

Charge

Pumps

Bank 0

Bank 1Bank 1

Bank 0Bank 0

Bank 1

RAM Block

4,608-Bit Dual-Port

SRAM or FIFO Block

VersaTile

CCC

I/Os

Bank 0

Bank 3Bank 3

Bank 1Bank 1

Bank 2

ISP AES

Decryption

User Nonvolatile

FlashRom

Flash*Freeze

Technology

Charge

Pumps

IGLOO nano Device Overview

1-6 Advance v0.8

Flash*Freeze Technology

The IGLOO nano device has an ultra-low-power static mode, called Flash*Freeze mode, which

retains all SRAM and register information and can still quickly return to normal operation.

Flash*Freeze technology enables the user to quickly (within 1 µs) enter and exit Flash*Freeze mode

by activating the Flash*Freeze pin while all power supplies are kept at their original values. I/Os,

global I/Os, and clocks can still be driven and can be toggling without impact on power

consumption, and the device retains all core registers, SRAM information, and I/O states. I/Os can

be individually configured to either hold their previous state or be tristated during Flash*Freeze

mode.

Alternatively, I/Os can be set to a specific state using weak pull-up or pull-down I/O attribute

configuration. No power is consumed by the I/O banks, clocks, JTAG pins, or PLL, and the device

consumes as little as 2 µW in this mode.

Flash*Freeze technology allows the user to switch to Active mode on demand, thus simplifying the

power management of the device.

The Flash*Freeze pin (active low) can be routed internally to the core to allow the user's logic to

decide when it is safe to transition to this mode. Refer to Figure 1-5 for an illustration of

entering/exiting Flash*Freeze mode. It is also possible to use the Flash*Freeze pin as a regular I/O if

Flash*Freeze mode usage is not planned.

VersaTiles

The IGLOO nano core consists of VersaTiles, which have been enhanced beyond the ProASICPLUS®

core tiles. The IGLOO nano VersaTile supports the following:

• All 3-input logic functions—LUT-3 equivalent

• Latch with clear or set

• D-flip-flop with clear or set

• Enable D-flip-flop with clear or set

Refer to Figure 1-6 for VersaTile configurations.

Figure 1-5 • IGLOO nano Flash*Freeze Mode

Actel IGLOO Nano

FPGA

Flash*Freeze

Mode Control

Flash*Freeze Pin

Figure 1-6 • VersaTile Configurations

LUT-3

Data Y

CLK

Enable

CLR

D-FF

Data Y

CLK

CLR D-FF

LUT-3 Equivalent D-Flip-Flop with Clear or Set Enable D-Flip-Flop with Clear or Set

IGLOO nano Device Overview

Advance v0.8 1-7

User Nonvolatile FlashROM

Actel IGLOO nano devices have 1 kbit of on-chip, user-accessible, nonvolatile FlashROM. The

FlashROM can be used in diverse system applications:

• Internet protocol addressing (wireless or fixed)

• System calibration settings

• Device serialization and/or inventory control

• Subscription-based business models (for example, set-top boxes)

• Secure key storage for secure communications algorithms

• Asset management/tracking

• Date stamping

• Version management

The FlashROM is written using the standard IGLOO nano IEEE 1532 JTAG programming interface.

The core can be individually programmed (erased and written), and on-chip AES decryption can be

used selectively to securely load data over public networks (except in the AGLN030 and smaller

devices), as in security keys stored in the FlashROM for a user design.

The FlashROM can be programmed via the JTAG programming interface, and its contents can be

read back either through the JTAG programming interface or via direct FPGA core addressing. Note

that the FlashROM can only be programmed from the JTAG interface and cannot be programmed

from the internal logic array.

The FlashROM is programmed as 8 banks of 128 bits; however, reading is performed on a byte-by-

byte basis using a synchronous interface. A 7-bit address from the FPGA core defines which of the 8

banks and which of the 16 bytes within that bank are being read. The three most significant bits

(MSBs) of the FlashROM address determine the bank, and the four least significant bits (LSBs) of

the FlashROM address define the byte.

The Actel IGLOO nano development software solutions, Libero® Integrated Design Environment

(IDE) and Designer, have extensive support for the FlashROM. One such feature is auto-generation

of sequential programming files for applications requiring a unique serial number in each part.

Another feature enables the inclusion of static data for system version control. Data for the

FlashROM can be generated quickly and easily using Actel Libero IDE and Designer software tools.

Comprehensive programming file support is also included to allow for easy programming of large

numbers of parts with differing FlashROM contents.

SRAM and FIFO

IGLOO nano devices (except the AGLN030 and smaller devices) have embedded SRAM blocks along

their north and south sides. Each variable-aspect-ratio SRAM block is 4,608 bits in size. Available

memory configurations are 256×18, 512×9, 1k×4, 2k×2, and 4k×1 bits. The individual blocks have

independent read and write ports that can be configured with different bit widths on each port.

For example, data can be sent through a 4-bit port and read as a single bitstream. The embedded

SRAM blocks can be initialized via the device JTAG port (ROM emulation mode) using the UJTAG

macro (except in the AGLN030 and smaller devices).

In addition, every SRAM block has an embedded FIFO control unit. The control unit allows the

SRAM block to be configured as a synchronous FIFO without using additional core VersaTiles. The

FIFO width and depth are programmable. The FIFO also features programmable Almost Empty

(AEMPTY) and Almost Full (AFULL) flags in addition to the normal Empty and Full flags. The

embedded FIFO control unit contains the counters necessary for generation of the read and write

address pointers. The embedded SRAM/FIFO blocks can be cascaded to create larger configurations.

IGLOO nano Device Overview

1-8 Advance v0.8

PLL and CCC

Higher density IGLOO nano devices using either the two I/O bank or four I/O bank architectures

provide designers with very flexible clock conditioning capabilities. AGLN060, AGLN125, and

AGLN250 contain six CCCs. One CCC (center west side) has a PLL. The AGLN030 and smaller devices

use different CCCs in their architecture (CCC-GL). These CCC-GLs contain a global MUX but do not

have any PLLs or programmable delays.

For devices using the six CCC block architecture, these are located at the four corners and the

centers of the east and west sides. All six CCC blocks are usable; the four corner CCCs and the east

CCC allow simple clock delay operations as well as clock spine access.

The inputs of the six CCC blocks are accessible from the FPGA core or from dedicated connections

to the CCC block, which are located near the CCC.

The CCC block has these key features:

• Wide input frequency range (fIN_CCC) = 1.5 MHz up to 250 MHz

• Output frequency range (fOUT_CCC) = 0.75 MHz up to 250 MHz

• 2 programmable delay types for clock skew minimization

• Clock frequency synthesis (for PLL only)

Additional CCC specifications:

• Internal phase shift = 0°, 90°, 180°, and 270°. Output phase shift depends on the output

divider configuration (for PLL only).

• Output duty cycle = 50% ± 1.5% or better (for PLL only)

• Low output jitter: worst case < 2.5% × clock period peak-to-peak period jitter when single

global network used (for PLL only)

• Maximum acquisition time is 300 µs (for PLL only)

• Exceptional tolerance to input period jitter—allowable input jitter is up to 1.5 ns (for PLL

only)

• Four precise phases; maximum misalignment between adjacent phases of 40 ps × 250 MHz /

fOUT_CCC (for PLL only)

Global Clocking

IGLOO nano devices have extensive support for multiple clocking domains. In addition to the CCC

and PLL support described above, there is a comprehensive global clock distribution network.

Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three

quadrant global networks. The VersaNets can be driven by the CCC or directly accessed from the

core via multiplexers (MUXes). The VersaNets can be used to distribute low-skew clock signals or for

rapid distribution of high-fanout nets.

I/Os with Advanced I/O Standards

IGLOO nano FPGAs feature a flexible I/O structure, supporting a range of voltages (1.2 V, 1.5 V,

1.8 V, 2.5 V, 3.0 V wide range, and 3.3 V).

The I/Os are organized into banks with two, three, or four banks per device. The configuration of

these banks determines the I/O standards supported.

Each I/O module contains several input, output, and enable registers. These registers allow the

implementation of various single-data-rate applications for all versions of nano devices and

double-data-rate applications for the AGLN060, AGLN125, and AGLN250 devices.

IGLOO nano devices support LVTLL and LVCMOS I/O standards, are hot-swappable, and support

cold-sparing and Schmitt trigger.

Hot-swap (also called hot-plug, or hot-insertion) is the operation of hot-insertion or hot-removal of

a card in a powered-up system.

Cold-sparing (also called cold-swap) refers to the ability of a device to leave system data

undisturbed when the system is powered up, while the component itself is powered down, or

when power supplies are floating.

IGLOO nano Device Overview

Advance v0.8 1-9

Wide Range I/O Support

Actel nano devices support JEDEC-defined wide range I/O operation. IGLOO nano devices support

both the JESD8-B specification, covering both 3 V and 3.3 V supplies, for an effective operating

range of 2.7 V to 3.6 V, and JESD8-12 with its 1.2 V nominal, supporting an effective operating

range of 1.14 V to 1.575 V.

Wider I/O range means designers can eliminate power supplies or power conditioning components

from the board or move to less costly components with greater tolerances. Wide range eases I/O

bank management and provides enhanced protection from system voltage spikes, while providing

the flexibility to easily run custom voltage applications.

Part Number and Revision Date

Part Number 51700110-001-7

Revised January 2010

List of Changes

The following table lists critical changes that were made in the current version of the document.

Previous Version Changes in Current Version (Advance v0.8) Page

Advance v0.7

(April 2009)

The "Reprogrammable Flash Technology" section was revised to add "250 MHz

(1.5 V systems) and 160 MHz (1.2 V systems) System Performance."

The note for AGLN030 in the "IGLOO nano Devices" table was revised. It states

AGLN030 is available in the Z feature grade only.

The "I/Os with Advanced I/O Standards" section was revised to add definitions for

hot-swap and cold-sparing.

1-8

Advance v0.6

(February 2009)

The –F speed grade is no longer offered for IGLOO PLUS devices. The speed grade

column and note regarding –F speed grade were removed from "IGLOO nano

Ordering Information". The "Speed Grade and Temperature Grade Matrix"

section was removed.

III, IV

Advance v0.5

(February 2009)

The QN100 package was removed for all devices. N/A

Table 1 · IGLOO nano Devices was updated to change the maximum user I/Os for

AGLN030 from 81 to 77.

The "Device Marking" section is new. III

Advance v0.4

(December 2008)

The following table note was removed from Table 1 · IGLOO nano Devices: "Six

chip (main) and three quadrant global networks are available for AGLN060 and

above."

The CS81 package was added for AGLN250 in the "IGLOO nano Product Available

in the Z Feature Grade" table.

Advance v0.3

(November 2008)

The second table note in Table 1 · IGLOO nano Devices was revised to state,

"AGLN060, AGLN125, and AGLN250 in the CS81 package do not support PLLs.

AGLN030 and smaller devices do not support this feature."

The I/Os per package for CS81 were revised to 60 for AGLN060, AGLN125, and

AGLN250 in the "I/Os Per Package"table.

Advance v0.2

(October 2008)

The "Advanced I/Os" section was updated to include wide power supply voltage

support for 1.14 V to 1.575 V.

The AGLN030 device was added to product tables and replaces AGL030 entries

that were formerly in the tables.

I to IV

The "I/Os Per Package"table was updated for the CS81 package to change the

number of I/Os for AGLN060, AGLN125, and AGLN250 from 66 to 64.

The "Wide Range I/O Support" section is new. 1-9

IGLOO nano Device Overview

1-10 Advance v0.8

Advance v0.1

(October 2008)

The following tables and sections were updated to add the UC81 and CS81

packages for AGL030:

"IGLOO nano Devices"

"I/Os Per Package"

"IGLOO nano Product Available in the Z Feature Grade"

"Temperature Grade Offerings"

N/A

The "I/Os Per Package" table was updated to add the following information to

table note 4: "For nano devices, the VQ100 package is offered in both leaded and

RoHS-compliant versions. All other packages are RoHS-compliant only."

The "IGLOO nano Product Available in the Z Feature Grade" section was updated

to remove QN100 for AGLN250.

The device architecture figures, Figure 1-3 · IGLOO Device Architecture Overview

with Two I/O Banks (AGLN060, AGLN125) through Figure 1-4 · IGLOO Device

Architecture Overview with Four I/O Banks (AGLN250), were revised.

Figure 1-1 · IGLOO Device Architecture Overview with Two I/O Banks and No RAM

(AGLN010 and AGLN030) is new.

1-4

through

1-5

Advance v0.1

(continued)

The "PLL and CCC" section was revised to include information about CCC-GLs in

AGLN020 and smaller devices.

1-8

The "I/Os with Advanced I/O Standards" section was revised to add information

about IGLOO nano devices supporting double-data-rate applications.

1-8

Previous Version Changes in Current Version (Advance v0.8) Page

Advance v0.3 2-1

2 – IGLOO nano DC and Switching Characteristics

General Specifications

The Z feature grade does not support the enhanced nano features of Schmitt trigger input,

Flash*Freeze bus hold, cold-sparing, and hot-swap I/O capability. Refer to the ordering information

in the IGLOO nano Product Brief for more information.

Operating Conditions

Stresses beyond those listed in Table 2-1 may cause permanent damage to the device.

Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Absolute Maximum Ratings are stress ratings only; functional operation of the device at these or

any other conditions beyond those listed under the Recommended Operating Conditions specified

in Table 2-2 on page 2-2 is not implied.

Table 2-1 • Absolute Maximum Ratings

Symbol Parameter Limits Units

VCC DC core supply voltage –0.3 to 1.65 V

VJTAG JTAG DC voltage –0.3 to 3.75 V

VPUMP Programming voltage –0.3 to 3.75 V

VCCPLL Analog power supply (PLL) –0.3 to 1.65 V

VCCI DC I/O buffer supply voltage –0.3 to 3.75 V

VI I/O input voltage –0.3 V to 3.6 V V

TSTG 2Storage temperature –65 to +150 °C

TJ2Junction temperature +125 °C

Notes:

1. The device should be operated within the limits specified by the datasheet. During transitions, the input

signal may undershoot or overshoot according to the limits shown in Table 2-4 on page 2-3.

2. For flash programming and retention maximum limits, refer to Table 2-3 on page 2-2, and for

recommended operating limits, refer to Table 2-2 on page 2-2.

IGLOO nano DC and Switching Characteristics

2-2 Advance v0.3

Table 2-2 • Recommended Operating Conditions 1

Symbol Parameter Extended Commercial Industrial Units

TAAmbient temperature –20 to +70 2 –40 to +85 2 °C

TJJunction temperature –20 to + 85 2 –40 to +100 2 °C

VCC 1.5 V DC core supply voltage3 1.425 to 1.575 1.425 to 1.575 V

1.2 V–1.5 V wide range core voltage41.14 to 1.575 1.14 to 1.575 V

VJTAG JTAG DC voltage 1.425 to 3.6 1.425 to 3.6 V

VPUMP 5Programming voltage Programming mode 3.15 to 3.45 3.15 to 3.45 V

Operation 0 to 3.45 0 to 3.45 V

VCCPLL 6Analog power supply

(PLL)

1.5 V DC core supply voltage3 1.425 to 1.575 1.425 to 1.575 V

1.2 V–1.5 V wide range core

supply voltage41.14 to 1.575 1.14 to 1.575 V

VCCI

and

VMV 7,9

1.2 V DC supply voltage 4 1.14 to 1.26 1.14 to 1.26 V

1.2 V DC wide range supply voltage 41.14 to 1.575 1.14 to 1.575 V

1.5 V DC supply voltage 1.425 to 1.575 1.425 to 1.575

1.8 V DC supply voltage 1.7 to 1.9 1.7 to 1.9 V

2.5 V DC supply voltage 2.3 to 2.7 2.3 to 2.7 V

3.3 V DC supply voltage 3.0 to 3.6 3.0 to 3.6 V

3.3 V DC wide range supply voltage 82.7 to 3.6 2.7 to 3.6

Notes:

1. All parameters representing voltages are measured with respect to GND unless otherwise specified.

2. To ensure targeted reliability standards are met across ambient and junction operating temperatures, Actel

recommends that the user follow best design practices using Actel’s timing and power simulation tools.

3. For IGLOO® nano V5 devices

4. For IGLOO nano V2 devices only, operating at VCCI

≥

VCC

5. VPUMP can be left floating during operation (not programming mode).

6. VCCPLL pins should be tied to VCC pins. See Pin Descriptions for further information.

7. VMV pins must be connected to the corresponding VCCI pins. See Pin Descriptions for further information.

8. 3.3 V wide range is compliant to the JESD8-B specification and supports 3.0 V VCCI operation.

9. The ranges given here are for power supplies only. The recommended input voltage ranges specific to each

I/O standard are given in Table 2-20 on page 2-19. VCCI should be at the same voltage within a given I/O

bank.

Table 2-3 • Flash Programming Limits – Retention, Storage, and Operating Temperature1

Product Grade Programming Cycles

Program Retention

(biased/unbiased)

Maximum Storage

Temperature TSTG (°C) 2

Maximum Operating Junction

Temperature TJ (°C) 2

Commercial 500 20 years 110 100

Industrial 500 20 years 110 100

Notes:

1. This is a stress rating only; functional operation at any condition other than those indicated is not implied.

2. These limits apply for program/data retention only. Refer to Table 2-1 on page 2-1 and Table 2-2 for device

operating conditions and absolute limits.

IGLOO nano DC and Switching Characteristics

Advance v0.3 2-3

I/O Power-Up and Supply Voltage Thresholds for Power-On Reset

(Commercial and Industrial)

Sophisticated power-up management circuitry is designed into every IGLOO nano device. These

circuits ensure easy transition from the powered-off state to the powered-up state of the device.

The many different supplies can power up in any sequence with minimized current spikes or surges.

In addition, the I/O will be in a known state through the power-up sequence. The basic principle is

shown in Figure 2-1 on page 2-4.

There are five regions to consider during power-up.

IGLOO nano I/Os are activated only if ALL of the following three conditions are met:

1. VCC and VCCI are above the minimum specified trip points (Figure 2-1 and Figure 2-2 on

page 2-5).

2. VCCI > VCC – 0.75 V (typical)

3. Chip is in the operating mode.

VCCI Trip Point:

Ramping up (V5 devices): 0.6 V < trip_point_up < 1.2 V

Ramping down (V5 devices): 0.5 V < trip_point_down < 1.1 V

Ramping up (V2 devices): 0.75 V < trip_point_up < 1.05 V

Ramping down (V2 devices): 0.65 V < trip_point_down < 0.95 V

VCC Trip Point:

Ramping up (V5 devices): 0.6 V < trip_point_up < 1.1 V

Ramping down (V5 devices): 0.5 V < trip_point_down < 1.0 V

Ramping up (V2 devices): 0.65 V < trip_point_up < 1.05 V

Ramping down (V2 devices): 0.55 V < trip_point_down < 0.95 V

VCC and VCCI ramp-up trip points are about 100 mV higher than ramp-down trip points. This

specifically built-in hysteresis prevents undesirable power-up oscillations and current surges. Note

the following:

• During programming, I/Os become tristated and weakly pulled up to VCCI.

• JTAG supply, PLL power supplies, and charge pump VPUMP supply have no influence on I/O

behavior.

Table 2-4 • Overshoot and Undershoot Limits 1

VCCI

Average VCCI–GND Overshoot or

Undershoot Duration

as a Percentage of Clock Cycle2Maximum Overshoot/

Undershoot2

2.7 V or less 10% 1.4 V

5% 1.49 V

3 V 10% 1.1 V

5% 1.19 V

3.3 V 10% 0.79 V

5% 0.88 V

3.6 V 10% 0.45 V

5% 0.54 V

Notes:

1. Based on reliability requirements at 85°C.

2. The duration is allowed at one out of six clock cycles. If the overshoot/undershoot occurs at one out of two

cycles, the maximum overshoot/undershoot has to be reduced by 0.15 V.

IGLOO nano DC and Switching Characteristics

2-4 Advance v0.3

PLL Behavior at Brownout Condition

Actel recommends using monotonic power supplies or voltage regulators to ensure proper power-

up behavior. Power ramp-up should be monotonic at least until VCC and VCCPLX exceed brownout

activation levels (see Figure 2-1 and Figure 2-2 on page 2-5 for more details).

When PLL power supply voltage and/or VCC levels drop below the VCC brownout levels (0.75 V ±

0.25 V for V5 devices, and 0.75 V ± 0.2 V for V2 devices), the PLL output lock signal goes LOW

and/or the output clock is lost. Refer to the "Brownout Voltage" section in the Power-Up/-Down

Behavior of Low-Power Flash Devices chapter of the ProASIC3 and ProASIC3E handbooks for

information on clock and lock recovery.

Internal Power-Up Activation Sequence

1. Core

2. Input buffers

3. Output buffers, after 200 ns delay from input buffer activation

To make sure the transition from input buffers to output buffers is clean, ensure that there is no

path longer than 100 ns from input buffer to output buffer in your design.

Figure 2-1 • V5 Devices – I/O State as a Function of VCCI and VCC Voltage Levels

Region 1: I/O buffers are OFF

Region 2: I/O buffers are ON.

I/Os are functional (except differential inputs)

but slower because VCCI/VCC are below

specification. For the same reason, input

buffers do not meet VIH/VIL levels, and

output buffers do not meet VOH/VOL levels.

Min VCCI datasheet specification

voltage at a selected I/O

standard; i.e., 1.425 V or 1.7 V

or 2.3 V or 3.0 V

VCC

VCC = 1.425 V

Region 1: I/O Buffers are OFF

Activation trip point:

Va = 0.85 V ± 0.25 V

Deactivation trip point:

Vd = 0.75 V ± 0.25 V

Activation trip point:

Va = 0.9 V ± 0.3 V

Deactivation trip point:

Vd = 0.8 V ± 0.3 V

VCC = 1.575 V

Region 5: I/O buffers are ON

and power supplies are within

specification.

I/Os meet the entire datasheet

and timer specifications for

speed, VIH/VIL , VOH/VOL , etc.

Region 4: I/O

buffers are ON.

I/Os are functional

(except differential

but slower because VCCI is

below specification. For the

same reason, input buffers do not

meet VIH/VIL levels, and output

buffers do not meet VOH/VOL levels.

Region 4: I/O

buffers are ON.

I/Os are functional

(except differential inputs)

where VT can be from 0.58 V to 0.9 V (typically 0.75 V)

VCCI

Region 3: I/O buffers are ON.

I/Os are functional; I/O DC

specifications are met,

but I/Os are slower because

the VCC is below specification.

VCC = VCCI + VT

IGLOO nano DC and Switching Characteristics

Advance v0.3 2-5

Figure 2-2 • V2 Devices – I/O State as a Function of VCCI and VCC Voltage Levels

Region 1: I/O buffers are OFF

Region 2: I/O buffers are ON.

I/Os are functional (except differential inputs)

but slower because V

CCI

are below

specification. For the same reason, input

buffers do not meet V

levels, and

output buffers do not meet V

levels.

Min VCCI datasheet specification

voltage at a selected I/O

standard; i.e., 1.14 V,1.425 V, 1.7 V,

2.3 V, or 3.0 V

VCC

VCC = 1.14 V

Region 1: I/O Buffers are OFF

Activation trip point:

Va = 0.85 V ± 0.2 V

Deactivation trip point:

Vd = 0.75 V ± 0.2 V

Activation trip point:

Va = 0.9 V ± 0.15 V

Deactivation trip point:

Vd = 0.8 V ± 0.15 V

VCC = 1.575 V

Region 5: I/O buffers are ON

and power supplies are within

specification.

I/Os meet the entire datasheet

and timer specifications for

speed, V

, V

, etc.

Region 4: I/O

buffers are ON.

I/Os are functional

(except differential

but slower because V

CCI

below specification. For the

same reason, input buffers do not

meet V

levels, and output

buffers do not meet V

levels.

Region 4: I/O

buffers are ON.

I/Os are functional

(except differential inputs)

where VT can be from 0.58 V to 0.9 V (typically 0.75 V)

VCCI

Region 3: I/O buffers are ON.

I/Os are functional; I/O DC

specifications are met,

but I/Os are slower because

the V

is below specification.

VCC = VCCI + VT

IGLOO nano DC and Switching Characteristics

2-6 Advance v0.3

Thermal Characteristics

Introduction

The temperature variable in the Actel Designer software refers to the junction temperature, not

the ambient temperature. This is an important distinction because dynamic and static power

consumption cause the chip junction temperature to be higher than the ambient temperature.

EQ 2-1 can be used to calculate junction temperature.

TJ = Junction Temperature = ΔT + TA

EQ 2-1

where:

TA = Ambient temperature

ΔT = Temperature gradient between junction (silicon) and ambient ΔT = θja * P

θja = Junction-to-ambient of the package. θja numbers are located in Figure 2-5.

P = Power dissipation

Package Thermal Characteristics

The device junction-to-case thermal resistivity is θjc and the junction-to-ambient air thermal

resistivity is θja. The thermal characteristics for θja are shown for two air flow rates. The maximum

operating junction temperature is 100°C. EQ 2-2 shows a sample calculation of the maximum

operating power dissipation allowed for a 484-pin FBGA package at commercial temperature and

in still air.

EQ 2-2

Temperature and Voltage Derating Factors

Maximum Power Allowed Max. junction temp. (°C) Max. ambient temp. (°C)–

θja(°C/W)

--------------------------------------------------------------------------------------------------------------------------------------- 100°C70°C–

20.5°C/W

------------------------------------ 1 . 4 6 W===

Table 2-5 • Package Thermal Resistivities

Package Type

Count θjc

θja

UnitsStill Air

200 ft./

min.

500 ft./

min.

Chip Scale Package (CSP) 36 TBD TBD TBD TBD C/W

81 TBD TBD TBD TBD C/W

Quad Flat No Lead (QFN) 48 TBD TBD TBD TBD C/W

68 TBD TBD TBD TBD C/W

100 TBD TBD TBD TBD C/W

Very Thin Quad Flat Pack (VQFP) 100 10.0 35.3 29.4 27.1 C/W

Table 2-6 • Temperature and Voltage Derating Factors for Timing Delays (normalized to TJ = 70°C,

VCC =1.425V)

For IGLOO nano V2 or V5 Devices, 1.5 V DC Core Supply Voltage

Array Voltage

VCC (V)

Junction Temperature (°C)

–40°C –20°C 0°C 25°C 70°C 85°C 125°C

1.425 0.966 0.972 0.977 0.991 1.000 1.006 1.013

1.5 0.877 0.882 0.888 0.899 0.907 0.913 0.919

1.575 0.815 0.820 0.824 0.835 0.843 0.848 0.854

IGLOO nano DC and Switching Characteristics

Advance v0.3 2-7

Calculating Power Dissipation

Quiescent Supply Current

Quiescent supply current (IDD) calculation depends on multiple factors, including operating

voltages (VCC, VCCI, and VJTAG), operating temperature, system clock frequency, and power mode

usage. Actel recommends using the Power Calculator and SmartPower software estimation tools to

evaluate the projected static and active power based on the user design, power mode usage,

operating voltage, and temperature.

Table 2-7 • Temperature and Voltage Derating Factors for Timing Delays (normalized to TJ = 70°C,

VCC =1.14V)

For IGLOO nano V2, 1.2 V DC Core Supply Voltage

Array Voltage

VCC (V)

Junction Temperature (°C)

–40°C –20°C 0°C 25°C 70°C 85°C 110°C

1.14 0.968 0.973 0.978 0.991 1.000 1.006 1.012

1.2 0.863 0.869 0.874 0.885 0.892 0.898 0.904

1.26 0.793 0.798 0.802 0.812 0.820 0.825 0.830

1.3 0.746 0.750 0.754 0.764 0.771 0.776 0.781

1.35 0.690 0.694 0.698 0.707 0.714 0.718 0.723

1.425 0.615 0.618 0.622 0.630 0.636 0.640 0.644

1.5 0.558 0.561 0.565 0.572 0.577 0.581 0.585

1.575 0.519 0.522 0.525 0.532 0.536 0.540 0.543

Table 2-8 • Quiescent Supply Current (IDD) Characteristics, IGLOO nano Flash*Freeze Mode*

Core

Voltage AGLN010 AGLN015 AGLN020 AGLN060 AGLN125 AGLN250 Units

Typical (25°C) 1.2 V 1.7 3.3 3.3 8 13 20 µA

1.5 V 3 6 6 10 18 34 µA

*IDD includes VCC, VPUMP, VCCI, VJTAG, and VCCPLL currents.

Table 2-9 • Quiescent Supply Current (IDD) Characteristics, IGLOO nano Sleep Mode (VCC = 0 V)*

Core

Voltage AGLN010 AGLN015 AGLN020 AGLN060 AGLN125 AGLN250 Units

VCCI/VJTAG = 1.2 V (per bank)

Typical (25°C)

1.2 V 1.7 1.7 1.7 1.7 1.7 1.7 µA

VCCI/VJTAG = 1.5 V (per bank)

Typical (25°C)

1.2 V /

1.5 V

1.8 1.8 1.8 1.8 1.8 1.8 µA

VCCI/VJTAG = 1.8 V (per bank)

Typical (25°C)

1.2 V /

1.5 V

1.9 1.9 1.9 1.9 1.9 1.9 µA

VCCI/VJTAG = 2.5 V (per bank)

Typical (25°C)

1.2 V /

1.5 V

2.2 2.2 2.2 2.2 2.2 2.2 µA

VCCI/VJTAG = 3.3 V (per bank)

Typical (25°C)

1.2 V /

1.5 V

2.5 2.5 2.5 2.5 2.5 2.5 µA

*IDD includes VCC, VPUMP, and VCCPLL currents.

IGLOO nano DC and Switching Characteristics

2-8 Advance v0.3

Table 2-10 • Quiescent Supply Current (IDD) Characteristics, IGLOO nano Shutdown Mode (VCC, VCCI = 0 V)*

Core Voltage AGLN010 AGLN015 AGLN020 AGLN060 AGLN125 AGLN250 Units

Typical

(25°C)

1.2 V / 1.5 V 0 0 0 0 0 0 µA

*IDD includes VCC, VPUMP, VCCI, and VCCPLL currents.

Table 2-11 • Quiescent Supply Current (IDD), No IGLOO nano Flash*Freeze Mode1

Core

Voltage AGLN010 AGLN015 AGLN020 AGLN060 AGLN125 AGLN250 Units

ICCA Current2

Typical (25°C) 1.2 V 3.7 5 5 10 13 18 µA

1.5 V 8 14 14 20 28 44 µA

ICCI or IJTAG Current3

VCCI / VJTAG = 1.2 V (per bank)

Typical (25°C)

1.2 V 1.7 1.7 1.7 1.7 1.7 1.7 µA

VCCI / VJTAG = 1.5 V (per bank)

Typical (25°C)

1.2 V / 1.5 V 1.8 1.8 1.8 1.8 1.8 1.8 µA

VCCI / VJTAG = 1.8 V (per bank)

Typical (25°C)

1.2 V / 1.5 V 1.9 1.9 1.9 1.9 1.9 1.9 µA

VCCI / VJTAG = 2.5 V (per bank)

Typical (25°C)

1.2 V / 1.5 V 2.2 2.2 2.2 2.2 2.2 2.2 µA

VCCI / VJTAG = 3.3 V (per bank)

Typical (25°C)

1.2 V / 1.5 V 2.5 2.5 2.5 2.5 2.5 2.5 µA

Notes:

1. To calculate total device IDD, multiply the number of banks used by ICCI and add ICCA contribution.

2. Includes VCC, VCCPLL, and VPUMP currents.

3. Per VCCI or VJTAG bank

IGLOO nano DC and Switching Characteristics

Advance v0.3 2-9

Power per I/O Pin

Table 2-12 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings

Applicable to IGLOO nano I/O Banks

VCCI (V)

Dynamic Power

PAC9 (µW/MHz) 1

Single-Ended

3.3 V LVTTL / 3.3 V LVCMOS 3.3 16.26

3.3 V LVTTL / 3.3 V LVCMOS – Schmitt Trigger 3.3 18.95

2.5 V LVCMOS 2.5 4.59

2.5 V LVCMOS – Schmitt Trigger 2.5 6.01

1.8 V LVCMOS 1.8 1.61

1.8 V LVCMOS – Schmitt Trigger 1.8 1.70

1.5 V LVCMOS (JESD8-11) 1.5 0.96

1.5 V LVCMOS (JESD8-11) – Schmitt Trigger 1.5 0.90

1.2 V LVCMOS 21.2 0.55

1.2 V LVCMOS 2 – Schmitt Trigger 1.2 0.47

Notes:

1. PAC9 is the total dynamic power measured on VCCI.

2. Applicable to IGLOO nano V2 devices operating at VCCI ≥ VCC.

Table 2-13 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings1

Applicable to IGLOO nano I/O Banks

CLOAD (pF) VCCI (V)

Dynamic Power

PAC10 (µW/MHz)2

Single-Ended

3.3 V LVTTL / 3.3 V LVCMOS 5 3.3 107.98

2.5 V LVCMOS 5 2.5 61.24

1.8 V LVCMOS 5 1.8 31.28

1.5 V LVCMOS (JESD8-11) 5 1.5 21.50

1.2 V LVCMOS351.2 21.05

Notes:

1. Dynamic power consumption is given for standard load and software default drive strength and output

slew.

2. PAC10 is the total dynamic power measured on VCCI.

3. Applicable for IGLOO nano V2 devices operating at VCCI ≥ VCC.

IGLOO nano DC and Switching Characteristics

2-10 Advance v0.3

Power Consumption of Various Internal Resources

Table 2-14 • Different Components Contributing to Dynamic Power Consumption in IGLOO nano Devices

For IGLOO nano V2 or V5 Devices, 1.5 V Core Supply Voltage

Parameter Definition

Device Specific Dynamic Power (µW/MHz)

AGLN250 AGLN125 AGLN060 AGLN020 AGLN015 AGLN010

PAC1 Clock contribution of a Global Rib 11.03 11.03 9.3 9.3 9.3 9.3

PAC2 Clock contribution of a Global

Spine

1.58 0.81 0.81 0.41 0.41 0.41

PAC3 Clock contribution of a VersaTile

row

0.81

PAC4 Clock contribution of a VersaTile

used as a sequential module

0.11

PAC5 First contribution of a VersaTile

used as a sequential module

0.057

PAC6 Second contribution of a VersaTile

used as a sequential module

0.207

PAC7 Contribution of a VersaTile used as

a combinatorial module

0.17

PAC8 Average contribution of a routing

net

0.7

PAC9 Contribution of an I/O input pin

(standard-dependent)

See Table 2-12 on page 2-9.

PAC10 Contribution of an I/O output pin

(standard-dependent)

See Table 2-13.

PAC11 Average contribution of a RAM

block during a read operation

25.00 N/A

PAC12 Average contribution of a RAM

block during a write operation

30.00 N/A

PAC13 Dynamic contribution for PLL 2.70 N/A

Table 2-15 • Different Components Contributing to the Static Power Consumption in IGLOO nano Devices

For IGLOO nano V2 or V5 Devices, 1.5 V Core Supply Voltage

Parameter Definition

Device -Specific Static Power (mW)

AGLN250 AGLN125 AGLN060 AGLN020 AGLN015 AGLN010

PDC1 Array static power in Active mode See Table 2-11 on page 2-8

PDC2 Array static power in Static (Idle)

mode

See Table 2-11 on page 2-8

PDC3 Array static power in Flash*Freeze

mode

See Table 2-8 on page 2-7

PDC4 2Static PLL contribution 1.84 N/A

PDC5 Bank quiescent power

(VCCI-dependent)

See Table 2-11 on page 2-8

Notes:

1. For a different output load, drive strength, or slew rate, Actel recommends using the Actel power

spreadsheet calculator or the SmartPower tool in Actel Libero® Integrated Design Environment (IDE).

2. Minimum contribution of the PLL when running at lowest frequency.

IGLOO nano DC and Switching Characteristics

Advance v0.3 2-11

Table 2-16 • Different Components Contributing to Dynamic Power Consumption in IGLOO nano Devices

For IGLOO nano V2 Devices, 1.2 V Core Supply Voltage

Parameter Definition

Device-Specific Dynamic Power (µW/MHz)

AGLN250 AGLN125 AGLN060 AGLN020 AGLN015 AGLN010

PAC1 Clock contribution of a Global Rib 7.07 7.07 5.96 5.96 5.96 5.96

PAC2 Clock contribution of a Global Spine 1.01 0.52 0.52 0.26 0.26 0.26

PAC3 Clock contribution of a VersaTile

row

0.52

PAC4 Clock contribution of a VersaTile

used as a sequential module

0.07

PAC5 First contribution of a VersaTile used

as a sequential module

0.045

PAC6 Second contribution of a VersaTile

used as a sequential module

0.186

PAC7 Contribution of a VersaTile used as a

combinatorial module

0.11

PAC8 Average contribution of a routing

net

0.45

PAC9 Contribution of an I/O input pin

(standard-dependent)

See Table 2-12 on page 2-9

PAC10 Contribution of an I/O output pin

(standard-dependent)

See Table 2-13 on page 2-9

PAC11 Average contribution of a RAM

block during a read operation

25.00 N/A

PAC12 Average contribution of a RAM

block during a write operation

30.00 N/A

PAC13 Dynamic contribution for PLL 2.10 N/A

Table 2-17 • Different Components Contributing to the Static Power Consumption in IGLOO nano Devices

For IGLOO nano V2 Devices, 1.2 V Core Supply Voltage

Parameter Definition

Device-Specific Static Power (mW)

AGLN250 AGLN125 AGLN060 AGLN020 AGLN015 AGLN010

PDC1 Array static power in Active mode See Table 2-11 on page 2-8

PDC2 Array static power in Static (Idle)

mode

See Table 2-11 on page 2-8

PDC3 Array static power in Flash*Freeze

mode

See Table 2-8 on page 2-7

PDC4 2Static PLL contribution 0.90 N/A

PDC5 Bank quiescent power

(VCCI-dependent)

See Table 2-11 on page 2-8

Notes:

1. For a different output load, drive strength, or slew rate, Actel recommends using the Actel power

spreadsheet calculator or the SmartPower tool in Actel Libero IDE.

2. Minimum contribution of the PLL when running at lowest frequency.

IGLOO nano DC and Switching Characteristics

2-12 Advance v0.3

Power Calculation Methodology

This section describes a simplified method to estimate power consumption of an application. For

more accurate and detailed power estimations, use the SmartPower tool in Actel Libero IDE

software.

The power calculation methodology described below uses the following variables:

• The number of PLLs as well as the number and the frequency of each output clock

generated

• The number of combinatorial and sequential cells used in the design

•The internal clock frequencies

• The number and the standard of I/O pins used in the design

• The number of RAM blocks used in the design

• Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in Table 2-18 on

page 2-14.

• Enable rates of output buffers—guidelines are provided for typical applications in

Table 2-19 on page 2-14.

• Read rate and write rate to the memory—guidelines are provided for typical applications in

Table 2-19 on page 2-14. The calculation should be repeated for each clock domain defined

in the design.

Methodology

Total Power Consumption—PTOTAL

PTOTAL = PSTAT + PDYN

PSTAT is the total static power consumption.

PDYN is the total dynamic power consumption.

Total Static Power Consumption—PSTAT

PSTAT = (PDC1 or PDC2 or PDC3) + NBANKS * PDC5

NBANKS is the number of I/O banks powered in the design.

Total Dynamic Power Consumption—PDYN

PDYN = PCLOCK + PS-CELL + PC-CELL + PNET + PINPUTS + POUTPUTS + PMEMORY + PPLL

Global Clock Contribution—PCLOCK

PCLOCK = (PAC1 + NSPINE*PAC2 + NROW*PAC3 + NS-CELL* PAC4) * FCLK

NSPINE is the number of global spines used in the user design—guidelines are provided

in Table 2-18 on page 2-14.

NROW is the number of VersaTile rows used in the design—guidelines are provided in

Table 2-18 on page 2-14.

FCLK is the global clock signal frequency.

NS-CELL is the number of VersaTiles used as sequential modules in the design.

PAC1, PAC2, PAC3, and PAC4 are device-dependent.

Sequential Cells Contribution—PS-CELL

PS-CELL = NS-CELL * (PAC5 + α1 / 2 * PAC6) * FCLK

NS-CELL is the number of VersaTiles used as sequential modules in the design. When a

multi-tile sequential cell is used, it should be accounted for as 1.

α1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-18 on

page 2-14.

FCLK is the global clock signal frequency.

IGLOO nano DC and Switching Characteristics

Advance v0.3 2-13

Combinatorial Cells Contribution—PC-CELL

PC-CELL = NC-CELL* α1 / 2 * PAC7 * FCLK

NC-CELL is the number of VersaTiles used as combinatorial modules in the design.

α1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-18 on

page 2-14.

FCLK is the global clock signal frequency.

Routing Net Contribution—PNET

PNET = (NS-CELL + NC-CELL) * α1 / 2 * PAC8 * FCLK

NS-CELL is the number of VersaTiles used as sequential modules in the design.

NC-CELL is the number of VersaTiles used as combinatorial modules in the design.

α1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-18 on

page 2-14.

FCLK is the global clock signal frequency.

I/O Input Buffer Contribution—PINPUTS

PINPUTS = NINPUTS * α2 / 2 * PAC9 * FCLK

NINPUTS is the number of I/O input buffers used in the design.

α2 is the I/O buffer toggle rate—guidelines are provided in Table 2-18 on page 2-14.

FCLK is the global clock signal frequency.

I/O Output Buffer Contribution—POUTPUTS

POUTPUTS = NOUTPUTS * α2 / 2 * β1 * PAC10 * FCLK

NOUTPUTS is the number of I/O output buffers used in the design.

α2 is the I/O buffer toggle rate—guidelines are provided in Table 2-18 on page 2-14.

β1 is the I/O buffer enable rate—guidelines are provided in Table 2-19 on page 2-14.

FCLK is the global clock signal frequency.

RAM Contribution—PMEMORY

PMEMORY = PAC11 * NBLOCKS * FREAD-CLOCK * β2 + PAC12 * NBLOCK * FWRITE-CLOCK * β3

NBLOCKS is the number of RAM blocks used in the design.

FREAD-CLOCK is the memory read clock frequency.

β2 is the RAM enable rate for read operations.

FWRITE-CLOCK is the memory write clock frequency.

β3 is the RAM enable rate for write operations—guidelines are provided in Table 2-19

on page 2-14.

PLL Contribution—PPLL

PPLL = PDC4 + PAC13 *FCLKOUT

FCLKOUT is the output clock frequency.1

1. If a PLL is used to generate more than one output clock, include each output clock in the formula by adding its

corresponding contribution (PAC13* FCLKOUT product) to the total PLL contribution.

IGLOO nano DC and Switching Characteristics

2-14 Advance v0.3

Guidelines

Toggle Rate Definition

A toggle rate defines the frequency of a net or logic element relative to a clock. It is a percentage.

If the toggle rate of a net is 100%, this means that this net switches at half the clock frequency.

Below are some examples:

• The average toggle rate of a shift register is 100% because all flip-flop outputs toggle at

half of the clock frequency.

• The average toggle rate of an 8-bit counter is 25%:

– Bit 0 (LSB) = 100%

– Bit 1 = 50%

– Bit 2 = 25%

–…

– Bit 7 (MSB) = 0.78125%

– Average toggle rate = (100% + 50% + 25% + 12.5% + . . . + 0.78125%) / 8

Enable Rate Definition

Output enable rate is the average percentage of time during which tristate outputs are enabled.

When nontristate output buffers are used, the enable rate should be 100%.

Table 2-18 • Toggle Rate Guidelines Recommended for Power Calculation

Component Definition Guideline

α1Toggle rate of VersaTile outputs 10%

α2I/O buffer toggle rate 10%

Table 2-19 • Enable Rate Guidelines Recommended for Power Calculation

Component Definition Guideline

β1I/O output buffer enable rate 100%

β2RAM enable rate for read operations 12.5%

β3RAM enable rate for write operations 12.5%

IGLOO nano DC and Switching Characteristics

Advance v0.3 2-15

User I/O Characteristics

Timing Model

Figure 2-3 • Timing Model

Operating Conditions: STD Speed, Commercial Temperature Range (TJ = 70°C), Worst-Case

VCC = 1.425 V, for DC 1.5 V Core Voltage, Applicable to V2 and V5 Devices

DQ DQ

Combinational Cell

I/O Module

(Registered)

I/O Module

(Non-Registered)

I/O Module

(Registered)

I/O Module

(Non-Registered)

LVCMOS 2.5V Output Drive

Strength = 8 mA High Slew Rate

Input LVCMOS 2.5 V

LVCMOS 1.5 V

LVTTL 3.3 V Output drive

strength = 8 mA High slew rate

Combinational Cell

I/O Module

(Non-Registered)

LVTTL Output drive strength = 8 mA

High slew rate

I/O Module

(Non-Registered)

LVCMOS 1.5 V Output drive strength = 2 mA

High slew rate

LVTTL Output drive strength = 4 mA

High slew rate

I/O Module

(Non-Registered)

Input LVTTL

Clock

Input LVTTL

Clock

Input LVTTL

Clock

= 1.18 ns t

= 0.90 ns

= 1.99 ns

= 1.60 ns t

= 2.35 ns

= 1.17 ns

= 1.96 ns

= 0.87 ns t

= 2.65 ns

= 0.91 ns

= 0.85 ns

CLKQ

= 0.89 ns t

OCLKQ

= 1.00 ns

SUD

= 0.81 ns t

OSUD

= 0.51 ns

= 1.96 ns

= 0.85 ns

= 1.15 ns

CLKQ

= 0.89 ns

SUD

= 0.81 ns

= 0.85 ns

ICLKQ

= 0.42 ns

ISUD

= 0.47 ns

= 1.06 ns

IGLOO nano DC and Switching Characteristics

2-16 Advance v0.3

Figure 2-4 • Input Buffer Timing Model and Delays (example)

tPY

(R)

PAD

Vtrip

GND tPY

(F)

Vtrip

50%

VIH

VCC

VIL

tDOUT

(R)

DIN

GND tDOUT

(F)

50%50%

VCC

PAD Y

tPY

CLK

I/O Interface

DIN

tDIN

To Array

tPY = MAX(tPY(R), tPY(F))

tDIN = MAX(tDIN(R), tDIN(F))

IGLOO nano DC and Switching Characteristics

Advance v0.3 2-17

Figure 2-5 • Output Buffer Model and Delays (example)

tDP

(R)

PAD VOL

tDP

(F)

Vtrip

VOH

VCC

D50% 50%

VCC

0 V

DOUT 50% 50% 0 V

tDOUT

(R)

tDOUT

(F)

From Array

PAD

tDP

Std

Load

CLK

I/O Interface

DOUT

tDOUT

tDP = MAX(tDP(R), tDP(F))

tDOUT = MAX(tDOUT(R), tDOUT(F))

IGLOO nano DC and Switching Characteristics

2-18 Advance v0.3

Figure 2-6 • Tristate Output Buffer Timing Model and Delays (example)

CLK

10% V

CCI

trip

50%

90% V

CCI

trip

50% 50% t

50%

EOUT

PAD

E50%

EOUT (R)

50%

EOUT (F)

PAD

DOUT

EOUT

I/O Interface

EOUT

ZLS

trip

50%

ZHS

trip

50%

EOUT

PAD

E50% 50%

EOUT (R)

EOUT (F)

50%

CCI

, t

ZLS

, t

ZHS

EOUT

= MAX(t

EOUT

(r), t

EOUT

(f))

IGLOO nano DC and Switching Characteristics

Advance v0.3 2-19

Overview of I/O Performance

Summary of I/O DC Input and Output Levels – Default I/O Software

Settings

Table 2-20 • Summary of Maximum and Minimum DC Input and Output Levels

Applicable to Commercial and Industrial Conditions—Software Default Settings

I/O Standard

Drive

Strength

Slew

Rate

VIL VIH VOL VOH IOL 1IOH 1

Min, V Max, V Min, V Max, V Max, V Min, V mA mA

3.3 V LVTTL /

3.3 V LVCMOS

8 mA High –0.3 0.8 2 3.6 0.4 2.4 8 8

3.3 V Wide Range Any 2High –0.3 0.8 2 3.6 0.2 VCCI – 0.2 100

µA

100

µA

2.5 V LVCMOS 8 mA High –0.3 0.7 1.7 3.6 0.7 1.7 8 8

1.8 V LVCMOS 4 mA High –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI – 0.45 4 4

1.5 V LVCMOS 2 mA High –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 22

1.2 V LVCMOS 31 mA High –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 11

1.2 V LVCMOS

Wide Range 3Any 4High –0.3 0.3 * VCCI 0.7 * VCCI 3.6 0.1 VCCI – 0.1 100

µA

100

µA

Notes:

1. Currents are measured at 85°C junction temperature.

2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range, as specified in the JESD8-B

specification.

3. Applicable to IGLOO nano V2 devices operating at VCCI

≥

VCC .

4. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range, as specified in the JESD8-12

specification.

Table 2-21 • Summary of Maximum and Minimum DC Input Levels

Applicable to Commercial and Industrial Conditions

DC I/O Standards

Commercial1Industrial2

IIL 3IIH 4IIL 3IIH 4

µA µA µA µA

3.3 V LVTTL / 3.3 V LVCMOS 10 10 15 15

3.3 V LVCOMS Wide Range 10 10 15 15

2.5 V LVCMOS 10 10 15 15

1.8 V LVCMOS 10 10 15 15

1.5 V LVCMOS 10 10 15 15

1.2 V LVCMOS 5 10 10 15 15

1.2 V LVCMOS Wide Range 5 10 10 15 15

Notes:

1. Commercial range (–20°C < TA < 70°C)

2. Industrial range (–40°C < TA < 85°C)

3. IIH is the input leakage current per I/O pin over recommended operating conditions, where VIH < VIN < VCCI.

Input current is larger when operating outside recommended ranges.

4. IIL is the input leakage current per I/O pin over recommended operating conditions, where –0.3 V < VIN

< VIL.

5. Applicable to IGLOO nano V2 devices operating at VCCI

≥

VCC.

IGLOO nano DC and Switching Characteristics

2-20 Advance v0.3

Summary of I/O Timing Characteristics – Default I/O Software Settings

Table 2-22 • Summary of AC Measuring Points

Standard Measuring Trip Point (Vtrip)

3.3 V LVTTL / 3.3 V LVCMOS 1.4 V

3.3 V LVCMOS Wide Range 1.4 V

2.5 V LVCMOS 1.2 V

1.8 V LVCMOS 0.90 V

1.5 V LVCMOS 0.75 V

1.2 V LVCMOS 0.60 V

1.2 V LVCMOS Wide Range 0.60 V

Table 2-23 • I/O AC Parameter Definitions

Parameter Parameter Definition

tDP Data to Pad delay through the Output Buffer

tPY Pad to Data delay through the Input Buffer

tDOUT Data to Output Buffer delay through the I/O interface

tEOUT Enable to Output Buffer Tristate Control delay through the I/O interface

tDIN Input Buffer to Data delay through the I/O interface

tHZ Enable to Pad delay through the Output Buffer—HIGH to Z

tZH Enable to Pad delay through the Output Buffer—Z to HIGH

tLZ Enable to Pad delay through the Output Buffer—LOW to Z

tZL Enable to Pad delay through the Output Buffer—Z to LOW

tZHS Enable to Pad delay through the Output Buffer with delayed enable—Z to HIGH

tZLS Enable to Pad delay through the Output Buffer with delayed enable—Z to LOW

IGLOO nano DC and Switching Characteristics

Advance v0.3 2-21

Applies to IGLOO nano at 1.5 V Core Operating Conditions

Applies to IGLOO nano at 1.2 V Core Operating Conditions

Table 2-24 • Summary of I/O Timing Characteristics—Software Default Settings

STD Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI = 3.0 V

I/O Standard

Drive Strength (mA)

Slew Rate

Capacitive Load (pF)

tDOUT

tDP

tDIN

tPY

tPYS

tEOUT

tZL

tZH

tLZ

tHZ

Units

3.3 V LVTTL /

3.3 V LVCMOS

8 mA High 5 pF 0.97 1.96 0.19 0.85 1.14 0.66 1.73 1.32 2.04 2.38 ns

3.3 V LVCMOS

Wide Range

Any 1High 5 pF TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD

2.5 V LVCMOS 8 mA High 5 pF 0.97 1.99 0.19 1.06 1.22 0.66 1.76 1.42 2.04 2.25 ns

1.8 V LVCMOS 4 mA High 5 pF 0.97 2.30 0.19 0.99 1.43 0.66 2.01 1.64 2.08 2.15 ns

1.5 V LVCMOS 2 mA High 5 pF 0.97 2.65 0.19 1.15 1.62 0.66 2.31 1.85 2.13 2.11 ns

Notes:

1. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range, as specified in the JESD8-B

specification.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

Table 2-25 • Summary of I/O Timing Characteristics—Software Default Settings

STD Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V,

Worst-Case VCCI = 3.0 V

I/O Standard

Drive Strength (mA)

Slew Rate

Capacitive Load (pF)

tDOUT

tDP

tDIN

tPY)

tPYS

tEOUT

tZL

tZH

tLZ

tHZ

Units

3.3 V LVTTL /

3.3 V LVCMOS

8 mA High 5 pF 1.55 2.81 0.26 0.99 1.14 1.10 2.53 2.01 2.48 3.10 ns

3.3 V LVCMOS

Wide Range

Any 1High 5 pF TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD ns

2.5 V LVCMOS 8 mA High 5 pF 1.55 2.82 0.26 1.20 1.22 1.10 2.53 2.15 2.46 2.93 ns

1.8 V LVCMOS 4 mA High 5 pF 1.55 3.11 0.26 1.12 1.43 1.10 2.76 2.46 2.49 2.75 ns

1.5 V LVCMOS 2 mA High 5 pF 1.55 3.50 0.26 1.26 1.62 1.10 3.09 2.76 2.53 2.67 ns

1.2 V LVCMOS 1 mA High 5 pF 1.55 4.47 0.26 1.56 1.66 1.10 3.56 3.18 3.00 3.25 ns

1.2 V LVCMOS

Wide Range

100 µA High 5 pF TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD ns

Notes:

1. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range, as specified in the JESD8-B

specification.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

IGLOO nano DC and Switching Characteristics

2-22 Advance v0.3

Detailed I/O DC Characteristics

Table 2-26 • Input Capacitance

Symbol Definition Conditions Min. Max. Units

CIN Input capacitance VIN = 0, f = 1.0 MHz 8 pF

CINCLK Input capacitance on the clock pin VIN = 0, f = 1.0 MHz 8 pF

Table 2-27 • I/O Output Buffer Maximum Resistances 1

Standard Drive Strength

RPULL-DOWN

(Ω)2RPULL-UP

(Ω)3

3.3 V LVTTL / 3.3V LVCMOS 2 mA 100 300

4 mA 100 300

6 mA 50 150

8 mA 50 150

3.3 V LVCMOS Wide Range 100 µA TBD TBD

2.5 V LVCMOS 2 mA 100 200

4 mA 100 200

6 mA 50 100

8 mA 50 100

1.8 V LVCMOS 2 mA 200 225

4 mA 100 112

1.5 V LVCMOS 2 mA 200 224

1.2 V LVCMOS 42 mA TBD TBD

1.2 V LVCMOS Wide Range 4100 µA TBD TBD

Notes:

1. These maximum values are provided for informational reasons only. Minimum output buffer resistance

values depend on VCCI, drive strength selection, temperature, and process. For board design considerations

and detailed output buffer resistances, use the corresponding IBIS models located on the Actel website at

http://www.actel.com/download/ibis/default.aspx.

2. R(PULL-DOWN-MAX) = (VOLspec) / IOLspec

3. R(PULL-UP-MAX) = (VCCImax – VOHspec) / IOHspec

4. Applicable to IGLOO nano V2 devices operating at VCCI

≥

VCC.

IGLOO nano DC and Switching Characteristics

Advance v0.3 2-23

Table 2-28 • I/O Weak Pull-Up/Pull-Down Resistances

Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values

VCCI

R(WEAK PULL-UP)1

(Ω)

R(WEAK PULL-DOWN)2

(Ω)

Min. Max. Min. Max.

3.3 V 10 k 45 k 10 k 45 k

2.5 V 11 k 55 k 12 k 74 k

1.8 V 18 k 70 k 17 k 110 k

1.5 V 19 k 90 k 19 k 140 k

1.2 V 25 k 110 k 25 k 150 k

Notes:

1. R(WEAK PULL-UP-MAX) = (VOLspec) / I(WEAK PULL-UP-MIN)

2. R(WEAK PULL-UP-MAX) = (VCCImax – VOHspec) / I(WEAK PULL-UP-MIN)

Table 2-29 • I/O Short Currents IOSH/IOSL

Drive Strength IOSL (mA)* IOSH (mA)*

3.3 V LVTTL / 3.3 V LVCMOS 2 mA 25 27

4 mA 25 27

6 mA 51 54

8 mA 51 54

3.3 V LVCMOS Wide Range 100 µA TBD TBD

2.5 V LVCMOS 2 mA 16 18

4 mA 16 18

6 mA 32 37

8 mA 32 37

1.8 V LVCMOS 2 mA 9 11

4 mA 17 22

1.5 V LVCMOS 2 mA 13 16

1.2 V LVCMOS 1 mA TBD TBD

1.2 V LVCMOS Wide Range 100 µA TBD TBD

*TJ = 100°C

IGLOO nano DC and Switching Characteristics

2-24 Advance v0.3

The length of time an I/O can withstand IOSH/IOSL events depends on the junction temperature. The

reliability data below is based on a 3.3 V, 8 mA I/O setting, which is the worst case for this type of

analysis.

For example, at 110°C, the short current condition would have to be sustained for more than three

months to cause a reliability concern. The I/O design does not contain any short circuit protection,

but such protection would only be needed in extremely prolonged stress conditions.

Table 2-30 • Duration of Short Circuit Event before Failure

Temperature Time before Failure

–40°C > 20 years

–20°C > 20 years

0°C > 20 years

25°C > 20 years

70°C 5 years

85°C 2 years

100°C 6 months

110°C 3 months

Table 2-31 • Schmitt Trigger Input Hysteresis

Hysteresis Voltage Value (Typ.) for Schmitt Mode Input Buffers

Input Buffer Configuration Hysteresis Value (typ.)

3.3 V LVTTL / LVCMOS (Schmitt trigger mode) 240 mV

2.5 V LVCMOS (Schmitt trigger mode) 140 mV

1.8 V LVCMOS (Schmitt trigger mode) 80 mV

1.5 V LVCMOS (Schmitt trigger mode) 60 mV

1.2 V LVCMOS (Schmitt trigger mode) 40 mV

Table 2-32 • I/O Input Rise Time, Fall Time, and Related I/O Reliability

Input Buffer

Input Rise/Fall Time

(min.)

Input Rise/Fall Time

(max.) Reliability

LVTTL/LVCMOS (Schmitt trigger

disabled)

No requirement 10 ns * 20 years (100°C)

LVTTL/LVCMOS (Schmitt trigger

enabled)

No requirement No requirement, but

input noise voltage

cannot exceed

Schmitt hysteresis.

20 years (100°C)

*The maximum input rise/fall time is related to the noise induced into the input buffer trace. If the

noise is low, then the rise time and fall time of input buffers can be increased beyond the

maximum value. The longer the rise/fall times, the more susceptible the input signal is to the

board noise. Actel recommends signal integrity evaluation/characterization of the system to

ensure that there is no excessive noise coupling into input signals.

IGLOO nano DC and Switching Characteristics

Advance v0.3 2-25

Single-Ended I/O Characteristics

3.3 V LVTTL / 3.3 V LVCMOS

Low-Voltage Transistor–Transistor Logic (LVTTL) is a general-purpose standard (EIA/JESD) for 3.3 V

applications. It uses an LVTTL input buffer and push-pull output buffer.

Table 2-33 • Minimum and Maximum DC Input and Output Levels

3.3 V LVTTL /

3.3 V LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL 1IIH 2

Drive

Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA3Max., mA3µA4µA4

2 mA –0.3 0.8 2 3.6 0.4 2.4 2 2 25 27 10 10

4 mA –0.3 0.8 2 3.6 0.4 2.4 4 4 25 27 10 10

6 mA –0.3 0.8 2 3.6 0.4 2.4 6 6 51 54 10 10

8 mA –0.3 0.8 2 3.6 0.4 2.4 8 8 51 54 10 10

Notes:

1. IIL is the input leakage current per I/O pin over recommended operating conditions where –0.3 < VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions where VIH < VIN < VCCI.

Input current is larger when operating outside recommended ranges.

3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

4. Currents are measured at 85°C junction temperature.

5. Software default selection highlighted in gray.

Figure 2-7 • AC Loading

Table 2-34 • 3.3 V LVTTL/LVCMOS AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V) Measuring Point* (V) CLOAD (pF)

03.31.45

*Measuring point = Vtrip. See Table 2-22 on page 2-20 for a complete table of trip points.

Test Point Test Point

Enable Path

Datapath 5 pF

R = 1 k R to VCCI for tLZ/tZL/tZLS

R to GND for tHZ/tZH/tZHS

35 pF for tZH/tZHS/tZL/tZLS

5 pF for tHZ/tLZ

IGLOO nano DC and Switching Characteristics

2-26 Advance v0.3

Timing Characteristics

Applies to 1.5 V DC Core Voltage

Table 2-35 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Drive Strength Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units

2 mA STD 0.97 3.94 0.19 0.85 1.14 0.66 3.39 2.95 1.82 1.87 ns

4 mA STD 0.97 3.94 0.19 0.85 1.14 0.66 3.39 2.95 1.82 1.87 ns

6 mA STD 0.97 3.20 0.19 0.85 1.14 0.66 2.88 2.65 2.04 2.27 ns

8 mA STD 0.97 3.20 0.19 0.85 1.14 0.66 2.88 2.65 2.04 2.27 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

Table 2-36 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Drive Strength Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units

2 mA STD 0.97 2.35 0.19 0.85 1.14 0.66 1.88 1.43 1.81 1.98 ns

4 mA STD 0.97 2.35 0.19 0.85 1.14 0.66 1.88 1.43 1.81 1.98 ns

6 mA STD 0.97 1.96 0.19 0.85 1.14 0.66 1.73 1.32 2.04 2.38 ns

8 mA STD 0.97 1.96 0.19 0.85 1.14 0.66 1.73 1.32 2.04 2.38 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

IGLOO nano DC and Switching Characteristics

Advance v0.3 2-27

Applies to 1.2 V DC Core Voltage

Table 2-37 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V

Drive Strength Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units

2 mA STD 1.55 5.23 0.26 0.99 1.14 1.10 4.56 3.93 2.25 2.56 ns

4 mA STD 1.55 5.23 0.26 0.99 1.14 1.10 4.56 3.93 2.25 2.56 ns

6 mA STD 1.55 4.21 0.26 0.99 1.14 1.10 3.81 3.42 2.48 2.97 ns

8 mA STD 1.55 4.21 0.26 0.99 1.14 1.10 3.81 3.42 2.48 2.97 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

Table 2-38 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V

Drive Strength Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units

2 mA STD 1.55 3.49 0.26 0.99 1.14 1.10 2.91 2.33 2.24 2.68 ns

4 mA STD 1.55 3.49 0.26 0.99 1.14 1.10 2.91 2.33 2.24 2.68 ns

6 mA STD 1.55 2.81 0.26 0.99 1.14 1.10 2.53 2.01 2.48 3.10 ns

8 mA STD 1.55 2.81 0.26 0.99 1.14 1.10 2.53 2.01 2.48 3.10 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

IGLOO nano DC and Switching Characteristics

2-28 Advance v0.3

3.3 V LVCOMOS Wide Range

Table 2-39 • Minimum and Maximum DC Input and Output Levels for LVCMOS 3.3 V Wide Range

3.3 V LVCMOS

Wide Range VIL VIH VOL VOH IOL IOH IIL 1IIH 2

Drive

Strength Min., V Max., V Min., V Max., V Max., V Min., V µA µA µA3µA3

All 4–0.3 0.8 2 3.6 0.2 VDD – 0.2 100 100 10 10

Notes:

1. IIL is the input leakage current per I/O pin over recommended operating conditions where –0.3 < VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions where VIH < VIN < VCCI.

Input current is larger when operating outside recommended ranges.

3. Currents are measured at 85°C junction temperature.

4. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V Wide Range, as specified in the JEDEC JESD8-B

specification.

IGLOO nano DC and Switching Characteristics

Advance v0.3 2-29

2.5 V LVCMOS

Low-Voltage CMOS for 2.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-

purpose 2.5 V applications. It uses a 5 V–tolerant input buffer and push-pull output buffer.

Table 2-40 • Minimum and Maximum DC Input and Output Levels

2.5 V

LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL 1IIH 2

Drive

Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA3Max., mA3µA4µA4

2 mA –0.3 0.7 1.7 3.6 0.7 1.7 2 2 16 18 10 10

4 mA –0.3 0.7 1.7 3.6 0.7 1.7 4 4 16 18 10 10

6 mA –0.3 0.7 1.7 3.6 0.7 1.7 6 6 32 37 10 10

8 mA –0.3 0.7 1.7 3.6 0.7 1.7 8 8 32 37 10 10

Notes:

1. IIL is the input leakage current per I/O pin over recommended operating conditions where –0.3 < VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions where VIH < VIN < VCCI.

Input current is larger when operating outside recommended ranges.

3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

4. Currents are measured at 85°C junction temperature.

5. Software default selection highlighted in gray.

Figure 2-8 • AC Loading

Table 2-41 • 2.5 V LVCMOS AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V) Measuring Point* (V) CLOAD (pF)

02.51.25

*Measuring point = Vtrip. See Table 2-22 on page 2-20 for a complete table of trip points.

Test Point Test Point

Enable Path

Datapath 5 pF

R = 1 k R to VCCI for tLZ/tZL/tZLS

R to GND for tHZ/tZH/tZHS

35 pF for tZH/tZHS/tZL/tZLS

5 pF for tHZ/tLZ

IGLOO nano DC and Switching Characteristics

2-30 Advance v0.3

Timing Characteristics

Applies to 1.5 V DC Core Voltage

Table 2-42 • 2.5 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V

Drive Strength Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units

2 mA STD 0.97 4.44 0.19 1.06 1.22 0.66 3.87 3.47 1.80 1.70 ns

4 mA STD 0.97 4.44 0.19 1.06 1.22 0.66 3.87 3.47 1.80 1.70 ns

8 mA STD 0.97 3.61 0.19 1.06 1.22 0.66 3.27 3.11 2.05 2.17 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

Table 2-43 • 2.5 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V

Drive Strength Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units

2 mA STD 0.97 2.41 0.19 1.06 1.22 0.66 1.93 1.57 1.79 1.77 ns

4 mA STD 0.97 2.41 0.19 1.06 1.22 0.66 1.93 1.57 1.79 1.77 ns

6 mA STD 0.97 1.99 0.19 1.06 1.22 0.66 1.76 1.42 2.04 2.25 ns

8 mA STD 0.97 1.99 0.19 1.06 1.22 0.66 1.76 1.42 2.04 2.25 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

IGLOO nano DC and Switching Characteristics

Advance v0.3 2-31

Applies to 1.2 V DC Core Voltage

Table 2-44 • 2.5 LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V

Drive Strength Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units

2 mA STD 1.55 5.75 0.26 1.20 1.22 1.10 5.05 4.57 2.21 2.35 ns

4 mA STD 1.55 5.75 0.26 1.20 1.22 1.10 5.05 4.57 2.21 2.35 ns

6 mA STD 1.55 4.63 0.26 1.20 1.22 1.10 4.21 3.94 2.47 2.83 ns

8 mA STD 1.55 4.63 0.26 1.20 1.22 1.10 4.21 3.94 2.47 2.83 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

Table 2-45 • 2.5 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V

Drive Strength Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units

2 mA STD 1.55 3.52 0.26 1.20 1.22 1.10 2.94 2.60 2.21 2.44 ns

4 mA STD 1.55 3.52 0.26 1.20 1.22 1.10 2.94 2.60 2.21 2.44 ns

6 mA STD 1.55 2.82 0.26 1.20 1.22 1.10 2.53 2.15 2.46 2.93 ns

8 mA STD 1.55 2.82 0.26 1.20 1.22 1.10 2.53 2.15 2.46 2.93 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

IGLOO nano DC and Switching Characteristics

2-32 Advance v0.3

1.8 V LVCMOS

Low-voltage CMOS for 1.8 V is an extension of the LVCMOS standard (JESD8-5) used for general-

purpose 1.8 V applications. It uses a 1.8 V input buffer and a push-pull output buffer.

Table 2-46 • Minimum and Maximum DC Input and Output Levels

1.8 V

LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL 1IIH 2

Drive

Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA3Max., mA3µA4µA4

2 mA –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI – 0.45 2 2 9 11 10 10

4 mA –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI – 0.45 4 4 17 22 10 10

Notes:

1. IIL is the input leakage current per I/O pin over recommended operating conditions where –0.3 < VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions where VIH < VIN < VCCI.

Input current is larger when operating outside recommended ranges.

3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

4. Currents are measured at 85°C junction temperature.

5. Software default selection highlighted in gray.

Figure 2-9 • AC Loading

Table 2-47 • 1.8 V LVCMOS AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V) Measuring Point* (V) CLOAD (pF)

01.80.95

*Measuring point = Vtrip. See Table 2-22 on page 2-20 for a complete table of trip points.

Test Point Test Point

Enable Path

Datapath 5 pF

R = 1 k R to VCCI for tLZ/tZL/tZLS

R to GND for tHZ/tZH/tZHS

35 pF for tZH/tZHS/tZL/tZLS

5 pF for tHZ/tLZ

IGLOO nano DC and Switching Characteristics

Advance v0.3 2-33

Timing Characteristics

Applies to 1.5 V DC Core Voltage

Applies to 1.2 V DC Core Voltage

Table 2-48 • 1.8 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V

Drive Strength Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units

2 mA STD 0.97 5.89 0.19 0.99 1.43 0.66 5.20 4.48 1.78 1.30 ns

4 mA STD 0.97 4.82 0.19 0.99 1.43 0.66 4.39 4.04 2.08 2.07 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

Table 2-49 • 1.8 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V

Drive Strength Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units

2 mA STD 0.97 2.82 0.19 0.99 1.43 0.66 2.25 1.86 1.78 1.35 ns

4 mA STD 0.97 2.30 0.19 0.99 1.43 0.66 2.01 1.64 2.08 2.15 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

Table 2-50 • 1.8 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V

Drive Strength Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units

2 mA STD 1.55 7.30 0.26 1.12 1.43 1.10 6.45 5.82 2.18 1.87 ns

4 mA STD 1.55 5.88 0.26 1.12 1.43 1.10 5.35 4.98 2.49 2.67 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

Table 2-51 • 1.8 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V

Drive Strength Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units

2 mA STD 1.55 4.24 0.26 1.12 1.43 1.10 3.28 3.11 2.18 1.92 ns

4 mA STD 1.55 3.11 0.26 1.12 1.43 1.10 2.76 2.46 2.49 2.75 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

IGLOO nano DC and Switching Characteristics

2-34 Advance v0.3

1.5 V LVCMOS (JESD8-11)

Low-Voltage CMOS for 1.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-

purpose 1.5 V applications. It uses a 1.5 V input buffer and a push-pull output buffer.

Table 2-52 • Minimum and Maximum DC Input and Output Levels

1.5 V

LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL 1IIH 2

Drive

Strength

Min.,

V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA3Max., mA3µA4µA4

2 mA –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 2 2 13 16 10 10

Notes:

1. IIL is the input leakage current per I/O pin over recommended operating conditions where –0.3 < VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions where VIH < VIN < VCCI.

Input current is larger when operating outside recommended ranges.

3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

4. Currents are measured at 85°C junction temperature.

5. Software default selection highlighted in gray.

Figure 2-10 • AC Loading

Table 2-53 • 1.5 V LVCMOS AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V) Measuring Point* (V) CLOAD (pF)

01.50.755

*Measuring point = Vtrip. See Table 2-22 on page 2-20 for a complete table of trip points.

Test Point Test Point

Enable Path

Datapath 5 pF

R = 1 k R to VCCI for tLZ/tZL/tZLS

R to GND for tHZ/tZH/tZHS

35 pF for tZH/tZHS/tZL/tZLS

5 pF for tHZ/tLZ

IGLOO nano DC and Switching Characteristics

Advance v0.3 2-35

Timing Characteristics

Applies to 1.5 V DC Core Voltage

Applies to 1.2 V DC Core Voltage

Table 2-54 • 1.5 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V

Drive Strength Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units

2 mA STD 0.97 6.07 0.19 1.15 1.62 0.66 5.57 4.89 2.13 2.02 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

Table 2-55 • 1.5 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V

Drive Strength Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units

2 mA STD 0.97 2.65 0.19 1.15 1.62 0.66 2.31 1.85 2.13 2.11 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

Table 2-56 • 1.5 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V

Drive Strength Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units

2 mA STD 1.55 7.23 0.26 1.26 1.62 1.10 6.61 5.94 2.53 2.58 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

Table 2-57 • 1.5 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V

Drive Strength Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units

2 mA STD 1.55 3.50 0.26 1.26 1.62 1.10 3.09 2.76 2.53 2.67 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

IGLOO nano DC and Switching Characteristics

2-36 Advance v0.3

1.2 V LVCMOS (JESD8-12A)

Low-Voltage CMOS for 1.2 V complies with the LVCMOS standard JESD8-12A for general purpose

1.2 V applications. It uses a 1.2 V input buffer and a push-pull output buffer.

Timing Characteristics

Applies to 1.2 V DC Core Voltage

Table 2-58 • Minimum and Maximum DC Input and Output Levels

1.2 V

LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL 1IIH 2

Drive

Strength

Min.,

Max.,

V Min., V Max., V Max., V Min., V mA mA Max., mA3Max., mA3µA4µA4

1 mA –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 1 1 TBD TBD 10 10

Notes:

1. IIL is the input leakage current per I/O pin over recommended operating conditions where –0.3 < VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions where VIH < VIN < VCCI.

Input current is larger when operating outside recommended ranges.

3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

4. Currents are measured at 85°C junction temperature.

5. Software default selection highlighted in gray.

Figure 2-11 • AC Loading

Table 2-59 • 1.2 V LVCMOS AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V) Measuring Point* (V) CLOAD (pF)

01.20.65

*Measuring point = Vtrip. See Table 2-22 on page 2-20 for a complete table of trip points.

Test Point Test Point

Enable Path

Datapath 5 pF

R = 1 k R to VCCI for tLZ/tZL/tZLS

R to GND for tHZ/tZH/tZHS

35 pF for tZH/tZHS/tZL/tZLS

5 pF for tHZ/tLZ

Table 2-60 • 1.2 V LVCMOS Low Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V

Drive Strength Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units

1 mA STD 1.55 10.33 0.26 1.56 1.66 1.10 8.52 7.30 3.00 3.12 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

Table 2-61 • 1.2 V LVCMOS High Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V

Drive Strength Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units

1 mA STD 1.55 4.47 0.26 1.56 1.66 1.10 3.56 3.18 3.00 3.25 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

IGLOO nano DC and Switching Characteristics

Advance v0.3 2-37

I/O Register Specifications

Fully Registered I/O Buffers with Asynchronous Preset

Figure 2-12 • Timing Model of Registered I/O Buffers with Asynchronous Preset

INBUF INBUF

TRIBUF

CLKBUF

INBUF

CLKBUF

Data Input I/O Register with:

Active High Preset

Positive-Edge Triggered

Data Output Register and

Enable Output Register with:

Active High Preset

Postive-Edge Triggered

Pad Out

CLK

Preset

Data_out

Data

EOUT

DOUT

CLK

DFN1P1

PRE

DFN1P1

PRE

DFN1P1

PRE

D_Enable

Core

Array

IGLOO nano DC and Switching Characteristics

2-38 Advance v0.3

Table 2-62 • Parameter Definition and Measuring Nodes

Parameter Name Parameter Definition

Measuring Nodes

(from, to)*

tOCLKQ Clock-to-Q of the Output Data Register H, DOUT

tOSUD Data Setup Time for the Output Data Register F, H

tOHD Data Hold Time for the Output Data Register F, H

tOPRE2Q Asynchronous Preset-to-Q of the Output Data Register L, DOUT

tOREMPRE Asynchronous Preset Removal Time for the Output Data Register L, H

tORECPRE Asynchronous Preset Recovery Time for the Output Data Register L, H

tOECLKQ Clock-to-Q of the Output Enable Register H, EOUT

tOESUD Data Setup Time for the Output Enable Register J, H

tOEHD Data Hold Time for the Output Enable Register J, H

tOEPRE2Q Asynchronous Preset-to-Q of the Output Enable Register I, EOUT

tOEREMPRE Asynchronous Preset Removal Time for the Output Enable Register I, H

tOERECPRE Asynchronous Preset Recovery Time for the Output Enable Register I, H

tICLKQ Clock-to-Q of the Input Data Register A, E

tISUD Data Setup Time for the Input Data Register C, A

tIHD Data Hold Time for the Input Data Register C, A

tIPRE2Q Asynchronous Preset-to-Q of the Input Data Register D, E

tIREMPRE Asynchronous Preset Removal Time for the Input Data Register D, A

tIRECPRE Asynchronous Preset Recovery Time for the Input Data Register D, A

*See Figure 2-12 on page 2-37 for more information.

IGLOO nano DC and Switching Characteristics

Advance v0.3 2-39

Fully Registered I/O Buffers with Asynchronous Clear

Figure 2-13 • Timing Model of the Registered I/O Buffers with Asynchronous Clear

CLK

Pad Out

CLK

CLR

Data_out

Data

EOUT

DOUT

Core

Array

DFN1C1

CLR

DFN1C1

CLR

DFN1C1

CLR

D_Enable

CLKBUF

INBUF

TRIBUF

INBUF CLKBUF

INBUF

Data Input I/O Register with

Active High Clear

Positive-Edge Triggered

Data Output Register and

Enable Output Register with

Active High Clear

Positive-Edge Triggered

IGLOO nano DC and Switching Characteristics

2-40 Advance v0.3

Table 2-63 • Parameter Definition and Measuring Nodes

Parameter Name Parameter Definition

Measuring Nodes

(from, to)*

tOCLKQ Clock-to-Q of the Output Data Register HH, DOUT

tOSUD Data Setup Time for the Output Data Register FF, HH

tOHD Data Hold Time for the Output Data Register FF, HH

tOCLR2Q Asynchronous Clear-to-Q of the Output Data Register LL, DOUT

tOREMCLR Asynchronous Clear Removal Time for the Output Data Register LL, HH

tORECCLR Asynchronous Clear Recovery Time for the Output Data Register LL, HH

tOECLKQ Clock-to-Q of the Output Enable Register HH, EOUT

tOESUD Data Setup Time for the Output Enable Register JJ, HH

tOEHD Data Hold Time for the Output Enable Register JJ, HH

tOECLR2Q Asynchronous Clear-to-Q of the Output Enable Register II, EOUT

tOEREMCLR Asynchronous Clear Removal Time for the Output Enable Register II, HH

tOERECCLR Asynchronous Clear Recovery Time for the Output Enable Register II, HH

tICLKQ Clock-to-Q of the Input Data Register AA, EE

tISUD Data Setup Time for the Input Data Register CC, AA

tIHD Data Hold Time for the Input Data Register CC, AA

tICLR2Q Asynchronous Clear-to-Q of the Input Data Register DD, EE

tIREMCLR Asynchronous Clear Removal Time for the Input Data Register DD, AA

tIRECCLR Asynchronous Clear Recovery Time for the Input Data Register DD, AA

*See Figure 2-13 on page 2-39 for more information.

IGLOO nano DC and Switching Characteristics

Advance v0.3 2-41

Input Register

Timing Characteristics

1.5 V DC Core Voltage

Figure 2-14 • Input Register Timing Diagram

50%

Clear

Out_1

CLK

Data

Preset

50%

ISUD

IHD

50% 50%

ICLKQ

IRECPRE

IREMPRE

IRECCLR

IREMCLR

IWCLR

IWPRE

IPRE2Q

ICLR2Q

ICKMPWH

ICKMPWL

50% 50%

50% 50% 50%

50% 50%

50% 50% 50% 50% 50% 50%

50%

Table 2-64 • Input Data Register Propagation Delays

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V

Parameter Description Std. Units

tICLKQ Clock-to-Q of the Input Data Register 0.42 ns

tISUD Data Setup Time for the Input Data Register 0.47 ns

tIHD Data Hold Time for the Input Data Register 0.00 ns

tICLR2Q Asynchronous Clear-to-Q of the Input Data Register 0.79 ns

tIPRE2Q Asynchronous Preset-to-Q of the Input Data Register 0.79 ns

tIREMCLR Asynchronous Clear Removal Time for the Input Data Register 0.00 ns

tIRECCLR Asynchronous Clear Recovery Time for the Input Data Register 0.24 ns

tIREMPRE Asynchronous Preset Removal Time for the Input Data Register 0.00 ns

tIRECPRE Asynchronous Preset Recovery Time for the Input Data Register 0.24 ns

tIWCLR Asynchronous Clear Minimum Pulse Width for the Input Data Register 0.19 ns

tIWPRE Asynchronous Preset Minimum Pulse Width for the Input Data Register 0.19 ns

tICKMPWH Clock Minimum Pulse Width HIGH for the Input Data Register 0.31 ns

tICKMPWL Clock Minimum Pulse Width LOW for the Input Data Register 0.28 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

IGLOO nano DC and Switching Characteristics

2-42 Advance v0.3

1.2 V DC Core Voltage

Table 2-65 • Input Data Register Propagation Delays

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V

Parameter Description Std. Units

tICLKQ Clock-to-Q of the Input Data Register 0.68 ns

tISUD Data Setup Time for the Input Data Register 0.97 ns

tIHD Data Hold Time for the Input Data Register 0.00 ns

tICLR2Q Asynchronous Clear-to-Q of the Input Data Register 1.19 ns

tIPRE2Q Asynchronous Preset-to-Q of the Input Data Register 1.19 ns