Freescale Semiconductor
Data Sheet: Technical Data
Document Number: MCF51AC256
Rev.7, 9/2011
© Freescale Semiconductor, Inc., 2008-2011. All rights reserved.
This document contains information on a product under development. Freescale reserves the
right to change or discontinue this product without notice.
MCF51AC256
80 LQFP
14 mm 14 mm
64 LQFP
10 mm 10 mm
64 QFP
14 mm 14 mm
44 LQFP
10 mm 10 mm
The MCF51AC256 series are members of the
ColdFire® family of 32-bit variable-length reduced
instruction set (RISC) microcontroller. This
document provides an overview of the
MCF51AC256 series, focusing on its highly
integrated and diverse feature set.
The MCF51AC256 series are based on the V1
ColdFire core and operates at processor core speeds
up to 50.33 MHz. As part of Freescale’s Controller
Continuum®, it is an ideal upgrade for designs
based on the MC9S08AC128 series of 8-bit
microcontrollers.
The MCF51AC256 features the following
functional units:
• V1 ColdFire core with background debug
module
• Up to 256 KB of flash memory
• Up to 32 KB of static RAM (SRAM)
• Up to two analog comparators (ACMP)
• Analog-to-digital converter (ADC) with up
to 24 channels
• Controller-area network (CAN)
• Cyclic redundancy check (CRC)
• Inter-integrated circuit (IIC)
• Keyboard interrupt (KBI)
• Multipurpose clock generator (MCG)
• Rapid general-purpose input/output
(RGPIO)
• T wo serial communications interfaces (SCI)
• Up to two serial peripheral interfaces (SPI)
• Two flexible timer modules (FTM)
• Timer pulse-width modulator (TPM)
MCF51AC256 Series
ColdFire Microcontroller
Covers:MCF51AC256A
MCF51AC256B
MCF51AC128A
MCF51AC128C
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.7
Freescale Semiconductor2
Table of Contents
1 MCF51AC256 Family Configurations . . . . . . . . . . . . . . . . . . . .3
1.1 Device Comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.2 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
1.3.1 Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
1.4 Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
1.5 Pinouts and Packaging . . . . . . . . . . . . . . . . . . . . . . . . .12
2 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
2.1 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . .17
2.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . .17
2.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .18
2.4 Electrostatic Discharge (ESD) Protection Characteristics
19
2.5 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
2.6 Supply Current Characteristics . . . . . . . . . . . . . . . . . . .25
2.7 Analog Comparator (ACMP) Electricals . . . . . . . . . . . .27
2.8 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .28
2.9 External Oscillator (XOSC) Characteristics . . . . . . . . .31
2.10 MCG Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .32
2.11 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
2.11.1 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . .34
2.11.2 Timer (TPM/FTM) Module Timing . . . . . . . . . . .35
2.11.3 MSCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
2.12 SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
2.13 Flash Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .38
2.14 EMC Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
2.14.1 Radiated Emissions. . . . . . . . . . . . . . . . . . . . . .39
3 Mechanical Outline Drawings . . . . . . . . . . . . . . . . . . . . . . . . .40
4 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
List of Figures
Figure 1.MCF51AC256 Series Block Diagram . . . . . . . . . . . . . . 5
Figure 2.MCF51AC256 Series ColdFire Microcontroller
80-Pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 3.MCF51AC256 Series ColdFire Microcontroller
64-Pin QFP/LQFP. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 4.MCF51AC256 Series ColdFire Microcontroller
44-Pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 5.Typical IOH vs. VDD–VOH at VDD = 3 V
(Low Drive, PTxDSn = 0) . . . . . . . . . . . . . . . . . . . . . . 22
Figure 6.Typical IOH vs. VDD–VOH at VDD = 3 V
(High Drive, PTxDSn = 1) . . . . . . . . . . . . . . . . . . . . . . 23
Figure 7.Typical IOH vs. VDD–VOH at VDD = 5 V
(Low Drive, PTxDSn = 0) . . . . . . . . . . . . . . . . . . . . . . 23
Figure 8.Typical IOH vs. VDD–VOH at VDD = 5 V
(High Drive, PTxDSn = 1) . . . . . . . . . . . . . . . . . . . . . . 24
Figure 9.Typical Run IDD vs. System Clock Freq.
for FEI and FBE Modes . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 10.ADC Input Impedance Equivalency Diagram. . . . . . . 29
Figure 11.Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 12.IRQ/KBIPx Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 13.Timer External Clock . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 14.Timer Input Capture Pulse . . . . . . . . . . . . . . . . . . . . . 35
Figure 15.SPI Master Timing (CPHA = 0) . . . . . . . . . . . . . . . . . 37
Figure 16.SPI Master Timing (CPHA =1) . . . . . . . . . . . . . . . . . . 37
Figure 17.SPI Slave Timing (CPHA = 0) . . . . . . . . . . . . . . . . . . 38
Figure 18.SPI Slave Timing (CPHA = 1) . . . . . . . . . . . . . . . . . . 38
List of Tables
Table 1. MCF51AC256 Series Device Comparison . . . . . . . . . . 3
Table 2. MCF51AC256 Series Functional Units . . . . . . . . . . . . . 6
Table 3. Orderable Part Number Summary. . . . . . . . . . . . . . . . 10
Table 4. Pin Availability by Package Pin-Count . . . . . . . . . . . . . 14
Table 5. Parameter Classifications . . . . . . . . . . . . . . . . . . . . . . 17
Table 6. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . 18
Table 7. Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . . . 18
Table 8. ESD and Latch-up Test Conditions . . . . . . . . . . . . . . . 20
Table 9. ESD and Latch-Up Protection Characteristics. . . . . . . 20
Table 10.DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 11. Supply Current Characteristics. . . . . . . . . . . . . . . . . . 25
Table 12.Analog Comparator Electrical Specifications. . . . . . . . 27
Table 13.5 Volt 12-bit ADC Operating Conditions . . . . . . . . . . . 28
Table 14.5 Volt 12-bit ADC Characteristics
(VREFH = VDDA, VREFL = VSSA) . . . . . . . . . . . . . . . . . . 29
Table 15.Oscillator Electrical Specifications
(Temperature Range = –40 to 105 C Ambient) . . . . . 31
Table 16.MCG Frequency Specifications
(Temperature Range = –40 to 105 C Ambient) . . . . . 32
Table 17.Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 18.TPM/FTM Input Timing . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 19.MSCAN Wake-Up Pulse Characteristics . . . . . . . . . . . 35
Table 20.SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 21.Flash Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 22.Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 23.Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
MCF51AC256 Family Configurations
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.7
Freescale Semiconductor 3
1 MCF51AC256 Family Configurations
1.1 Device Comparison
The MCF51AC256 series is summarized in Table 1.
Table 1. MCF51AC256 Series Device Comparison
Feature
MCF51AC256A MCF51AC256B MCF51AC128A MCF51AC128C
80-pin 64-pin 80-pin 64-pin 44-pin 80-pin 64-pin 80-pin 64-pin 44-pin
Flash memory size (Kbytes) 256 128
RAM size (Kbytes) 32 32 or 161
V1 ColdFire core with BDM (background
debug module)
Ye s
ACMP1 (analog comparator) Yes
ACMP2 (analog comparator) Yes Yes No Yes No
ADC (analog-to-digital converter) channels
(12-bit)
24 20 24 20 9 24 20 24 20 9
CAN (controller area network) Yes No Yes No
COP (computer operating properly) Yes
CRC (cyclic redundancy check) Yes
RTI Ye s
DBG (debug) Ye s
IIC1 (inter-integrated circuit) Yes
IRQ (interrupt request input) Yes
INTC (interrupt controller) Yes
KBI (keyboard interrupts) Yes
LVD (low-voltage detector) Yes
MCG (multipurpose clock generator) Yes
OSC (crystal oscillator) Yes
Port I/O269 54 69 54 36 69 54 69 54 36
RGPIO (rapid general-purpose I/O) 16 12 16 12
SCI1, SCI2 (serial communications
interfaces)
Ye s
SPI1 (serial peripheral interface) Yes
SPI2 (serial peripheral interface) Yes No Yes No Yes No Yes No
FTM1 (flexible timer module) channels 6 4 6 4
FTM2 channels 6 2 6 2 2 6 2 6 2 2
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.7
MCF51AC256 Family Configurations
Freescale Semiconductor4
1.2 Block Diagram
Figure 1 shows the connections between the MCF51AC256 series pins and modules.
TPM3 (timer pulse-width modulator)
channels
2
VBUS (debug visibility bus) Yes No Yes No Yes No Yes No
1The members of MCF51AC128A with CAN support have 32 KB RAM. The other members have 16 KB RAM.
2Up to 16 pins on Ports E and F are shared with the ColdFire Rapid GPIO module.
Table 1. MCF51AC256 Series Device Comparison (continued)
Feature
MCF51AC256A MCF51AC256B MCF51AC128A MCF51AC128C
80-pin 64-pin 80-pin 64-pin 44-pin 80-pin 64-pin 80-pin 64-pin 44-pin
MCF51AC256 Family Configurations
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.7
Freescale Semiconductor 5
Figure 1. MCF51AC256 Series Block Diagram
Port B
PTB3/AD1P3
PTB4/AD1P4
PTB5/AD1P5
PTB2/AD1P2
PTB1/TPM3CH1/AD1P1
PTB0/TPM3CH0/AD1P0
PTB6/AD1P6
PTB7/AD1P7
Port D
PTD3/KBI1P6/AD1P11
PTD4/FTM2CLK/AD1P12
PTD5/AD1P13
PTD2/KBI1P5/AD1P10/ACMP1O
PTD1/AD1P9/ACMP1–
PTD0/AD1P8/ACMP1+
PTD6/FTM1CLK/AD1P14
PTD7/KBI1P7/AD1P15
Port C
PTC3/TxD2
PTC4/SS2
PTC5/RxD2
PTC2/MCLK
PTC1/SDA1
PTC0/SCL1
PTC6/FTM2FLT
Port F
PTF3/RGPIO11/FTM1CH5
PTF4/RGPIO12/FTM2CH0
PTF5/RGPIO13/FTM2CH1
PTF2/RGPIO10/FTM1CH4
PTF1/RGPIO9/FTM1CH3
PTF0/RGPIO8/FTM1CH2
PTF6/RGPIO14/FTM1FLT
PTF7/RGPIO15
Port E
PTE3/RGPIO3/FTM1CH1
PTE4/RGPIO4/SS1
PTE5/RGPIO5/MISO1
PTE2/RGPIO2/FTM1CH0
PTE1/RGPIO1/RxD1
PTE0/RGPIO0/TxD1
PTE6/RGPIO6/MOSI1
PTE7/RGPIO7/SPSCK1
Por t G
PTG3/KBI1P3/AD1P18
PTG4/KBI1P4/AD1P19
PTG5/XTAL
PTG2/KBI1P2
PTG1/KBI1P1
PTG0/KBI1P0
PTG6/EXTAL
Port H
PTH3/FTM2CH5/BKPT/AD1P23
PTH4/SPSCK2
PTH2/FTM2CH4/PSTCLK1/AD1P22
PTH1/FTM2CH3/PSTCLK0/AD1P21
PTH0/FTM2CH2/AD1P20
Port J
PTJ3/PST3
PTJ4/DDATA0
PTJ2/PST2
PTJ1/PST1
PTJ0/PST0
Por t A
PTA3/ACMP2O
PTA4/ACMP2–
PTA5/ACMP2+
PTA2
PTA1/RxCAN
PTA0/TxCAN
PTA6/AD1P16
PTA7/AD1P17
ADC
VREFH
VREFL
VDDA
VSSA
CAN
TPMCLK
FTM1
TPMCLK
SPI1
SCI1
MCG
VREG
SIM
ColdFire V1 core
Port G:
EXTAL
XTAL
Port E:
RxD1
TxD1
Port E:
SS1
SPSCK1
MOSI1
MISO1
Port F:
FTM1CH5
FTM1CH4
FTM1CH3
FTM1CH2
Port E:
FTM1CH1
FTM1CH0
TPM3
Port B:
TPM3CH1
TPM3CH0 Port A:
RxCAN
TxCAN
IIC
Port C:
SDA1
SCL1
SCI2
Port C:
RxD2
TxD2
Port B:
AD1P7–
AD1P0
Port D:
AD1P15–
AD1P8
SPI2
Port H:
SPSCK2
MOSI2
MISO2
KBI
Port G:
KBI1P4
KBI1P3
KBI1P1
Port D:
KBI1P7
KBI1P6
KBI1P5
KBI1P2
RGPIO
Port F:
RGPIO15
RGPIO14
RGPIO13
RGPIO12
RGPIO11
RGPIO10
RGPIO9
RGPIO8
Port E:
RGPIO7
RGPIO6
RGPIO5
RGPIO4
RGPIO3
RGPIO2
RGPIO1
RGPIO0
ACMP1
Port D:
ACMP1O
ACMP1–
ACMP1+
RTI
IRQ/
VREFH
VREFL
VDDA
VSSA
BKGD/MS
RESET
VDD
VSS
VSS
COP
FLASH
MCF51AC256A/B = 256 KB
OSC
DBG
FTM2
TPMCLK Port H:
FTM2CH5
FTM2CH4
FTM2CH3
FTM2CH2
Port F:
FTM2CH1
FTM2CH0
Port A:
ADP17–
ADP16
Port G:
ADP19–
ADP18
Port H:
ADP23–
ADP20
ACMP2
Port A:
ACMP2O
ACMP2–
ACMP2+
PTH6/MISO2
PTH5/MOSI2
PTJ7/DDATA3
PTJ6/DDATA2
PTJ5/DDATA1
TPMCLK
CRC
VBUS
Port J:
DDATA3-
DDATA0
PST0
Port H:
PSTCLK
BKPT
PST3-
KBI1P0
MCF51AC128A/C = 128 KB
RAM
MCF51AC256A/B = 32 KB
MCF51AC128A = 32 KB
BDM
LVD IRQ
MCF51AC128C = 16 KB
Port C:
SS2
LPO
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.7
MCF51AC256 Family Configurations
Freescale Semiconductor6
1.3 Features
Table 2 describes the functional units of the MCF51AC256 series.
Table 2. MCF51AC256 Series Functional Units
Functional Unit Function
CF1 Core (V1 ColdFire core) Executes programs and interrupt handlers
BDM (background debug module) Provides single pin debugging interface (part of the V1 ColdFire core)
DBG (debug) Provides debugging and emulation capabilities (part of the V1 ColdFire
core)
VBUS (debug visibility bus) Allows for real-time program traces (part of the V1 ColdFire core)
SIM (system integration module) Controls resets and chip level interfaces between modules
Flash (flash memory) Provides storage for program code, constants and variables
RAM (random-access memory) Provides storage for program variables
RGPIO (rapid general-purpose input/output) Allows for I/O port access at CPU clock speeds
VREG (voltage regulator) Controls power management across the device
COP (computer operating properly) Monitors a countdown timer and generates a reset if the timer is not
regularly reset by the software
LVD (low-voltage detect) Monitors internal and external supply voltage levels, and generates a reset
or interrupt when the voltages are too low
CF1_INTC (interrupt controller) Controls and prioritizes all device interrupts
ADC (analog-to-digital converter) Measures analog voltages at up to 12 bits of resolution
FTM1, FTM2 (flexible timer/pulse-width
modulators)
Provides a variety of timing-based features
TPM3 (timer/pulse-width modulator) Provides a variety of timing-based features
CRC (cyclic redundancy check) Accelerates computation of CRC values for ranges of memory
ACMP1, ACMP2 (analog comparators) Compares two analog inputs
IIC (inter-integrated circuit) Supports standard IIC communications protocol
KBI (keyboard interrupt) Provides pin interrupt capabilities
MCG (multipurpose clock generator) Provides clocking options for the device, including a phase-locked loop
(PLL) and frequency-locked loop (FLL) for multiplying slower reference
clock sources
OSC (crystal oscillator) Allows a crystal or ceramic resonator to be used as the system clock source
or reference clock for the PLL or FLL
LPO (low-power oscillator) Provides a second clock source for COP and RTI.
CAN (controller area network) Supports standard CAN communications protocol
SCI1, SCI2 (serial communications interfaces) Serial communications UARTs capable of supporting RS-232 and LIN
protocols
SPI1 (8-bit serial peripheral interfaces) Provides 8-bit 4-pin synchronous serial interface
SPI2 (16-bit serial peripheral interfaces) Provides 16-bit 4-pin synchronous serial interface with FIFO
MCF51AC256 Family Configurations
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.7
Freescale Semiconductor 7
1.3.1 Feature List
• 32-bit Version 1 ColdFire® central processor unit (CPU)
— Up to 50.33 MHz at 2.7 V – 5.5 V
— Provide 0.94 Dhrystone 2.1 DMIPS per MHz performance when running from internal RAM
(0.76 DMIPS per MHz when running from flash)
— Implements instruction set revision C (ISA_C)
• On-chip memory
— Up to 256 KB flash memory read/program/erase over full operating voltage and temperature
— Up to 32 KB static random access memory (SRAM)
— Security circuitry to prevent unauthorized access to SRAM and flash contents
• Power-Saving Modes
— Three low-power stop plus wait modes
— Peripheral clock enable register can disable clocks to unused modules, reducing currents;
allows clocks to remain enabled to specific peripherals in stop3 mode
• System protection features
— Watchdog computer operating properly (COP) reset with options to run from independent LPO
clock or bus clock
— Low-voltage detection with reset or interrupt
— Illegal opcode and illegal address detection with programmable reset or exception response
— Flash block protection
• Debug support
— Single-wire background debug interface
— Real-time debug support, with 6 hardware breakpoints (4 PC, 1 address pair and 1 data) that
can be configured into a 1- or 2-level trigger
— On-chip trace buffer provides programmable start/stop recording conditions plus support for
continuous or PC-profiling modes
— Support for real-time program (and optional partial data) trace using the debug visibility bus
• V1 ColdFire interrupt controller (CF1_INTC)
— Support of 40 peripheral I/O interrupt requests plus seven software (one per level) interrupt
requests
— Fixed association between interrupt request source and level plus priority, up to two requests
can be remapped to the highest maskable level + priority
— Unique vector number for each interrupt source
— Support for service routine interrupt acknowledge (software IACK) read cycles for improved
system performance
• Multipurpose clock generator (MCG)
— Oscillator (XOSC); loop-control Pierce oscillator; crystal or ceramic resonator range of 31.25
kHz to 38.4 kHz or 1 MHz to 16 MHz
— LPO clock as an optional independent clock source for COP and RTI
— FLL/PLL controlled by internal or external reference
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.7
MCF51AC256 Family Configurations
Freescale Semiconductor8
— Trimmable internal reference allows 0.2% resolution and 2% deviation
• Analog-to-digital converter (ADC)
— 24 analog inputs with 12 bits resolution
— Output formatted in 12-, 10- or 8-bit right-justified format
— Single or continuous conversion (automatic return to idle after single conversion)
— Operation in low-power modes for lower noise operation
— Asynchronous clock source for lower noise operation
— Automatic compare with interrupt for less-than, or greater-than or equal-to, programmable
value
— On-chip temperature sensor
• Flexible timer/pulse-width modulators (FTM)
— 16-bit Free-running counter or a counter with initial and final value. The counting can be up
and unsigned, up and signed, or up-down and unsigned
— Up to 6 channels, and each channel can be configured for input capture, output compare or
edge-aligned PWM mode, all channels can be configured for center-aligned PWM mode
– Channels can operate as pairs with equal outputs, pairs with complimentary outputs or
independent channels (with independent outputs)
– Each pair of channels can be combined to generate a PWM signal (with independent control
of both edges of PWM signal)
– Deadtime insertion is available for each complementary pair
— The load of the FTM registers which have write buffer can be synchronized; write protection
for critical registers
— Generation of the triggers to ADC (hardware trigger)
— A fault input for global fault control
— Backwards compatible with TPM
• Timer/pulse width modulator (TPM)
— 16-bit free-running or modulo up/down count operation
— Two channels, each channel may be input capture, output compare, or edge-aligned PWM
— One interrupt per channel plus terminal count interrupt
• Cyclic redundancy check (CRC) generator
— High speed hardware CRC generator circuit using 16-bit shift register
— CRC16-CCITT compliancy with x16 + x12 + x5 + 1 polynomial
— Error detection for all single, double, odd, and most multi-bit errors
— Programmable initial seed value
• Analog comparators (ACMP)
— Full rail to rail supply operation
— Selectable interrupt on rising edge, falling edge, or either rising or falling edges of comparator
output
— Option to compare to fixed internal bandgap reference voltage
— Option to allow comparator output to be visible on a pin, ACMPxO
MCF51AC256 Family Configurations
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.7
Freescale Semiconductor 9
• Inter-integrated circuit (IIC)
— Compatible with IIC bus standard
— Multi-master operation
— Software programmable for one of 64 different serial clock frequencies
— Interrupt driven byte-by-byte data transfer
— Arbitration lost interrupt with automatic mode switching from master to slave
— Calling address identification interrupt
— Bus busy detection
— 10-bit address extension
• Controller area network (CAN)
— Implementation of the CAN protocol — Version 2.0A/B
– S tandard and extended data frames
– Zero to eight bytes data length
– Programmable bit rate up to 1 Mbps
– Support for remote frames
— Five receive buffers with FIFO storage scheme
— Three transmit buffers with internal prioritization using a “local priority” concept
— Flexible maskable identifier filter supports two full-size (32-bit) extended identifier filters, four
16-bit filters, or eight 8-bit filters
— Programmable wakeup functionality with integrated low-pass filter
— Programmable loopback mode supports self-test operation
— Programmable listen-only mode for monitoring of CAN bus
— Programmable bus-off recovery functionality
— Separate signalling and interrupt capabilities for all CAN receiver and transmitter error states
(warning, error passive, bus-off)
— Internal timer for time-stamping of received and transmitted messages
• Serial communications interfaces (SCI)
— Full-duplex, standard non-return-to-zero (NRZ) format
— Double-buffered transmitter and receiver with separate enables
— Programmable baud rates (13-bit modulo divider)
— Interrupt-driven or polled operation
— Hardware parity generation and checking
— Programmable 8-bit or 9-bit character length
— Receiver wakeup by idle-line or address-mark
— Optional 13-bit break character generation / 11-bit break character detection
— Selectable transmitter output polarity
• Serial peripheral interfaces (SPI)
— Master or slave mode operation
— Full-duplex or single-wire bidirectional option
— Programmable transmit bit rate
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.7
MCF51AC256 Family Configurations
Freescale Semiconductor10
— Double-buffered transmit and receive
— Serial clock phase and polarity options
— Slave select output
— Selectable MSB-first or LSB-first shifting
— 16-bit and FIFO operations in SPI2
• Input/Output
— 69 GPIOs
— 8 keyboard interrupt pins with selectable polarity
— Hysteresis and configurable pull-up device on all input pins; Configurable slew rate and drive
strength on all output pins
— 16-bits Rapid GPIO pins connected to the processor’ s local 32-bit platform bus with set, clear,
and faster toggle functionality
1.4 Part Numbers
Table 3. Orderable Part Number Summary
Freescale Part Number Description Flash / SRAM
(Kbytes) Package Temperature
MCF51AC256AVFUE MCF51AC256 ColdFire Microcontroller with CAN 256 / 32 64 QFP –40°C to 105°C
MCF51AC256BVFUE MCF51AC256 ColdFire Microcontroller without CAN 256 / 32 64 QFP –40°C to 105°C
MCF51AC256AVLKE MCF51AC256 ColdFire Microcontroller with CAN 256 / 32 80 LQFP –40°C to 105°C
MCF51AC256BVLKE MCF51AC256 ColdFire Microcontroller without CAN 256 / 32 80 LQFP –40°C to 105°C
MCF51AC256AVPUE MCF51AC256 ColdFire Microcontroller with CAN 256 / 32 64 LQFP –40°C to 105°C
MCF51AC256BVPUE MCF51AC256 ColdFire Microcontroller without CAN 256 / 32 64 LQFP –40°C to 105°C
MCF51AC128AVFUE MCF51AC128 ColdFire Microcontroller with CAN 128 / 32 64 QFP –40°C to 105°C
MCF51AC128CVFUE MCF51AC128 ColdFire Microcontroller without CAN 128 / 16 64 QFP –40°C to 105°C
MCF51AC128AVLKE MCF51AC128 ColdFire Microcontroller with CAN 128 / 32 80 LQFP –40°C to 105°C
MCF51AC128CVLKE MCF51AC128 ColdFire Microcontroller without CAN 128 / 16 80 LQFP –40°C to 105°C
MCF51AC128AVPUE MCF51AC128 ColdFire Microcontroller with CAN 128 / 32 64 LQFP –40°C to 105°C
MCF51AC128CVPUE MCF51AC128 ColdFire Microcontroller without CAN 128 / 16 64 LQFP –40°C to 105°C
MCF51AC256ACFUE MCF51AC256 ColdFire Microcontroller with CAN 256 / 32 64 QFP –40°C to 85°C
MCF51AC256BCFUE MCF51AC256 ColdFire Microcontroller without CAN 256 / 32 64 QFP –40°C to 85°C
MCF51AC256ACLKE MCF51AC256 ColdFire Microcontroller with CAN 256 / 32 80 LQFP –40°C to 85°C
MCF51AC256BCLKE MCF51AC256 ColdFire Microcontroller without CAN 256 / 32 80 LQFP –40°C to 85°C
Package designator
Temperature range
Family
Status
Core
Pb free indicator
(V = –40C to 105C, C= –40C to 85C )
(MCF = Fully Qualified ColdFire)
MCF AC 256 XX E
Memory size designator
V51
(PCF = Product Engineering)
X
CAN Feature (A: With CAN, B/C: Without CAN)
MCF51AC256 Family Configurations
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.7
Freescale Semiconductor 11
MCF51AC256ACPUE MCF51AC256 ColdFire Microcontroller with CAN 256 / 32 64 LQFP –40°C to 85°C
MCF51AC256BCPUE MCF51AC256 ColdFire Microcontroller without CAN 256 / 32 64 LQFP –40°C to 85°C
MCF51AC256BCFGE MCF51AC256 ColdFire Microcontroller without CAN 256/32 44 LQFP –40°C to 85°C
MCF51AC128ACFUE MCF51AC128 ColdFire Microcontroller with CAN 128 / 32 64 QFP –40°C to 85°C
MCF51AC128CCFUE MCF51AC128 ColdFire Microcontroller without CAN 128 / 16 64 QFP –40°C to 85°C
MCF51AC128ACLKE MCF51AC128 ColdFire Microcontroller with CAN 128 / 32 80 LQFP –40°C to 85°C
MCF51AC128CCLKE MCF51AC128 ColdFire Microcontroller without CAN 128 / 16 80 LQFP –40°C to 85°CC
MCF51AC128ACPUE MCF51AC128 ColdFire Microcontroller with CAN 128 / 32 64 LQFP –40°C to 85°C
MCF51AC128CCPUE MCF51AC128 ColdFire Microcontroller without CAN 128 / 16 64 LQFP –40°C to 85°C
MCF51AC128CCFGE MCF51AC128 ColdFire Microcontroller without CAN 128 / 16 44 LQFP –40°C to 85°C
Table 3. Orderable Part Number Summary
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.7
MCF51AC256 Family Configurations
Freescale Semiconductor12
1.5 Pinouts and Packaging
Figure 2 shows the pinout of the 80-pin LQFP.
Figure 2. MCF51AC256 Series ColdFire Microcontroller 80-Pin LQFP
Figure 3 shows the pinout of the 64-pin LQFP and QFP.
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
80-Pin
LQFP
PTG3 / KBI1P3 / AD1P18
PTC4 / SS2
PTC5 / RxD2
PTD3 / KBI1P6 / AD1P11
IRQ / TPMCLK
PTD2 / KBI1P5 / AD1P10 / ACMP1O
RESET
VSSA
PTF0 / RGPIO8 / FTM1CH2
VDDA
PTF1 / RGPIO9 / FTM1CH3
PTD1 / AD1P9 / ACMP1–
PTF2/RGPIO10/FTM1CH4
PTD0 / AD1P8 / ACMP1+
PTF5 / RGPIO13 / FTM2CH1
PTB7 / AD1P7
PTF6 / RGPIO14 / FTM1FLT
PTB6 / AD1P6
PTJ0 / PST0
PTB5 / AD1P5
PTJ1 / PST1
PTB4 / AD1P4
PTJ2 / PST2
PTB3 / AD1P3
PTJ3 / PST3
PTB2 / AD1P2
PTE0 / RGPIO0 / TxD1
PTH3 / FTM2CH5 / BKPT / AD1P23
PTE1 / RGPIO1 / RxD1
PTH2 / FTM2CH4 / PSTCLK1 / AD1P22
PTF3/RGPIO11/FTM1CH5
PTH1 / FTM2CH3 / PSTCLK0 / AD1P21
PTF4/RGPIO12/FTM2CH0
PTC3 / TxD2
PTC2 / MCLK
PTH6 / MISO2
PTH5 / MOSI2
PTC0 / SCL1
VSS
PTG6 / EXTAL
PTJ6 / DDATA2
PTG5 / XTAL
PTJ7 / DDATA3
VREFH
PTG2 / KBI1P2
PTD7 / KBI1P7 / AD1P15
•PTA0 / TxCAN
PTD6 / FTM1CLK / AD1P14
PTD5 / AD1P13
PTD4/FTM2CLK/AD1P12
PTG0 / KBI1P0
PTG4 / KBI1P4 / AD1P19
PTG1 / KBI1P1
PTC6 / FTM2FLT
PTF7 / RGPIO15
PTE2 / RGPIO2 / FTM1CH0
PTE3 / RGPIO3 / FTM1CH1
PTH0 / FTM2CH2 / AD1P20
PTB1 / TPM3CH1 / AD1P1
PTB0 / TPM3CH0 / AD1P0
PTA7 / AD1P17
PTH4 / SPSCK2
PTC1 / SDA1
BKGD / MS
VREFL
•PTA1 / RxCAN
PTA2
PTA3 / ACMP2O
PTA4 / ACMP2–
PTA5 / ACMP2+
PTA6 / AD1P16
PTE4 / RGPIO4 / SS1
PTE5 / RGPIO5 / MISO1
VSS
VDD
PTE6 / RGPIO6 / MOSI1
PTE7 / RGPIO7 / SPSCK1
PTJ4 / DDATA0
PTJ5 / DDATA1
VDD
• TxCAN and RxCAN are not available in the
members that do not support CAN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
MCF51AC256 Family Configurations
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.7
Freescale Semiconductor 13
Figure 3. MCF51AC256 Series ColdFire Microcontroller 64-Pin QFP/LQFP
Figure 4 shows the pinout of the 44-pin LQFP.
PTF2 / RGPIO10 / FTM1CH4
2
3
4
5
6
7
8
RESET
PTF0 / RGPIO8 / FTM1CH2
PTF3 / RGPIO11 / FTM1CH5
PTF4 / RGPIO12 / FTM2CH0
PTC6 / FTM2FLT
PTF7 / RGPIO15
PTG2 / KBI1P2
PTG1 / KBI1P1
PTG0 / KBI1P0
VDD
VSS
PTE7 / RGPIO7 / SPSCK1
PTE6 / RGPIO6 / MOSI1
PTB7 / AD1P7
PTD0 / AD1P8 / ACMP1+
PTD1 / AD1P9 / ACMP1–
VDDA
VSSA
PTB1 / TPM3CH1 / AD1P1
PTB6 / AD1P6
PTD5 / AD1P13
VREFH
PTC5 / RxD2
PTG5 / XTAL
BKGD / MS
VREFL
PTG3 / KBI1P3 / AD1P18
PTD6 / FTM1CLK / AD1P14
PTD7 / KBI1P7 / AD1P15
43
42
41
40
39
38
18
19
20
21
22
23
50
51
52
53
54
55
17
32
9
PTF5/RGPIO13/FTM2CH1
10
PTF6 / RGPIO14 / FTM1FLT
11
PTE0 / RGPIO0 / TxD1
16
PTE3 / RGPIO3 / FTM1CH1
•PTA0 / TxCAN
24
•PTA1 / RxCAN
25
PTA2
26
PTA3 / ACMP2O
27
PTB5 / AD1P5
37
PTB4 / AD1P4
36
PTB3 / AD1P3
35
PTB2 / AD1P2
34
PTG6 / EXTAL
56
VSS
57
PTC0 / SCL1
58
PTC1 / SDA1
59
PTF1 / RGPIO9 / FTM1CH3
12
PTE1 / RGPIO1 / RxD1
13
14
15
PTE2 / RGPIO2 / FTM1CH0
PTA4 / ACMP2–
28
29
30
31
PTD2 / KBI1P5 / AD1P10 /ACMP1O
44
45
46
PTD3 / KBI1P6 / AD1P11
47
PTC3 / TxD2
63
62
61
PTC2 / MCLK
60
PTC4
IRQ / TPMCLK
PTE4 / RGPIO4 / SS1
PTE5 / RGPIO5 / MISO1
PTA5 / ACMP2+
PTA6 / AD1P16
PTB0 / TPM3CH0 / AD1P0
PTA7 / AD1P17
PTD4 / FTM2CLK / AD1P12
PTG4 / KBI1P4 / AD1P19
64-Pin QFP
64-Pin LQFP
1
33
48
49
64
• TxCAN and RxCAN are not available in the
members that do not support CAN
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.7
MCF51AC256 Family Configurations
Freescale Semiconductor14
Figure 4. MCF51AC256 Series ColdFire Microcontroller 44-Pin LQFP
Table 4 shows the package pin assignments.
Table 4. Pin Availability by Package Pin-Count
Pin Number Lowest <-- Priority --> Highest
80 64 44 Port Pin Alt 1 Alt 2 Alt 3
1 1 1 PTC4 SS2
222 IRQ TPMCLK
1
3 3 3 RESET
4 4 4 PTF0 RGPIO8 FTM1CH2
5 5 5 PTF1 RGPIO9 FTM1CH3
6 6 — PTF2 RGPIO10 FTM1CH4
7 7 — PTF3 RGPIO11 FTM1CH5
PTF4/RGPIO12/FTM2CH0
1
2
3
4
5
6
7
8
RESET
PTF0/RGPIO8/FTM1CH2
PTG2/KBI1P2
PTG1/KBI1P1
PTG0/KBI1P0
VDD
VSS
PTE7/RGPIO7/SPSCK1
PTE6/RGPIO6/MOSI1
PTD0/AD1P8/ACMP1+
PTD1/AD1P9/ACMP1-
VDDA
VSSA
PTB1/TPM3CH1/AD1P1
VREFH
PTC5/RxD2
PTG5/XTAL
BKGD/MS
VREFL
PTG3/KBI1P3/AD1P18
31
30
29
28
27
26
13 14 15 16 17 18
34
35
12 22
23
33
44
9
PTF5/RGPIO13/FTM2CH1
10
PTE0/RGPIO0/TxD1
11
PTE3/RGPIO3/FTM1CH1
•PTA0/TxCAN
19
•PTA1/RxCAN
20 21
PTB3/AD1P3
PTB2/AD1P2
PTG6/EXTAL
36
VSS
37
PTC0/SCL1
38
PTC1/SDA1
39
PTF1/RGPIO9/FTM1CH3
PTE1/RGPIO1/RxD1
PTE2/RGPIO2/FTM1CH0
PTD2/KBI1P5/AD1P10/ACMP1O
32 PTD3/KBI1P6/AD1P11
PTC3/TxD2
43 42 41
PTC2/MCLK
40
PTC4
IRQ/TPMCLK
PTE4/RGPIO4/SS1
PTE5/RGPIO5/MISO1
PTB0/TPM3CH0/AD1P0
44-Pin LQFP
25
24
• TxCAN and RxCAN are not available in the
members that do not support CAN
MCF51AC256 Family Configurations
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.7
Freescale Semiconductor 15
8 8 6 PTF4 RGPIO12 FTM2CH0
9 9 — PTC6 FTM2FLT
10 10 — PTF7 RGPIO15
11 11 7 PTF5 RGPIO13 FTM2CH1
12 12 — PTF6 RGPIO14 FTM1FLT
13 — — PTJ0 PST0
14 — — PTJ1 PST1
15 — — PTJ2 PST2
16 — — PTJ3 PST3
17 13 8 PTE0 RGPIO0 TxD1
18 14 9 PTE1 RGPIO1 RxD1
19 15 10 PTE2 RGPIO2 FTM1CH0
20 16 11 PTE3 RGPIO3 FTM1CH1
21 17 12 PTE4 RGPIO4 SS1
22 18 13 PTE5 RGPIO5 MISO1
23 19 14 PTE6 RGPIO6 MOSI1
24 20 15 PTE7 RGPIO7 SPSCK1
25 21 16 VSS
26 22 17 VDD
27 — — PTJ4 DDATA0
28 — — PTJ5 DDATA1
29 — — PTJ6 DDATA2
30 — — PTJ7 DDATA3
31 23 18 PTG0 KBI1P0
32 24 19 PTG1 KBI1P1
33 25 20 PTG2 KBI1P2
34 26 21 PTA0 TxCAN2
35 27 22 PTA1 RxCAN3
36 28 — PTA2
37 29 — PTA3 ACMP2O
38 30 — PTA4 ACMP2–
39 31 — PTA5 ACMP2+
40 32 — PTA6 AD1P16
41 33 — PTA7 AD1P17
42 — — PTH0 FTM2CH2 AD1P20
43 — — PTH1 FTM2CH3 PSTCLK0 AD1P21
44 — — PTH2 FTM2CH4 PSTCLK1 AD1P22
45 — — PTH3 FTM2CH5 BKPT AD1P23
46 34 23 PTB0 TPM3CH0 AD1P0
47 35 24 PTB1 TPM3CH1 AD1P1
48 36 25 PTB2 AD1P2
Table 4. Pin Availability by Package Pin-Count (continued)
Pin Number Lowest <-- Priority --> Highest
80 64 44 Port Pin Alt 1 Alt 2 Alt 3
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.7
MCF51AC256 Family Configurations
Freescale Semiconductor16
49 37 26 PTB3 AD1P3
50 38 — PTB4 AD1P4
51 39 — PTB5 AD1P5
52 40 — PTB6 AD1P6
53 41 — PTB7 AD1P7
54 42 27 PTD0 AD1P8 ACMP1+
55 43 28 PTD1 AD1P9 ACMP1–
56 44 29 VDDA
57 45 30 VSSA
58 46 31 PTD2 KBI1P5 AD1P10 ACMP1O
59 47 32 PTD3 KBI1P6 AD1P11
60 48 33 PTG3 KBI1P3 AD1P18
61 49 — PTG4 KBI1P4 AD1P19
62 50 — PTD4 FTM2CLK AD1P12
63 51 — PTD5 AD1P13
64 52 — PTD6 FTM1CLK AD1P14
65 53 — PTD7 KBI1P7 AD1P15
66 54 34 VREFH
67 55 35 VREFL
68 56 36 BKGD MS
69 57 37 PTG5 XTAL
70 58 38 PTG6 EXTAL
71 59 39 VSS
72 — — VDD
73 60 40 PTC0 SCL1
74 61 41 PTC1 SDA1
75 — — PTH4 SPCK2
76 — — PTH5 MOSI2
77 — — PTH6 MISO2
78 62 42 PTC2 MCLK
79 63 43 PTC3 TxD2
80 64 44 PTC5 RxD2
1TPMCLK, FTM1CLK, and FTM2CLK options are configured via
software; out of reset, FTM1CLK, FTM2CLK, and TPMCLK are
available to FTM1, FTM2, and TPM3 respectively.
2TxCAN is available in the member that supports CAN.
3RxCAN is available in the member that supports CAN.
Table 4. Pin Availability by Package Pin-Count (continued)
Pin Number Lowest <-- Priority --> Highest
80 64 44 Port Pin Alt 1 Alt 2 Alt 3
Electrical Characteristics
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.7
Freescale Semiconductor 17
2 Electrical Characteristics
This section contains electrical specification tables and reference timing diagrams for the MCF51AC256
microcontroller, including detailed information on power considerations, DC/AC electrical characteristics,
and AC timing specifications.
The electrical specifications are preliminary and are from previous designs or design simulations. These
specifications may not be fully tested or guaranteed at this early stage of the product life cycle. These
specifications will, however , be met for production silicon. Finalized specifications will be published after
complete characterization and device qualifications have been completed.
NOTE
The parameters specified in this data sheet supersede any values found in
the module specifications.
2.1 Parameter Classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the
customer a better understanding the following classification is used and the parameters are tagged
accordingly in the tables where appropriate:
NOTE
The classification is shown in the column labeled “C” in the parameter
tables where appropriate.
2.2 Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not
guaranteed. Stress beyond th e limits specified in Table 6 may affect device reliability or cause permanent
damage to the device. For functional operating conditions, refer to the remaining tables in this section.
This device contains circuitry protecting against damage due to high static voltage or electrical fields;
however, it is advised that normal precautions be taken to avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage level (for instance, either VSS or VDD).
Table 5. Parameter Classifications
PThose parameters are guaranteed during production testing on each individual device.
CThose parameters are achieved by the design characterization by measuring a statistically relevant
sample size across process variations.
T
Those parameters are achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted. All values shown in the typical column are within this
category.
DThose parameters are derived mainly from simulations.
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.7
Electrical Characteristics
Freescale Semiconductor18
2.3 Thermal Characteristics
This section provides information about operating temperature range, power dissipation, and package
thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in
on-chip logic and it is user-determined rather than being controlled by the MCU design. In order to take
PI/O into account in power calculations, determine the difference between actual pin voltage and VSS or
VDD and multiply by the pin current for each I/O pin. Except in cases of unusually high pin current (heavy
loads), the difference between pin voltage and VSS or VDD will be very small.
Table 6. Absolute Maximum Ratings
Rating Symbol Value Unit
Supply voltage VDD –0.3 to 5.8 V
Input voltage VIn –0.3 to VDD + 0.3 V
Instantaneous maximum current
Single pin limit (applies to all port pins)1,2,3
1Input must be current limited to the value specified. To determine the value of the required
current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp
voltages, then use the larger of the two resistance values.
2All functional non-supply pins are internally clamped to VSS and VDD.
3Power supply must maintain regulation within operating VDD range during instantaneous and
operating maximum current conditions. If positive injection current (VIn > VDD) is greater than
IDD, the injection current may flow out of VDD and could result in external power supply going
out of regulation. Ensure external VDD load will shunt current greater than maximum injection
current. This will be the greatest risk when the MCU is not consuming power. Examples are: if
no system clock is present, or if the clock rate is very low which would reduce overall power
consumption.
ID25 mA
Maximum current into VDD IDD 120 mA
Storage temperature Tstg –55 to 150 C
Table 7. Thermal Characteristics
Rating Symbol Value Unit
Operating temperature range (packaged) TA–40 to 105 C
Maximum junction temperature TJ150 C
Thermal resistance 1,2,3,4
80-pin LQFP
1s
2s2p
64-pin LQFP
1s
2s2p
64-pin QFP
1s
2s2p
44-pin LQFP
1s
2s2p
JA
51
38
59
41
50
36
67
45
C/W
Electrical Characteristics
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.7
Freescale Semiconductor 19
The average chip-junction temperature (TJ) in C can be obtained from:
TJ = TA + (PD JA)Eqn. 1
where: TA = Ambient temperature, C
JA = Package thermal resistance, junction-to-ambient, C/W
PD = Pint PI/O
Pint = IDD VDD, Watts — chip internal power
PI/O = Power dissipation on input and output pins — user determined
For most applications, PI/O  Pint and can be neglected. An approximate relationship between PD and TJ
(if PI/O is neglected) is:
PD = K (TJ + 273C) Eqn. 2
Solving Equation 1 and Equation 2 for K gives:
K = PD (TA + 273C) + JA (PD)2Eqn. 3
where K is a constant pertaining to the particular part. K can be determined from Equation 3 by measuring
PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by
solving Equation 1 and Equation 2 iteratively for any value of TA.
2.4 Electrostatic Discharge (ESD) Protection Characteristics
Although damage from static discharge is much less common on these devices than on early CMOS
circuits, normal handling precautions should be used to avoid exposure to static discharge. Qualification
tests are performed to ensure that these devices can withstand exposure to reasonable levels of static
without suffering any permanent damage.
All ESD testing is in conformity with CDF-AEC-Q00 Stress Test Qualification for Automotive Grade
Integrated Circuits. (http://www.aecouncil.com/) This device was qualified to AEC-Q100 Rev E.
A device is considered to have failed if, after exposure to ESD pulses, the device no longer meets the
device specification requirements. Complete dc parametric and functional testing is performed per the
1Junction temperature is a function of die size, on-chip power dissipation, package thermal
resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation
of other components on the board, and board thermal resistance
2Junction to Ambient Natural Convection
31s — Single layer board, one signal layer
42s2p — Four layer board, 2 signal and 2 power layers
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.7
Electrical Characteristics
Freescale Semiconductor20
applicable device specification at room temperature followed by hot temperature, unless specified
otherwise in the device specification.
2.5 DC Characteristics
This section includes information about power supply requirements, I/O pin characteristics, and power
supply current in various operating modes.
Table 8. ESD and Latch-up Test Conditions
Model Description Symbol Value Unit
Human body Series resistance R1 1500
Storage capacitance C 100 pF
Number of pulse per pin — 3
Charge device
model
Series resistance R1 0
Storage capacitance C 0 pF
Number of pulse per pin — 3 —
Latch-up Minimum input voltage limit — –2.5 V
Maximum input voltage limit — 7.5 V
Table 9. ESD and Latch-Up Protection Characteristics
Num Rating Symbol Min Max Unit
1 Human body model (HBM) VHBM ±2000 — V
2 Charge device model (CDM) VCDM ±500 — V
3 Latch-up current at TA = 85 CI
LAT ±100 — mA
Table 10. DC Characteristics
Num C Parameter Symbol Min Typical1Max Unit
1 — Operating voltage 2.7 — 5.5 V
2P
Output high voltage — Low drive (PTxDSn = 0)
5 V, ILoad = –4 mA
3 V, ILoad = –2 mA
5 V, ILoad = –2 mA
3 V, ILoad = –1 mA VOH
VDD – 1.5
VDD – 1.5
VDD – 0.8
VDD – 0.8
—
—
—
—
—
—
—
—V
Output high voltage — High drive (PTxDSn = 1)
5 V, ILoad = –15 mA
3 V, ILoad = –8 mA
5 V, ILoad = –8 mA
3 V, ILoad = –4 mA
VDD – 1.5
VDD – 1.5
VDD – 0.8
VDD – 0.8
—
—
—
—
—
—
—
—
Electrical Characteristics
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.7
Freescale Semiconductor 21
3P
Output low voltage — Low Drive (PTxDSn = 0)
5 V, ILoad = 4 mA
3 V, ILoad = 2 mA
5 V, ILoad = 2 mA
3 V, ILoad = 1 mA VOL
——
1.5
1.5
0.8
0.8 V
Output low voltage — High Drive (PTxDSn = 1)
5 V, ILoad = 15 mA
3 V, ILoad = 8 mA
5 V, ILoad = 8 mA
3 V, ILoad = 4 mA
——
1.5
1.5
0.8
0.8
4C
Output high current — Max total IOH for all ports
5V
3V
IOHT ——
100
60
mA
5C
Output low current — Max total IOL for all ports
5 V
3 V
IOLT ——
100
60
mA
6 P Input high voltage; all digital inputs VIH 0.65 VDD ——V
P Input low voltage; all digital inputs VIL — — 0.35 VDD V7
D Input hysteresis; all digital inputs Vhys 0.06 VDD ——mV8
9 P Input leakage current; input only pins2|IIn|— 0.1 1A
10 P High impedance (off-state) leakage current2|IOZ|— 0.1 1A
11 P Internal pullup resistors3RPU 20 45 65 k
12 P Internal pulldown resistors4RPD 20 45 65 k
13 C Input capacitance; all non-supply pins CIn —— 8pF
14 P POR rearm voltage VPOR 0.9 1.4 2.0 V
15 D POR rearm time tPOR 10 — — s
16 P
Low-voltage detection threshold —
high range
VDD falling
VDD rising
VLVD H 4.2
4.27
4.35
4.4
4.5
4.6
V
P
Low-voltage detection threshold —
low range
VDD falling
VDD rising
VLVD L 2.48
2.5
2.68
2.7
2.7
2.72
V17
P
Low-voltage warning threshold —
high range
VDD falling
VDD rising
VLVW H 4.2
4.27
4.4
4.45
4.5
4.6
V18
19 P
Low-voltage warning threshold
low range
VDD falling
VDD rising
VLVW L 2.48
2.5
2.68
2.7
2.7
2.72
V
20 T
Low-voltage inhibit reset/recover hysteresis
5 V
3 V
Vhys —100
60 —mV
21 D RAM retention voltage VRAM —0.61.0V
Table 10. DC Characteristics (continued)
Num C Parameter Symbol Min Typical1Max Unit
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.7
Electrical Characteristics
Freescale Semiconductor22
Figure 5. Typical IOH vs. VDD–VOH at VDD = 3 V (Low Drive, PTxDSn = 0)
22 D
DC injection current5 6 7 8 (single pin limit)
VIN >VDD
VIN <VSS
IIC
0
0—2
–0.2
mA
DC injection current (Total MCU limit, includes sum of all
stressed pins)
VIN >VDD
VIN <VSS
0
0
—25
–5
mA
1Typical values are based on characterization data at 25C unless otherwise stated.
2Measured with VIn = VDD or VSS.
3Measured with VIn = VSS.
4Measured with VIn = VDD.
5Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current
conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result
in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum injection
current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or
if clock rate is very low (which would reduce overall power consumption).
6All functional non-supply pins are internally clamped to VSS and VDD.
7Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate
resistance values for positive and negative clamp voltages, then use the larger of the two values.
8The RESET pin does not have a clamp diode to VDD. Do not drive this pin above VDD.
Table 10. DC Characteristics (continued)
Num C Parameter Symbol Min Typical1Max Unit
–5.0E-3
–4.0E-3
–3.0E-3
–2.0E-3
–1.0E-3
000E+0 0 0.3 0.5 0.8 0.9 1.2 1.5
VDD–VOH (V)
VSupply–VOH
Average of IOH
IOH (A)
25C
–6.0E-3
105C
-40C
Electrical Characteristics
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.7
Freescale Semiconductor 23
Figure 6. Typical IOH vs. VDD–VOH at VDD = 3 V (High Drive, PTxDSn = 1)
Figure 7. Typical IOH vs. VDD–VOH at VDD = 5 V (Low Drive, PTxDSn = 0)
–20.0E-3
–18.0E-3
–16.0E-3
–14.0E-3
–12.0E-3
–10.0E-3
–8.0E-3
–6.0E-3
–4.0E-3
–2.0E-3
000E+0
0 0.3 0.5 0.8 0.9 1.2 1.5
VSupply–VOH
VDD–VOH (V)
Average of IOH
IOH (A)
25C
105C
-40C
–5.0E-3
–4.0E-3
–3.0E-3
–2.0E-3
–1.0E-3
000E+0 0.00 0.30
Average of IOH
–6.0E-3
–7.0E-3
0.50 0.80 1.00 1.30 2.00
VDD–VOH (V)
VSupply–VOH
IOH (A)
25C
105C
-40C
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.7
Electrical Characteristics
Freescale Semiconductor24
Figure 8. Typical IOH vs. VDD–VOH at VDD = 5 V (High Drive, PTxDSn = 1)
Electrical Characteristics
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.7
Freescale Semiconductor 25
2.6 Supply Current Characteristics
Table 11. Supply Current Characteristics
Num C Parameter Symbol VDD (V) Typical1Max2Unit
1T
Run supply current measured at
FEI mode, all modules off,
system clock at:
2 MHz
RIDD
52.27 —
mA
3.3 2.24 —
4 MHz 53.67 —
3.3 3.64 —
8 MHz 56.55 —
3.3 6.54 —
16 MHz 5 11.90 —
3.3 11.85 —
2T
Run supply current measured at
FEI mode, all modules on,
system clock at:
2 MHz 53.28 —
3.3 3.26 —
4 MHz 54.33 —
3.3 4.32 —
8 MHz 58.17 —
3.3 8.05 —
16 MHz 514.8 —
3.3 14.74 —
3T
Run supply current measured at
FBE mode, all modules off
(RANGE = 1, HGO = 0), system
clock at:
2 MHz 53.28 —
3.3 3.26 —
4 MHz 54.69 —
3.3 4.67 —
8 MHz 57.48 —
3.3 7.46 —
16 MHz 5 13.10 —
3.3 13.07 —
4T
Run supply current measured at
FBE mode, all modules on
(RANGE = 1, HGO = 0), system
clock at:
2 MHz 53.64 —
3.3 3.63 —
4 MHz 55.38 —
3.3 5.35 —
8 MHz 58.65 —
3.3 8.64 —
16 MHz 5 15.55 —
3.3 15.40 —
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.7
Electrical Characteristics
Freescale Semiconductor26
5C
Wait mode supply3 current measured at
(CPU clock = 2 MHz, fBus = 1 MHz)
WIDD
51.3 2
mA
31.29 2
6C
Wait mode supply3 current measured at
(CPU clock = 16 MHz, fBus = 8 MHz)
55.11 8 mA
35.1 8
7C
Wait mode supply3 current measured at
(CPU clock = 50 MHz, fBus = 25 MHz)
5 15.24 25 mA
315.2 25
8C
Stop2 mode supply current
–40 C
25 C
120 C
–40 C
25 C
120C
S2IDD
51.402.5
2.5
200
A
31.162.5
2.5
200
A
9C
Stop3 mode supply current
–40 C
25 C
120C
–40 C
25 C
120 C
S3IDD
51.602.5
2.5
220
A
31.35
2.5
2.5
220
A
10 C RTI adder to stop2 or stop33, 25 C S23IDDRTI
5300 nA
3300 nA
11 C Adder to stop3 for oscillator enabled4
(ERCLKEN =1 and EREFSTEN = 1) S3IDDOSC 5, 3 5 A
1Typicals are measured at 25 C.
2Values given here are preliminary estimates prior to completing characterization.
3Most customers are expected to find that auto-wakeup from stop2 or stop3 can be used instead of the higher current wait
mode.
4Values given under the following conditions: low range operation (RANGE = 0), low power mode (HGO = 0).
Table 11. Supply Current Characteristics (continued)
Num C Parameter Symbol VDD (V) Typical1Max2Unit
Electrical Characteristics
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.7
Freescale Semiconductor 27
Figure 9. Typical Run IDD vs. System Clock Freq. for FEI and FBE Modes
2.7 Analog Comparator (ACMP) Electricals
Table 12. Analog Comparator Electrical Specifications
Num C Rating Symbol Min Typical Max Unit
1 — Supply voltage VDD 2.7 — 5.5 V
2 T Supply current (active) IDDAC —2035A
3 D Analog input voltage VAIN VSS – 0.3 — VDD V
4 D Analog input offset voltage VAIO —2040mV
5 D Analog comparator hysteresis VH3.0 6.0 20.0 mV
6 D Analog input leakage current IALKG ——1.0A
7 D Analog comparator initialization delay tAINIT ——1.0s
8P
Bandgap voltage reference
factory trimmed at VDD = 5.3248 V, Temp = 25 CV
BG 1.18 1.20 1.21 V
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.7
Electrical Characteristics
Freescale Semiconductor28
2.8 ADC Characteristics
Table 13. 5 Volt 12-bit ADC Operating Conditions
Num C Characteristic Conditions Symb Min Typical1
1Typical values assume VDDA = 5.0 V, Temp = 25 C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.
Max Unit Comment
1
D
Supply voltage
Absolute VDDA 2.7 — 5.5 V
DDelta to VDD
(VDD – VDDA)2
2DC potential difference.
VDDA –100 0 100 mV
2 D Ground voltage Delta to VSS
(VSS – VSSA)2VSSA –100 0 100 mV
3D
Reference
voltage high VREFH 2.7 VDDA VDDA V
4D
Reference
voltage low VREFL VSSA VSSA VSSA V
5 D Input voltage VADIN VREFL —V
REFH V
6C
Input
capacitance CADIN —4.55.5pF
7C
Input
resistance RADIN —3 5k
8
C
Analog source
resistance
12-bit mode
fADCK > 4MHz
fADCK < 4MHz
RAS
—
—
—
—
2
5
kExternal
to MCUC
10-bit mode
fADCK > 4MHz
fADCK < 4MHz
—
—
—
—
5
10
C8-bit mode (all valid
fADCK)—— 10
9
DADC
conversion
clock
frequency
High speed
(ADLPC = 0)
fADCK
0.4 — 8.0
MHz
DLow power
(ADLPC = 1) 0.4 — 4.0
Electrical Characteristics
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.7
Freescale Semiconductor 29
Figure 10. ADC Input Impedance Equivalency Diagram
Table 14. 5 Volt 12-bit ADC Characteristics (VREFH = VDDA, VREFL = VSSA)
Num C Characteristic Conditions Symb Min Typical1Max Unit Comment
1T
Supply current
ADLPC = 1
ADLSMP = 1
ADCO = 1
IDDA —133 —A
2T
Supply current
ADLPC = 1
ADLSM = 0
ADCO = 1
IDDA —218 —A
3T
Supply current
ADLPC = 0
ADLSMP = 1
ADCO = 1
IDDA —327 —A
4D
Supply current
ADLPC = 0
ADLSMP = 0
ADCO = 1
IDDA —0.582 1 mA
5 T Supply current Stop, reset, module off IDDA —0.011 1 A
6P
ADC
asynchronous
clock source
High speed (ADLPC = 0)
fADACK
23.3 5
MHz tADACK =
1/fADACK
Low power (ADLPC = 1) 1.25 2 3.3
+
–
+
–
V
AS
R
AS
C
AS
V
ADIN
Z
AS
Pad
leakage
due to
input
protection
Z
ADIN
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
R
ADIN
ADC SAR
ENGINE
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
INPUT PIN
R
ADIN
C
ADIN
INPUT PIN
R
ADIN
INPUT PIN
R
ADIN
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.7
Electrical Characteristics
Freescale Semiconductor30
7P
Conversion
time (including
sample time)
Short sample (ADLSMP = 0)
tADC
—20 —
ADCK
cycles
See
Ta b l e 1 0
for
conversion
time
variances
Long sample (ADLSMP = 1) — 40 —
8TSample time
Short sample (ADLSMP = 0)
tADS
—3.5 —
ADCK
cycles
Long sample (ADLSMP = 1) — 23.5 —
9
TTot a l
unadjusted
error
12-bit mode
ETUE
—3.0 —
LSB2
Includes
quantizatio
n
P 10-bit mode — 12.5
T 8-bit mode — 0.5 1.0
10
T
Differential
non-linearity
12-bit mode
DNL
—1.75 —
LSB2
P 10-bit mode3—0.5 1.0
T 8-bit mode3—0.3 0.5
11
T
Integral
non-linearity
12-bit mode
INL
—1.5 —
LSB2
T 10-bit mode — 0.5 1.0
T 8-bit mode — 0.3 0.5
12
T
Zero-scale
error
12-bit mode
EZS
—1.5 —
LSB2VADIN =
VSSA
P 10-bit mode — 0.5 1.5
T 8-bit mode — 0.5 0.5
13
T
Full-scale error
12-bit mode
EFS
—1—
LSB2VADIN =
VDDA
P 10-bit mode — 0.5 1
T 8-bit mode — 0.5 0.5
14 D Quantization
error
12-bit mode
EQ
— –1 to 0 —
LSB2
10-bit mode — — 0.5
8-bit mode — — 0.5
15 D Input leakage
error
12-bit mode
EIL
—1—
LSB2
Pad
leakage4 *
RAS
10-bit mode — 0.2 2.5
8-bit mode — 0.1 1
16 D Temp sensor
voltage 25CV
TEMP25 —1.396 — V
17 D Temp sensor
slope
–40 C–25 C
m
—3.266 —
mV/C
25 C–85 C—3.638—
1Typical values assume VDDA = 5.0 V, Temp = 25 C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for reference only
and are not tested in production.
21 LSB = (VREFH – VREFL)/2N.
Table 14. 5 Volt 12-bit ADC Characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Num C Characteristic Conditions Symb Min Typical1Max Unit Comment
Electrical Characteristics
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.7
Freescale Semiconductor 31
2.9 External Oscillator (XOSC) Characteristics
3Monotonicity and No-Missing-Codes guaranteed in 10-bit and 8-bit modes
4Based on input pad leakage current. Refer to pad electricals.
Table 15. Oscillator Electrical Specifications (Temperature Range = –40 to 105 C Ambient)
Num C Rating Symbol Min Typical1
1Data in Typical column was characterized at 5.0 V, 25 C or is typical recommended value.
Max Unit
1C
Oscillator crystal or resonator (EREFS = 1, ERCLKEN = 1)
Low range (RANGE = 0)
High range (RANGE = 1) FEE or FBE mode2
High range (RANGE = 1) PEE or PBE mode3
High range (RANGE = 1, HGO = 1) BLPE mode
High range (RANGE = 1, HGO = 0) BLPE mode
2When MCG is configured for FEE or FBE mode, input clock source must be divisible using RDIV to within the range of
31.25 kHz to 39.0625 kHz.
3When MCG is configured for PEE or PBE mode, input clock source must be divisible using RDIV to within the range of 1 MHz
to 2 MHz.
flo
fhi-fll
fhi-pll
fhi-hgo
fhi-lp
32
1
1
1
1
—
—
—
—
—
38.4
5
16
16
8
kHz
MHz
MHz
MHz
MHz
2 — Load capacitors C1
C2
See crystal or resonator
manufacturer’s recommendation.
3—
Feedback resistor
Low range (32 kHz to 38.4 kHz)
High range (1 MHz to 16 MHz)
RF10
1M
4—
Series resistor
Low range, low gain (RANGE = 0, HGO = 0)
Low range, high gain (RANGE = 0, HGO = 1)
High range, low gain (RANGE = 1, HGO = 0)
High range, high gain (RANGE = 1, HGO = 1)
8 MHz
MHz
MHz
RS
—
—
—
—
—
—
0
100
0
0
0
0
—
—
—
0
10
20
k
5T
Crystal start-up time 4
Low range, low gain (RANGE = 0, HGO = 0)
Low range, high gain (RANGE = 0, HGO = 1)
High range, low gain (RANGE = 1, HGO = 0)5
High range, high gain (RANGE = 1, HGO = 1)5
4This parameter is characterized and not tested on each device. Proper PC board layout procedures must be followed to
achieve specifications.
54 MHz crystal
tCSTL-LP
tCSTL-HGO
tCSTH-LP
tCSTH-HGO
—
—
—
—
200
400
5
15
—
—
—
—
ms
6T
Square wave input clock frequency (EREFS = 0, ERCLKEN =
1)
FEE or FBE mode 2
PEE or PBE mode 3
BLPE mode
fextal 0.03125
1
0
—
—
—
5
16
40
MHz
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.7
Electrical Characteristics
Freescale Semiconductor32
2.10 MCG Specifications
Table 16. MCG Frequency Specifications (Temperature Range = –40 to 105 C Ambient)
Num C Rating Symbol Min Typical1Max Unit
1C
Internal reference frequency — factory trimmed at
VDD = 5 V and temperature = 25 Cfint_ft — 32.768 — kHz
2 C Average internal reference frequency — untrimmed fint_ut 31.25 — 39.0625 kHz
3 T Internal reference startup time tirefst —60 100s
4
CDCO output frequency
range — untrimmed 2
Low range (DRS=00)
fdco_ut
16 — 20
MHzC Mid range (DRS=01) 32 — 40
C High range (DRS=10) 48 — 60
5
PDCO output frequency2
reference =32768Hz
and DMX32 = 1
Low range (DRS=00)
fdco_DMX32
— 16.82 —
MHzP Mid range (DRS=01) — 33.69 —
P High range (DRS=10) — 50.48 —
6D
Resolution of trimmed DCO output frequency at fixed
voltage and temperature (using FTRIM) fdco_res_t —0.1 0.2 %fdco
7D
Resolution of trimmed DCO output frequency at fixed
voltage and temperature (not using FTRIM) fdco_res_t —0.2 0.4 %fdco
8D
Total deviation of trimmed DCO output frequency over
voltage and temperature fdco_t —0.5
–1.0 2%f
dco
9D
Total deviation of trimmed DCO output frequency over
fixed voltage and temperature range of 0–70 Cfdco_t —0.5 1%f
dco
10 D FLL acquisition time3tfll_acquire —— 1 ms
11 D PLL acquisition time4tpll_acquire —— 1 ms
12 D Long term jitter of DCO output clock (averaged over
2ms interval) 5CJitter —0.02 0.2%f
dco
13 D VCO operating frequency fvco 7.0 — 55.0 MHz
16 D Jitter of PLL output clock measured over 625 ns6fpll_jitter_625ns —0.566
6—%f
pll
17 D Lock entry frequency tolerance 7Dlock 1.49 — 2.98 %
MCU
EXTAL XTAL
Crystal or Resonator
R
S
C2
RF
C1
Electrical Characteristics
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.7
Freescale Semiconductor 33
o
2.11 AC Characteristics
This section describes ac timing characteristics for each peripheral system.
18 D Lock exit frequency tolerance 8Dunl 4.47 — 5.97 %
19 D Lock time — FLL tfll_lock ——
tfll_acquire+
1075(1/fint_t)
s
20 D Lock time — PLL tpll_lock ——
tpll_acquire+
1075(1/fpll_ref)
s
21 D
Loss of external clock minimum frequency —
RANGE = 0 floc_low (3/5) fint — — kHz
1Data in Typical column was characterized at 5.0 V, 25 C or is typical recommended value.
2The resulting bus clock frequency must not exceed the maximum specified bus clock frequency of the device.
3This specification applies when the FLL reference source or reference divider is changed, trim value changed or changing from
FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this
specification assumes it is already running.
4This specification applies when the PLL VCO divider or reference divider is changed, or changing from PLL disabled (BLPE,
BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes it is already
running.
5Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBUS.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the FLL circuitry via VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage for
a given interval.
6625 ns represents 5 time quanta for CAN applications, under worst case conditions of 8 MHz CAN bus clock, 1 Mbps CAN bus
speed, and 8 time quanta per bit for bit time settings. 5 time quanta is the minimum time between a synchronization edge and
the sample point of a bit using 8 time quanta per bit.
7Below Dlock minimum, the MCG enters lock. Above Dlock maximum, the MCG will not enter lock. But if the MCG is already in
lock, then the MCG may stay in lock.
8Below Dunl minimum, the MCG will not exit lock if already in lock. Above Dunl maximum, the MCG is guaranteed to exit lock.
Table 16. MCG Frequency Specifications (continued)(Temperature Range = –40 to 105 C Ambient)
Num C Rating Symbol Min Typical1Max Unit
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.7
Electrical Characteristics
Freescale Semiconductor34
2.11.1 Control Timing
Figure 11. Reset Timing
Figure 12. IRQ/KBIPx Timing
Table 17. Control Timing
Num C Parameter Symbol Min Typical1
1Typical values are based on characterization data at VDD = 5.0 V, 25 C unless otherwise stated.
Max Unit
1 D Bus frequency (tcyc = 1/fBus)f
Bus dc — 24 MHz
2 D Internal low-power oscillator period tLPO 800 — 1500 s
3D
External reset pulse width2
(tcyc = 1/fSelf_reset)
2This is the shortest pulse that is guaranteed to be recognized as a reset pin request. Shorter pulses are not guaranteed to
override reset requests from internal sources.
textrst 100 — — ns
4 D Reset low drive trstdrv 66 tcyc ——ns
5 D Active background debug mode latch setup time tMSSU 500 — — ns
6 D Active background debug mode latch hold time tMSH 100 — — ns
7D
IRQ pulse width
Asynchronous path2
Synchronous path3
3This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case.
tILIH, tIHIL
100
1.5 tcyc
——ns
8D
KBIPx pulse width
Asynchronous path2
Synchronous path3tILIH, tIHIL
100
1.5 tcyc
——ns
9D
Port rise and fall time (load = 50 pF)4
Slew rate control disabled (PTxSE = 0), Low Drive
Slew rate control enabled (PTxSE = 1), Low Drive
Slew rate control disabled (PTxSE = 0), Low Drive
Slew rate control enabled (PTxSE = 1), Low Drive
4Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range –40 C to 105 C.
tRise, tFall
—
—
—
—
11
35
40
75
—ns
textrst
RESET PIN
tIHIL
IRQ/KBIPx
tILIH
IRQ/KBIPx
Electrical Characteristics
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.7
Freescale Semiconductor 35
2.11.2 Timer (TPM/FTM) Module Timing
Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that
can be used as the optional external source to the timer counter. These synchronizers operate from the
current bus rate clock.
Figure 13. Timer External Clock
Figure 14. Timer Input Capture Pulse
2.11.3 MSCAN
Table 18. TPM/FTM Input Timing
NUM C Function Symbol Min Max Unit
1—
External clock frequency fTPMext DC fBus/4 MHz
2—
External clock period tTPMext 4—
tcyc
3D
External clock high time tclkh 1.5 — tcyc
4D
External clock low time tclkl 1.5 — tcyc
5D
Input capture pulse width tICPW 1.5 — tcyc
Table 19. MSCAN Wake-Up Pulse Characteristics
Num C Parameter Symbol Min Typical1
1Typical values are based on characterization data at VDD = 5.0 V, 25 C unless otherwise stated.
Max Unit
1 D MSCAN wake-up dominant pulse filtered tWUP —— 2s
2 D MSCAN wake-up dominant pulse pass tWUP 5—5s
tTPMext
tclkh
tclkl
TPMxCLK
tICPW
TPMxCHn
tICPW
TPMxCHn
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.7
Electrical Characteristics
Freescale Semiconductor36
2.12 SPI Characteristics
Table 20 and Figure 15 through Figure 18 describe the timing requirements for the SPI system.
Table 20. SPI Timing
No. C Function Symbol Min Max Unit
—D
Operating frequency
Master
Slave
fop fBus/2048
0
fBus/2
fBus/4
Hz
1D
SPSCK period
Master
Slave
tSPSCK 2
4
2048
—
tcyc
tcyc
2D
Enable lead time
Master
Slave
tLead 12
1
—
—
tSPSCK
tcyc
3D
Enable lag time
Master
Slave
tLag 12
1
—
—
tSPSCK
tcyc
4D
Clock (SPSCK) high or low time
Master
Slave
tWSPSCK tcyc –30
tcyc – 30
1024 tcyc
—
ns
ns
5D
Data setup time (inputs)
Master
Slave
tSU 15
15
—
—
ns
ns
6D
Data hold time (inputs)
Master
Slave
tHI 0
25
—
—
ns
ns
7 D Slave access time ta—1t
cyc
8 D Slave MISO disable time tdis —1t
cyc
9D
Data valid (after SPSCK edge)
Master
Slave
tv—
—
25
25
ns
ns
10 D
Data hold time (outputs)
Master
Slave
tHO 0
0
—
—
ns
ns
11 D
Rise time
Input
Output
tRI
tRO
—
—
tcyc – 25
25
ns
ns
12 D
Fall time
Input
Output
tFI
tFO
—
—
tcyc – 25
25
ns
ns
Electrical Characteristics
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.7
Freescale Semiconductor 37
Figure 15. SPI Master Timing (CPHA = 0)
Figure 16. SPI Master Timing (CPHA =1)
SPSCK
(OUTPUT)
SPSCK
(OUTPUT)
MISO
(INPUT)
MOSI
(OUTPUT)
SS1
(OUTPUT)
MSB IN2
BIT 6 . . . 1
LSB IN
MSB OUT2LSB OUT
BIT 6 . . . 1
(CPOL = 0)
(CPOL = 1)
NOTES:
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
1. SS output mode (DDS7 = 1, SSOE = 1).
1
23
4
56
910
11
12
4
9
SPSCK
(OUTPUT)
SPSCK
(OUTPUT)
MISO
(INPUT)
MOSI
(OUTPUT)
MSB IN(2)
BIT 6 . . . 1
LSB IN
MASTER MSB OUT(2) MASTER LSB OUT
BIT 6 . . . 1
PORT DATA
(CPOL = 0)
(CPOL = 1)
PORT DATA
SS(1)
(OUTPUT)
1. SS output mode (DDS7 = 1, SSOE = 1).
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
NOTES:
2
1
12 11 3
4 4 11 12
56
910
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.7
Electrical Characteristics
Freescale Semiconductor38
Figure 17. SPI Slave Timing (CPHA = 0)
Figure 18. SPI Slave Timing (CPHA = 1)
2.13 Flash Specifications
This section provides details about program/erase times and program-erase endurance for the Flash
memory.
Program and erase operations do not require any special power sources other than the normal VDD supply.
For more detailed information about program/erase operations, see Chapter 4, “Memory.”
SPSCK
(INPUT)
SPSCK
(INPUT)
MOSI
(INPUT)
MISO
(OUTPUT)
SS
(INPUT)
MSB IN
BIT 6 . . . 1
LSB IN
MSB OUT SLAVE LSB OUT
BIT 6 . . . 1
(CPOL = 0)
(CPOL = 1)
NOTE:
SLAVE SEE
NOTE
1. Not defined but normally MSB of character just received
1
2
3
4
56
7
8
910
11
12
411 12
10
SPSCK
(INPUT)
SPSCK
(INPUT)
MOSI
(INPUT)
MISO
(OUTPUT)
MSB IN
BIT 6 . . . 1
LSB IN
MSB OUT SLAVE LSB OUT
BIT 6 . . . 1
SEE
(CPOL = 0)
(CPOL = 1)
SS
(INPUT)
NOTE:
SLAVE
NOTE
1. Not defined but normally LSB of character just received
1
2
3
4
56
7
8
910
11
12
411 12
Electrical Characteristics
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.7
Freescale Semiconductor 39
2.14 EMC Performance
Electromagnetic compatibility (EMC) performance is highly dependant on the environment in which the
MCU resides. Board design and layout, circuit topology choices, location and characteristics of external
components as well as MCU software operation all play a significant role in EMC performance. The
system designer should consult Freescale applications notes such as AN2321, AN1050, AN1263,
AN2764, and AN1259 for advice and guidance specifically targeted at optimizing EMC performance.
2.14.1 Radiated Emissions
Microcontroller radiated RF emissions are measured from 150 kHz to 1 GHz using the TEM/GTEM Cell
method in accordance with the IEC 61967-2 and SAE J1752/3 standards. The measurement is performed
with the microcontroller installed on a custom EMC evaluation board while running specialized EMC test
software. The radiated emissions from the microcontroller are measured in a TEM cell in two package
orientations (North and East). For more detailed information concerning the evaluation results, conditions
and setup, please refer to the EMC Evaluation Report for this device.
Table 21. Flash Characteristics
Num C Characteristic Symbol Min Typical1
1Typical values are based on characterization data at VDD = 5.0 V, 25 C unless otherwise stated.
Max Unit
1 — Supply voltage for program/erase Vprog/erase 2.7 — 5.5 V
2 — Supply voltage for read operation VRead 2.7 — 5.5 V
3 — Internal FCLK frequency2
2The frequency of this clock is controlled by a software setting.
fFCLK 150 — 200 kHz
4 — Internal FCLK period (1/FCLK) tFcyc 5 — 6.67 s
5 — Byte program time (random location)2tprog 9t
Fcyc
6 — Byte program time (burst mode)2tBurst 4t
Fcyc
7 — Page erase time3
3These values are hardware state machine controlled. User code does not need to count cycles. This information
supplied for calculating approximate time to program and erase.
tPage 4000 tFcyc
8 — Mass erase time2tMass 20,000 tFcyc
9C
Program/erase endurance4
TL to TH = –40 C to 105 C
T = 25 C
4Typical endurance for flash was evaluated for this product family on the 9S12Dx64. For additional information on
how Freescale Semiconductor defines typical endurance, please refer to Engineering Bulletin EB619/D, Typ i cal
Endurance for Nonvolatile Memory.
— 10,000
—
—
100,000
—
—
cycles
10 C Data retention5
5Typical data retention values are based on intrinsic capability of the technology measured at high temperature and
de-rated to 25C using the Arrhenius equation. For additional information on how Freescale Semiconductor defines
typical data retention, please refer to Engineering Bulletin EB618/D, Typical Data Retention for Nonvolatile Memory.
tD_ret 15 100 — years
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.7
Mechanical Outline Drawings
Freescale Semiconductor40
3 Mechanical Outline Drawings
Table 22 provides the available package types and their document numbers. The latest package
outline/mechanical drawings are available on the MCF51AC256 Series Product Summary pages at
http://www.freescale.com.
To view the latest drawing, either:
• Click on the appropriate link in Table 22, or
• Open a browser to the FreescaleÆ website (http://www.freescale.com), and enter the appropriate
document number (from Table 22) in the “Enter Keyword” search box at the top of the page.
Table 22. Package Information
Pin Count Type Document No.
80 LQFP 98ARL10530D
64 LQFP 98ASS23234W
64 QFP 98ASB42844B
44 LQFP 98ASS23225W
Revision History
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.7
Freescale Semiconductor 41
4 Revision History
Table 23. Revision History
Revision Description
1 Initial published
2 Updated ADC channels, Item 1, 4-5 on Table 2.10
3 Completed all theTBDs.
Changed RTC to RTI in Figure 1.
Corrected the block diagram.
Changed VDDAD to VDDA, VSSAD to VSSA.
Added charge device model data and removed machine data in Ta b l e 8 .
Updated the specifications of VLV DH , VLVDL, VLV WH and VLV WL in Ta b l e 1 0 .
Updated S2IDD, S3IDD in Ta bl e 1 1 .
Added C column in Ta bl e 1 4 .
Updated fdco_DMX32 in Tab l e 1 6 .
4 Corrected the expansion of SPI to serial peripheral interface.
5 Updated VLV DL in the Ta b l e 1 0 .
Updated RIDD in the Ta bl e 1 1 .
6 Updated VLV DH , VLV D L, VLV WH and VLV W L in the Table 10.
Added LPO on the Figure 1 and LPO features in the Section 1.3, “Features.”
7 Added 44-pin LQFP package information for AC256 and AC128.
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MCF51AC256
Rev.7
9/2011
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