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LMH6601

LMH6601-Q1

SNOSAK9F –JUNE 2006–REVISED JUNE 2015

LMH6601 and LMH6601-Q1 250-MHz, 2.4-V CMOS Operational Amplifier With Shutdown

1 Features 3 Description

The LMH6601 device is a low-voltage (2.4 V to 5.5

1• LMH6601-Q1 Qualified for Automotive V), high-speed voltage feedback operational amplifier

Applications suitable for use in a variety of consumer and

– AEC-Q100 Grade 3 industrial applications. With a bandwidth of 125 MHz

– –40°C to 85°C Ambient Operating at a gain of +2 and ensured high-output current of

100 mA, the LMH6601 is an ideal choice for video

Temperature Range line driver applications, including HDTV. Low-input

• VS= 3.3 V, TA= 25°C, AV= 2 V/V, RL= 150 Ωto bias current (50 pA maximum), rail-to-rail output, and

V−, Unless Specified low current noise allow the use of the LMH6601 in

• 125 MHz −3 dB Small Signal Bandwidth various industrial applications such as

transimpedance amplifiers, active filters, or high-

• 75 MHz −3 dB Large Signal Bandwidth impedance buffers. The LMH6601 is an attractive

• 30 MHz Large Signal 0.1-dB Gain Flatness solution for systems which require high performance

• 260 V/μs Slew Rate at low supply voltages. The LMH6601 is available in a

• 0.25%/0.25° Differential Gain and Differential 6-pin SC70 package, and includes a micropower

Phase shutdown feature.

• Rail-to-Rail Output Device Information(1)

• 2.4-V to 5.5-V Single-Supply Operating Range PART NUMBER PACKAGE BODY SIZE (NOM)

• 6-Pin SC70 Package LMH6601 SC70 (6) 2.00 mm × 1.25 mm

LMH6601-Q1

2 Applications (1) For all available packages, see the orderable addendum at

• Video Amplifiers the end of the data sheet.

• Charge Amplifiers Response at a Gain of +2

• Set-Top Boxes for Various Supply Voltages

• Sample and Holds

• Transimpedance Amplifiers

• Line Drivers

• High-Impedance Buffers

• Automotive

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

LMH6601

LMH6601-Q1

SNOSAK9F –JUNE 2006–REVISED JUNE 2015

www.ti.com

Table of Contents

7.1 Overview................................................................. 20

1 Features.................................................................. 17.2 Feature Description................................................. 20

2 Applications ........................................................... 17.3 Device Functional Modes........................................ 21

3 Description............................................................. 18 Application and Implementation ........................ 23

4 Revision History..................................................... 28.1 Application Information............................................ 23

5 Pin Configuration and Functions......................... 38.2 Typical Application.................................................. 29

6 Specifications......................................................... 39 Power Supply Recommendations...................... 32

6.1 Absolute Maximum Ratings ...................................... 310 Layout................................................................... 32

6.2 ESD Ratings - for LMH6601 ..................................... 310.1 Layout Guidelines ................................................. 32

6.3 ESD Ratings - for LMH6601-Q1 ............................... 410.2 Layout Examples................................................... 32

6.4 Recommended Operating Conditions....................... 411 Device and Documentation Support................. 33

6.5 Thermal Information.................................................. 411.1 Documentation Support ........................................ 33

6.6 Electrical Characteristics, 5 V................................... 411.2 Related Links ........................................................ 33

6.7 Electrical Characteristics, 3.3 V................................ 611.3 Community Resources.......................................... 33

6.8 Electrical Characteristics, 2.7 V................................ 811.4 Trademarks........................................................... 33

6.9 Switching Characteristics, 5 V ................................ 10 11.5 Electrostatic Discharge Caution............................ 33

6.10 Switching Characteristics, 3.3 V ........................... 11 11.6 Glossary................................................................ 33

6.11 Switching Characteristics, 2.7 V ........................... 11 12 Mechanical, Packaging, and Orderable

6.12 Typical Characteristics.......................................... 12 Information........................................................... 33

7 Detailed Description............................................ 20

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision E (March 2013) to Revision F Page

• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional

Modes,Application and Implementation section, Power Supply Recommendations section, Layout section, Device

and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1

• Removed IOS over temperature limit in Electrical Characteristics, 2.7 V ............................................................................... 8

• Moved the SAG Compensation section to the Typical Application section.......................................................................... 25

• Changed section titled Other Applications to Charge Preamplifier ..................................................................................... 28

Changes from Revision D (March 2013) to Revision E Page

• Changed layout of National Data Sheet to TI format ............................................................................................................. 1

Product Folder Links: LMH6601 LMH6601-Q1

OUTPUT

V-

+IN

V+

-IN

LMH6601

LMH6601-Q1

www.ti.com

SNOSAK9F –JUNE 2006–REVISED JUNE 2015

5 Pin Configuration and Functions

DCK Package

6-Pin SC70

Top View

Pin Functions

PIN I/O DESCRIPTION

NO. NAME

1 OUTPUT O Output

2 V-I Negative supply

3 +IN I Noninverting input

4 -IN I Inverting input

5 SD I Shutdown

6 V+I Positive supply

6 Specifications

6.1 Absolute Maximum Ratings(1)

MIN MAX UNIT

VIN Differential ±2.5 V

Input Current(2) ±10 mA

Output Current 200 mA(3) mA

Supply Voltage (V+– V−) 6 V

Voltage at Input/Output Pins V++0.5, V

V−−0.5

Junction Temperature 150 °C

Infrared or Convection (20 sec.) 235

Soldering Information °C

Wave Soldering (10 sec.) 260

Storage Temperature −65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Negative input current implies current flowing out of the device.

(3) The maximum continuous output current (IOUT) is determined by device power dissipation limitations.

6.2 ESD Ratings - for LMH6601 VALUE UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000

V(ESD) Electrostatic discharge V

Charged-device model (CDM), per JEDEC specification JESD22- ±1000

C101(2)

(1) Human Body Model, applicable std. MIL-STD-883, Method 3015.7.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

Product Folder Links: LMH6601 LMH6601-Q1

LMH6601

LMH6601-Q1

SNOSAK9F –JUNE 2006–REVISED JUNE 2015

www.ti.com

6.3 ESD Ratings - for LMH6601-Q1 VALUE UNIT

Human body model (HBM), per AEC Q100-002(1) ±2000

V(ESD) Electrostatic discharge V

Charged-device model (CDM), per AEC Q100-011 ±1000

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.4 Recommended Operating Conditions(1)

MIN MAX UNIT

Supply Voltage (V+– V−) 2.4 5.5 V

Operating Temperature −40 85 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.5 Thermal Information LMH6601,

LMH6601-Q1

THERMAL METRIC(1) UNIT

DCK (SC70)

6 PINS

RθJA Junction-to-ambient thermal resistance 414 °C/W

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.6 Electrical Characteristics, 5 V

Single-Supply with VS= 5 V, AV= +2, RF= 604 Ω, SD tied to V+, VOUT = VS/2, RL= 150 Ωto V−unless otherwise specified.(1)

PARAMETER TEST CONDITIONS MIN(2) TYP(2) MAX(2) UNIT

FREQUENCY DOMAIN RESPONSE

SSBW VOUT = 0.25 VPP 130

–3-dB Bandwidth Small Signal MHz

SSBW_1 VOUT = 0.25 VPP, AV= +1 250

Peak Peaking VOUT = 0.25 VPP, AV= +1 2.5 dB

Peak_1 Peaking VOUT = 0.25 VPP 0 dB

LSBW –3-dB Bandwidth Large Signal VOUT = 2 VPP 81 MHz

Peak_2 Peaking VOUT = 2 VPP 0 dB

0.1 dB BW 0.1-dB Bandwidth VOUT = 2 VPP 30 MHz

GBWP_1k Unity Gain, RL= 1 kΩto VS/2 155

Gain Bandwidth Product MHz

GBWP_150 Unity Gain, RL= 150 Ωto VS/2 125

AVOL Large Signal Open-Loop Gain 0.5 V < VOUT < 4.5 V 56 66 dB

–1 dB, AV= +4, VOUT = 4.2 VPP,

PBW Full Power BW 30 MHz

RL= 150 Ωto VS/2

4.43 MHz, 1.7 V ≤VOUT ≤3.3 V,

DG Differential Gain 0.06%

RL= 150 Ωto V−

4.43 MHz, 1.7 V ≤VOUT ≤3.3 V

DP Differential Phase 0.10 deg

RL= 150 Ωto V−

TIME DOMAIN RESPONSE

OS Overshoot 0.25-V Step 10%

CLCapacitor Load Tolerance AV=−1, 10% Overshoot, 75 Ωin Series 50 pF

(1) Electrical Characteristics, 5 V values apply only for factory testing conditions at the temperature indicated. Factory testing conditions

result in very limited self-heating of the device such that TJ= TA. No specification of parametric performance is indicated in the electrical

tables under conditions of internal self-heating where TJ> TA.

(2) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary

over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped

production material.

Product Folder Links: LMH6601 LMH6601-Q1

LMH6601

LMH6601-Q1

www.ti.com

SNOSAK9F –JUNE 2006–REVISED JUNE 2015

Electrical Characteristics, 5 V (continued)

Single-Supply with VS= 5 V, AV= +2, RF= 604 Ω, SD tied to V+, VOUT = VS/2, RL= 150 Ωto V−unless otherwise specified.(1)

PARAMETER TEST CONDITIONS MIN(2) TYP(2) MAX(2) UNIT

DISTORTION and NOISE PERFORMANCE

HD2 2 VPP, 10 MHz −56

Harmonic Distortion (2nd) dBc

HD2_1 4 VPP, 10 MHz, RL= 1 kΩto VS/2 −61

HD3 2 VPP, 10 MHz −73

Harmonic Distortion (3rd) dBc

HD3_1 4 VPP, 10 MHz, RL= 1 kΩto VS/2 −64

THD Total Harmonic Distortion 4 VPP, 10 MHz, RL= 1 kΩto VS/2 −58

VN1 >10 MHz 7

Input Voltage Noise nV/√Hz

VN2 1 MHz 10

INInput Current Noise >1 MHz 50 fA/√Hz

STATIC, DC PERFORMANCE

±1 ±2.4

VIO Input Offset Voltage mV

At temperature extremes ±5

DVIO Input Offset Voltage Average Drift See (3) −5μV/°C

IBInput Bias Current See (4) 5 50 pA

IOS Input Offset Current See (4) 2 25 pA

RIN Input Resistance 0 V ≤VIN ≤3.5 V 10 TΩ

CIN Input Capacitance 1.3 pF

55 59

Positive Power Supply Rejection

+PSRR DC dB

At temperature

Ratio 51

extremes 53 61

Negative Power Supply Rejection

−PSRR DC dB

At temperature

Ratio 50

extremes 56 68

CMRR Common-Mode Rejection Ratio DC dB

At temperature 53

extremes

CMRR > 50 dB (At temperature

CMVR Input Voltage Range V−– 0.20 – V+– 1.5 V

extremes) 9.6 11.5

Normal Operation mA

At temperature

VOUT = VS/2 13.5

ICC Supply Current extremes

Shutdown 100 nA

SD tied to ≤0.5 V (5)

–210 –190

VOH1 RL= 150 Ωto V–At temperature –480

extremes

Output High Voltage

VOH2 RL= 75 Ωto VS/2 –190 mV

(Relative to V+)–60 –12

VOH3 RL= 10 kΩto V–At temperature –110

extremes

(3) Drift determined by dividing the change in parameter at temperature extremes by the total temperature change.

(4) This parameter is ensured by design and/or characterization and is not tested in production.

(5) SD logic is CMOS compatible. To ensure proper logic level and to minimize power supply current, SD should typically be less than 10%

of total supply voltage away from either supply rail.

Product Folder Links: LMH6601 LMH6601-Q1

LMH6601

LMH6601-Q1

SNOSAK9F –JUNE 2006–REVISED JUNE 2015

www.ti.com

Electrical Characteristics, 5 V (continued)

Single-Supply with VS= 5 V, AV= +2, RF= 604 Ω, SD tied to V+, VOUT = VS/2, RL= 150 Ωto V−unless otherwise specified.(1)

PARAMETER TEST CONDITIONS MIN(2) TYP(2) MAX(2) UNIT

5 45

VOL1 RL= 150 Ωto V–At temperature 125

extremes

Output Low Voltage

VOL2 RL= 75 Ωto VS/2 120 mV

(Relative to V–)5 45

VOL3 RL= 10 kΩto V–At temperature 125

extremes

Source 150

VOUT < 0.6 V from

IORespective Supply Sink 180

Output Current mA

VOUT = VS/2,

IO_1 ±100

VID = ±18 mV (6)

THD < −30 dBc, f = 200 kHz,

Load Output Load Rating 20 Ω

RLtied to VS/2, VOUT = 4 VPP

RO_Enabled Output Resistance Enabled, AV= +1 0.2 Ω

RO_Disabled Output Resistance Shutdown >100 MΩ

CO_Disabled Output Capacitance Shutdown 5 pF

MISCELLANEOUS PERFORMANCE

VDMAX Voltage Limit for Disable (Pin 5) See (5) (At temperature extremes) 0 0.5 V

VDMIN Voltage Limit for Enable (Pin 5) See (5) (At temperature extremes) 4.5 5 V

IiLogic Input Current (Pin 5) SD = 5 V(5) 10 pA

V_glitch Turnon Glitch 2.2 V

IsolationOFF Off Isolation 1 MHz, RL= 1 kΩ60 dB

(6) “VID” is input differential voltage (input overdrive).

6.7 Electrical Characteristics, 3.3 V

Single-Supply with VS= 3.3 V, AV= +2, RF= 604Ω, SD tied to V+, VOUT = VS/2, RL= 150 Ωto V−unless otherwise specified.(1)

PARAMETER TEST CONDITIONS MIN(2) TYP(2) MAX(2) UNIT

FREQUENCY DOMAIN RESPONSE

SSBW VOUT = 0.25 VPP 125

–3-dB Bandwidth Small Signal MHz

SSBW_1 VOUT = 0.25 VPP, AV= +1 250

Peak Peaking VOUT = 0.25 VPP, AV= +1 3 dB

Peak_1 Peaking VOUT = 0.25 VPP 0.05 dB

LSBW –3-dB Bandwidth Large Signal VOUT = 2 V PP 75 MHz

Peak_2 Peaking VOUT = 2 VPP 0 dB

0.1 dB BW 0.1-dB Bandwidth VOUT = 2 VPP 30 MHz

GBWP_1k Unity Gain, RL= 1 kΩto VS/2 115

Gain Bandwidth Product MHz

GBWP_150 Unity Gain, RL= 150 Ωto VS/2 105

AVOL Large Signal Open-Loop Gain 0.3 V < VOUT < 3 V 56 67 dB

–1 dB, AV= +4, VOUT = 2.8 VPP,

PBW Full Power BW 30 MHz

RL= 150 Ωto VS/2

4.43 MHz, 0.85 V ≤VOUT ≤2.45 V,

DG Differential Gain 0.06%

RL= 150 Ωto V−

4.43 MHz, 0.85 V ≤VOUT ≤2.45 V

DP Differential Phase 0.23 deg

RL= 150 Ωto V−

(1) Electrical Characteristics, 3.3 V values apply only for factory testing conditions at the temperature indicated. Factory testing conditions

result in very limited self-heating of the device such that TJ= TA. No specification of parametric performance is indicated in the electrical

tables under conditions of internal self-heating where TJ> TA.

(2) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary

over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped

production material.

Product Folder Links: LMH6601 LMH6601-Q1

LMH6601

LMH6601-Q1

www.ti.com

SNOSAK9F –JUNE 2006–REVISED JUNE 2015

Electrical Characteristics, 3.3 V (continued)

Single-Supply with VS= 3.3 V, AV= +2, RF= 604Ω, SD tied to V+, VOUT = VS/2, RL= 150 Ωto V−unless otherwise specified.(1)

PARAMETER TEST CONDITIONS MIN(2) TYP(2) MAX(2) UNIT

TIME DOMAIN RESPONSE

OS Overshoot 0.25-V Step 10%

CLCapacitor Load Tolerance AV=−1, 10% Overshoot, 82 Ωin Series 50 pF

DISTORTION and NOISE PERFORMANCE

HD2 2 VPP, 10 MHz −61

Harmonic Distortion (2nd) dBc

2 VPP, 10 MHz

HD2_1 −79

RL= 1 kΩto VS/2

HD3 2 VPP, 10 MHz −53

Harmonic Distortion (3rd) dBc

2 VPP, 10 MHz

HD3_2 −69

RL= 1 kΩto VS/2

2 VPP, 10 MHz

THD Total Harmonic Distortion −66 dBc

RL= 1 kΩto VS/2

VN1 >10 MHz 7

Input Voltage Noise nV/√Hz

VN2 1 MHz 10

INInput Current Noise >1 MHz 50 fA/√Hz

STATIC, DC PERFORMANCE

±1 ±2.6

VIO Input Offset Voltage mV

At temperature extremes ±5.5

DVIO Input Offset Voltage Average Drift See (3) −4.5 μV/°C

IBInput Bias Current See (4) 5 50 pA

IOS Input Offset Current See (4) 2 25 pA

RIN Input Resistance 0 V ≤VIN ≤1.8 V 15 TΩ

CIN Input Capacitance 1.4 pF

DC 61 80

Positive Power Supply Rejection

+PSRR dB

Ratio At temperature extremes 51

DC 57 72

Negative Power Supply Rejection

−PSRR dB

Ratio At temperature extremes 52

DC 58 73

CMRR Common-Mode Rejection Ratio dB

At temperature extremes 55

CMRR > 50 dB (At temperature

CMVR Input Voltage V−– 0.20 V+– 1.5 V

extremes) 9.2 11

Normal Operation mA

At temperature

VOUT = VS/2

ICC Supply Current 13

extremes

Shutdown: SD tied to ≤0.33 V(5) 100 nA

–210 –190

VOH1 RL= 150 Ωto V–At temperature –360

extremes

Output High Voltage

VOH2 RL= 75 Ωto VS/2 –190 mV

(Relative to V+)–50 –10

VOH3 RL= 10 kΩto V−At temperature –100

extremes

(3) Drift determined by dividing the change in parameter at temperature extremes by the total temperature change.

(4) This parameter is ensured by design and/or characterization and is not tested in production.

(5) SD logic is CMOS compatible. To ensure proper logic level and to minimize power supply current, SD should typically be less than 10%

of total supply voltage away from either supply rail.

Product Folder Links: LMH6601 LMH6601-Q1

LMH6601

LMH6601-Q1

SNOSAK9F –JUNE 2006–REVISED JUNE 2015

www.ti.com

Electrical Characteristics, 3.3 V (continued)

Single-Supply with VS= 3.3 V, AV= +2, RF= 604Ω, SD tied to V+, VOUT = VS/2, RL= 150 Ωto V−unless otherwise specified.(1)

PARAMETER TEST CONDITIONS MIN(2) TYP(2) MAX(2) UNIT

4 45

VOL1 RL= 150 Ωto V–At temperature 125

extremes

Output Low Voltage

VOL2 RL= 75 Ωto VS/2 105 mV

(Relative to V–)4 45

VOL3 RL= 10 kΩto V–At temperature 125

extremes

VOUT < 0.6 V from Source 50

IORespective

Output Current Sink 75 mA

Supply

IO_1 VOUT = VS/2, VID = ±18 mV(6) ±75

THD < −30 dBc, f = 200 kHz,

Load Output Load Rating 25 Ω

RLtied to VS/2, VOUT = 2.6 VPP

RO_Enabled Output Resistance Enabled, AV= +1 0.2 Ω

RO_Disabled Output Resistance Shutdown >100 MΩ

CO_Disabled Output Capacitance Shutdown 5.6 pF

MISCELLANEOUS PERFORMANCE

VDMAX Voltage Limit for Disable (Pin 5) See (5) (At temperature extremes) 0 0.33 V

VDMIN Voltage Limit for Enable (Pin 5) See (5) (At temperature extremes) 2.97 3.3 V

IiLogic Input Current (Pin 5) SD = 3.3 V(5) 8 pA

V_glitch Turnon Glitch 1.6 V

IsolationOFF Off Isolation 1 MHz, RL= 1 kΩ60 dB

(6) “VID” is input differential voltage (input overdrive).

6.8 Electrical Characteristics, 2.7 V

Single-Supply with VS= 2.7 V, AV= +2, RF= 604 Ω, SD tied to V+, VOUT = VS/2, RL= 150 Ωto V−unless otherwise

specified.(1)

PARAMETER TEST CONDITIONS MIN(2) TYP(2) MAX(2) UNIT

FREQUENCY DOMAIN RESPONSE

SSBW VOUT = 0.25 VPP 120

–3-dB Bandwidth Small Signal MHz

SSBW_1 VOUT = 0.25 VPP, AV= +1 250

Peak Peaking VOUT = 0.25 VPP, AV= +1 3.1 dB

Peak_1 Peaking VOUT = 0.25 VPP 0.1 dB

LSBW –3-dB Bandwidth Large Signal VOUT = 2 V PP 73 MHz

Peak_2 Peaking VOUT = 2 VPP 0 dB

0.1 dB BW 0.1-dB Bandwidth VOUT = 2 VPP 30 MHz

GBWP_1k Unity Gain, RL= 1 kΩto VS/2 110

Gain Bandwidth Product MHz

GBWP_150 Unity Gain, RL= 150 Ωto VS/2 81

AVOL Large Signal Open-Loop Gain 0.25 V < VOUT < 2.5 V 56 65 dB

–1 dB, AV= +4, VOUT = 2 VPP,

PBW Full Power BW 13 MHz

RL= 150 Ωto VS/2

4.43 MHz, 0.45 V ≤VOUT ≤2.05 V

DG Differential Gain 0.12%

RL= 150 Ωto V−

(1) Electrical Characteristics, 2.7 V values apply only for factory testing conditions at the temperature indicated. Factory testing conditions

result in very limited self-heating of the device such that TJ= TA. No specification of parametric performance is indicated in the electrical

tables under conditions of internal self-heating where TJ> TA.

(2) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary

over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped

production material.

Product Folder Links: LMH6601 LMH6601-Q1

LMH6601

LMH6601-Q1

www.ti.com

SNOSAK9F –JUNE 2006–REVISED JUNE 2015

Electrical Characteristics, 2.7 V (continued)

Single-Supply with VS= 2.7 V, AV= +2, RF= 604 Ω, SD tied to V+, VOUT = VS/2, RL= 150 Ωto V−unless otherwise

specified.(1)

PARAMETER TEST CONDITIONS MIN(2) TYP(2) MAX(2) UNIT

4.43 MHz, 0.45 V ≤VOUT ≤2.05 V

DP Differential Phase 0.62 deg

RL= 150 Ωto V−

TIME DOMAIN RESPONSE

OS Overshoot 0.25-V Step 10%

DISTORTION and NOISE PERFORMANCE

HD2 Harmonic Distortion (2nd) 1 VPP, 10 MHz −58 dBc

HD3 Harmonic Distortion (3rd) 1 VPP, 10 MHz −60 dBc

VN1 >10 MHz 8.4

Input Voltage Noise nV/√Hz

VN2 1 MHz 12

INInput Current Noise >1 MHz 50 fA/√Hz

STATIC, DC PERFORMANCE

±1 ±3.5

VIO Input Offset Voltage mV

At temperature extremes ±6.5

DVIO Input Offset Voltage Average Drift See (3) −6.5 μV/°C

IBInput Bias Current See (4) 5 50 pA

IOS Input Offset Current See (4) 2 25 pA

RIN Input Resistance 0V ≤VIN ≤1.2V 20 TΩ

CIN Input Capacitance 1.6 pF

58 68

Positive Power Supply Rejection

+PSRR DC dB

At temperature

Ratio 53

extremes 56 69

Negative Power Supply Rejection

−PSRR DC dB

At temperature

Ratio 53

extremes 57 77

CMRR Common-Mode Rejection Ratio DC dB

At temperature 52

extremes

CMRR > 50 dB (At temperature

CMVR Input Voltage V−– 0.20 – V+– 1.5 V

extremes) 9 10.6

Normal Operation mA

At temperature

VOUT = VS/2 12.5

ICC Supply Current extremes

Shutdown 100 nA

SD tied to ≤0.27 V(5)

–260 –200

VOH1 RL= 150 Ωto V–At temperature –420

extremes

Output High Voltage

VOH2 RL= 75 Ωto VS/2 –200 mV

(Relative to V+)–50 –10

VOH3 RL= 10 kΩto V–At temperature 100

extremes

(3) Drift determined by dividing the change in parameter at temperature extremes by the total temperature change.

(4) This parameter is ensured by design and/or characterization and is not tested in production.

(5) SD logic is CMOS compatible. To ensure proper logic level and to minimize power supply current, SD should typically be less than 10%

of total supply voltage away from either supply rail.

Product Folder Links: LMH6601 LMH6601-Q1

LMH6601

LMH6601-Q1

SNOSAK9F –JUNE 2006–REVISED JUNE 2015

www.ti.com

Electrical Characteristics, 2.7 V (continued)

Single-Supply with VS= 2.7 V, AV= +2, RF= 604 Ω, SD tied to V+, VOUT = VS/2, RL= 150 Ωto V−unless otherwise

specified.(1)

PARAMETER TEST CONDITIONS MIN(2) TYP(2) MAX(2) UNIT

4 45

VOL1 RL= 150 Ωto V–125

VOL2 Output Low Voltage RL= 75 Ωto VS/2 125 mV

(Relative to V–)4 45

VOL3 RL= 10 kΩto V–At temperature 125

extremes

VOUT ≤0.6 V from Source 25

IORespective Sink 62

Supply

Output Current mA

Source 25

VOUT = VS/2, VID

IO_1 = ±18 mV(6) Sink 35

THD < −30 dBc, f = 200 kHz, RLtied to

Load Output Load Rating 40 Ω

VS/2, VOUT = 2.2 VPP

RO_Enable Output Resistance Enabled, AV= +1 0.2 Ω

RO_Disabled Output Resistance Shutdown >100 MΩ

CO_Disabled Output Capacitance Shutdown 5.6 pF

MISCELLANEOUS PERFORMANCE

VDMAX Voltage Limit for Disable (Pin 5) See (5) (At temperature extremes) 0 0.27 V

VDMIN Voltage Limit for Enable (Pin 5) See (5) (At temperature extremes) 2.43 2.7 V

IiLogic Input Current (Pin 5) SD = 2.7 V(5) 4 pA

V_glitch Turnon Glitch 1.2 V

IsolationOFF Off Isolation 1 MHz, RL= 1 kΩ60 dB

(6) “VID” is input differential voltage (input overdrive).

6.9 Switching Characteristics, 5 V

Single-Supply with VS= 5 V, AV = +2, RF = 604 Ω, SD tied to V+, VOUT = VS/2, RL = 150 Ωto V−unless otherwise

specified. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

TIME DOMAIN RESPONSE

TRS/TRL Rise and Fall Time 0.25-V Step 2.6 ns

SR Slew Rate 2-V Step 275 V/μs

TS1-V Step, ±0.1% 50

Settling Time ns

TS_1 1-V Step, ±0.02% 220

PD Propagation Delay Input to Output, 250-mV Step, 50% 2.4 ns

MISCELLANEOUS PERFORMANCE

Ton Turnon Time 1.4 µs

Toff Turnoff Time 520 ns

T_OL Overload Recovery <20 ns

Product Folder Links: LMH6601 LMH6601-Q1

LMH6601

LMH6601-Q1

www.ti.com

SNOSAK9F –JUNE 2006–REVISED JUNE 2015

6.10 Switching Characteristics, 3.3 V

Single-Supply with VS= 3.3 V, AV= +2, RF= 604Ω, SD tied to V+, VOUT = VS/2, RL= 150 Ωto V−unless otherwise specified.(1)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

TIME DOMAIN RESPONSE

TRS/TRL Rise and Fall Time 0.25-V Step 2.7 ns

SR Slew Rate 2-V Step 260 V/μs

TS1-V Step, ±0.1% 70

Settling Time ns

TS_1 1-V Step, ±0.02% 300

PD Propagation Delay Input to Output, 250-mV Step, 50% 2.6 ns

MISCELLANEOUS PERFORMANCE

Ton Turnon Time 3.5 µs

Toff Turnoff Time 500 ns

(1) Electrical Characteristics, 3.3 V values apply only for factory testing conditions at the temperature indicated. Factory testing conditions

result in very limited self-heating of the device such that TJ= TA. No specification of parametric performance is indicated in the electrical

tables under conditions of internal self-heating where TJ> TA.

6.11 Switching Characteristics, 2.7 V

Single-Supply with VS= 2.7 V, AV= +2, RF= 604 Ω, SD tied to V+, VOUT = VS/2, RL= 150 Ωto V−unless otherwise

specified.(1)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

TIME DOMAIN RESPONSE

TRS/TRL Rise and Fall Time 0.25-V Step 2.7 ns

SR Slew Rate 2-V Step 260 V/μs

TS1-V Step, ±0.1% 147

Settling Time ns

TS_1 1-V Step, ±0.02% 410

PD Propagation Delay Input to Output, 250-mV Step, 50% 3.4 ns

MISCELLANEOUS PERFORMANCE

Ton Turnon Time 5.2 µs

Toff Turnoff Time 760 ns

(1) Electrical Characteristics, 2.7 V values apply only for factory testing conditions at the temperature indicated. Factory testing conditions

result in very limited self-heating of the device such that TJ= TA. No specification of parametric performance is indicated in the electrical

tables under conditions of internal self-heating where TJ> TA.

Product Folder Links: LMH6601 LMH6601-Q1

FREQUENCY (MHz)

NORMALIZED GAIN (dB)

PHASE (°)

110 100 1000

-21

-18

-15

-12

-9

-6

-3

VOUT = 0.25 VPP

GAIN

PHASE

-100

-80

-60

-40

-20

AV = +1 AV = +2

AV = +5

AV = +10

AV = +1

AV = +2

AV = +5

AV = +10

FREQUENCY (MHz)

NORMALIZED GAIN (dB)

PHASE (°)

110 100 1000

-21

-18

-15

-12

-9

-6

-3

VOUT = 0.25 VPP

GAIN

PHASE

-100

-80

-60

-40

-20

AV = -1

AV = -2

AV = -5

AV = -10

110 100 1000

FREQUENCY (MHz)

NORMALIZED GAIN (dB)

VS = 2.7V

-18

-15

-12

-9

-6

-3

-200

-160

-120

-80

-40

PHASE (°)

GAIN

PHASE

0.25 VPP

1 VPP

2 VPP

2.5 3 3.5 4 4.5 5

100

125

150

-3 dB BW (MHz)

VS (V)

AV = +2 0.25 VPP

1 VPP

2 VPP

110 100 1000

FREQUENCY (MHz)

NORMALIZED GAIN (dB)

VS = 5V

GAIN

PHASE 0.25 VPP

1 VPP

2 VPP

-18

-15

-12

-9

-6

-3

-200

-160

-120

-80

-40

PHASE (°)

110 100 1000

FREQUENCY (MHz)

NORMALIZED GAIN (dB)

VS = 3.3V

-18

-15

-12

-9

-6

-3

-200

-160

-120

-80

-40

PHASE (°)

GAIN

PHASE

0.25 VPP

1 VPP

2 VPP

LMH6601

LMH6601-Q1

SNOSAK9F –JUNE 2006–REVISED JUNE 2015

www.ti.com

6.12 Typical Characteristics

Unless otherwise noted, all data is with AV= +2, RF= RG= 604 Ω, VS= 3.3V, VOUT = VS/2, SD tied to V+, RL= 150 Ωto V−, T

= 25°C.

Figure 1. Frequency Response Figure 2. Frequency Response

for Various Output Amplitudes for Various Output Amplitudes

Figure 4. −3 dB BW vs. Supply Voltage

Figure 3. Frequency Response for Various Output Swings

for Various Output Amplitudes

Figure 5. Noninverting Frequency Response Figure 6. Inverting Frequency Response

for Various Gain for Various Gain

Product Folder Links: LMH6601 LMH6601-Q1

110 100 1000

FREQUENCY (MHz

-1

MAGNITUDE (dB)

2.7V

3.3V

10k 100k 1M 10M 100M

FREQUENCY (Hz)

VOUT (VPP)

VS = 5V

AV = +2

RL = 150: to VS/2

THD < -30 dBc

110 100 1000

FREQUENCY (MHz)

-18

-15

-12

-9

-6

-3

NORMALIZED GAIN (dB)

VOUT = 0.25 VPP

RL = 1 k: || CL to V-

0 pF

5 pF

10 pF 20 pF

20 pF 0 pF

-40 -20 0 20 40 60 80

TEMPERATURE (°C)

100

110

120

130

140

-3 dB BW (MHz)

AV = +2

VOUT = 2 VPP

3.3V

100

110 100 1000

FREQUENCY (MHz)

-18

-15

-12

-9

-6

-3

NORMALIZED GAIN (dB)

1 k:

50:

150:

VOUT = 0.25 VPP

RL TIED TO V-

110 100 1000

FREQUENCY (MHz)

-18

-15

-12

-9

-6

-3

NORMALIZED GAIN (dB)

AV = +1

VOUT = 0.25 VPP

GAIN

PHASE 2.7V

3.3V

2.7V

3.3V

5V -210

-180

-150

-120

-90

-60

-30

PHASE (°)

LMH6601

LMH6601-Q1

www.ti.com

SNOSAK9F –JUNE 2006–REVISED JUNE 2015

Typical Characteristics (continued)

Unless otherwise noted, all data is with AV= +2, RF= RG= 604 Ω, VS= 3.3V, VOUT = VS/2, SD tied to V+, RL= 150 Ωto V−, T

= 25°C.

Figure 7. Frequency Response Figure 8. Frequency Response

for Various Loads for Various Supply Voltages

Figure 9. −3 dB BW Figure 10. Frequency Response

vs. Ambient Temperature for Various Capacitor Load

Figure 11. Frequency Response Figure 12. Maximum Output Swing

for Various Supply Voltage vs. Frequency

Product Folder Links: LMH6601 LMH6601-Q1

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

-100

-90

-80

-70

-60

-50

-40

THD (dBc)

OUTPUT (VPP)

RL = 1 k: to VS/2

VS = 5V

1 MHz

10 MHz

0.1 100

FREQUENCY (MHz)

-90

-70

-50

-30

HD3 (dBc)

-40

-60

-80

2.7V

3.3V

VOUT = 2 VPP

-75

-85

-65

-55

-45

-35

0.1 100

FREQUENCY (MHz)

-90

-70

-50

-30

HD2 (dBc)

-40

-60

-80

2.7V

3.3V

VOUT = 2 VPP

-35

-45

-55

-65

-75

-85

0.1

0.01 0 20 40 60 80 100

ISOURCE (mA)

VOUT FROM V+ (V)

3.3V

10 20 30 40 50 60 70 80 90 100

0.5

1.5

2.5

PEAK SWING (VP)

RL (:)

3.3V

2.7V

AV = +5 V/V

RL to VS/2

VOUT_DC = VS/2

UNDISORTED OUTPUT SWING

(LIMITED BY SOURCE CURRENT)

0.1

0.01 0 20 40 60 80 100

ISINK (mA)

VOUT FROM V- (V)

3.3V

LMH6601

LMH6601-Q1

SNOSAK9F –JUNE 2006–REVISED JUNE 2015

www.ti.com

Typical Characteristics (continued)

Unless otherwise noted, all data is with AV= +2, RF= RG= 604 Ω, VS= 3.3V, VOUT = VS/2, SD tied to V+, RL= 150 Ωto V−, T

= 25°C.

Figure 14. Output Swing vs. Sink Current

Figure 13. Peak Output Swing vs. RLfor Various Supply Voltages

Figure 15. Output Swing vs. Source Current Figure 16. HD2 vs. Frequency

for Various Supply Voltages

Figure 18. THD vs. Output Swing

Figure 17. HD3 vs. Frequency

Product Folder Links: LMH6601 LMH6601-Q1

0 50 100 150 200 250

100

150

200

250

RISO (:)

CL (pF)

ISOLATION RESISTOR

SETTLING TIME

AV = -1

RL = RF = 1 k:

VS = 5V

VO = 1 VPP STEP

10% OVERSHOOT

ACROSS CL

±5% SETTLING TIME (ns)

0 50 100 150 200 250

100

150

200

250

RISO (:)

CL (pF)

ISOLATION RESISTOR

SETTLING TIME

AV = -1

RL = RF = 1 k:

VS = 3.3V

VO = 1 VPP STEP

10% OVERSHOOT

ACROSS CL

±5% SETTLING TIME (ns)

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

SETTLING TIME (ns)

VOUT (VPP)

AV = -1

RL = 150: to VS/2

VS = 5V

(0.2%/DIV)

TIME (20 ns/DIV)

VS = 5V

RL = 150: to VS/2

AV = -1

VOUT = 1 VPP

00.5 1 1.5 2 2.5 3

OUTPUT (VPP)

-100

-90

-80

-70

-60

-50

-40

-30

-20

THD (dBc)

RL = 1 k: to VS/2

VS = 3.3V

10 MHz

1 MHz

-40 -20 0 20 40 60 80 100

150

170

190

210

230

250

270

290

310

SLEW RATE (V/Ps)

TEMPERATURE (°C)

AV = +2

VOUT = 2 VPP

5V, FALLING

3.3V, FALLING

5V, RISING

3.3V RISING

LMH6601

LMH6601-Q1

www.ti.com

SNOSAK9F –JUNE 2006–REVISED JUNE 2015

Typical Characteristics (continued)

Unless otherwise noted, all data is with AV= +2, RF= RG= 604 Ω, VS= 3.3V, VOUT = VS/2, SD tied to V+, RL= 150 Ωto V−, T

= 25°C.

Figure 20. Slew Rate vs. Ambient Temperature

Figure 19. THD vs. Output Swing

Figure 22. Output Settling

Figure 21. Settling Time (±1%) vs. Output Swing

Figure 23. Isolation Resistor and Settling Time vs. CLFigure 24. Isolation Resistor and Settling Time vs. CL

Product Folder Links: LMH6601 LMH6601-Q1

1k 100k 100M

FREQUENCY (Hz)

CMRR (dB)

10M

10k

10k 100k 1M 10M 100M

FREQUENCY (Hz)

+PSRR (dB)

3.3V

2.7V

10 1k 100k 10M

FREQUENCY (Hz)

1000

10000

10k

100

NOISE VOLTAGE (nV/ Hz)

2.7V

3.3V

1k 100k 10M 500M

FREQUENCY (Hz)

GAIN (dB)

100M1M

10k

100

250

150

200

PHASE (°)

PHASE

GAIN

100 10k 1M 100M

FREQUENCY (Hz)

0.1

100

|ZOUT| (:)

10M100k

AV = +1

2.7V

3.3V

100k 1M 10M 100M

FREQUENCY (Hz)

-90

-80

-70

-60

-50

-40

-30

-20

-10

ISOLATION (dB)

VS = 5V

AV = +2

RF = RG = 510:

RL = 100 k:

LMH6601

LMH6601-Q1

SNOSAK9F –JUNE 2006–REVISED JUNE 2015

www.ti.com

Typical Characteristics (continued)

Unless otherwise noted, all data is with AV= +2, RF= RG= 604 Ω, VS= 3.3V, VOUT = VS/2, SD tied to V+, RL= 150 Ωto V−, T

= 25°C.

Figure 25. Closed-Loop Output Impedance Figure 26. Off Isolation vs. Frequency

vs. Frequency for Various Supply Voltages

Figure 27. Noise Voltage vs. Frequency Figure 28. Open-Loop Gain and Phase

Figure 29. CMRR vs. Frequency Figure 30. +PSRR vs. Frequency

Product Folder Links: LMH6601 LMH6601-Q1

-1.8 -1.4 -1 -0.6 -0.2 0.2 0.6 1 1.4 1.8 2.2

VIO (mV)

6.5

5.5

4.5

3.5

2.5

1.5

0.5

RELATIVE FREQUENCY (%)

VS = 3.3V

-40 -20 0 20 40 60 80 100

-0.80

-0.60

-0.40

-0.20

0.00

0.20

0.40

0.60

0.80

1.00

VIO (mV)

TEMPERATURE (°C)

VS = 2.7V

UNIT 2

UNIT 1

UNIT 3

1.5 2 2.5 3 3.5 4 4.5

VS (V)

ICC (mA)

125°C

-40°C

25°C

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5

ICC (mA)

VCM (V)

25°C

85°C

VS = 5V

VCM MEASURE FROM V-

-40°C

10k 100k 1M 10M 100M

FREQUENCY (Hz)

-PSRR (dB)

3.3V 2.7V

-40 -20 020 40 60 80 100

8.2

8.4

8.6

8.8

9.2

9.4

9.6

9.8

IS (mA)

TEMPERATURE (°C)

3.3V

2.7V

LMH6601

LMH6601-Q1

www.ti.com

SNOSAK9F –JUNE 2006–REVISED JUNE 2015

Typical Characteristics (continued)

Unless otherwise noted, all data is with AV= +2, RF= RG= 604 Ω, VS= 3.3V, VOUT = VS/2, SD tied to V+, RL= 150 Ωto V−, T

= 25°C.

Figure 32. Supply Current vs. Ambient Temperature

Figure 31. −PSRR vs. Frequency

Figure 33. Supply Current vs. VCM Figure 34. Supply Current vs. Supply Voltage

Figure 35. Offset Voltage Figure 36. Offset Voltage Distribution

vs. Ambient Temperature for 3 Representative Units

Product Folder Links: LMH6601 LMH6601-Q1

TIME (ns)

0 10 20 30

0.5

1.5

2.5

VOUT (V)

RL = 100: to V-

AV = +1

OUTPUT

0.5 V/DIV

2.5 Ps/DIV

2 V/DIV

VS = ±1.65V

RL = 150: to VS/2

0 20 40 60 80 100

1.1

1.2

1.3

1.4

1.5

OUTPUT (V)

TIME (ns)

VOUT = 0.25 VPP

AV = +2

VS = 2.7V

0 20 40 60 80 100

0.5

1.5

2.5

OUTPUT (V)

TIME (ns)

VOUT = 2 VPP

AV = +2

VS = 2.7V

-1 0 1 2 3 4 5

VCM (V)

.01

100

1000

|IB| (pA)

125°C

25°C

VS = 5V

125°

OPERATION IS NOT

RECOMMENDED

0 0.5 1 1.5 2 2.5

-10

-8

-6

-4

-2

VIO (mV)

VCM (V)

85°C

-40°C

25°C

VS = 3.3V

VCM MEASURED FROM V-

LMH6601

LMH6601-Q1

SNOSAK9F –JUNE 2006–REVISED JUNE 2015

www.ti.com

Typical Characteristics (continued)

Unless otherwise noted, all data is with AV= +2, RF= RG= 604 Ω, VS= 3.3V, VOUT = VS/2, SD tied to V+, RL= 150 Ωto V−, T

= 25°C.

Figure 37. Offset Voltage Figure 38. Input Bias Current

vs. VCM (Typical Part) vs. Common Mode Voltage

Figure 40. Large Signal Step Response

Figure 39. Small Signal Step Response

Figure 42. Turn On/Off Waveform

Figure 41. Large Signal Step Response

Product Folder Links: LMH6601 LMH6601-Q1

-1 -0.6 -0.2 0.2 0.6 1

-1

-0.8

-0.6

-0.4

-0.2

0.2

0.4

0.6

0.8

DP (°)

VOUT FROM VS/2 (V)

VS = 5V

RL = 150:

DP MEASURED RELATIVE TO

VOUT = VS/2 IN EACH CASE

AC COUPLED

DC COUPLED

-1 -0.6 -0.2 0.2 0.6 1

-0.2

-0.1

0.1

0.2

0.3

0.4

DG (%)

VOUT FROM VS/2 (V)

VS = 5V

RL = 150:

DG MEASURED

RELATIVE TO VOUT = VS/2

IN EACH CASE

AC COUPLED

DC COUPLED

-2.5 -2 -0.5 -1 -0.5 0 0.5 1 1.5 2

-0.2

-0.1

0.1

0.2

DG (%)

VOUT FROM VS/2 (V)

VS = 5V VS = 3.3V

VS = 2.5V

RL = 150: TO V-

DC COUPLED

DG MEASURED RELATIVE

TO VOUT = VS/2 IN EACH

CASE

-2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2

-0.6

-0.5

-0.4

-0.3

-0.2

-0.1

0.1

0.2

DP (°)

VOUT FROM VS/2 (V)

VS = 2.5V VS = 3.3V

VS = 5V

RL = 150: TO V-

DC COUPLED

DP MEASURED

RELATIVE TO VOUT =

VS/2 IN EACH CASE

LMH6601

LMH6601-Q1

www.ti.com

SNOSAK9F –JUNE 2006–REVISED JUNE 2015

Typical Characteristics (continued)

Unless otherwise noted, all data is with AV= +2, RF= RG= 604 Ω, VS= 3.3V, VOUT = VS/2, SD tied to V+, RL= 150 Ωto V−, T

= 25°C.

Figure 44. DP vs. VOUT for Various VS

Figure 43. DG vs. VOUT for Various VS

Figure 45. DG vs. VOUT Figure 46. DP vs. VOUT

(DC- and AC-Coupled Load Compared) (DC- and AC-Coupled Load Compared)

Product Folder Links: LMH6601 LMH6601-Q1

(VOLTS)

TIME (10 ns/DIV)

VS = ±2.5V

OUTPUT (1V/DIV)

INPUT (4 VPP)

LMH6601

LMH6601-Q1

SNOSAK9F –JUNE 2006–REVISED JUNE 2015

www.ti.com

7 Detailed Description

7.1 Overview

The high-speed, ultra-high input impedance of the LMH6601 and its fast slew rate make the device an ideal

choice for video amplifier and buffering applications. There are cost benefits in having a single operating supply.

Single-supply video systems can take advantage of the low supply voltage operation of the LMH6601 along with

its ability to operate with input common-mode voltages at or slightly below the V−rail. Additional cost savings can

be achieved by eliminating or reducing the value of the input and output AC-coupling capacitors commonly

employed in single-supply video applications.

7.2 Feature Description

7.2.1 Shutdown Capability and Turn On/Off Behavior

With the device in shutdown mode, the output goes into high-impedance (ROUT > 100 MΩ) mode. In this mode,

the only path between the inputs and the output pin is through the external components around the device. So,

for applications where there is active signal connection to the inverting input, with the LMH6601 in shutdown, the

output could show signal swings due to current flow through these external components. For noninverting

amplifiers in shutdown, no output swings would occur, because of complete input-output isolation, with the

exception of capacitive coupling.

For maximum power saving, the LMH6601 supply current drops to around 0.1 μA in shutdown. All significant

power consumption within the device is disabled for this purpose. Because of this, the LMH6601 turnon time is

measured in microseconds whereas its turnoff is fast (nanoseconds) as would be expected from a high speed

device like this.

The LMH6601 SD pin is a CMOS compatible input with a pico-ampere range input current drive requirement.

This pin must be tied to a level or otherwise the device state would be indeterminate. The device shutdown

threshold is half way between the V+and V−pin potentials at any supply voltage. For example, with V+tied to 10

V and V−equal to 5 V, you can expect the threshold to be at 7.5 V. The state of the device (shutdown or normal

operation) is ensured over temperature as long as the SD pin is held to within 10% of the total supply voltage.

For V+= 10 V, V−= 5 V, as an example:

• Shutdown Range 5 V ≤SD ≤5.5 V

• Normal Operation Range 9.5 V ≤SD ≤10 V

7.2.2 Overload Recovery and Swing Close to Rails

The LMH6601 can recover from an output overload in less than 20 ns. See Figure 47 for the input and output

scope photos:

Figure 47. LMH6601 Output Overload Recovery Waveform

In Figure 47, the input step function is set so that the output is driven to one rail and then the other and then the

output recovery is measured from the time the input crosses 0 V to when the output reaches this point.

Product Folder Links: LMH6601 LMH6601-Q1

1 ms/DIV

OUTPUT INPUT

(1 V/DIV)

VS = ±2.5V

LMH6601

LMH6601-Q1

www.ti.com

SNOSAK9F –JUNE 2006–REVISED JUNE 2015

Feature Description (continued)

Also, when the LMH6601 input voltage range is exceeded near the V+rail, the output does not experience output

phase reversal, as do some op amps. This is particularly advantageous in applications where output phase

reversal must be avoided at all costs, such as in servo loop control among others. This adds to the set of

features of the LMH6601, which make this device easy to use.

In addition, the LMH6601 output swing close to either rail is well-behaved as shown in the scope photo of

Figure 48.

Figure 48. Clean Swing of the LMH6601 to Either Rail

With some op amps, when the output approaches either one or both rails and saturation starts to set in, there is

significant increase in the transistor parasitic capacitances which leads to loss of Phase Margin. That is why with

these devices, there are sometimes hints of instability with output close to the rails. With the LMH6601, as can

be seen in Figure 48, the output waveform remains free of instability throughout its range of voltages.

7.3 Device Functional Modes

7.3.1 Optimizing Performance

With many op amps, additional device nonlinearity and sometimes less loop stability arises when the output must

switch from current-source mode to current-sink mode or vice versa. When it comes to achieving the lowest

distortion and the best Differential Gain/ Differential Phase (DG/ DP, broadcast video specs), the LMH6601 is

optimized for single-supply DC-coupled output applications where the load current is returned to the negative rail

(V−). That is where the output stage is most linear (lowest distortion) and which corresponds to unipolar current

flowing out of this device. To that effect, it is easy to see that the distortion specifications improve when the

output is only sourcing current which is the distortion-optimized mode of operation for the LMH6601. In an

application where the LMH6601 output is AC-coupled or when it is powered by separate dual supplies for V+and

V−, the output stage supplies both source and sink current to the load and results in less than optimum distortion

(and DG/DP). Figure 49 compares the distortion results between a DC- and an AC-coupled load to show the

magnitude of this difference. See the DG/DP plots, Figure 43 through Figure 46,inTypical Characteristics, for a

comparison between DC- and AC-coupling of the video load.

Product Folder Links: LMH6601 LMH6601-Q1

V+

RPRL

IL-MAX

V+

RPRL

(a) DUAL SUPPLY (b) AC-COUPLED LOAD

(V–

VO_MIN

-1

RP≤RL

VO_MIN

IL_MAX

RP≤

VO_MIN is the most

negative swing at output

VO_MIN is the most

negative swing at output

and IL_MAX is maximum load

current with direction shown

LMH6601

)

0.1 1 10 100

FREQUENCY (MHz)

-100

-90

-80

-70

-60

-50

-40

-30

-20

HD (dBc)

VS = 3.3V

VOUT = 2 VPP

VOUT_DC = VS/2

HD2, DC COUPLED

HD3, DC COUPLED

HD2, AC COUPLED

HD3, AC COUPLED

LMH6601

LMH6601-Q1

SNOSAK9F –JUNE 2006–REVISED JUNE 2015

www.ti.com

Device Functional Modes (continued)

Figure 49. Distortion Comparison between DC- and AC-Coupling of the Load

In certain applications, it may be possible to optimize the LMH6601 for best distortion (and DG/DP) even though

the load may require bipolar output current by adding a pulldown resistor to the output. Adding an output

pulldown resistance of appropriate value could change the LMH6601 output loading into source-only. This comes

at the price of higher total power dissipation and increased output current requirement.

Figure 50 shows how to calculate the pulldown resistor value for both the dual-supply and for the AC-coupled

load applications.

Figure 50. Output Pulldown Value for Dual-Supply and AC-Coupling

Furthermore, with a combination of low closed-loop gain setting (that is, AV= +1 for example where device

bandwidth is the highest), light output loading (RL> 1 kΩ) , and with a significant capacitive load (CL> 10 pF) ,

the LMH6601 is most stable if output sink current is kept to less than about 5 mA. The pulldown method

described in Figure 50 is applicable in these cases as well where the current that would normally be sunk by the

op amp is diverted to the RPpath instead.

Product Folder Links: LMH6601 LMH6601-Q1

VIDEO IN (0-0.75V)

75:

VS = 2.7V

620:

75:RL

75:

VLOAD

LMH6601 75: CABLE

LMH6601

LMH6601-Q1

www.ti.com

SNOSAK9F –JUNE 2006–REVISED JUNE 2015

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

8.1.1 DC-Coupled, Single-Supply Baseband Video Amplifier and Driver

The LMH6601 output can swing very close to either rail to maximize the output dynamic range which is of

particular interest when operating in a low-voltage, single-supply environment. Under light output load conditions,

the output can swing as close as a few mV of either rail. This also allows a video amplifier to preserve the video

black level for excellent video integrity. In the example shown in Figure 51, the baseband video output is

amplified and buffered by the LMH6601 which then drives the 75-Ωback-terminated video cable for an overall

gain of +1 delivered to the 75-Ωload. The input video would normally have a level between 0 V to approximately

0.75 V.

Figure 51. Single-Supply Video Driver Capable of Maintaining Accurate Video Black Level

With the LMH6601 input common-mode range including the V−(ground) rail, there will be no need for AC-

coupling or level shifting and the input can directly drive the noninverting input which has the additional

advantage of high amplifier input impedance. With LMH6601’s wide rail-to-rail output swing, as stated earlier, the

video black level of 0 V is maintained at the load with minimal circuit complexity and using no AC-coupling

capacitors. Without true rail-to-rail output swing of the LMH6601, and more importantly without the LMH6601’s

ability of exceedingly close swing to V−, the circuit would not operate properly as shown at the expense of more

complexity. This circuit will also work for higher input voltages. The only significant requirement is that there is at

least 1.8 V from the maximum input voltage to the positive supply (V+).

The Composite Video Output of some low-cost consumer video equipment consists of a current source which

develops the video waveform across a load resistor (usually 75 Ω), as shown in Figure 52. With these

applications, the same circuit configuration just described and shown in Figure 52 will be able to buffer and drive

the Composite Video waveform which includes sync and video combined. However, with this arrangement, the

LMH6601 supply voltage must be at least 3.3 V or higher to allow proper input common-mode voltage headroom

because the input can be as high as 1-V peak.

Product Folder Links: LMH6601 LMH6601-Q1

R3=0.61

3.3V ± 0.61 = 0.227

1 + RF

-1 = 1.5V/V

RG||R3=2V

0.8V

VS = 3.3V

620:

560:

75:RL

75:

VLOAD

LMH6601

0V - 2V

1.3 k:

3.3V

30 k:

10 k:

75:

VIDEO IN

-0.3V to 0.75V

0.8VPP

0.61V ± 1.41V

3.3V

COMPOSITE

VIDEO IN 0-1V

75:

VS = 3.3V

620:

75:RL

75:

VLOAD

LMH6601

VIDEO DAC

CURRENT

OUTPUT

LMH6601

LMH6601-Q1

SNOSAK9F –JUNE 2006–REVISED JUNE 2015

www.ti.com

Application Information (continued)

Figure 52. Single-Supply Composite Video Driver for Consumer Video Outputs

If the Video In signal is Composite Video with negative going Sync tip, a variation of the previous configurations

should be used. This circuit produces a unipolar (more than 0 V) DC-coupled single-supply video signal as

shown in Figure 53.

Figure 53. Single-Supply, DC-Coupled Composite Video Driver for Negative Going Sync Tip

In the circuit of Figure 53, the input is shifted positive by means of R1, R2, and RTin order to satisfy the common-

mode input range of the U1. The signal will loose 20% of its amplitude in the process. The closed-loop gain of U1

must be set to make up for this 20% loss in amplitude. This gives rise to the gain expression shown in

Equation 1, which is based on a getting a 2 VPP output with a 0.8 VPP input:

(1)

R3will produce a negative shift at the output due to VS(3.3 V in this case). R3must be set so that the Video In

sync tip (−0.3 V at RTor 0.61 V at U1 noninverting input) corresponds to near 0 V at the output.

(2)

Equation 1 and Equation 2 must be solved simultaneously to arrive at the values of R3, RF, and RGwhich will

satisfy both. From the data sheet, one can set RF= 620 Ωto be close to the recommended value for a gain of

+2. It is easier to solve for RGand R3by starting with a good estimate for one and iteratively solving Equation 1

and Equation 2 to arrive at the results. Here is one possible iteration cycle for reference:

RF= 620 Ω(3)

Product Folder Links: LMH6601 LMH6601-Q1

-3 dB_BW = 0.35

RISE/FALL_TIME =0.35

6.8 ns =52 MHz

RISE/FALL_TIME = PIXEL_TIME

3=20.3 ns

3=6.8 ns

PIXEL_TIME (ns) = REFRESH_RATE

H x V

1x KH x KV

x 1 x 105

= 75 Hz

800 x 600

1x 76 x 96 x 1 x 105 = 20.3 ns

LMH6601

LMH6601-Q1

www.ti.com

SNOSAK9F –JUNE 2006–REVISED JUNE 2015

Application Information (continued)

Table 1. Finding External Resistor Values by Iteration for Figure 53

ESTIMATE CALCULATED Equation 1 LHS COMMENT

RG(Ω) (from Equation 2) CALCULATED (COMPARE Equation 1 LHS calculated to RHS)

R3 (Ω)

1k 1.69k 0.988 Increase Equation 1 LHS by reducing RG

820 1.56k 1.15 Increase Equation 1 LHS by reducing RG

620 1.37k 1.45 Increase Equation 1 LHS by reducing RG

390 239 4.18 Reduce Equation 1 LHS by increasing RG

560 1.30k 1.59 Close to target value of 1.5V/V for Equation 1

The final set of values for RGand R3in Table 1 are values which will result in the proper gain and correct video

levels (0 V to 1 V) at the output (VLOAD).

8.1.2 How to Pick the Right Video Amplifier

Apart from output current drive and voltage swing, the op amp used for a video amplifier and cable driver should

also possess the minimum requirement for speed and slew rate. For video type loads, it is best to consider Large

Signal Bandwidth (or LSBW in the TI data sheet tables) as video signals could be as large as 2 VPP when

applied to the commonly used gain of +2 configuration. Because of this relatively large swing, the op amp Slew

Rate (SR) limitation should also be considered. Table 2 shows these requirements for various video line rates

calculated using a rudimentary technique and intended as a first-order estimate only.

Table 2. Rise Time, −3 dB BW, and Slew Rate Requirements for Various Video Line Rates

VIDEO LINE RATE REFRESH HORIZONTA VERTICAL PIXEL TIME RISE TIME LSBW SR

STANDARD (HxV) RATE L ACTIVE (ns) (ns) (MHz) (V/μs)

(Hz) ACTIVE (KV%)

(KH%)

TV_NTSC 451x483 30 84 92 118.3 39.4 9 41

VGA 640x480 75 80 95 33 11 32 146

SVGA 800x600 75 76 96 20.3 6.8 52 237

XGA 1024x768 75 77 95 12.4 4.1 85 387

SXGA 1280x1024 75 75 96 7.3 2.4 143 655

UXGA 1600x1200 75 74 96 4.9 1.6 213 973

For any video line rate (HxV corresponding to the number of Active horizontal and vertical lines), the speed

requirements can be estimated if the Horizontal Active (KH%) and Vertical Active (KV%) numbers are known.

These percentages correspond to the percentages of the active number of lines (horizontal or vertical) to the total

number of lines as set by VESA standards. Here are the general expressions and the specific calculations for the

SVGA line rate shown in Table 2.

(4)

Requiring that an “On” pixel is illuminated to at least 90 percent of its final value before changing state will result

in the rise/fall time equal to, at most, ⅓the pixel time as shown in Equation 5:

(5)

Assuming a single pole frequency response roll-off characteristic for the closed-loop amplifier used, we have:

(6)

Product Folder Links: LMH6601 LMH6601-Q1

0.1 1 10 100

100

200

300

400

500

600

CAPACITANCE (pF)

REVERSED BIAS VOLTAGE (V)

T = 23°C

PIN-RD100

PIN-RD100A

PIN-RD15

PIN-RD07

VBIAS

CDCA

LMH6601

VOUT

SR(V/Ps) = 1.6V

RISE/FALL_TIME (ns) =1.6V

6.8 ns= 237(V/Ps)

x 1 x 103

LMH6601

LMH6601-Q1

SNOSAK9F –JUNE 2006–REVISED JUNE 2015

www.ti.com

Rise/Fall times are 10%-90% transition times, which for a 2 VPP video step would correspond to a total voltage

shift of 1.6V (80% of 2 V). So, the Slew Rate requirement can be calculated as follows:

(7)

The LMH6601 specifications show that it would be a suitable choice for video amplifiers up to and including the

SVGA line rate as demonstrated above.

For more information about this topic and others relating to video amplifiers, see Application Note 1013, Video

Amplifier Design for Computer Monitors (SNVA031).

8.1.3 Current to Voltage Conversion (Transimpedance Amplifier (TIA)

Being capable of high speed and having ultra low input bias current makes the LMH6601 a natural choice for

Current to Voltage applications such as photodiode I-V conversion. In these type of applications, as shown in

Figure 54, the photodiode is tied to the inverting input of the amplifier with RFset to the proper gain (gain is

measured in Ω).

Figure 54. Typical Connection of a Photodiode Detector to an Op Amp

With the LMH6601 input bias current in the femto-amperes range, even large values of gain (RF) do not increase

the output error term appreciably. This allows circuit operation to a lower light intensity level which is always of

special importance in these applications. Most photo-diodes have a relatively large capacitance (CD) which would

be even larger for a photo-diode designed for higher sensitivity to light because of its larger area. Some

applications may run the photodiode with a reverse bias to reduce its capacitance with the disadvantage of

increased contributions from both dark current and noise current. Figure 55 shows a typical photodiode

capacitance plot vs. reverse bias for reference.

Figure 55. Typical Capacitance vs. Reverse Bias (Source: OSI Optoelectronics)

Product Folder Links: LMH6601 LMH6601-Q1

2SRFCIN

f-3 dB GBWP

CF = CIN

2S(GBWP)RF

NOISE GAIN (NG)

OP AMP OPEN-

LOOP GAIN

I-V GAIN (Ω)

GAIN (dB)

0 dB

FREQUENCY

1 + sRF(CIN + CF)

1 + sRFCF

1 + CIN

GBWP

fz=1

2 Rπ FCIN

fP=1

2 Rπ FCF

LMH6601

LMH6601-Q1

www.ti.com

SNOSAK9F –JUNE 2006–REVISED JUNE 2015

The diode capacitance (CD) combined with the input capacitance of the LMH6601 (CA) has a bearing on the

stability of this circuit and how it is compensated. With large transimpedance gain values (RF), the total combined

capacitance on the amplifier inverting input (CIN = CD+ CA) will work against RFto create a zero in the Noise

Gain (NG) function (see Figure 56). If left untreated, at higher frequencies where NG equals the open-loop

transfer function excess phase shift around the loop (approaching 180°) and therefore, the circuit could be

unstable. This is illustrated in Figure 56.

Figure 56. Transimpedance Amplifier Graphical Stability Analysis and Compensation

Figure 56 shows that placing a capacitor, CF, with the proper value, across RFwill create a pole in the NG

function at fP. For optimum performance, this capacitor is usually picked so that NG is equal to the open-loop

gain of the op amp at fP. This will cause a “flattening” of the NG slope beyond the point of intercept of the two

plots (open-loop gain and NG) and will results in a Phase Margin (PM) of 45° assuming fPand fZare at least a

decade apart. This is because at the point of intercept, the NG pole at fPwill have a 45° phase lead contribution

which leaves 45° of PM. For reference, Figure 56 also shows the transimpedance gain (I-V (Ω))

Here is the theoretical expression for the optimum CFvalue and the expected −3-dB bandwidth:

(8)

(9)

Table 3 lists the results, along with the assumptions and conditions, of testing the LMH6601 with various

photodiodes having different capacitances (CD) at a transimpedance gain (RF) of 10 kΩ.

Table 3. Transimpedance Amplifier Compensation and Performance Results for Figure 54

CDCIN CF_CALCULATED CFUSED −3 dB BW −3 dB BW STEP RESPONSE

(pF) (pF) (pF) (pF) CALCULATED MEASURED (MHz) OVERSHOOT (%)

(MHz)

10 12 1.1 1 14 15 6

50 52 2.3 3 7 7 4

500 502 7.2 8 2 2.5 9

CA= 2 pF GBWP = 155 MHz VS= 5 V (10)

8.1.4 Transimpedance Amplifier Noise Considerations

When analyzing the noise at the output of the I-V converter, it is important to note that the various noise sources

(that is, op amp noise voltage, feedback resistor thermal noise, input noise current, photodiode noise current) do

not all operate over the same frequency band. Therefore, when the noise at the output is calculated, this should

be taken into account.

Product Folder Links: LMH6601 LMH6601-Q1

2 k:

VOUT

LMH6601

RGRF

VIN

LMH6601

VOUT

10 k:RSCD

VBIAS 1000 pF

RF = 10 M: to 10 G:

RS = 1 M: or SMALLER FOR HIGH COUNTING RATES

CF = 1 pF

CD = 1 pF to 10 PF

VOUT = Q/CF WHERE Q is CHARGE

CREATED BY ONE PHOTON or PARTICLE

ADJUST VBIAS FOR MAXIMUM SNR

LMH6601

LMH6601-Q1

SNOSAK9F –JUNE 2006–REVISED JUNE 2015

www.ti.com

The op amp noise voltage will be gained up in the region between the noise gain’s “zero” and its “pole” (fzand fp

in Figure 56). The higher the values of RFand CIN, the sooner the noise gain peaking starts and therefore its

contribution to the total output noise would be larger. It is obvious to note that it is advantageous to minimize CIN

(for example, by proper choice of op amp, by applying a reverse bias across the diode at the expense of excess

dark current and noise). However, most low noise op amps have a higher input capacitance compared to

ordinary op amps. This is due to the low noise op amp’s larger input stage.

8.1.5 Charge Preamplifier

Figure 57. Charge Preamplifier Taking Advantage of the Femto-Ampere Range Input Bias Current of the

LMH6601

8.1.6 Capacitive Load

The LMH6601 can drive a capacitive load of up to 1000 pF with correct isolation and compensation. Figure 58

illustrates the in-loop compensation technique to drive a large capacitive load.

Figure 58. In-Loop Compensation Circuit for Driving a Heavy Capacitive Load

When driving a high-capacitive load, an isolation resistor (RS) should be connected in series between the op amp

output and the capacitive load to provide isolation and to avoid oscillations. A small-value capacitor (CF) is

inserted between the op amp output and the inverting input as shown such that this capacitor becomes the

dominant feedback path at higher frequency. Together these components allow heavy capacitive loading while

keeping the loop stable.

There are few factors which affect the driving capability of the op amp:

• Op amp internal architecture

• Closed-loop gain and output capacitor loading

Table 4 shows the measured step response for various values of load capacitors (CL), series resistor (RS) and

feedback resistor (CF) with gain of +2 (RF= RG= 604 Ω) and RL=2kΩ:

Product Folder Links: LMH6601 LMH6601-Q1

620:

75:

VOUT

LMH6601

U1 CO

220 PF

CABLE

VIN

CG2

47 PF+

CIN

0.47 PF

510 k:

RIN

75:

10 100 1000

RISE TIME (ns)

CAP LOAD CL (pF)

LMH6601

LMH6601-Q1

www.ti.com

SNOSAK9F –JUNE 2006–REVISED JUNE 2015

Table 4. LMH6601 Step Response Summary for the Circuit of Figure 58

CLRSCFtrise/ tfall OVERSHOOT

(pF) (Ω) (pF) (ns) (%)

10 0 1 6(1) 8

50 0 1 7(1) 6

110 47 1 10 16

300 6 10 12 20

500 80 10 33 10

910 192 10 65 10

(1) Response limited by input step generator rise time of 5 ns

Figure 59 shows the increase in rise/fall time (bandwidth decrease) at VOUT with larger capacitive loads,

illustrating the trade-off between the two:

Figure 59. LMH6601 In-Loop Compensation Response

8.2 Typical Application

8.2.1 SAG Compensation for AC-Coupled Video

Many monitors and displays accept AC-coupled inputs. This simplifies the amplification and buffering task in

some respects. The capacitors shown in Figure 60 (except CG2), and especially CO, are the large electrolytic type

which are considerably costly and take up valuable real estate on the board. It is possible to reduce the value of

the output coupling capacitor, CO, which is the largest of all, by using what is called SAG compensation. SAG

refers to what the output video experiences due to the low frequency video content it contains which cannot

adequately go through the output AC-coupling scheme due to the low frequency limit of this circuit. The −3 dB

low frequency limit of the output circuit is given by:

f_low_frequency (−3 dB)= 1/ (2*π* 75*2(Ω) * Co) = ∼4.82 Hz for CO = 220 μF (11)

Figure 60. AC-Coupled Video Amplifier and Driver

Product Folder Links: LMH6601 LMH6601-Q1

VCC_5V RO

75:

LMH6601

68 PFCABLE

VCC_5V

CIN

0.47 PFR1

510 k:

2 k:R3

1 k:

22 PF

680:

VIN VO

75:RL

75:

LMH6601

LMH6601-Q1

SNOSAK9F –JUNE 2006–REVISED JUNE 2015

www.ti.com

Typical Application (continued)

8.2.2 Design Requirements

As shown in Figure 60, R1and R2simply set the input to the center of the input linear range while CIN AC

couples the video onto the input of the op amp. The op amp is set for a closed-loop gain of 2 with RFand RG. CG

is there to make sure the device output is also biased at mid-supply. Because of the DC bias at the output, the

load must be AC-coupled as well through CO. Some applications implement a small valued ceramic capacitor

(not shown) in parallel with COwhich is electrolytic. The reason for this is that the ceramic capacitor will tend to

shunt the inductive behavior of the Electrolytic capacitor at higher frequencies for an improved overall low

impedance output.

CG2 is intended to boost the high-frequency gain to improve the video frequency response. This value is to be set

and trimmed on the board to meet the specific system requirements of the application.

A possible implementation of the SAG compensation is shown in Figure 61.

Figure 61. AC-Coupled Video Amplifier/Driver With SAG Compensation

8.2.3 Detailed Design Procedure

In the circuit of Figure 61, the output coupling capacitor value and size is reduced at the expense of a slightly

more complicated circuitry. Note that C1is not only part of the SAG compensation, but it also sets the amplifier’s

DC gain to 0 dB so that the output is set to mid-rail for linearity purposes. Also, exceptionally high values are

chosen for the R1and R2biasing resistors (510 kΩ). The LMH6601 has extremely low input bias current which

allows this selection thereby reducing the CIN value in this circuit such that CIN can even be a nonpolar capacitor

which will reduce cost.

At high enough frequencies where both CO and C1 can be considered to be shorted out, R3shunts R4and the

closed-loop gain is determined by:

Closed_loop_Gain (V/V) = VL/VIN = (1+ (R3||R4)/ R5) x [RL/(RL+RO)]= 0.99 V/V (12)

At intermediate frequencies, where the CO, RO, RLpath experiences low frequency gain loss, the R3, R5, C1path

provides feedback from the load side of CO. With the load side gain reduced at these lower frequencies, the

feedback to the op amp inverting node reduces, causing an increase at the output of the op amp as a response.

For NTSC video, low values of COinfluence how much video black level shift occurs during the vertical blanking

interval (∼1.5 ms) which has no video activity and thus is sensitive to the charge dissipation of the COthrough the

load which could cause output SAG. An especially tough pattern is the NTSC pattern called “Pulse & Bar.” With

this pattern the entire top and bottom portion of the field is black level video where, for about 11 ms, COis

discharging through the load with no video activity to replenish that charge.

Product Folder Links: LMH6601 LMH6601-Q1

2Vp-p

(A)

50% DUTY CYCLE

NO CLIPPING

(B)

LOW DUTY CYCLE

CLIPPED POSITIVE

(C)

HIGH DUTY CYCLE

CLIPPED NEGATIVE

4.0V (+) CLIPPING

2.5V

1.0V (-) CLIPPING

4.0V (+) CLIPPING

2.5V

1.0V (-) CLIPPING

4.0V (+) CLIPPING

2.5V

1.0V (-) CLIPPING

LMH6601

LMH6601-Q1

www.ti.com

SNOSAK9F –JUNE 2006–REVISED JUNE 2015

Typical Application (continued)

8.2.4 Application Curves

Figure 62 shows the output of the Figure 61 circuit highlighting the SAG.

Figure 62. AC-Coupled Video Amplifier/Driver Output Scope Photo Showing Video SAG

With the circuit of Figure 61 and any other AC-coupled pulse amplifier, the waveform duty cycle variations exert

additional restrictions on voltage swing at any node. This is illustrated in the waveforms shown in Figure 63.

If a stage has a 3 VPP unclipped swing capability available at a given node, as shown in Figure 63, the maximum

allowable amplitude for an arbitrary waveform is ½ of 3 V or 1.5 VPP. This is due to the shift in the average value

of the waveform as the duty cycle varies. Figure 63 shows what would happen if a 2 VPP signal were applied. A

low duty cycle waveform, such as the one in Figure 63B, would have high positive excursions. At low enough

duty cycles, the waveform could get clipped on the top, as shown, or a more subtle loss of linearity could occur

prior to full-blown clipping. The converse of this occurs with high duty cycle waveforms and negative clipping, as

depicted in Figure 63C.

Figure 63. Headroom Considerations With AC-Coupled Amplifiers

Product Folder Links: LMH6601 LMH6601-Q1

LMH6601

LMH6601-Q1

SNOSAK9F –JUNE 2006–REVISED JUNE 2015

www.ti.com

9 Power Supply Recommendations

The LMH6601 can operate off a single-supply or with dual supplies. The input CM capability of the parts (CMVR)

extends all the way down to the V- rail to simplify single-supply applications. Supplies should be decoupled with

low-inductance, often ceramic, capacitors to ground less than 0.5 inches from the device pins. TI recommends

the use of ground plane, and as in most high-speed devices, it is advisable to remove ground plane close to

device sensitive pins such as the inputs.

10 Layout

10.1 Layout Guidelines

Generally, a good high-frequency layout will keep power supply and ground traces away from the inverting input

and output pins. Parasitic capacitances on these nodes to ground will cause frequency response peaking and

possible circuit oscillations (see Application Note OA-15, Frequent Faux Pas in Applying Wideband Current

Feedback Amplifiers,SNOA367, for more information).

10.2 Layout Examples

SC-70 Board Layout (Actual size = 1.5 in × 1.5 in

Figure 64. Layer 1 Silk

SC-70 Board Layout (Actual size = 1.5 in × 1.5 in

Figure 65. Layer 2 Silk

Product Folder Links: LMH6601 LMH6601-Q1

LMH6601

LMH6601-Q1

www.ti.com

SNOSAK9F –JUNE 2006–REVISED JUNE 2015

11 Device and Documentation Support

11.1 Documentation Support

11.1.1 Related Documentation

For additional information, see the following:

• Application Note 1013, Video Amplifier Design for Computer Monitors,SNVA031

• Application Note OA-15, Frequent Faux Pas in Applying Wideband Current Feedback Amplifiers,SNOA367

11.2 Related Links

The table below lists quick access links. Categories include technical documents, support and community

resources, tools and software, and quick access to sample or buy.

Table 5. Related Links

TECHNICAL TOOLS & SUPPORT &

PARTS PRODUCT FOLDER SAMPLE & BUY DOCUMENTS SOFTWARE COMMUNITY

LMH6601 Click here Click here Click here Click here Click here

LMH6601-Q1 Click here Click here Click here Click here Click here

11.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

11.4 Trademarks

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

11.5 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

11.6 Glossary

SLYZ022 —TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Product Folder Links: LMH6601 LMH6601-Q1

PACKAGE OPTION ADDENDUM

www.ti.com 11-Sep-2016

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

LMH6601MG/NOPB ACTIVE SC70 DCK 6 1000 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 A95

LMH6601MGX/NOPB ACTIVE SC70 DCK 6 3000 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 A95

LMH6601QMG/NOPB ACTIVE SC70 DCK 6 1000 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 AKA

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

PACKAGE OPTION ADDENDUM

www.ti.com 11-Sep-2016

Addendum-Page 2

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF LMH6601, LMH6601-Q1 :

•Catalog: LMH6601

•Automotive: LMH6601-Q1

NOTE: Qualified Version Definitions:

•Catalog - TI's standard catalog product

•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

LMH6601MG/NOPB SC70 DCK 6 1000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3

LMH6601MGX/NOPB SC70 DCK 6 3000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3

LMH6601QMG/NOPB SC70 DCK 6 1000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3

PACKAGE MATERIALS INFORMATION

www.ti.com 10-Aug-2016

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

LMH6601MG/NOPB SC70 DCK 6 1000 210.0 185.0 35.0

LMH6601MGX/NOPB SC70 DCK 6 3000 210.0 185.0 35.0

LMH6601QMG/NOPB SC70 DCK 6 1000 210.0 185.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 10-Aug-2016

Pack Materials-Page 2

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