2018 - 2019 Microchip Technology Inc. DS20006085B-page 1
MIC5166
Features
• Operating Voltage Range:
-V
DDQ Supply: 0.9V to 3.6V
- Bias Supply: 2.5V to 5.5V
• High Bandwidth: Very Fast Transient Response
• Stable with Two 10 µF Ceramic Output Capacitors
• Two 10 µF Output Capacitors used in Most
Applications
• High Output Voltage Accuracy:
- 0.015% Line Regulation
- 1.5% Load Regulation
• Logic Level Enable Input
• Power Good (PG)
• Thermally Enhanced 3 mm x 3 mm DFN
• Junction Temperature Range –40°C to +125°C
• This Device Meets DDR4 Requirements
Applications
• Desktop Computers
• Notebook Computers
• Datacom Systems
•Servers
• Video Cards
General Description
The MIC5166 is a 3A, high-speed, linear, low VIN,
double data rate (DDR), memory terminator power
supply. The part is small and requires small output
capacitors, making it a tiny overall solution. This allows
it to be conveniently placed close to the DDR memory,
minimizing circuit board layout inductance that may
cause excessive voltage ripple at the DDR memory.
The MIC5166 contains a precision voltage divider
network in order to take in the VDDQ voltage as a
reference voltage and conveniently output the
terminator voltage (VTT) at one half of the VDDQ input
voltage.
The MIC5166 is capable of sinking and sourcing up to
3A. It is stable with only two 10 µF ceramic output
capacitors. The part is available in a small 3 mm x
3 mm DFN thermally-enhanced package.
The MIC5166 has a high-side NMOS output stage
offering very low output impedance, and very high
bandwidth. The NMOS output stage offers a unique
ability to respond very quickly to sudden load changes
such as is required for DDR memory termination power
supply applications.
Package Type
MIC5166
10-Lead 3 mm x 3 mm DFN (ML)
(Top View)
AGND
BIAS
VREF
VDDQ
PG SNS
EN
PGND
VTT
VIN
EP
110
2
3
4
56
7
8
9
3A High-Speed, Low-VIN DDR Terminator
MIC5166
DS20006085B-page 2 2018 - 2019 Microchip Technology Inc.
Typical Application Circuit
Functional Block Diagram
VTT
1.0μF
PGND 22μF
AGNDPG
EP
VREF
1.0μF
MIC5166
BIAS
10Nȍ SNS
10μF
VIN
PG
9
1
3
6
2
7
8
10
4.7μF
4
VDDQ
EN
EN
5
VBIAS
2.5V TO 5.5V
VIN
0.9V TO 3.6V
VDDQ
0.9V TO 3.6V
VTT
±3A
VREF
10mA
PG
2x10μF
MIC5166
EN
VTT
SNS
EN
PGND
BIAS
VIN
10μF
CONTROL
LOGIC
UVLO
THERMAL
SHUTDOWN
V
BIAS
2.5V TO 5.5V
10Nȍ
45Nȍ
5Nȍ
5Nȍ
1.0μF
45Nȍ
4.7μF
90%
VREF
110%
VREF
PG
VDDQ
VREF
AGND
V
DDQ
0.9V TO 3.6V
UVLO
1μF
EP
V
IN
0.9V TO 3.6V
V
TT
±3A
V
BIAS
2018 - 2019 Microchip Technology Inc. DS20006085B-page 3
MIC5166
1.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings †
VBIAS ............................................................................................................................................................ –0.3V to +6V
VIN..............................................................................................................................................................–0.3V to VBIAS
VDDQ ..............................................................................................................................................................–0.3V to VIN
VTT .................................................................................................................................................................–0.3V to VIN
VEN............................................................................................................................................................. –0.3V to VBIAS
VPG.............................................................................................................................................................–0.3V to VBIAS
PGND to AGND ........................................................................................................................................ –0.3V to +0.3V
Junction Temperature (TJ)..................................................................................................................................... +150°C
Storage Temperature (TS)...................................................................................................................... –65°C to +150°C
Lead Temperature (Soldering, 10 sec.)................................................................................................................. +260°C
Continuous Power Dissipation (TA = +25°C; De-Rated 16.4 mW/°C above 25°C).................................................1.64W
Continuous Power Dissipation (TA = +85°C) .......................................................................................................656 mW
ESD Rating (HBM, Note 1) ........................................................................................................................................ 2 kV
Operating Ratings ††
Supply Voltage (VBIAS).............................................................................................................................. +2.5V to +5.5V
Supply Voltage (VIN, Note 2)..................................................................................................................... +0.9V to +3.6V
Supply Voltage (VDDQ, Note 3)...................................................................................................................... +0.9V to VIN
Power Good Voltage (VPG) .............................................................................................................................0V to VBIAS
Enable Input Voltage (VEN) .............................................................................................................................0V to VBIAS
Junction Temperature Range (TJ) .......................................................................................................... –40°C to +125°C
Package Thermal Resistance
3 mm x 3 mm DFN (JC) ....................................................................................................................................28.7°C/W
3 mm x 3 mm DFN (JA) ....................................................................................................................................60.7°C/W
† Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at those or any other conditions above those indicated
in the operational sections of this specification is not intended. Exposure to maximum rating conditions for extended
periods may affect device reliability.
†† Notice: The device is not guaranteed to function outside its operating ratings.
Note 1: Devices are ESD sensitive. Handling precautions recommended. Human body model, 1.5 k in series with
100 pF.
2: If VBIAS 3.6V, then VIN(MAX) = VBIAS.
3: If VBIAS 4V, then VDDQ(MAX) = 2 x (VBIAS – 2.2V). If VBIAS > 4V, then VDDQ(MAX) = 3.6V.
MIC5166
DS20006085B-page 4 2018 - 2019 Microchip Technology Inc.
ELECTRICAL CHARACTERISTICS
Electrical Characteristics: VIN = 1.5V, VBIAS = 3.3V, VDDQ = 1.5V, TA = +25°C, unless noted. Bold values indicate
–40°C TJ +125°C. Note 1
Parameter Sym. Min. Typ. Max. Units Conditions
Power Input Supply
Input Voltage Range VIN 0.9 —3.6 V—
Undervoltage Lockout Trip
Level —0.625 0.8 0.9 VV
IN rising
UVLO Hysteresis — — 150 — mV —
Quiescent Supply Current IIN —0.110µAI
OUT = 0A
Shutdown Current ISHDN —0.1 5 µAV
EN = 0V
Bias Supply
Bias Voltage Range VBIAS 2.5 —5.5 V—
Undervoltage Lockout Trip
Level —1.9 2.23 2.33 VV
BIAS rising
UVLO Hysteresis — — 70 — mV —
Quiescent Supply Current IBIAS
—1.6 3mA IOUT = 1 mA
—1.6 3IOUT = 1A
Shutdown Current ISHDN —0.1 5 µAV
EN = 0V
VTT Output
VTT Accuracy — –25 —25 mV Variation from VREF, IOUT = –2A to 2A
Load Regulation — —1.52.1 %VSNS = 0.75V, IOUT = +10 mA to +3A
–1.8 –1.4 — VSNS = 0.75V, IOUT = –10 mA to –3A
Line Regulation —
–0.05 0.005 0.05
%/V
VIN = 1.5V to 3.6V, VBIAS = 5.5V, IOUT =
100 mA
–0.1 0.015 0.17 VIN = 1.5V, VBIAS = 2.5V to 5.5V, IOUT =
100 mA
VREF Output
VREF Voltage Accuracy VREF –1 —1%
Variation from (VDDQ/2),
IREF = –10 mA to 10 mA,
VREF Output = 0.6V (DDR4), IOUT = 0A.
Bias Supply Dropout Voltage
Dropout Voltage
(VBIAS – VTT)VDO
—1.15—
V
IOUT = 100 mA
—1.25— I
OUT = 500 mA
—1.652.2 IOUT = 3A
Enable Control
EN Logic High Level VIH 1.2 —— VLogic high
EN Logic Low Level VIL ——0.2 Logic low
EN Current IEN
—1.0—µA VEN = 0.2V
—6.0— V
EN = 1.2V
Start-Up Time tSU —55—µs
From EN pin going high to VTT 90% of
VREF
Note 1: Specification for packaged product only.
2018 - 2019 Microchip Technology Inc. DS20006085B-page 5
MIC5166
Short-Current Protection
Sourcing Current Limit ILIM 3.1 4.9 7.8 AV
IN = 2.7V, VTT = 0V
Sinking Current Limit ILIM –3.1 –4.9 –7.8 AV
IN = 2.7V, VTT = VIN
Internal FETs
Top MOSFET RDS(ON) — 130 190 mSource, IOUT = 3A (VTT to PGND)
Bottom MOSFET RDS(ON) — 130 190 mSink, IOUT = –3A (VIN to VTT)
Power Good (PG)
PG Window — 90 — 110 % Threshold percent of VTT from VREF
Hysteresis — — 2 — % —
PG Output Low Voltage — — 430 — mV IPG = 4 mA (sinking)
PG Leakage Current — — — 1.0 µA VPG = 5.5V, VSNS = VREF
Thermal Protection
Overtemperature
Shutdown — — 150 — °C TJ rising
Overtemperature
Shutdown Hysteresis ——10—°C—
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Characteristics: VIN = 1.5V, VBIAS = 3.3V, VDDQ = 1.5V, TA = +25°C, unless noted. Bold values indicate
–40°C TJ +125°C. Note 1
Parameter Sym. Min. Typ. Max. Units Conditions
Note 1: Specification for packaged product only.
MIC5166
DS20006085B-page 6 2018 - 2019 Microchip Technology Inc.
TEMPERATURE SPECIFICATIONS
Parameters Sym. Min. Typ. Max. Units Conditions
Temperature Ranges
Junction Temperature Range TJ–40 — +125 °C —
Maximum Junction Temperature TJ(MAX) — — +150 °C —
Lead Temperature — — — +260 °C Soldering, 10 sec.
Storage Temperature Range TS–65 — +150 °C —
Package Thermal Resistances
Thermal Resistance, 3x3 DFN 10-Ld JC —28.7 —°C/W—
Thermal Resistance, 3x3 DFN 10-Ld JA —60.7 —°C/W—
Note 1: The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable
junction temperature and the thermal resistance from junction to air (i.e., TA, TJ, JA). Exceeding the
maximum allowable power dissipation will cause the device operating junction temperature to exceed the
maximum +125°C rating. Sustained junction temperatures above +125°C can impact the device reliability.
2018 - 2019 Microchip Technology Inc. DS20006085B-page 7
MIC5166
2.0 TYPICAL PERFORMANCE CURVES
FIGURE 2-1: VIN Operating Supply
Current vs. Input Voltage.
FIGURE 2-2: VIN Shutdown Current vs.
Input Voltage.
FIGURE 2-3: VREF/VDDQ Tracking Ratio
vs. VDDQ Voltage.
FIGURE 2-4: VBIAS Operating Supply
Current vs. BIAS Voltage.
FIGURE 2-5: VBIAS Shutdown Current vs.
BIAS Voltage.
FIGURE 2-6: VREF/VDDQ Tracking Ratio
vs. BIAS Voltage.
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
MIC5166
DS20006085B-page 8 2018 - 2019 Microchip Technology Inc.
FIGURE 2-7: Enable Threshold vs. Input
Voltage.
FIGURE 2-8: Enable Pin Current vs. Input
Voltage.
FIGURE 2-9: Power Good Window/VTT
Ratio vs. Input Voltage.
FIGURE 2-10: Top MOSFET
On-Resistance vs. Input Voltage.
FIGURE 2-11: Bottom MOSFET
On-Resistance vs. Input Voltage.
FIGURE 2-12: Current Limit vs. Input
Voltage.
2018 - 2019 Microchip Technology Inc. DS20006085B-page 9
MIC5166
FIGURE 2-13: Load Regulation vs. Input
Voltage.
FIGURE 2-14: VREF – VTT vs. I_Load.
FIGURE 2-15: VTT vs. I_Load.
FIGURE 2-16: VREF/VDDQ vs. I_Load.
FIGURE 2-17: VTT/VDDQ vs. I_Load.
FIGURE 2-18: VIN Operating Supply
Current vs. Temperature.
MIC5166
DS20006085B-page 10 2018 - 2019 Microchip Technology Inc.
FIGURE 2-19: VIN Shutdown Current vs.
Temperature.
FIGURE 2-20: VIN UVLO Threshold vs.
Temperature.
FIGURE 2-21: Enable Threshold vs.
Temperature.
FIGURE 2-22: Sourcing Load Regulation
vs. Temperature.
FIGURE 2-23: Sinking Load Regulation vs.
Temperature.
FIGURE 2-24: VREF/VDDQ Tracking Ration
vs. Temperature.
2018 - 2019 Microchip Technology Inc. DS20006085B-page 11
MIC5166
FIGURE 2-25: Output Voltage vs.
Temperature.
FIGURE 2-26: Current Limit vs.
Temperature.
FIGURE 2-27: Enable Pin Current vs.
Temperature.
FIGURE 2-28: Top MOSFET
On-Resistance vs. Temperature.
FIGURE 2-29: Bottom MOSFET
On-Resistance vs. Temperature.
FIGURE 2-30: EN Turn-On.
MIC5166
DS20006085B-page 12 2018 - 2019 Microchip Technology Inc.
FIGURE 2-31: EN Turn-Off.
FIGURE 2-32: VIN Turn-On (UVLO).
FIGURE 2-33: VIN Turn-Off UVLO.
FIGURE 2-34: VBIAS Turn-On (UVLO).
FIGURE 2-35: VBIAS Turn-Off (UVLO).
FIGURE 2-36: Load Transient (±3A).
2018 - 2019 Microchip Technology Inc. DS20006085B-page 13
MIC5166
FIGURE 2-37: Line Transient.
MIC5166
DS20006085B-page 14 2018 - 2019 Microchip Technology Inc.
3.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1: PIN FUNCTION TABLE
Pin Number Pin Name Description
1VREF
Reference Voltage. This output provides an output of the internal reference voltage
VDDQ/2. The VREF output is used to provide the reference voltage for the memory chip.
Connect a 1.0 µF capacitor to ground at this pin. This pin can sink and source 10 mA.
2BIAS
BIAS Supply Voltage. The BIAS supply is the power MOSFET gate drive supply volt-
age and the supply bus for the IC. The BIAS voltage must be greater than (VTT +
2.2V). A 1.0 µF ceramic capacitor from the BIAS pin to PGND must be placed next to
the IC.
3 AGND Analog Ground. Internal signal ground for all low-power circuits.
4 VDDQ Input Supply. VDDQ is connected to an internal precision divider that provides the
VREF. Connect a 4.7 µF capacitor to ground at this pin.
5PG
Power Good. This is an open-drain output that indicates when the output voltage is
within ±10% of the reference voltage. The PG flag is asserted typically with 65 µs delay
when the enable is set low or when the output goes outside ±10% the window thresh-
old.
6 SNS Feedback. Input to the error amplifier.
7EN
Enable. Logic level control of the output. Logic high enables the MIC5166 and a logic
low shuts down the MIC5166. In the off state, supply current of the device is greatly
reduced (typically 0.2 µA). The EN pin should not be left open.
8PGND
Power Ground. Internal ground connection to the source of the internal, low-side drive,
N-channel MOSFET.
9VTT
Power Output. This is the connection to the source of the internal high-side N-channel
MOSFET and drain of the low-side N-channel MOSFET. This is a high-frequency,
high-power connection, therefore two 10 µF output capacitors must be placed as close
to the IC as possible.
10 VIN
High-Side N-Channel MOSFET Drain Connection. The VIN operating voltage range is
from 0.9V to 3.6V. An input capacitor between the VIN pin and the PGND is required
as close to the chip as possible.
EP ePAD Exposed Pad. Must be connected to a GND plane for best thermal performance.
2018 - 2019 Microchip Technology Inc. DS20006085B-page 15
MIC5166
4.0 FUNCTIONAL DIAGRAM
DDR memory requires two power supplies: one for the
memory chip, referred to as VDDQ, and the other for a
termination supply, VTT, which is one-half VDDQ. With
memory speeds in excess of 300 MHz, the memory
system bus must be treated as a transmission line. To
maintain good signal integrity the memory bus must be
terminated to minimize signal reflections. Figure 4-1
shows the simplified termination circuit. Each control,
address and data lines have these termination resistors
RS and RT connected to them.
FIGURE 4-1: DDR Memory Termination
Circuit.
Bus termination provides a means to increase signaling
speed while maintaining good signal integrity. The
termination network consists of a series resistor (RS)
and a terminating resistor (RT). Values of RS range
between 10 to 30 with a typical of 22, while RT
ranges from 22 to 28 with a typical value of 25.
VREF must maintain half VDDQ with a ±1% tolerance,
while VTT will dynamically sink and source current to
maintain a termination voltage of ±40 mV from the
VREF line under all conditions. This method of bus
termination reduces common-mode noise, settling
time, voltage swings, EMI/RFI, and improves slew
rates.
VDDQ powers all the memory ICs, memory drivers and
receivers for all the memory bits in the DDR memory
system. The MIC5166 regulates VTT to VDDQ/2 during
sourcing or sinking current.
The memory bits are not usually all at a logic high or
logic low at the same time, so the VTT supply is usually
not sinking or sourcing –3A or +3A current
continuously.
4.1 VTT
VTT is regulated to VREF. Due to high-speed signaling,
the load current seen by VTT is constantly changing. To
maintain adequate transient response, two 10 µF
ceramic capacitors are required. The proper placement
of ceramic capacitors is important to reduce both ESR
and ESL such that high-current and high-speed
transients do not exceed the dynamic voltage tolerance
requirement of VTT. The ceramic capacitors provide
current during the fast edges of the bus transition.
Using several smaller ceramic capacitors distributed
near the termination resistors is important to reduce the
effects of PCB trace inductance.
4.2 VDDQ
The VDDQ input on the MIC5166 is used to create the
internal reference voltage for VTT. The reference
voltage is generated from an internal resistor divider
network of two 500 k resistors, generating a
reference voltage VREF that is VDDQ/2. The VDDQ input
should be Kelvin connected as close as possible to the
memory supply voltage.
Because the reference is simply VDDQ/2, any
perturbations on VDDQ will also appear at half the
amplitude on the reference. For this reason, a 4.7 µF
ceramic capacitor is required on the VDDQ supply. This
will aid performance by improving the source
impedance over a wide frequency range.
4.3 Sense
The sense (SNS) pin provides the path for the error
amplifier to regulate VTT. The SNS input must also be
Kelvin connected to the VTT bypass capacitors. If the
SNS input is connected too close to the MIC5166, the
IR drop of the PCB trace can cause the VTT voltage at
the memory chip to be too low. Placing the MIC5166 as
close as possible to the DDR memory will improve the
load regulation performance.
4.4 Enable
The MIC5166 features an active-high enable input (EN)
that allows on-off control of the regulator. The current
through the device reduces to near “zero” when the
device is shutdown, with only <0.2 µA of leakage
current. The EN input may be directly tied to VBIAS. The
active-high enable pin uses CMOS technology and the
enable pin cannot be left floating. A floating enable pin
may cause an indeterminate state on the output.
4.5 Power Good (PG)
The power good (PG) output provides an undervoltage
and overvoltage fault flag for the VTT output. The PG
output remains high as long as VTT is within ±10%
range of VREF and goes low if the output moves beyond
this range.
-
+
DDR
MEMORY
VTT
VDDQ
1.0μF
PGND
22μF
AGND
EN
EP
VREF
1.0μF
R
T
R
S
V
DDQ
1
.8V
MIC5166
-
+
CHIP SET
R
T
R
S
VDDQ VDDQ
VDDQ
VREF
+
BIAS
V
BIAS
SNS
10μF
VIN
EN
4.7μF
PGPG
10Nȍ
MIC5166
DS20006085B-page 16 2018 - 2019 Microchip Technology Inc.
FIGURE 4-2: Power Good Threshold.
The PG has an open-drain output. A pull-up resistor
must be connected to VBIAS, VIN, or an external source.
The external source voltage must not exceed the
maximum rating of the pin. The PG pin can be
connected to another regulator’s enable pin for
sequencing of the outputs.
4.6 VBIAS Requirement
A 1 µF ceramic input capacitor is required on the VBIAS
pin. To achieve the ultra-fast transient response, the
MIC5166 uses an all N-channel power output stage as
shown in the Functional Block Diagram. The high-side
N-channel MOSFET requires the VBIAS voltage to be
2.2V higher than the VTT to be able to fully enhance the
high-side MOSFET.
4.7 VIN Requirement
VIN is used to supply the rail voltage for the high-side
N-channel power output stage. It is normally connected
to VDDQ, but it can be connected to a lower voltage to
reduce power dissipation. In this case, the input voltage
must be higher than the VTT voltage to ensure that the
output stage is not operating in dropout.
V
REF
PG
0.90*V
REF
0.88*V
REF
0V
0V
1.10*V
REF
1.08*V
REF
2018 - 2019 Microchip Technology Inc. DS20006085B-page 17
MIC5166
5.0 COMPONENT SELECTION
5.1 Input Capacitor
A 10 µF ceramic input capacitor is all that is required for
most applications if it is close to a bulk capacitance.
The input capacitor must be placed on the same side of
the board and next to the MIC5166 to minimize the
dropout voltage and voltage ringing during transient
and short-circuit conditions. It is also recommended
that each capacitor to be connected to the PGND
directly, not through vias. X7R or X5R dielectric
ceramic capacitors are recommended because of their
temperature performance. X7R-type capacitors
change capacitance by 15% over their operating
temperature range and are the most stable type of
ceramic capacitors. Z5U and Y5V dielectric capacitors
change value by as much as 50% and 60%
respectively over their operating temperature ranges.
To use a ceramic chip capacitor with Y5V dielectric, the
value must be much higher than an X7R ceramic.
5.2 Output Capacitor
As part of the frequency compensation, the MIC5166
requires two 10 µF ceramic output capacitors for best
transient performance. To improve transient response,
any other type of capacitor can be placed in parallel as
long as the two 10 µF ceramic output capacitors are
placed next to the MIC5166.
The output capacitor type and placement criteria are
the same as the input capacitor. See the Input
Capacitor section for a detailed description.
5.3 Thermal Considerations
The MIC5166 is packaged in the 3 mm x 3 mm DFN, a
package that has excellent thermal performance. This
maximizes heat transfer from the junction to the
exposed pad (ePAD) that connects to the ground plane.
The size of the ground plane attached to the exposed
pad determines the overall thermal resistance from the
junction to the ambient air surrounding the printed
circuit board.
5.4 Thermal Design
The most complicated design parameters to consider
are thermal characteristics. Thermal design requires
the following application-specific parameters:
• Maximum ambient temperature (TA)
• Output current (IOUT)
• Output voltage (VOUT)
• Input voltage (VIN)
• Ground current (IGND)
First, calculate the power dissipation of the regulator
from these numbers and the device parameters from
this data sheet.
EQUATION 5-1:
For example, given an expected maximum ambient
temperature (TA) of 70°C with VIN = 1.2V, VBIAS = 3.3V,
VTT = 0.9V, and IOUT = 3A, first calculate the expected
PD using Equation 5-1:
EQUATION 5-2:
Next, determine the junction temperature for the
expected power dissipation above using the thermal
resistance (JA) of the 10-pin 3 mm x 3 mm DFN (YML)
adhering to the following criteria for the PCB design
(1oz. copper and 100 mm2 copper area for the
MIC5166):
EQUATION 5-3:
To determine the maximum power dissipation allowed
that would not exceed the IC’s maximum junction
temperature (125°C) when operating at a maximum
ambient temperature of 70°C:
EQUATION 5-4:
PDVIN VTT
–IOUT
VBIAS IGND
+=
Where:
IOUT = Approximated by using numbers from the
Electrical Characteristics or Typical Performance
Curves.
PD1.2V0.9V–3A3.3V+ 0.0016A0.90528W==
TJJA PD
TA
+=
TJ60.7C/W 0.90528W70C+=
TJ124.95C=
PDMAX TJMAX
TA
–
JA
=
PDMAX 125C70C–60.7C/W0.9061W==
MIC5166
DS20006085B-page 18 2018 - 2019 Microchip Technology Inc.
5.5 Thermal Measurements
It is always wise to measure the IC’s case temperature
to make sure that it is within its operating limits.
Although this might seem like a very elementary task, it
is very easy to get erroneous results. The most
common mistake is to use the standard thermocouple
that comes with the thermal voltage meter. This
thermocouple wire gauge is large, typically 22 gauge,
and behaves like a heat sink, resulting in a lower case
measurement.
There are two suggested methods for measuring the IC
case temperature: a thermocouple or an infrared
thermometer. If a thermocouple is used, it must be
constructed of 36 gauge wire or higher to minimize the
wire heat sinking effect. In addition, the thermocouple
tip must be covered in either thermal grease or thermal
glue to make sure that the thermocouple junction
makes good contact to the case of the IC. This
thermocouple from Omega (5SC-TT-K-36-36) is
adequate for most applications.
To avoid this messy thermocouple grease or glue, an
infrared thermometer is recommended. Most infrared
thermometers’ spot size is too large for an accurate
reading on small form factor ICs. However, an IR
thermometer from Optris has a 1 mm spot size, which
makes it ideal for the 3 mm x 3 mm DFN package.
5.6 Sequencing
The following diagrams illustrate methods for
connecting MIC5166s to achieve sequencing
requirements:
FIGURE 5-1: Turn-On Sequence with
Soft-Start (RC = 3.3 nF).
PVIN SW
FBPG
22μF
x4
VDDQ
1.8V/7A
1.0μH
PGND
47μF
x2
MIC22705
PG1
COMP
VIN
5.0V
EN/DLY
EN1
4Nȍ
SGND
20Nȍ
39pF
SVIN
RC
3.3nF
EP
DELAY
R1
1.10Nȍ
R2
69ȍ
VTT
1.0μF
22μF
AGND
EN
EP
VDDQ
4.7μF
MIC5166
BIAS
VDDQ SNS
10μF
VIN
EN2
VTT
0.9V/±3A
PG
PG2
PGND
VREF
1.0μF
VREF
10mA
EN/EN2
VDDQ
VTT
VIN = 5V
VDDQ = 1.8V
VTT = 0.9V
IOUT1 = 1A
IOUT2 = 1A
RC = 3.3nF
Time (4ms/div)
2018 - 2019 Microchip Technology Inc. DS20006085B-page 19
MIC5166
FIGURE 5-2: Turn-On Sequence without
Soft-Start (RC = Open).
VIN
5.0V
PG1
EN1
VDDQ
EN2
PG2
Nȍ
1.0μF
10μF
22μF
x4
PVIN
SVIN
PGND
PG
EN/DLY
RC
SW
EP
SGND
FB
DELAY
COMP
1.0μH
BIAS
VIN
PGND
EN
PG
VDDQ
VTT
SNS
EP
AGND
VREF
VDDQ
1.8V/7A
R1
Nȍ
R2
ȍ
39pF
Nȍ
4.7μF
VTT
0.9V/±3A
VREF
10mA
22μF
1.0μF
MIC22705
MIC5166
47μF
x2
EN/EN2
VDDQ
VTT
VIN = 5V
VDDQ = 1.8V
VTT = 0.9V
IOUT1 = 1A
IOUT2 = 1A
RC = OPEN
Time (4ms/div)
MIC5166
DS20006085B-page 20 2018 - 2019 Microchip Technology Inc.
6.0 PCB LAYOUT GUIDELINES
To minimize EMI and output noise, follow these layout
recommendations.
PCB layout is critical to achieve reliable, stable, and
efficient performance. A ground plane is required to
control EMI and minimize the inductance in power,
signal, and return paths.
The following guidelines should be followed to ensure
proper operation of the MIC5166 converter.
6.1 IC
• The 10 µF ceramic capacitor, which is connected
to the VIN pin, must be located right at the IC. The
VDDQ pin is very noise sensitive and placement
of the capacitor is very critical. Use wide traces to
connect to the VDDQ and AGND pins.
• The signal ground pin (AGND) must be connected
directly to the ground planes. Do not route the
AGND pin to the PGND Pad on the top layer.
• Place the IC close to the point-of-load (POL).
• Use wide traces to route the input and output
power lines.
• Signal and power grounds should be kept
separate and connected at only one location.
6.2 Input Capacitor
• A 10 µF X5R or X7R dielectric ceramic capacitor
is recommended on each of the VIN pins for
bypassing.
• Place the input capacitors on the same side of the
board and as close to the IC as possible.
• Keep both the VIN pin and PGND connections
short.
• Place several vias to the ground plane close to
the input capacitor ground terminal.
• Use either X7R or X5R dielectric input capacitors.
Do not use Y5V or Z5U type capacitors.
• Do not replace the ceramic input capacitor with
any other type of capacitor. Any type of capacitor
can be placed in parallel with the input capacitor.
• If a Tantalum input capacitor is placed in parallel
with the input capacitor, it must be recommended
for switching regulator applications and the
operating voltage must be derated by 50%.
• In hot-plug applications, a Tantalum or Electrolytic
bypass capacitor must be used to limit the
overvoltage spike seen on the input supply with
power is suddenly applied.
6.3 Output Capacitor
• Use a wide trace to connect the output capacitor
ground terminal to the input capacitor ground
terminal.
• Phase margin will change as the output capacitor
value and ESR changes. Contact the factory if the
output capacitor is different from what is shown in
the BOM.
• The feedback divider network must be place close
to the IC with the bottom of R2 connected to
AGND.
• The feedback trace should be separate from the
power trace and connected as close as possible
to the output capacitor. Sensing a long high
current load trace can degrade the DC load
regulation.
2018 - 2019 Microchip Technology Inc. DS20006085B-page 21
MIC5166
7.0 EVALUATION BOARD SCHEMATICS
FIGURE 7-1: U1 Schematic.
FIGURE 7-2: U2 Schematic.
5V_INPUT
TP19
R7 49.9
C7
39pF
TP18
C13
470μF/10V
C1
22μF/6.3V
C4
1nF
R6
1
10
2
8
1
7
11 16
U1
MIC22405YML
C10
47μF/6.3V
C11
47μF/6.3V
R3
20K
TP4
TP7
17
VIN
PVIN
SVIN
POR
EN
RC
DELAY
PVIN
3
5
SW
SW
SW
SW
FB
CF
COMP
9
PGND
PGND
SGND
J2
PGND
5VIN
C3
2.2μF/6.3V
R4
47.5K
C2
22μF
RC
C6
1nF
C5
OPEN
9
18
20
19
SW
1
L1 1μH
12
13
14
15
6
2
3
4
5
C8
390pF
C9
100pF R2
698
R1A
1.1K
R1B
1.1K
R1C
1.1K
R1D
1.1K
C12
1nF/50V
TP21
TP20
VIN
VDDQ
PG
GND
5VIN
VDDQ
VBIAS
VIN
J5
J8
J10
J7
TP1
R11 2.2
R8 2.2
C14
100μF/6.3V
TP9
C16
1μF/6.3V
C17
4.7μF
C18
1μF
R9
10k
1
1
2
3
4
56
7
8
9
10
U2
MIC5166YMM
C15
10μF/6.3V
C24
10μF/6.3V VTT
R10
1k
TP10
J9
GND
C19
22μF/6.3V
TP11
R12 0
3
VREF
VBIAS
AGND
VDDQ EN
EP
VIN
VTT
PGND
PG VSNS
MIC5166
DS20006085B-page 22 2018 - 2019 Microchip Technology Inc.
FIGURE 7-3: Evaluation Board Schematic.
U4
MIC1557YM5
C22
0.1μF
RV1
2
3
10K
R19
1K
11
53
4
T/T
OUT
GND
VS
CS
2
VBIAS
R20
100K C21
1μF
J15
BIAS
SOURCE
SINK
CLK_IN
1
2
3
TP15
TP13
1
2
1
2
1
TP16
R16
100K
R18
100K
U3
VBIAS
1
2
3
4
5
6
7
8
9
10 11
13
12
1A
1B
2A
2B
3A
3B
4A
4B
VCC
GND
1Y
2Y
3Y
4Y
14
C23
1μF
C20
10μF
VBIAS
J14
SN74AHCT00
U5
MIC4425
1
2
3
45
6
7
8
VS
INA
INB
GND
NC
OUTA
OUTB
NC
VIN
R13
R14
R15
TP22
1, 2, 3
4, 5, 6, 7, 8
4, 5, 6, 7, 8
1, 2, 3
1
TP14
Q3
SIR172DP
Q4
SIR172DP
J6
VTT
VTT
4
R21
2.2
R22
0.5
R23
0.5
R24
TP23
2018 - 2019 Microchip Technology Inc. DS20006085B-page 23
MIC5166
TABLE 7-1: BILL OF MATERIALS
Item Part Number Manufacturer Description Qty.
C1, C2,
C19
08056D226MAT AVX
22 µF, 6.3V, ceramic capacitor, X5R, 0805 3C2012X5R0J226K TDK
GRM21BR60J226ME39L Murata
C3
08056D225KAT2A AVX
2.2µF, 6.3V, ceramic capacitor, X5R, 0805 1C2012X5R0J225K TDK
GRM21BR60J225KA01L Murata
C4, C6,
C12
06035C102KAT AVX
1 nF, 50V, ceramic capacitor, X7R, 0603 3C1608X7R1H102K TDK
GRM188R71H102KA01D Murata
C7
06035A390JAT2A AVX
39 pF, 50V, ceramic capacitor, NPO, 0603 1C1608C0G1H390J TDK
GRM1885C1H390JA01D Murata
C8
06035A391JAT2A AVX
390 pF, 50V, ceramic capacitor, NPO, 0603 1C1608C0G1H391J TDK
GRM188R71H391KA01D Murata
C9
06035A101JAT2A AVX
100 pF, 50V, ceramic capacitor, NPO, 0603 1C1608C0G1H101J TDK
GRM1885C1H101JA01D Murata
C10, C11
12066D476MAT2A AVX
47µF, 6.3V, ceramic capacitor, X5R,1206 2C3216X5R0J476M TDK
GRM31CR60J476ME19L Murata
C14
12106D107MAT2A AVX
100 µF, 6.3V, ceramic capacitor, X5R, 1210 1C3225X5R0J107M TDK
GRM32ER60J107ME20L Murata
C15, C20,
C24
06036D106MAT AVX
10 µF, 6.3V, ceramic capacitor, X5R, 0603 3FP3-1R0-R TDK
GRM188R60J106ME47D Murata
C16, C18,
C21, C23
06036D105KAT2A AVX
1 µF, 6.3V, ceramic capacitor, X5R, 0603 4C1608X5R0J105K TDK
GRM188R60J105KA01D Murata
C17
06036D475KAT2A AVX
4.7 µF, 6.3V, ceramic capacitor, X5R, 0603 1C1608X5R0J475M TDK
C1608X5R0J475M Murata
C5 — — N.U. 0603 ceramic capacitor 1
C22
06035C104KAT2A AVX
0.1 µF, 50V, ceramic capacitor, X7R, 0603 1C1608X7R1H104K TDK
GRM188R71H104KA93D Murata
C13 EEU-FC1A471 Panasonic 470 µF/10V, Elect., 20%, 8x11.5, Radial 1
L1 FP3-1R0-R Cooper 1 µH,6.26A Inductor 1
Q3, Q4 NDS8425 Fairchild MOSFET, N-CH 20V 7.4A 8-SOIC 2
R1A CRCW0603300RFKEA Vishay Dale 300, resistor, 1%, 0603 1
R1B CRCW06031101FKEA Vishay Dale 510, resistor, 1%, 0603 1
R1C CRCW0603806RFKEA Vishay Dale 806, resistor, 1%, 0603 1
R1D CRCW06031K10FKEA Vishay Dale 1.1 k, resistor, 1%, 0603 1
MIC5166
DS20006085B-page 24 2018 - 2019 Microchip Technology Inc.
R2 CRCW0603698RFKEA Vishay Dale 698, resistor, 1%, 0603 1
R3 CRCW06032002FKEA Vishay Dale 20 k, resistor, 1%, 0603 1
R4 CRCW06034752FKEA Vishay Dale 47.5 k, resistor, 1%, 0603 1
R6, R8,
R11, R17,
R21
CRCW06032R20RFKEA Vishay Dale 2.2, resistor, 1%, 0603 5
R7 CRCW060349R9RFKEA Vishay Dale 49.9, resistor, 1%, 0603 1
R9 CRCW06031002FKEA Vishay Dale 10 k, resistor, 1%, 0603 1
R10, R19 CRCW06031K00FKEA Vishay Dale 1 k, resistor, 1%, 0603 2
R12 CRCW0603000RFKEA Vishay Dale 0, resistor, 1%, 0603 1
R13, R14,
R24 CRCW25121R00FKEGHP Vishay Dale 1, resistor, 1.5W, 1%, 2512 3
R15 CRCW25122R00JNEG Vishay Dale 2, resistor, 1.5W, 1%, 2512 1
R16, R18,
R20 CRCW06031003FKEA Vishay Dale 100 k, resistor, 1%, 0603 3
R22, R23 LR2512-R50FW Vishay Dale 0.5, resistor, 1.5W, 1%, 2512 2
RV1 PV36W103C01B00 Murata Pot, 10 k, 0.5W, 9.6x5x10 1
U1 MIC22405YML Microchip 4A, Synchronous Buck Regulator 1
U2 MIC5166YMM Microchip 3A High-Speed Low VIN DDR Terminator 1
U3 SN74AHCT00RGYR TI Quad, 2IN Pos-NAND Gate, 14-pin, QFN 1
U4 MIC1557YM5 Microchip 5 MHz RC Timer Oscillator 1
U5 MIC4425 Microchip 3A Dual Inverting and Non-Inverting MOSFET
Driver 1
TABLE 7-1: BILL OF MATERIALS (CONTINUED)
Item Part Number Manufacturer Description Qty.
2018 - 2019 Microchip Technology Inc. DS20006085B-page 25
MIC5166
7.1 PCB Layout Recommendations
FIGURE 7-4: Top Silk.
FIGURE 7-5: Copper Layer 1.
MIC5166
DS20006085B-page 26 2018 - 2019 Microchip Technology Inc.
FIGURE 7-6: Copper Layer 2.
FIGURE 7-7: Copper Layer 3.
2018 - 2019 Microchip Technology Inc. DS20006085B-page 27
MIC5166
FIGURE 7-8: Copper Layer 4.
FIGURE 7-9: Bottom Silk.
MIC5166
DS20006085B-page 28 2018 - 2019 Microchip Technology Inc.
8.0 PACKAGING INFORMATION
8.1 Package Marking Information
10-Lead DFN* Example
Y
XXXX
NNN
Y
5166
288
Legend: XX...X Product code or customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
, , Pin one index is identified by a dot, delta up, or delta down (triangle
mark).
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information. Package may or may not include
the corporate logo.
Underbar (_) and/or Overbar () symbol may not be to scale.
3
e
3
e
2018 - 2019 Microchip Technology Inc. DS20006085B-page 29
MIC5166
10-Lead 3 mm x 3 mm DFN Package Outline & Recommended Land Pattern
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging.
MIC5166
DS20006085B-page 30 2018 - 2019 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging.
2018 - 2019 Microchip Technology Inc. DS20006085B-page 31
MIC5166
APPENDIX A: REVISION HISTORY
Revision A (October 2018)
• Converted Micrel document MIC5166 to Micro-
chip data sheet template DS20006085A.
• Minor grammatical text changes throughout.
Revision B (March 2019)
• EN and PG pin names/numbers corrected in Typi-
cal Application Circuit and Figure 7-2.
• Updated VTT Accuracy values in the Electrical
Characteristics table.
MIC5166
DS20006085B-page 32 2018 - 2019 Microchip Technology Inc.
NOTES:
2018 - 2019 Microchip Technology Inc. DS20006085B-page 33
MIC5166
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office.
Examples:
a) MIC5166YML-TR: MIC5166, –40°C to +125°C
Temperature Range,
10-Lead 3 mm x 3 mm DFN,
5,000/Reel
Device: MIC5166: 3A High-Speed, Low VIN DDR Terminator
Junction
Temperature
Range:
Y = –40°C to +125°C, RoHS-Compliant
Package: ML = 10-Lead 3 mm x 3 mm x 0.9 mm DFN
Media Type: TR = 5,000/Reel
Note 1: Tape and Reel identifier only appears in the
catalog part number description. This identifier is
used for ordering purposes and is not printed on
the device package. Check with your Microchip
Sales Office for package availability with the
Tape and Reel option.
Device X XX -XX
Part No. Junction
Temp. Range
Package Media Type
Note: DFN is a green, RoHS-compliant package. Lead finish is
NiPdAu. Mold compound is Halogen free.
MIC5166
DS20006085B-page 34 2018 - 2019 Microchip Technology Inc.
NOTES:
2018 - 2019 Microchip Technology Inc. DS20006085B-page 35
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate, AVR,
AVR logo, AVR Freaks, BitCloud, chipKIT, chipKIT logo,
CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo,
JukeBlox, KeeLoq, Kleer, LANCheck, LINK MD, maXStylus,
maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB,
OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip
Designer, QTouch, SAM-BA, SpyNIC, SST, SST Logo,
SuperFlash, tinyAVR, UNI/O, and XMEGA are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
and other countries.
ClockWorks, The Embedded Control Solutions Company,
EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS,
mTouch, Precision Edge, and Quiet-Wire are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
Capacitor, AnyIn, AnyOut, BodyCom, CodeGuard,
CryptoAuthentication, CryptoAutomotive, CryptoCompanion,
CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, INICnet, Inter-Chip Connectivity,
JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi,
motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB,
MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation,
PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon,
QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O,
SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated in
the U.S.A.
Silicon Storage Technology is a registered trademark of Microchip
Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2018 - 2019, Microchip Technology Incorporated, All Rights
Reserved.
ISBN: 978-1-5224-4306-3
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITYMANAGEMENTS
YSTEM
CERTIFIEDBYDNV
== ISO/TS16949==
DS20006085B-page 36 2018 - 2019 Microchip Technology Inc.
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Tel: 46-31-704-60-40
Sweden - Stockholm
Tel: 46-8-5090-4654
UK - Wokingham
Tel: 44-118-921-5800
Fax: 44-118-921-5820
Worldwide Sales and Service
08/15/18
