Stereo Audio
DIGITAL-TO-ANALOG CONVERTER
With Programmable PLL
TM
49%
FPO
PCM1723
FEATURES
●ACCEPTS 16-, 20-, OR 24-BIT INPUT DATA
●COMPLETE STEREO DAC: Includes Digital Filter
and Output Amp
●DYNAMIC RANGE: 94dB
●MULTIPLE SAMPLING FREQUENCIES:
16kHz, 22.05kHz, 24kHz
32kHz, 44.1kHz, 48kHz
64kHz, 88.2kHz, 96kHz
●PROGRAMMABLE PLL CIRCUIT:
256fS/384fS from 27MHz Master Clock
●NORMAL OR I2S™ DATA INPUT FORMATS
●SELECTABLE FUNCTIONS:
Soft Mute
Digital Attenuator (256 Steps)
Digital De-emphasis
●OUTPUT MODE: Left, Right, Mono, Mute
DESCRIPTION
The PCM1723 is a complete, low-cost, stereo audio
digital-to-analog converter (DAC) with a phase-locked
loop (PLL) circuit included. The PLL derives either a
256fS or 384fS system clock from an external 27MHz
reference frequency. The DAC contains a 3rd-order
delta-sigma (∆Σ) modulator, a digital interpolation filter,
and an analog output amplifier. The PCM1723 can
accept 16-, 20-, or 24-bit input data in either normal or
I2S formats.
The digital filter performs an 8X interpolation function
and includes selectable features such as soft mute,
digital attenuation and digital de-emphasis. The PLL
can be programmed for sampling at standard digital
audio frequencies as well as one-half and double
sampling frequencies.
The PCM1723 is ideal for applications which combine
compressed audio and video data such as DVD, DVD-
ROM, set-top boxes and MPEG sound cards.
Serial
Input
I/F
Mode
Control
I/F
8X Oversampling
Digital Filter
with Function
Controller
PLL OSC
256f
S
/384f
S
V
CP
PGND V
CC
AGND
Multi-level
Delta-Sigma
Modulator
V
OUT
L
CAP
Open Drain
DAC
Multi-level
Delta-Sigma
Modulator
Low-Pass
Filter
Low-Pass
Filter
BPZ-Cont.
V
OUT
R
ZERO
DAC
MC
MD
ML
LRCIN
DIN
BCKIN
RSTB
Power Supply
XTI XTO V
DD
DGNDMCKOSCKO
PCM1723E
SBAS057A – JANUARY 1996 – REVISED MAY 2007
www.ti.com
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 1996-2007, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SoundPLUS is a trademark of Texas Instruments.
I2S is a trademark of NXP Semiconductors.
All other trademarks are the property of their respective owners.
PCM1723
2SBAS057A
www.ti.com
PIN NAME TYPE FUNCTION
1 XTI IN Master Clock Input.
2 SCKO OUT System Clock Out. This output is 256fS or 384fS.
system clock generated by the internal PLL.
3V
CP PWR PLL Power Supply (+5V).
4 NC N/A No connection.
5 MCKO Out Buffered clock output of crystal oscillator.
6(1) ML IN Latch for serial control data.
7(1) MC IN Clock for serial control data.
8(1) MD IN Data for serial control.
9(1) RSTB IN Reset Input. When this pin is low, the digital
filters and modulators are held in reset.
10 ZERO OUT Zero Data Flag. This pin is low when the input
data is continuously zero for more than 65, 535
cycles of BCKIN.
11 VOUTR OUT Right Channel Analog Output.
12 AGND GND Analog Ground.
13 VCC PWR Analog Power Supply (+5V).
14 VOUTL OUT Left Channel Analog Output.
15 CAP Common pin for analog output amplifiers.
16(2) BCKIN IN Bit clock for clocking in the audio data.
17(2) DIN IN Serial audio data input.
18(2) LRCIN IN Left/Right Word Clock. Frequency is equal to fS.
19 NC N/A No connection.
20 RES N/A Reserved for factory use, do not connect.
21 VDD PWR Analog Power Supply (+5V).
22 DGND GND Digital Ground.
23 PGND GND PLL Ground.
24 XTO Out Crystal oscillator output.
NOTES: (1) Schmitt trigger input with internal pull-up resistors.
(2) Schmitt triger input.
PIN ASSIGNMENTS
PIN CONFIGURATION
TOP VIEW SSOP
PACKAGE INFORMATION(1)
PACKAGE
PRODUCT PACKAGE DESIGNATOR
PCM1723E 24-Pin SSOP DB
NOTE: (1) For the most current package and ordering information, see the
Package Option Addendum at the end of this data sheet, or see the TI web
site at www.ti.com
ABSOLUTE MAXIMUM RATINGS(1)
Power Supply Voltage ......................................................................+6.5V
+VCC to +VDD Difference ................................................................... ±0.1V
Input Logic Voltage .................................................. –0.3V to (VDD + 0.3V)
Input Current (except power supply)............................................... ±10mA
Power Dissipation .......................................................................... 530mW
Operating Temperature Range ......................................... –25°C to +85°C
Storage Temperature...................................................... –55°C to +125°C
Lead Temperature (soldering, 5s).................................................. +260°C
Thermal Resistance,
θ
JA ....................................................................................... +70°C/W
NOTE: (1) Stresses above those listed under Absolute Maximum Ratings may
cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
XTI
SCKO
VCP
NC
MCKO
ML
MC
MD
RSTB
ZERO
VOUTR
AGND
XTO
PGND
DGND
VDD
RES
NC
LRCIN
DIN
BCKIN
CAP
VOUTL
VCC
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handled with appropriate precautions. Failure to observe
proper handling and installation procedures can cause
damage.
ESD damage can range from subtle performance degrada-
tion to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.
PCM1723 3
SBAS057A www.ti.com
ELECTRICAL CHARACTERISTICS
All specifications at +25°C, +VCC = +VDD = +VCP = +5V, fS = 44.1kHz, and 16-bit input data, SYSCLK = 384fS, unless otherwise noted.
PCM1723
PARAMETER CONDITIONS MIN TYP MAX UNITS
RESOLUTION 16 Bits
DATA FORMAT
Audio Data Interface Format Standard/I2S Selectable
Data Bit Length 16/20/24 Selectable
Audio Data Format MSB First, Binary Two’s Complement
Sampling Frequency (fS) Standard fS32 44.1 48 kHz
One-half fS16 22.05 24 kHz
Double fS64 88.2 96 kHz
PLL PERFORMANCE
Master Clock Input Frequency(4) 26.73 27 27.27 MHz
Master Clock Output Frequency 4.096 36.864 MHz
Generated SYSCLK Frequency 256fS/384fS
Output Logic Level VOH IOH = 2mA VDD – 0.4 VDC
(MCKO, SCKO) VOL IOL = 4mA 0.5 VDC
Generated SYSCLK Jitter Standard Dev ±150 ps
Generated SYSCLK Transient(1) fM = 27MHz 20 ms
Power-Up Time To Programmed Frequency 15 30 ms
Generated SYSCLK Duty Cycle fM = 27MHz, CL = 15pF 40 50 60 %
DIGITAL INPUT LOGIC LEVEL TTL
DYNAMIC PERFORMANCE(2)
THD+N at fS (0dB) fs = 44.1kHz –89 –80 dB
fs = 96kHz –87 dB
THD+N at –60dB fs = 44.1kHz –31 dB
fs = 96kHz –29 dB
Dynamic Range (EIAJ Method) fs = 44.1kHz 90 94 dB
fs = 96kHz 91 dB
Signal-to-Noise Ratio(3) (EIAJ Method) fs = 44.1kHz 90 96 dB
fs = 96kHz 95 dB
Channel Separation fs = 44.1kHz 88 93 dB
DC ACCURACY
Gain Error ±1.0 ±3.0 % of FSR
Gain Mismatch, Channel-to-Channel ±1.0 ±2.0 % of FSR
Bipolar Zero Error VOUT = VCC/2 at BPZ ±30 mV
ANALOG OUTPUT
Output Voltage Full Scale (–0dB) 0.62 x VCC VPP
Center Voltage VCC/2 VDC
Load Impedance AC Load 5 kΩ
DIGITAL FILTER PERFORMANCE
Passband 0.445 fS
Stop Band 0.555 fS
Passband Ripple ±0.17 dB
Stop Band Attenuation –35 dB
Delay Time 11.125/fSsec
De-emphasis Error –0.2 +0.55 dB
INTERNAL ANALOG FILTER
–3dB Bandwidth 100 kHz
Passband Response f = 20kHz –0.16 dB
POWER SUPPLY REQUIREMENTS
Voltage Range VCC = VDD = VCP 4.5 5 5.5 VDC
Supply Current: ICC + IDD + ICP fS = 44.1kHz 20 24 mA
TEMPERATURE RANGE
Operating –25 +85 °C
Storage –55 +100 °C
NOTES: (1) Sysclk transient is the maximum frequency lock time when the PLL frequency is changed.
(2) Dynamic performance specs are tested with 20kHz low pass filter and THD+N specs are tested with 30kHz LPF, 400Hz HPF, Average-Mode.
(3) SNR is tested at Infinite Zero Detection off.
(4) PLL evaluations tested with 1ns maximum jitter on the 27MHz input clock.
PCM1723
4SBAS057A
www.ti.com
TYPICAL CHARACTERISTICS
At TA = +25°C, VCC = VDD = VCP = +5V, fS = 44.1kHz, 16-bit input data, 384fS, unless otherwise noted. Measurement bandwidth is 20kHz.
DYNAMIC PERFORMANCE
THD+N (0dB) vs TEMPERATURE and
VCC = 5V, 384fS
Temperature (°C)
THD+N (dB)
–70
–75
–80
–85
–90
–95–250 25507585
fS = 96k
fS = 44.1k
THD+N (0dB) vs POWER SUPPLY VOLTAGE
T
A
= 25°C, 384f
S
Power Supply Voltage (V)
THD+N (dB)
–70
–75
–80
–85
–90
–954.5 5.0 5.5
f
S
= 96k
f
S
= 44.1k
THD+N (0dB) vs SAMPLING RATE (f
S
)
V
CC
= 5V, T
A
= 25°C
Sampling Rate, f
S
(Hz)
THD+N (dB)
–70
–75
–80
–85
–90
–95
44.1k 48k 88.2k 96k
256f
S
384f
S
POWER SUPPLY CURRENT vs SAMPLING RATE (f
S
)
V
CC
= 5V, T
A
= 25°C
Sampling Rate, f
S
(Hz)
Supply Current (mA)
30
20
10
44.1k 48k 88.2k 96k
384f
S
256f
S
PCM1723 5
SBAS057A www.ti.com
PASSBAND RIPPLE CHARACTERISTIC
0
–0.2
–0.4
–0.6
–0.8
–10 0.1134fS0.2268fS0.3402fS0.4535fS
dB
Frequency (Hz)
TYPICAL CHARACTERISTICS (Cont.)
At TA = +25°C, VS = +5V, RL = 44.1kHz, and fSYS = 384fS, unless otherwise noted.
DIGITAL FILTER
0 0.4536f
S
1.3605f
S
2.2675f
S
3.1745f
S
4.0815f
S
0
–20
–40
–60
–80
–100
dB
OVERALL FREQUENCY CHARACTERISTIC
Frequency (Hz)
DE-EMPHASIS FREQUENCY RESPONSE (32kHz)
0 5k 10k 15k 20k 25k
Frequency (Hz)
0
–2
–4
–6
–8
–10
–12
DE-EMPHASIS FREQUENCY RESPONSE (44.1kHz)
0 5k 10k 15k 20k 25k
Frequency (Hz)
0
–2
–4
–6
–8
–10
–12
DE-EMPHASIS FREQUENCY RESPONSE (48kHz)
0 5k 10k 15k 20k 25k
Frequency (Hz)
0
–2
–4
–6
–8
–10
–12
Level (dB) Level (dB) Level (dB)
DE-EMPHASIS ERROR (32kHz)
0 3628 7256 10884 14512
0 4999.8375 9999.675 14999.5125 19999.35
0 5442 10884 16326 21768
Frequency (Hz)
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
DE-EMPHASIS ERROR (44.1kHz)
Frequency (Hz)
DE-EMPHASIS ERROR (48kHz)
Frequency (Hz)
Error (dB) Error (dB) Error (dB)
PCM1723
6SBAS057A
www.ti.com
TYPICAL CONNECTION DIAGRAM
Figure 1 illustrates the typical connection diagram for the
PCM1723 in an MPEG-2 application. The 27MHz master
video clock (fM) drives XTI (pin 1) of the PCM1723. A
programmable system clock is generated by the PCM1723
PLL, with SCKO used to drive the MPEG-2 decoder system
clock input. The standard audio signals (data, bit clock, and
word clock) are generated in the decoder from the PCM1723
system clock, providing synchronization of audio and video
signals.
PLL CIRCUIT
The PCM1723 has a programmable internal PLL circuit, as
shown in Figure 2. The PLL is designed to accept a 27MHz
master clock or crystal oscillator and generate all internal
system clocks required to operate the digital filter and ∆Σ
modulator, either at 256fS or 384fS. If an external master clock
is used, XTO mu st be connected to GND. In bo th cas es, th e
signal amplitude on XTI must satisfy the specification de-
scribed in Figure 3. Therefore, careful C1 and C2 determi-
nation is required to keep this specification satisfied when
FIGURE 1. Connection Diagram for External Master Clock in a Typical MPEG-2 Application.
Oscillator
XTO XTI MCKO PLL Generated
System Clock Out
Frequency
Selection ROM Phase Detector
and Loop Filter VCO
Sampling Frequency Selection
256f
S
/384f
S
Selection
N Counter
M Counter
24 1 5 2
FIGURE 2. PLL Block Diagram.
FIGURE 3. XTI Input Timing.
t
CH
XTI
1/27MHz
t
CL
1.2V
t
CH
: 10ns (min)
t
CL
: 15ns (min) I
IH
(V
IH
= V
DD
) : 4mA max
I
IL
(V
IL
= 0) : 700µA max
0.4V
DIN
BCKIN
LRCIN
SCKO
SERO
SCKO
LRCKO
SYSCKI
XTI
17
16
18
2
6
7
8
9
ML
MC
MD
RSTB
14
XTO
23 22 21 3
11
15
10
1
24
27MHz CLK OUT
+10µF
Post
LPF
Post
LPF
Analog
Mute
Analog
Mute
STRB
SCKO
SDO
PIO
System
Controller
Rch Analog Out
Lch Analog Out
12 13
Audio
Decoder
Buffer
256/384f
S
AGND
PGND DGND
V
CC
+5V Analog
+5V Analog
V
DD
V
CP
V
OUT
L
V
OUT
R
ZERO
CAP
PCM1723
Master
PLL
SCR
(1)
or
PCR
NOTE: (1) SCR: System Clock Reference
PCR: Program Clock Reference
PCM1723 7
SBAS057A www.ti.com
FIGURE 4. System Clock Connection.
14 15 16 1 2 3 14 15
1/fS
L_ch R_ch
MSB LSB
16
LRCIN (pin 4)
BCKIN (pin 6)
AUDIO DATA WORD = 16-BIT
DIN (pin 5) 123 14 15
MSB LSB
16
18 19 20 1 2 3 18 19
MSB LSB
20
AUDIO DATA WORD = 20-BIT
DIN (pin 5) 123 18 19
MSB LSB
20
23 24 1 2 3 22 23
MSB LSB
24
AUDIO DATA WORD = 24-BIT
DIN (pin 5) 123 22 23
MSB LSB
24
FIGURE 5. Normal Data Input Timing.
123 14 15
1/f
S
L_ch R_ch
MSB LSB
16
LRCIN (pin 4)
BCKIN (pin 6)
AUDIO DATA WORD = 16-BIT
DIN (pin 5) 123 14 15
MSB LSB
16
123 18 19
MSB LSB
20
AUDIO DATA WORD = 20-BIT
DIN (pin 5) 123 18 19
MSB LSB
20
21
21
21
123 22 23
MSB LSB
24
AUDIO DATA WORD = 24-BIT
DIN (pin 5) 1 2 3 22 23
MSB LSB
24
FIGURE 6. I2S Data Input Timing.
C1
C2
C1, C2 = 10 to 33pF
27MHz Internal Master Clock
XTIX’tal
RR
XTO
PCM1723
MCKO
Buffer
27MHz
Out
External Clock
27MHz Internal Master Clock
XTI
XTO
PCM1723
EXTERNAL CLOCK INPUTCRYSTAL RESONATOR CONNECTION
MCKO
PCM1723
8SBAS057A
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FIGURE 7. Audio Data Input Timing.
using a crystal oscillator. The PLL will directly track any
variations in the master clock frequency, and jitter on the
system clock is specified at 250ps maximum. Figure 3 illus-
trates the timing requirements for the 27MHz master clock.
Figure 4 illustrates the system clock connections for an
external clock or crystal oscillator.
The PCM1723 internal PLL can be programmed for nine
different sampling frequencies (LRCIN), as shown in Table
I. The internal sampling clocks generated by the various
programmed frequencies are shown in Table II. The system
clock output frequency for the PCM1723 is 100% accurate.
To provide MCKO clock and SCKO clock for external
circuit, external buffer circuit is effective to avoid degrading
audio performance.
SPECIAL FUNCTIONS
The PCM1723 includes several special functions, including
digital attenuation, digital de-emphasis, soft mute, data for-
mat selection and input word resolution. These functions are
controlled using a three-wire interface. MD (pin 8) is used
for the program data, MC (pin 7) is used to clock in the
program data, and ML (pin 6) is used to latch in the program
data. Table III lists the selectable special functions.
FUNCTION DEFAULT MODE
Input Audio Data Format Selection
Normal Format Normal Format
I2S Format
Input Audio Data Bit Selection
16/20/24 Bits 16 Bits
Input LRCIN Polarity Selection
Lch/Rch = High/Low Lch/Rch = High/Low
Lch/Rch = Low/High
De-emphasis Control OFF
Soft Mute Control OFF
Attenuation Control 0dB
Lch, Rch Individually Lch, Rch Individually Fixed
Lch, Rch Common
Infinite Zero Detection Circuit Control OFF
Operation Enable (OPE) Enabled
Sample Rate Selection
Internal System Clock Selection
256fS384fS
384fS
Double Sampling Rate Selection
Standard Sampling Rate—44.1/48/32kHz Standard Sampling Rate
Double Sampling Rate—88.2/96/32kHz
Half Sampling Rate—22.05/24/16kHz
Sampling Frequency
44.1kHz Group 44.1kHz
48kHz Group
32kHz Group
Analog Output Mode
L, R, Mono, Mute Stereo
TABLE III. Selectable Functions.
Sampling Frequencies-LRCIN (kHz)
Half of Standard Sampling Freq
16 22.05 24
Standard Sampling Freq
32 44.1 48
Double of Standard Sampling Freq
64 88.2 96
TABLE I. Sampling Frequencies.
Sampling
Frequency System Clock System Clock
(LRCIN) 256f
S
384f
S
16kHz
Half 4.096MHz 6.144MHz
32kHz
Standard 8.192MHz 12.288MHz
64kHz
Double 16.384MHz 24.576MHz
22.05kHz
Half 5.6448MHz 8.4672MHz
44.1kHz
Standard 11.2896MHz 16.9344MHz
88.2kHz
Double 22.5792MHz 33.8688MHz
24kHz
Half 6.144MHz 9.216MHz
48kHz
Standard 12.288MHz 18.432MHz
96kHz
Double 24.576MHz 36.864MHz
TABLE II. Sampling Frequencies vs Internal System
Clock (= Output Frequencies of PLL).
LRCKIN
BCKIN
DIN
1.4V
1.4V
1.4V
t
BCH
t
BCL
t
LB
t
BL
t
DS
BCKIN Pulse Cycle Time
BCKIN Pulse Width High
BCKIN Pulse Width Low
BCKIN Rising Edge to LRCIN Edge
LRCIN Edge to BCKIN Rising Edge
DIN Set-up Time
DIN Hold Time
: t
BCY
: t
BCH
: t
BCL
: t
BL
: t
LB
: t
DS
: t
DH
: 100ns (min)
: 50ns (min)
: 50ns (min)
: 30ns (min)
: 30ns (min)
: 30ns (min)
: 30ns (min)
t
DH
t
BCY
PCM1723 9
SBAS057A www.ti.com
level until LDL is set to 1. LDR in Register 1 has the same
function for right channel attenuation.
Attenuation Level (ATT) can be controlled as following
Resistor set AL (R) (7:0).
AL (R) (7:0) ATT LEVEL
00h –∞dB (Mute)
01h –48.16dB
..
..
..
FEh –0.07dB
FFh 0dB
REGISTER 1 (A1 = 0, A0 = 1)
MAPPING OF PROGRAM REGISTERS
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
MODE0 res res res res res A1 A0 LDL AL7 AL6 AL5 AL4 AL3 AL2 AL1 AL0
MODE1 res res res res res A1 A0 LDR AR7 AR6 AR5 AR4 AR3 AR2 AR1 AR0
MODE2 res res res res res A1 A0 PL3 PL2 PL1 PL0 IW1 IW0 OPE DEM MUT
MODE3 res res res res res A1 A0 IZD SF1 SF0 DSR1 DSR0 SYS ATC LRP I2S
PROGRAM REGISTER BIT MAPPING
The PCM1723 special functions are controlled using four
program registers that are 16 bits long. These registers are all
loaded using MD. After the 16 data bits are clocked in, ML
is used to latch in the data to the appropriate register. Table
IV shows the complete mapping of the four registers and
Figure 8 illustrates the serial interface timing.
REGISTER BIT
NAME NAME DESCRIPTION
Register 0 AL (7:0) DAC Attenuation Data for Lch
LDL Attenuation Data Load Control for Lch
A (1:0) Register Address
Res Reserved
Register 1 AR (7:0) DAC Attenuation Data for Rch
LDL Attenuation Data Load Control for Rch
A (1:0) Register Address
Res Reserved
Register 2 MUT Left and Right DACs Soft Mute Control
DEM De-emphasis Control
OPE Left and Right DACs Operation Control
IW (1:0) Input Audio Data Bit Select
PL (3:0) Output Mode Select
A (1:0) Register Address
res Reserved
Register 3 I2S Audio Data Format Select
LRP Polarity of LRCIN (pin 7) Select
ATC Attenuator Control
SYS System Clock Select
DSR (1:0) Double Sampling Rate Select
SF (1:0) Sampling Rate Select
IZD Infinite Zero Detection Circuit Control
A (1:0) Register Address
Res Reserved
TABLE IV. Internal Register Mapping.
REGISTER 0 (A1 = 0, A0 = 0)
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
res res res res res A1 A0 LDL AL7 AL6 AL5 AL4 AL3 AL2 AL1 AL0
Register 0 is used to control left channel attenuation. Bits
0 - 7 (AL0 - AL7) are used to determine the attenuation
level. The level of attenuation is given by:
ATT = [20 log10 (ATT_DATA/255)] dB
ATTENUATION DATA LOAD CONTROL
Bit 8 (LDL) is used to control the loading of attenuation data
in B0:B7. When LDL is set to 0, attenuation data will be
loaded into AL0:AL7, but it will not affect the attenuation
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
res res res res res A1 A0
LDR
AR7 AR6 AR5 AR4 AR3 AR2 AR1 AR0
Register 1 is used to control right channel attenuation. As
in Register 1, bits 0 - 7 (AR0 - AR7) control the level of
attenuation.
REGISTER 2 (A1 = 1, A0 = 0)
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
res res res res res A1 A0 PL3 PL2 PL1 PL0 IW1 IW0 OPE DEM MUTE
Register 2 is used to control soft mute, de-emphasis, opera-
tion enable, input resolution, and output format. Bit 0 is used
for soft mute: a HIGH level on bit 0 will cause the output to
be muted (this is ramped down in the digital domain, so no
click is audible). Bit 1 is used to control de-emphasis. A
LOW level on bit 1 disables de-emphasis, while a HIGH
level enables de-emphasis.
Bit 2 (OPE) is used for operational control. Table V illus-
trates the features controlled by OPE.
SOFTWARE MODE
DATA INPUT DAC OUTPUT INPUT
Zero Forced to BPZ(1) Enabled
Other Forced to BPZ(1) Enabled
Zero Controlled by IZD Enabled
Other Normal Enabled
OPE = 1
OPE = 0
TABLE V. Operation Enable (OPE) Function.
NOTE: (1) ∆∑ is disconnected from output amplifier.
PCM1723
10 SBAS057A
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OPE controls the operation of the DAC: when OPE is LOW,
the DAC will convert all non-zero input data. If the input
data is continuously zero for 65,536 cycles of BCKIN, the
output will be forced to zero only if IZD is HIGH. When
OPE is HIGH, the output of the DAC will be forced to
bipolar zero, irrespective of any input data.
IZD = 1
IZD = 0
DATA INPUT DAC OUTPUT
Zero Forced to BPZ(1)
Other Normal
Zero Zero(2)
Other Normal
TABLE VI. Infinite Zero Detection (IZD) Function.
RSTB = HIGH
RSTB = LOW
SOFTWARE
MODE
DATA INPUT DAC OUTPUT INPUT
Zero
Controlled by OPE and IZD
Enabled
Other
Controlled by OPE and IZD
Enabled
Zero Forced to BPZ(1) Disabled
Other Forced to BPZ(1) Disabled
TABLE VII. Reset (RSTB) Function.
Bits 3 (IW0) and 4 (IW1) are used to determine input word
resolution. PCM1723 can be set up for input word resolu-
tions of 16, 20, or 24 bits:
Bit 4 (IW1) Bit 3 (IW0) Input Resolution
0 0 16-bit Data Word
0 1 20-bit Data Word
1 0 24-bit Data Word
1 1 Reserved
Bits 5, 6, 7, and 8 (PL0:3) are used to control output format.
The output of PCM1723 can be programmed for 16 different
states, as shown in Table VIII.
PL0 PL1 PL2 PL3 Lch OUTPUT Rch OUTPUT NOTE
0 0 0 0 MUTE MUTE MUTE
0 0 0 1 MUTE R
0 0 1 0 MUTE L
0 0 1 1 MUTE (L + R)/2
0 1 0 0 R MUTE
0101 R R
0 1 1 0 R L REVERSE
0 1 1 1 R (L + R)/2
1 0 0 0 L MUTE
1 0 0 1 L R STEREO
1010 L L
1 0 1 1 L (L + R)/2
1 1 0 0 (L + R)/2 MUTE
1 1 0 1 (L + R)/2 R
1 1 1 0 (L + R)/2 L
1 1 1 1 (L + R)/2 (L + R)/2 MONO
TABLE VIII. Programmable Output Format.
REGISTER 3 (A1 = 1, A0 = 1)
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
res res res res res A1 A0 IZD SF1 SF0 DSR1 DSR0 SYS ATC LRP I
2
S
Register 3 is used to control input data format and polarity,
attenuation channel control, system clock frequency, sam-
pling frequency, and infinite zero detection.
Bits 0 (I2S) and 1 (LRP) are used to control the input data
format. A LOW on bit 0 sets the format to Normal (MSB-
first, right-justified Japanese format), and a HIGH sets the
format to I2S (Philips serial data protocol). Bit 1 (LRP) is
used to select the polarity of LRCIN (sample rate clock).
When bit 1 is LOW, left channel data are assumed when
LRCIN is in a HIGH phase and right channel data are
assumed when LRCIN is in a LOW phase. When bit 1 is
HIGH, the polarity assumption is reversed.
Bit 2 (ATC) is used for controlling the attenuator. When
bit 2 is HIGH, the attenuation data loaded in program
Register 0 are used for both left and right channels. When
bit 2 is LOW, the attenuation data for each register are
applied separately to left and right channels.
Bit 3 (SYS) is the system clock selection. When bit 3 is
LOW, the system clock frequency is set to 384fS. When bit
3 is HIGH, the system clock frequency is set to 256fS.
Bits 4 (DSR0) and 5 (DSR1) are used to control multiples
of the sampling rate:
DSR1 DSR0 Multiple
0 0 Normal 32/44.1/48kHz
0 1 Double 64/88.2/96kHz
1 0 One-half 16/22.05/24kHz
1 1 Reserved Not Defined
Bits 6 (SF0) and 7 (SF1) are used to select the sampling
frequency. Frequency selection must be made with an
interval time greater than 20µs.
SF1 SF0 Sampling Frequency
0 0 44.1kHz group 22.05/44.1/88.2kHz
0 1 48kHz group 24/48/96kHz
1 0 32kHz group 16/32/64kHz
1 1 Reserved Not Defined
Bit 8 is used to control the infinite zero detection function
(IZD).
When IZD is LOW, the zero detect circuit is off. Under
this condition, no automatic muting will occur if the input
is continuously zero. When IZD is HIGH, the zero detect
feature is enabled. If the input data are continuously zero
for 65,536 cycles of BCKIN, the output will be immedi-
ately forced to a bipolar zero state (VCC/2). The zero
detection feature is used to avoid noise which may occur
when the input is DC. When the output is forced to bipolar
zero, there may be an audible click. PCM1723 allows the
zero detect feature to be disabled so the user can imple-
ment an external muting circuit.
NOTE: (1) ∆∑ is disconnected from output amplifier.
NOTES: (1) ∆∑ is disconnected from output amplifier.
(2) ∆∑ is connected to output amplifier.
PCM1723 11
SBAS057A www.ti.com
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
ML (pin 6)
MC (pin 7)
MD (pin 8)
FIGURE 8. Three-Wire Serial Interface.
FIGURE 9. Program Register Input Timing.
APPLICATION
CONSIDERATIONS
DELAY TIME
There is a finite delay time in delta-sigma converters. In
analog-to-digital converters (ADCs), this is commonly re-
ferred to as latency. For a delta-sigma DAC, delay time is
determined by the order number of the FIR filter stage, and
the chosen sampling rate. The following equation expresses
the delay time of PCM1723:
tD = 11.125 x 1/fS
For fS = 44.1kHz, tD = 11.125/44.1kHz = 251.4µs
Applications using data from a disc or tape source, such as
CD audio, CD-Interactive, Video CD, DAT, Minidisc, etc.,
generally are not affected by delay time. For some profes-
sional applications such as broadcast audio for studios, it is
important for total delay time to be less than 2ms.
OUTPUT FILTERING
For testing purposes all dynamic tests are done on the
PCM1723 using a 20kHz low-pass filter. This filter limits
the measured bandwidth for THD+N, etc. to 20kHz. Failure
to use such a filter will result in higher THD+N and lower
SNR and Dynamic Range readings than are found in the
specifications. The low-pass filter removes out of band
noise. Although it is not audible, it may affect dynamic
specification numbers.
MC Pulse Cycle Time tMCY 100ns (min)
MC Pulse Width LOW tMCL 50ns (min)
MC Pulse Width HIGH tMCH 50ns (min)
MD Setup Time tMDS 30ns (min)
MD Hold Time tMDH 30ns (min)
ML Low Level Time tMLL 30ns + 1SYSCLK (min)
ML High Level Time tMLH 30ns + 1SYSCLK (min)
ML Setup Time tMLS 30ns (min)
ML Hold Time tMHH 30ns (min)
SYSCLK: 1/256fS or 1/384fS
1.4V
1.4V
1.4V
ML
MC
MD
tMLL
tMHH
tMCH tMCL
tMDS
tMCY
tMLS
tMLH
tMDH
LSB
PCM1723
12 SBAS057A
www.ti.com
The performance of the internal low-pass filter from DC to
24kHz is shown in Figure 10. The higher frequency rolloff
of the filter is shown in Figure 11. If an application has the
PCM1723 driving a wideband amplifier, it is recommended
to use an external low-pass filter. A simple 3rd-order filter
is shown in Figure 12. For some applications, a passive RC
filter or 2nd-order filter may be adequate.
Reset
The PCM1723 has both internal power-on reset circuit and
the RSTB pin (pin 9) that accepts an external forced reset by
RSTB = LOW. For internal power on reset, initialize (reset)
is done automatically at power on VDD >2.2V (typ). During
internal reset = LOW, the output of the DAC is invalid and
the analog outputs are forced to VCC/2. Figure 13 illustrates
the timing of internal power on reset.
The PCM1723 accepts an external forced reset when
RSTB = L. During RSTB = L, the output of the DAC is
invalid and the analog outputs are forced to VCC/2 after
internal initialize (1024 system clocks count after RSTB = H).
Figure 14 illustrates the timing of RSTB pin reset.
FIGURE 12. 3rd-Order Low-Pass Filter.
10kΩ
10kΩ
10kΩ
1500pF
100pF
680pF
+
VSIN –
90
0
–90
–180
–270
–360
100 1k 10k 100k 1M
GAIN vs FREQUENCY
Frequency (Hz)
Phase (°)
6
–14
–34
–54
–74
–94
Gain (dB)
Gain
Phase
OPA604
FIGURE 11. Low-Pass Filter Wideband Frequency Response.
FIGURE 10. Low-Pass Filter Frequency Response.
10
5
0
–5
–10
–15
–20
–25
–30
–35
–40
–45
–50
–55
10 100 1k 10k 100k 1M 10M
Frequency (Hz)
dB
–60
INTERNAL ANALOG FILTER FREQUENCY RESPONSE
(10Hz~10MHz)
1.0
0.5
0
–0.5
–1.0
dB
20 Frequency (Hz)
100 1k 10k 24k
INTERNAL ANALOG FILTER FREQUENCY RESPONSE
(20Hz~24kHz, Expanded Scale)
PCM1723 13
SBAS057A www.ti.com
1024 system (= XTI) clocks
Reset Reset Removal
2.6V
2.2V
1.8V
VCC/VDD
Internal Reset
XTI Clock
FIGURE 14. RSTB-Pin Reset Timing.
1024 system (XTI) clocks
Reset Reset Removal
XTI Clock
Internal Reset
RSTB 50% of VDD
tRST(1)
NOTE: (1) tRST = 20ns min
FIGURE 13. Internal Power-On Reset Timing.
FIGURE 15. Latch-up Prevention Circuit.
POWER SUPPLY
CONNECTIONS
The PCM1723 has three power supply connections: digital
(VDD), analog (VCC), and PLL (VCP). Each connection also
has a separate ground return pin. It is acceptable to use a
common +5V power supply for all three power pins. If
separate supplies are used without a common connection,
the delta between the supplies during ramp-up time must be
less than 0.6V. An application circuit to avoid a power-on
latch-up condition is shown in Figure 15.
BYPASSING POWER SUPPLIES
The power supplies should be bypassed as close as
possible to the unit. Refer to Figure 18 for optimal values of
bypass capacitors. It is also recommended to include a
0.1µF ceramic capacitor in parallel with the 10µF tantalum
capacitor.
DGND AGND
V
DD
V
CC
V
CP
Digital
Power Supply Analog
Power Supply
PCM1723
14 SBAS057A
www.ti.com
THEORY OF OPERATION
The delta-sigma section of the PCM1723 is based on a 5-
level amplitude quantizer and a 3rd-order noise shaper. This
section converts the oversampled input data to 5-level delta-
sigma format.
A block diagram of the 5-level delta-sigma modulator is
shown in Figure 16. This 5-level delta-sigma modulator has
the advantage of stability and clock jitter sensitivity over the
typical one-bit (2 level) delta-sigma modulator.
The combined oversampling rate of the delta-sigma modu-
lator and the internal 8X interpolation filter is 48fS for a
384fS system clock, and 64fS for a 256fS system clock. The
theoretical quantization noise performance of the 5-level
delta-sigma modulator is shown in Figure 17.
AC-3 APPLICATION CIRCUIT
A typical application for the PCM1723 is AC-3 5.1 channel
audio decoding and playback. This circuit uses the PCM1723
to develop the audio system clock from the 27MHz video
clock, with the SCKO pin used to drive the AC-3 decoder
and two PCM1720 units, the non-PLL version of the
PCM1723.
FIGURE 17. Quantization Noise Spectrum.
3rd ORDER ∆Σ MODULATOR
Frequency (kHz)
Gain (–dB)
20
0
–20
–40
–60
–80
–100
–120
–140
–160 0 5 10 15 20 25
FIGURE 16. 5-Level ∆Σ Modulator Block Diagram.
Out
48f
S
(384f
S
)
64f
S
(256f
S
)
In 8f
S
18-Bit
+++
4
3
2
1
0
5-level Quantizer
+
–
+Z
–1
+
–
+Z
–1
+
+Z
–1
PCM1723 15
SBAS057A www.ti.com
14
16
15
2
BCKO
LRCKO
DO_0
DO_1
DO_2
SYSCKI
BCKIN
LRCIN
DIN
SCKI
ML
MC
MD
RSTB
VOUTL
CAP
VOUTR
ZERO
Master Clock
Generator
or
PLL
Reset
µP
STRB
SCKO
SDO
+5V Analog
Post
Low-Pass
Filter
Three-wire I/F
(Serial I/O) 3
20
PCM1720
PCM1720
PCM1723
Buffer
19
DGND
AC-3
Audio
Decoder
VDD
AGND VCC
4
5
6
7
9
8
12
13
Analog
Mute
Post
Low-Pass
Filter
Analog
Mute
Mute
Control
+5V Analog
10 11
14
16
15
2
BCKIN
LRCIN
DIN
SCKI
ML
MC
MD
RSTB
VOUTL
CAP
VOUTR
ZERO
+5V Analog
Post
Low-Pass
Filter
10µF
+
20 19
DGND VDD
AGND VCC
4
5
6
7
9
8
12
13
Analog
Mute
Post
Low-Pass
Filter
Analog
Mute
Left-Channel
Front Speaker
Right-Channel
Front Speaker
Left-Channel
Surround Speaker
Left-Channel
Surround Speaker
Center Channel
Sub-Woofer
Mute
Control
+5V Analog
10 11
16
18
17
BCKIN
LRCIN
DIN
SCKO
XTI
ML
MC
MD
VOUTL
CAP
VOUTR
ZERO
+5V Analog
Post
Low-Pass
Filter
10µF
+
2223 21 3
DGNDPGND
VDD VDP
AGND
RSTB VCC
6
7
8
9
11
10
14
15
2
1
Analog
Mute
Post
Low-Pass
Filter
Analog
Mute
Mute
Control
+5V Analog
12 13
24
+
10µF
+
3.3µF
+
10µF
+
+
3.3µF
10µF
+
3.3µF
200Ω
10µF
+
200Ω
FIGURE 18. Connection Diagram for a 6-Channel AC-3 Application.
PCM1723
16 SBAS057A
www.ti.com
DATE REVISION PAGE SECTION DESCRIPTION
—Entire Document Updated format and added missing overbars to RSTB and ZERO pins.
Added "Selectable" to
Audio Data Interface Format
typical value column.
Deleted "Selectable" from
Audio Data Format
unit column.
Changed "XTO should be connected" to "XTO must be connected."
Added sentence regarding XTI signal amplitude and C1, C2 determination.
Figure 3 Changed 2.0V/0.8V to 1.2V/0.4V.
8 PLL Circuit Deleted paragraph regarding frequency error.
10 Register 3 Added sentence to Bit 6 regarding interval time must be greater than 20µs.
Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
5/07 A
2Electrical Characteristics
6PLL Circuit
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
PCM1723E ACTIVE SSOP DB 24 58 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCM1723E/2K ACTIVE SSOP DB 24 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCM1723E/2KG4 ACTIVE SSOP DB 24 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCM1723EG/2K ACTIVE Pb-Free
(RoHS) CU SNBI Level-2-260C-1 YEAR
PCM1723EG4 ACTIVE SSOP DB 24 58 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 11-Apr-2007
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm) W
(mm) Pin1
Quadrant
PCM1723E/2K SSOP DB 24 2000 330.0 17.4 8.5 8.6 2.4 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 13-Jun-2008
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
PCM1723E/2K SSOP DB 24 2000 336.6 336.6 28.6
PACKAGE MATERIALS INFORMATION
www.ti.com 13-Jun-2008
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE
4040065 /E 12/01
28 PINS SHOWN
Gage Plane
8,20
7,40
0,55
0,95
0,25
38
12,90
12,30
28
10,50
24
8,50
Seating Plane
9,907,90
30
10,50
9,90
0,38
5,60
5,00
15
0,22
14
A
28
1
2016
6,50
6,50
14
0,05 MIN
5,905,90
DIM
A MAX
A MIN
PINS **
2,00 MAX
6,90
7,50
0,65 M
0,15
0°–ā8°
0,10
0,09
0,25
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,and other changes to its products and services at any time and to discontinue any product or service without notice. Customers shouldobtain the latest relevant information before placing orders and should verify that such information is current and complete. All products aresold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standardwarranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except wheremandated by government requirements, testing of all parameters of each product is not necessarily performed.TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products andapplications using TI components. To minimize the risks associated with customer products and applications, customers should provideadequate design and operating safeguards.TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Informationpublished by TI regarding third-party products or services does not constitute a license from TI to use such products or services or awarranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectualproperty of the third party, or a license from TI under the patents or other intellectual property of TI.Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompaniedby all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptivebusiness practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additionalrestrictions.
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