SGLS217B − NOVEMBER 2003 − REVISED JUNE 2006
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DControlled Baseline
− One Assembly/Test Site, One Fabrication
Site
DExtended Temperature Performance of
−40°C to 125°C
DEnhanced Diminishing Manufacturing
Sources (DMS) Support
DEnhanced Product-Change Notification
DQualification Pedigree†
DESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 150 V
(TLV2252/52A) and 100 V (TLV2254/54A)
Using Machine Model (C = 200 pF, R = 0)
†Component qualification in accordance with JEDEC and industry
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
DOutput Swing Includes Both Supply Rails
DLow Noise . . . 19 nV/√Hz Typ at f = 1 kHz
DLow Input Bias Current ...1 pA Typ
DFully Specified for Both Single-Supply and
Split-Supply Operation
DVery Low Power ...34 µA Per Channel
(Typ)
DCommon-Mode Input Voltage Range
Includes Negative Rail
DLow Input Offset Voltage:
850 µV Max at TA = 25°C
DWide Supply Voltage Range:
2.7 V to 16 V
DMacromodel Included
description/ordering information
The TLV2252 and TLV2254 are dual and
quadruple low-voltage operational amplifiers from
Texas Instruments. Both devices exhibit rail-to-rail
output performance for increased dynamic range
in single- or split-supply applications. The
TLV225x family consumes only 34 µA of supply
current per channel. This micropower operation
makes them good choices for battery-powered
applications. This family is fully characterized at
3 V and 5 V and is optimized for low-voltage
applications. The noise performance has been
dramatically improved over previous generations
of CMOS amplifiers. The TLV225x has a noise
level of 19 nV / √Hz at 1kHz, four times lower than
competitive micropower solutions.
The TLV225x, exhibiting high input impedance
and low noise, are excellent for small-signal
conditioning for high-impedance sources, such as
piezoelectric transducers. Because of the micro-
power dissipation levels combined with 3-V
operation, these devices work well in hand-held
monitoring and remote-sensing applications. In addition, the rail-to-rail output feature with single or split supplies
makes this family a great choice when interfacing with analog-to-digital converters (ADCs). For precision
applications, the TLV225xA family is available and has a maximum input offset voltage of 850 µV.
Copyright 2003 − 2006, Texas Instruments Incorporated
!"#$%" & '##% & "! (')*%" %+
#"'%& "!"#$ %" &(!%"& (# %, %#$& "! & &%#'$%&
&%# -##%.+ #"'%" (#"&&/ "& "% &&#*. *'
%&%/ "! ** (#$%#&+
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Advanced LinCMOS is a trademark of Texas Instruments.
Figure 1
− High-Level Output Voltage − V
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
VOH
|IOH| − High-Level Output Current − µA
2
1.5
1
00 200 400
2.5
3
600 800
TA = 25°C
TA = 85°C
0.5
TA = 125°C
VDD = 3 V
TA = −40°C
SGLS217B − NOVEMBER 2003 − REVISED JUNE 2006
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description/ordering information (continued)
The TLV2252/2254 also make great upgrades to the TLV2322/2424 in standard designs. They of fer increased
output dynamic range, lower noise voltage, and lower input offset voltage. This enhanced feature set allows
them to b e used in a wider range of applications. For applications that require higher output drive and wider input
voltage range, see the TLV2432 and TLV2442 devices. If your design requires single amplifiers, please see the
TLV2211/21/31 family. These devices are single rail-to-rail operational amplifiers in the SOT-23 package. Small
size and low power consumption make them ideal for high density, battery-powered equipment.
ORDERING INFORMATION
TAVIOmax
AT 25°CPACKAGE†ORDERABLE
PART NUMBER TOP-SIDE
MARKING
850 V
SOIC (D) Tape and reel TLV2252AQDREP 2252AE
850 µVTSSOP (PW) Tape and reel TLV2252AQPWREP‡
1500 V
SOIC (D) Tape and reel TLV2252QDREP 2252EP
−40°C to 125°C
1500 µVTSSOP (PW) Tape and reel TLV2252QPWREP‡
−40°C to 125°C
850 V
SOIC (D) Tape and reel TLV2254AQDREP TLV2254AEP
850 µVTSSOP (PW) Tape and reel TLV2254AQPWREP‡
1500 V
SOIC (D) Tape and reel TLV2254QDREP TLV2254EP
1500 µVTSSOP (PW) Tape and reel TLV2254QPWREP‡
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available
at www.ti.com/sc/package. Product preview
TLV2252, TLV2252A
D OR PW PACKAGE
(TOP VIEW)
1
2
3
4
8
7
6
5
1OUT
1IN−
1IN+
VDD−/GND
VDD+
2OUT
2IN−
2IN+
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1OUT
1IN−
1IN+
VDD+
2IN+
2IN−
2OUT
4OUT
4IN−
4IN+
VDD−/GND
3IN+
3IN−
3OUT
TLV2254, TLV2254A
D PACKAGE
(TOP VIEW)
TLV2254, TLV2254A
PW PACKAGE
(TOP VIEW)
114
8
7
4OUT
4IN −
4IN +
VDD −/GND
3IN +
3IN −
3OUT
1OUT
1IN −
1IN +
VDD+
2IN +
2IN −
2OUT
0
000
SGLS217B − NOVEMBER 2003 − REVISED JUNE 2006
0
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
•3
equivalent schematic (each amplifier)
Q3 Q6 Q9 Q12 Q14 Q16
Q2 Q5 Q7 Q8 Q10 Q11
D1
Q17Q15Q13
Q4Q1
R5
C1
VDD+
IN+
IN−
R3 R4 R1 R2
OUT
VDD−/GND
R6
ACTUAL DEVICE COMPONENT COUNT†
COMPONENT TLV2252 TLV2254
Transistors 38 76
Resistors 30 56
Diodes 9 18
Capacitors 3 6
†Includes both amplifiers and all ESD, bias, and trim circuitry
SGLS217B − NOVEMBER 2003 − REVISED JUNE 2006
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VDD (see Note 1) 16 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differential input voltage, VID (see Note 2) ±VDD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (any input, see Note 1) VDD− − 0.3 V to VDD+
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input current, II (each input) ±5 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output current, IO ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Total current into VDD+ ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Total current out of VDD− ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Duration of short-circuit current (at or below 25°C) (see Note 3) Unlimited. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA −40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 in) from case for 10 s 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential voltages, are with respect to VDD −.
2. Differential voltages are at the noninverting input with respect to the inverting input. Excessive current flows when input is brought
below VDD− − 0.3 V.
3. The output may be shorted to either supply. Temperature and/or supply voltages must be limited to ensure that the maximum
dissipation rating is not exceeded.
DISSIPATION RATING TABLE
PACKAGE
TA
≤
25
°
C
DERATING FACTOR
TA = 85
°
C
TA = 125
°
C
PACKAGE
TA ≤ 25 C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 85 C
POWER RATING
TA = 125 C
POWER RATING
D−8 725 mW 5.8 mW/°C377 mW 145 mW
D−14 950 mW 7.6 mW/°C 494 mW 190 mW
PW−8 525 mW 4.2 mW/°C 273 mW 105 mW
PW−14 700 mW 5.6 mW/°C364 mW 140 mW
recommended operating conditions
MIN MAX UNIT
Supply voltage, VDD 2.7 8 V
Input voltage range, VIVDD− VDD+ −1.3 V
Common-mode input voltage, VIC VDD− VDD+ −1.3 V
Operating free-air temperature, TA−40 125 °C
NOTE 1: All voltage values, except differential voltages, are with respect to VDD −.
SGLS217B − NOVEMBER 2003 − REVISED JUNE 2006
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2252 electrical characteristics at specified free-air temperature, VDD = 3 V (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
TA†
TLV2252 TLV2252A
UNIT
PARAMETER
TEST CONDITIONS
T
A
†
MIN TYP MAX MIN TYP MAX
UNIT
VIO
Input offset voltage
V
DD
± = ±1.5 V
,
V
IC
= 0, 25°C 200 1500 200 850
µV
V
IO
Input offset voltage
VDD± = ±1.5 V,
VO = 0,
VIC = 0,
RS = 50 ΩFull range 1750 1000 µ
V
αVIO
Temperature coefficient
V
DD
± = ±1.5 V
,
V
IC
= 0,
25
°
C
0.5
0.5
µV/°C
αVIO
Temperature coefficient
of input offset voltage
VDD± = ±1.5 V,
VO = 0,
VIC = 0,
RS = 50 Ω
25 C
to 85°C
0.5
0.5
µ
V/
°
C
Input offset voltage
long-term drift
(see Note 4)
VDD± = ±1.5 V,
VO = 0, VIC = 0,
RS = 50 Ω25°C 0.003 0.003 µV/mo
IIO
Input offset current
V
DD
± = ±1.5 V
,
V
IC
= 0, 25°C 0.5 60 0.5 60
pA
I
IO
Input offset current
VDD± = ±1.5 V,
VO = 0,
VIC = 0,
RS = 50 Ω125°C1000 1000
pA
IIB
Input bias current
V
DD
± = ±1.5 V
,
V
IC
= 0, 25°C 1 60 1 60
pA
I
IB
Input bias current
VDD± = ±1.5 V,
VO = 0,
VIC = 0,
RS = 50 Ω125°C1000 1000
pA
0
−0.3
0
−0.3
25°C
0
to
−0.3
to
0
to
−0.3
to
VICR
Common-mode input
voltage range
RS = 50 Ω
|VIO|≤ 5 mV
25 C
to
2
to
2.2
to
2
to
2.2
V
V
ICR
Common-mode input
voltage range
R
S
= 50
Ω, |
V
IO| ≤
5 mV
0
0
V
voltage range
Full range
0
to
0
to
Full range
to
1.7
to
1.7
IOH = −20 µA
25°C
2.98 2.98
VOH
High-level
output voltage
IOH = −75 µA
25
°
C
2.9 2.9
V
V
OH
High-level
output voltage
I
OH
= −75
µ
A
Full range 2.8 2.8
V
output voltage
IOH = −150 µA 25°C 2.8 2.8
VIC = 1.5 V, IOL = 50 µA
25°C
10 10
Low-level
VIC = 1.5 V,
IOL = 500 µA
25
°
C
100 150 100 150
V
OL
Low-level
output voltage
V
IC
= 1.5 V,
I
OL
= 500
µ
A
Full range 165 165 mV
VOL
output voltage
VIC = 1.5 V,
IOL = 1 A
25°C 200 300 200 300
mV
V
IC
= 1.5 V,
I
OL
= 1
A
Full range 300 300
Large-signal differential
VIC = 1.5 V,
RL = 100 kه
25°C 100 250 100 250
A
VD
Large-signal differential
voltage amplification
VIC = 1.5 V,
VO = 1 V to 2 V
R
L
= 100 k
Ω
‡
Full range 10 10 V/mV
AVD
voltage amplification
VO = 1 V to 2 V
RL = 1 MΩ‡25°C 800 800
V/mV
ri(d) Differential
input resistance 25°C 1012 1012 Ω
ri(c) Common-mode
input resistance 25°C 1012 1012 Ω
ci(c) Common-mode
input capacitance f = 10 kHz 25°C 8 8 pF
zoClosed-loop
output impedance f = 25 kHz, AV = 10 25°C 220 220 Ω
CMRR
Common-mode
rejection ratio
VIC = 0 to 1.7 V,
V
O
= 1.5 V, 25°C 65 75 65 77
dB
CMRR
Common-mode
rejection ratio
VIC = 0 to 1.7 V,
RS = 50 Ω
VO = 1.5 V,
Full range 60 60
dB
kSVR
Supply-voltage rejection
ratio ( V /V)
V
DD
= 2.7 V to 8 V,
V = V /2, No load
25°C 80 95 80 100
dB
k
SVR
Supply-voltage rejection
ratio (∆VDD /∆VIO)
VDD = 2.7 V to 8 V,
VIC = VDD/2, No load Full range 80 80
dB
IDD
Supply current
VO = 1.5 V,
No load
25°C 68 125 68 125
µA
I
DD
Supply current
V
O
= 1.5 V,
No load
Full range 150 150 µ
A
†Full range is −40°C to 125°C.
‡Referenced to 1.5 V
NOTE 4: Typical values are based on the input offset voltage shift observed through 500 hours of operating life test at TA = 150°C extrapolated
to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
SGLS217B − NOVEMBER 2003 − REVISED JUNE 2006
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2252 operating characteristics at specified free-air temperature, VDD = 3 V
PARAMETER
TEST CONDITIONS
TA†
TLV2252 TLV2252A
UNIT
PARAMETER
TEST CONDITIONS
TA
†
MIN TYP MAX MIN TYP MAX
UNIT
25°C
0.07
0.1
0.07
0.1
VO = 0.8 V to 1.4 V,
RL = 100 kه,
25°C 0.07 0.1 0.07 0.1
SR Slew rate at unity gain VO = 0.8 V to 1.4 V
,
CL = 100 pF‡
RL = 100 kΩ
‡,
Full
0.05
0.05
V/µs
SR
Slew rate at unity gain
CL = 100 pF‡
Full
range 0.05 0.05
V/µs
Vn
Equivalent input noise
f = 10 Hz
25°C
35 35
nV/√Hz
Vn
Equivalent input noise
voltage f = 1 kHz 25°C19 19
nV/√Hz
VN(PP)
Peak-to-peak
equivalent input
f = 0.1 Hz to 1 Hz
25°C
0.6 0.6
V
VN(PP
)
equivalent input
noise voltage f = 0.1 Hz to 10 Hz 25°C1.1 1.1 µV
InEquivalent input noise
current 25°C 0.6 0.6 fA/√Hz
Gain-bandwidth
f = 1 kHz, ‡
RL = 50 k
Ω‡
,
25°C
0.187
0.187
MHz
Gain-bandwidth
product
f = 1 kHz,
C
L
= 100 pF‡
RL = 50 kه,
25°C 0.187 0.187 MHz
BOM
Maximum
output-swing
VO(PP) = 1 V,
‡
AV = 1, ‡
25°C
60
60
kHz
BOM
output-swing
bandwidth
VO(PP) = 1 V,
RL = 50 kه,
AV = 1,
CL = 100 pF‡25°C60 60 kHz
φmPhase margin
at unity gain RL = 50 kΩ‡, CL = 100 pF‡25°C 63°63°
Gain margin RL = 50 kΩ‡, CL = 100 pF‡25°C 15 15 dB
†Full range is −40°C to 125°C.
‡Referenced to 1.5 V
SGLS217B − NOVEMBER 2003 − REVISED JUNE 2006
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2252 electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
TA†
TLV2252 TLV2252A
UNIT
PARAMETER
TEST CONDITIONS
T
A
†
MIN TYP MAX MIN TYP MAX
UNIT
VIO
Input offset voltage
V
DD
± = ±2.5 V
,
VIC = 0,
25°C 200 1500 200 850
µV
V
IO
Input offset voltage
VDD± = ±2.5 V,
VO = 0,
VIC = 0,
RS = 50 ΩFull range 1750 1000 µ
V
αVIO
Temperature coefficient
V
DD
± = ±2.5 V
,
VIC = 0,
25
°
C
0.5
0.5
µV/°C
αVIO
Temperature coefficient
of input offset voltage
VDD± = ±2.5 V,
VO = 0,
VIC = 0,
RS = 50 Ω
25 C
to 85°C
0.5
0.5
µ
V/
°
C
Input offset voltage long-
term drift (see Note 4) VDD± = ±2.5 V,
VO = 0, VIC = 0,
RS = 50 Ω25°C 0.003 0.003 µV/mo
IIO
Input offset current
V
DD
± = ±2.5 V
,
VIC = 0,
25°C 0.5 60 0.5 60
pA
I
IO
Input offset current
VDD± = ±2.5 V,
VO = 0,
VIC = 0,
RS = 50 Ω125°C1000 1000
pA
IIB
Input bias current
V
DD
± = ±2.5 V
,
VIC = 0,
25°C 1 60 1 60
pA
I
IB
Input bias current
VDD± = ±2.5 V,
VO = 0,
VIC = 0,
RS = 50 Ω125°C1000 1000
pA
VICR
Common-mode
|VIO|≤5 mV,
RS = 50 Ω
25°C0
to
4
−0.3
to
4.2
0
to
4
−0.3
to
4.2
V
V
ICR
Common-mode
input voltage range |
V
IO| ≤
5 mV,
R
S
= 50
Ω
Full range 0
to
3.5
0
to
3.5
V
IOH = −20 µA
25°C
4.98 4.98
VOH
High-level
IOH = −75 µA
25
°
C
4.9 4.94 4.9 4.94
V
V
OH
High-level
output voltage
I
OH
= −75
µ
A
Full range 4.8 4.8
V
output voltage
IOH = −150 µA 25°C 4.8 4.88 4.8 4.88
VIC = 2.5 V, IOL = 50 µA
25°C
0.01 0.01
Low-level
VIC = 2.5 V,
IOL = 500 µA
25
°
C
0.09 0.15 0.09 0.15
V
OL
Low-level
output voltage
V
IC
= 2.5 V,
I
OL
= 500
µ
A
Full range 0.15 0.15 V
VOL
output voltage
VIC = 2.5 V,
IOL = 1 A
25°C 0.2 0.3 0.2 0.3
V
V
IC
= 2.5 V,
I
OL
= 1
A
Full range 0.3 0.3
Large-signal differential
VIC = 2.5 V,
RL = 100 kه
25°C 100 350 100 350
A
VD
Large-signal differential
voltage amplification
VIC = 2.5 V,
VO = 1 V to 4 V
R
L
= 100 k
Ω
‡
Full range 10 10 V/mV
AVD
voltage amplification
VO = 1 V to 4 V
RL = 1 MΩ‡25°C 1700 1700
V/mV
ri(d) Differential
input resistance 25°C 1012 1012 Ω
ri(c) Common-mode
input resistance 25°C 1012 1012 Ω
ci(c) Common-mode
input capacitance f = 10 kHz 25°C 8 8 pF
zoClosed-loop
output impedance f = 25 kHz, AV = 10 25°C 200 200 Ω
CMRR
Common-mode
VIC = 0 to 2.7 V,
25°C 70 83 70 83
dB
CMRR
Common-mode
rejection ratio
VIC = 0 to 2.7 V,
VO = 2.5 V, RS = 50 ΩFull range 70 70
dB
kSVR
Supply-voltage rejection
VDD = 4.4 V to 8 V,
25°C 80 95 80 95
dB
k
SVR
Supply-voltage rejection
ratio (∆VDD/∆VIO)
VDD = 4.4 V to 8 V,
VIC = VDD/2, No load Full range 80 80
dB
†Full range is −40°C to 125°C.
‡Referenced to 2.5 V
NOTE 4: Typical values are based on the input offset voltage shift observed through 500 hours of operating life test at TA = 150°C extrapolated
to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
SGLS217B − NOVEMBER 2003 − REVISED JUNE 2006
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2252 electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise
noted) (continued)
PARAMETER
TEST CONDITIONS
TA†
TLV2252 TLV2252A
UNIT
PARAMETER
TEST CONDITIONS
T
A
†
MIN TYP MAX MIN TYP MAX
UNIT
IDD
Supply current
VO = 2.5 V,
No load
25°C 70 125 70 125
µA
I
DD
Supply current
V
O
= 2.5 V,
No load
Full range 150 150 µ
A
†Full range is −40°C to 125°C for Q level part.
TLV2252 operating characteristics at specified free-air temperature, VDD = 5 V
PARAMETER
TEST CONDITIONS
TA†
TLV2252 TLV2252A
UNIT
PARAMETER
TEST CONDITIONS
TA
†
MIN TYP MAX MIN TYP MAX
UNIT
25°C
0.07
0.12
0.07
0.12
VO = 1.25 V to 2.75 V,
25°C 0.07 0.12 0.07 0.12
SR Slew rate at unity gain VO = 1.25 V to 2.75 V,
RL = 100 kΩ‡, CL = 100 pF‡
Full
0.05
0.05
V/µs
SR
Slew rate at unity gain
RL = 100 kΩ‡, CL = 100 pF‡
Full
range 0.05 0.05
V/µs
Vn
Equivalent input
f = 10 Hz 25°C 36 36
nV/√Hz
Vn
Equivalent input
noise voltage f = 1 kHz 25°C 19 19
nV/√Hz
VN(PP)
Peak-to-peak
equivalent input
f = 0.1 Hz to 1 Hz 25°C 0.7 0.7
V
VN(PP)
equivalent input
noise voltage f = 0.1 Hz to 10 Hz 25°C 1.1 1.1 µV
InEquivalent input
noise current 25°C 0.6 0.6 fA/√Hz
THD+N
Total harmonic
VO = 0.5 V to 2.5 V
,
f = 20 kHz,
AV = 1
25°C
0.2% 0.2%
THD+N
Total harmonic
distortion plus noise
O
f = 20 kHz,
R
L
= 50 kΩ‡AV = 10 25°C1% 1%
Gain-bandwidth product
f = 50 kHz,
RL = 50 k
Ω‡
,
25°C
0.2
0.2
MHz
Gain-bandwidth produc
t
f = 50 kHz,
C
L
= 100 pF‡
RL = 50 kه,
25°C 0.2 0.2 MHz
BOM
Maximum output-swing
VO(PP) = 2 V,
‡
AV = 1, ‡
25°C
30
30
kHz
BOM
Maximum output-swing
bandwidth
VO(PP) = 2 V,
R
L
= 50 kه,
AV = 1,
C
L
= 100 pF‡25°C30 30 kHz
φmPhase margin
at unity gain RL = 50 kΩ‡, CL = 100 pF‡25°C 63°63°
Gain margin RL = 50 kΩ‡, CL = 100 pF‡25°C 15 15 dB
†Full range is −40°C to 125°C.
‡Referenced to 2.5 V
SGLS217B − NOVEMBER 2003 − REVISED JUNE 2006
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2254 electrical characteristics at specified free-air temperature, VDD = 3 V (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
TA†
TLV2254 TLV2254A
UNIT
PARAMETER
TEST CONDITIONS
T
A
†
MIN TYP MAX MIN TYP MAX
UNIT
VIO
Input offset voltage
VDD± =
±
1.5 V,
VIC = 0,
25°C 200 1500 200 850
µV
V
IO
Input offset voltage
VDD± = ±1.5 V,
VO = 0,
VIC = 0,
RS = 50 ΩFull range 1750 1000 µ
V
αVIO
Temperature coefficient
VDD± =
±
1.5 V,
VIC = 0,
25
°
C
0.5
0.5
µV/°C
αVIO
Temperature coefficient
of input offset voltage
VDD± = ±1.5 V,
V
O
= 0,
VIC = 0,
R
S
= 50 Ω
25 C
to 125°C
0.5
0.5
µ
V/
°
C
Input offset voltage
long-term drift
(see Note 4)
VDD± = ±1.5 V,
VO = 0, VIC = 0,
RS = 50 Ω25°C 0.003 0.003 µV/mo
IIO
Input offset current
VDD± =
±
1.5 V,
VIC = 0,
25°C 0.5 60 0.5 60
pA
I
IO
Input offset current
VDD± = ±1.5 V,
VO = 0,
VIC = 0,
RS = 50 Ω125°C1000 1000
pA
IIB
Input bias current
VDD± =
±
1.5 V,
VIC = 0,
25°C 1 60 1 60
pA
I
IB
Input bias current
VDD± = ±1.5 V,
VO = 0,
VIC = 0,
RS = 50 Ω125°C1000 1000
pA
0
−0.3
0
−0.3
25°C
0
to
−0.3
to
0
to
−0.3
to
VICR
Common-mode
RS = 50 Ω
|VIO|≤5 mV
25 C
to
2
to
2.2
to
2
to
2.2
V
V
ICR
Common-mode
input voltage range
R
S
= 50
Ω, |
V
IO| ≤
5 mV
0
0
V
input voltage range
Full range
0
to
0
to
Full range
to
1.7
to
1.7
IOH = −20 µA
25°C
2.98 2.98
VOH
High-level
IOH = −75 µA
25
°
C
2.9 2.9
V
V
OH
High-level
output voltage
I
OH
= −75
µ
A
Full range 2.8 2.8
V
output voltage
IOH = −150 µA 25°C 2.8 2.8
VIC = 1.5 V, IOL = 50 µA
25°C
10 10
Low-level
VIC = 1.5 V,
IOL = 500 µA
25
°
C
100 150 100 150
V
OL
Low-level
output voltage
V
IC
= 1.5 V,
I
OL
= 500
µ
A
Full range 165 165 mV
VOL
output voltage
VIC = 1.5 V,
IOL = 1 A
25°C 200 300 200 300
mV
V
IC
= 1.5 V,
I
OL
= 1
A
Full range 300 300
Large-signal differential
VIC = 1.5 V,
RL = 100 kه
25°C 100 225 100 225
A
VD
Large-signal differential
voltage amplification
VIC = 1.5 V,
VO = 1 V to 2 V
R
L
= 100 k
Ω
‡
Full range 10 10 V/mV
AVD
voltage amplification
V
O
= 1 V to 2 V
RL = 1 MΩ‡25°C 800 800
V/mV
ri(d) Differential input
resistance 25°C 1012 1012 Ω
ri(c) Common-mode
input resistance 25°C 1012 1012 Ω
ci(c) Common-mode
input capacitance f = 10 kHz 25°C 8 8 pF
zoClosed-loop
output impedance f = 25 kHz, AV = 10 25°C 220 220 Ω
CMRR
Common-mode
VIC = 0 to 1.7 V,
VO = 1.5 V,
25°C 65 75 65 77
dB
CMRR
Common-mode
rejection ratio
VIC = 0 to 1.7 V,
R
S
= 50 Ω
VO = 1.5 V,
Full range 60 60
dB
kSVR
Supply-voltage
rejection ratio
V
DD
= 2.7 V to 8 V, 25°C 80 95 80 100
dB
k
SVR
rejection ratio
(∆VDD/∆VIO)
VDD = 2.7 V to 8 V,
VIC = VDD/2, No load Full range 80 80
dB
†Full range is −40°C to 125°C.
‡Referenced to 1.5 V
NOTE 4: Typical values are based on the input offset voltage shift observed through 500 hours of operating life test at TA = 150°C extrapolated
to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
SGLS217B − NOVEMBER 2003 − REVISED JUNE 2006
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2254 electrical characteristics at specified free-air temperature, VDD = 3 V (unless otherwise
noted) (continued)
PARAMETER
TEST CONDITIONS
TA†
TLV2254 TLV2254A
UNIT
PARAMETER
TEST CONDITIONS
T
A
†
MIN TYP MAX MIN TYP MAX
UNIT
IDD
Supply current
VO = 1.5 V,
No load
25°C 135 250 135 250
µA
I
DD
Supply current
(four amplifiers)
V
O
= 1.5 V,
No load
Full range 300 300 µ
A
†Full range is −40°C to 125°C for Q level part.
TLV2254 operating characteristics at specified free-air temperature, VDD = 3 V
PARAMETER
TEST CONDITIONS
TA†
TLV2254 TLV2254A
UNIT
PARAMETER
TEST CONDITIONS
TA
†
MIN TYP MAX MIN TYP MAX
UNIT
SR
Slew rate at unity gain
VO = 0.5 V to 1.7 V,
RL = 100 kه,
25°C0.07 0.1 0.07 0.1
V/µs
SR
Slew rate at unity gain
R
L
= 100 k
Ω
‡,
CL = 100 pF‡
Full range
0.05
0.05
V/
µ
s
L
CL = 100 pF
‡
Full range 0.05 0.05
Vn
Equivalent input noise voltage
f = 10 Hz
25°C
35 35
nV/√Hz
VnEquivalent input noise voltage f = 1 kHz 25°C19 19
nV/√Hz
VN(PP)
Peak-to-peak equivalent
f = 0.1 Hz to 1 Hz
25°C
0.6 0.6
V
VN(PP)
Peak-to-peak equivalent
input noise voltage f = 0.1 Hz to 10 Hz 25°C1.1 1.1 µV
InEquivalent input noise current 25°C 0.6 0.6 fA/√Hz
Gain-bandwidth product
f = 1 kHz,
RL = 50 kه,
25°C
0.187
0.187
MHz
Gain-bandwidth product
R
L
= 50 k
Ω
‡,
CL = 100 pF‡25°C 0.187 0.187 MHz
BOM
Maximum output-swing
VO(PP) = 1 V,
A
V
= 1,
‡
25°C
60
60
kHz
BOM
Maximum output-swing
bandwidth
AV = 1,
RL = 50 kه,
CL = 100 pF‡25°C 60 60 kHz
φmPhase margin at unity gain RL = 50 kΩ‡,
CL = 100 pF‡25°C 63°63°
Gain margin RL = 50 kه,
CL = 100 pF‡25°C 15 15 dB
†Full range is −40°C to 125°C for Q level part.
‡Referenced to 1.5 V
SGLS217B − NOVEMBER 2003 − REVISED JUNE 2006
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2254 electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
TA†
TLV2254 TLV2254A
UNIT
PARAMETER
TEST CONDITIONS
T
A
†
MIN TYP MAX MIN TYP MAX
UNIT
VIO
Input offset voltage
VDD± =
±
2.5 V,
VIC = 0,
25°C 200 1500 200 850
µV
V
IO
Input offset voltage
VDD± = ±2.5 V,
VO = 0,
VIC = 0,
RS = 50 ΩFull range 1750 1000 µ
V
αVIO
Temperature coefficient
VDD± =
±
2.5 V,
VIC = 0,
25
°
C
0.5
0.5
µV/°C
αVIO
Temperature coefficient
of input offset voltage
VDD± = ±2.5 V,
V
O
= 0,
VIC = 0,
R
S
= 50 Ω
25 C
to 125°C
0.5
0.5
µ
V/
°
C
Input offset voltage
long-term drift
(see Note 4)
VDD± = ±2.5 V,
VO = 0, VIC = 0,
RS = 50 Ω25°C 0.003 0.003 µV/mo
IIO
Input offset current
VDD± =
±
2.5 V,
VIC = 0,
25°C 0.5 60 0.5 60
pA
I
IO
Input offset current
VDD± = ±2.5 V,
VO = 0,
VIC = 0,
RS = 50 Ω125°C1000 1000
pA
IIB
Input bias current
VDD± =
±
2.5 V,
VIC = 0,
25°C 1 60 1 60
pA
I
IB
Input bias current
VDD± = ±2.5 V,
VO = 0,
VIC = 0,
RS = 50 Ω125°C1000 1000
pA
0
−0.3
0
−0.3
25°C
0
to
−0.3
to
0
to
−0.3
to
VICR
Common-mode
|VIO|≤5 mV,
RS = 50 Ω
25 C
to
4
to
4.2
to
4
to
4.2
V
V
ICR
Common-mode
input voltage range |
V
IO| ≤
5 mV,
R
S
= 50
Ω
0
0
V
input voltage range
Full range
0
to
0
to
Full range
to
3.5
to
3.5
IOH = −20 µA
25°C
4.98 4.98
VOH
High-level
IOH = −75 µA
25
°
C
4.9 4.94 4.9 4.94
V
V
OH
High-level
output voltage
I
OH
= −75
µ
A
Full range 4.8 4.8
V
output voltage
IOH = −150 µA 25°C 4.8 4.88 4.8 4.88
VIC = 2.5 V, IOL = 50 µA
25°C
0.01 0.01
Low-level
VIC = 2.5 V,
IOL = 500 µA
25
°
C
0.09 0.15 0.09 0.15
V
OL
Low-level
output voltage
V
IC
= 2.5 V,
I
OL
= 500
µ
A
Full range 0.15 0.15 V
VOL
output voltage
VIC = 2.5 V,
IOL = 1 A
25°C 0.2 0.3 0.2 0.3
V
V
IC
= 2.5 V,
I
OL
= 1
A
Full range 0.3 0.3
Large-signal differential
VIC = 2.5 V,
RL = 100 kه
25°C 100 350 100 350
A
VD
Large-signal differentia
l
voltage amplification
VIC = 2.5 V,
VO = 1 V to 4 V
R
L
= 100 k
Ω
‡
Full range 10 10 V/mV
AVD
voltage amplification
V
O
= 1 V to 4 V
RL = 1 MΩ‡25°C 1700 1700
V/mV
ri(d) Differential input
resistance 25°C 1012 1012 Ω
ri(c) Common-mode
input resistance 25°C 1012 1012 Ω
ci(c) Common-mode
input capacitance f = 10 kHz 25°C 8 8 pF
zoClosed-loop
output impedance f = 25 kHz, AV = 10 25°C 200 200 Ω
CMRR
Common-mode
VIC = 0 to 2.7 V,
VO = 2.5 V,
25°C 70 83 70 83
dB
CMRR
Common-mode
rejection ratio
VIC = 0 to 2.7 V,
R
S
= 50 Ω
VO = 2.5 V,
Full range 70 70
dB
kSVR
Supply-voltage
rejection ratio
VDD = 4.4 V to 8 V,
25°C 80 95 80 95
dB
kSVR
rejection ratio
(∆V
DD
/∆V
IO
)
VDD = 4.4 V to 8 V,
VIC = VDD/2, No load Full range 80 80 dB
†Full range is −40°C to 125°C.
‡Referenced to 2.5 V
NOTE 4: Typical values are based on the input offset voltage shift observed through 500 hours of operating life test at TA = 150°C extrapolated
to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
SGLS217B − NOVEMBER 2003 − REVISED JUNE 2006
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2254 electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise
noted) (continued)
PARAMETER
TEST CONDITIONS
TA†
TLV2254 TLV2254A
UNIT
PARAMETER
TEST CONDITIONS
T
A
†
MIN TYP MAX MIN TYP MAX
UNIT
IDD
Supply current
VO = 2.5 V,
No load
25°C 140 250 140 250
A
IDD
Supply current
(four amplifiers) VO = 2.5 V, No load Full range 300 300 µA
†Full range is −40°C to 125°C.
TLV2254 operating characteristics at specified free-air temperature, VDD = 5 V
PARAMETER
TEST CONDITIONS
TA†
TLV2254 TLV2254A
UNIT
PARAMETER
TEST CONDITIONS
TA
†
MIN TYP MAX MIN TYP MAX
UNIT
Slew rate
VO = 0.5 V to 3.5 V,
RL = 100 kه,
25°C0.07 0.12 0.07 0.12
SR
Slew rate
at unity gain
V
O
= 0.5 V to 3.5 V,
CL = 100 pF‡
R
L
= 100 k
Ω
‡,
Full
0.05
0.05
V/µs
SR
at unity gain
CL = 100 pF‡
Full
range 0.05 0.05
V/µs
Vn
Equivalent input
f = 10 Hz
25°C
36 36
nV/√Hz
Vn
Equivalent input
noise voltage f = 1 kHz 25°C19 19
nV/√Hz
VN(PP)
Peak-to-peak
equivalent input
f = 0.1 Hz to 1 Hz
25°C
0.7 0.7
V
VN(PP)
equivalent input
noise voltage f = 0.1 Hz to 10 Hz 25°C1.1 1.1 µV
InEquivalent input
noise current 25°C 0.6 0.6 fA/√Hz
THD+N
Total harmonic
distortion plus
VO = 0.5 V to 2.5 V,
f = 20 kHz,
AV = 1
25°C
0.2% 0.2%
THD+N
distortion plus
noise
O
f = 20 kHz,
R
L
= 50 kΩ‡AV = 10 25°C1% 1%
Gain-bandwidth
f = 50 kHz,
RL = 50 k
Ω‡
,
25°C
0.2
0.2
MHz
Gain-bandwidth
product
f = 50 kHz,
C
L
= 100 pF‡
RL = 50 kه,
25°C 0.2 0.2 MHz
BOM
Maximum output-
VO(PP) = 2 V,
‡
AV = 1, ‡
25°C
30
30
kHz
BOM
Maximum output-
swing bandwidth
VO(PP) = 2 V,
R
L
= 50 kه,
AV = 1,
C
L
= 100 pF‡25°C30 30 kHz
φmPhase margin
at unity gain RL = 50 kΩ‡, CL = 100 pF‡25°C 63°63°
Gain margin RL = 50 kΩ‡, CL = 100 pF‡25°C 15 15 dB
†Full range is −40°C to 125°C for Q level part.
‡Referenced to 2.5 V
SGLS217B − NOVEMBER 2003 − REVISED JUNE 2006
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
VIO Input offset voltage Distribution
vs Common-mode voltage 2−5
6, 7
αVIO Input offset voltage temperature coefficient Distribution 8−11
IIB/IIO Input bias and input offset currents vs Free-air temperature 12
VIInput voltage vs Supply voltage
vs Free-air temperature 13
14
VOH High-level output voltage vs High-level output current 15, 18
VOL Low-level output voltage vs Low-level output current 16, 17, 19
VO(PP) Maximum peak-to-peak output voltage vs Frequency 20
IOS Short-circuit output current vs Supply voltage
vs Free-air temperature 21
22
VID Differential input voltage vs Output voltage 23, 24
AVD Differential voltage amplification vs Load resistance 25
AVD Large-signal differential voltage amplification vs Frequency
vs Free-air temperature 26, 27
28, 29
zoOutput impedance vs Frequency 30, 31
CMRR Common-mode rejection ratio vs Frequency
vs Free-air temperature 32
33
kSVR Supply-voltage rejection ratio vs Frequency
vs Free-air temperature 34, 35
36
IDD Supply current vs Supply voltage 37, 38
SR Slew rate vs Load capacitance
vs Free-air temperature 39
40
VOInverting large-signal pulse response 41, 42
VOVoltage-follower large-signal pulse response 43, 44
VOInverting small-signal pulse response 45, 46
VOVoltage-follower small-signal pulse response 47, 48
VnEquivalent input noise voltage vs Frequency 49, 50
Input noise voltage Over a 10-s period 51
Integrated noise voltage vs Frequency 52
THD+N Total harmonic distortion plus noise vs Frequency 53
Gain-bandwidth product vs Supply voltage
vs Free-air temperature 54
55
φmPhase margin vs Frequency
vs Load capacitance 26, 27
56
Gain margin vs Load capacitance 57
B1Unity-gain bandwidth vs Load capacitance 58
Overestimation of phase margin vs Load capacitance 59
SGLS217B − NOVEMBER 2003 − REVISED JUNE 2006
14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 2
Precentage of Amplifiers − %
DISTRIBUTION OF TLV2252
INPUT OFFSET VOLTAGE
VIO − Input Offset Voltage − mV
10
5
0
20
15
−1.6 −0.8 0 0.8 1.6
1020 Amplifiers From 1 Wafer Lot
VDD = ±1.5 V
TA = 25°C
Figure 3
Precentage of Amplifiers − %
DISTRIBUTION OF TLV2252
INPUT OFFSET VOLTAGE
VIO − Input Offset Voltage − mV
10
5
0
20
15
−1.6 −0.8 0 0.8 1.6
1020 Amplifiers From 1 Wafer Lot
VDD = ±2.5 V
TA = 25°C
Figure 4
Percentage of Amplifiers − %
DISTRIBUTION OF TLV2254
INPUT OFFSET VOLTAGE
VIO − Input Offset Voltage − mV
15
10
5
0
20
35
−1.6 −0.8 0 0.8 1.6
25
30
682 Amplifiers From 1 Wafer Lot
VDD±= ±1.5 V
TA = 25°C
Figure 5
Percentage of Amplifiers − %
DISTRIBUTION OF TLV2254
INPUT OFFSET VOLTAGE
VIO − Input Offset Voltage − mV
20
10
5
0
25
35
−1.6 −0.8 0 0.8 1.6
682 Amplifiers From 1 Wafer Lot
VDD±= ±2.5 V
TA = 25°C
15
30
SGLS217B − NOVEMBER 2003 − REVISED JUNE 2006
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 6
− Input Offset Voltage − mV
INPUT OFFSET VOLTAGE†
vs
COMMON-MODE INPUT VOLTAGE
ÁÁ
ÁÁ
VIO
VIC − Common-Mode Input Voltage − V
1
0.8
0.6
0.4
0.2
0
−0.2
−0.4
−0.6
−0.8
−1−1 0 1 2
VDD = 3 V
RS = 50 Ω
TA = 25°C
3
Figure 7
− Input Offset Voltage − mV
INPUT OFFSET VOLTAGE†
vs
COMMON-MODE INPUT VOLTAGE
ÁÁ
ÁÁ
VIO
VIC − Common-Mode Input Voltage − V
1
0.8
0.6
0.4
0.2
0
−0.2
−0.4
−0.6
−0.8
−1
−1012345
VDD = 5 V
RS = 50 Ω
TA = 25°C
Figure 8
DISTRIBUTION OF TLV2252 INPUT OFFSET
VOLTAGE TEMPERATURE COEFFICIENT†
Percentage of Amplifiers − %
αVIO − Temperature Coefficient − µV/°C
15
10
5
0
20
25
−2 −1 0 1 2
62 Amplifiers From 1 Wafer Lot
VDD± = ±1.5 V
P Package
TA = 25°C to 85°C
Figure 9
DISTRIBUTION OF TLV2252 INPUT OFFSET
VOLTAGE TEMPERATURE COEFFICIENT†
Percentage of Amplifiers − %
αVIO − Temperature Coefficient − µV/°C
15
10
5
0
20
25
−2 −1 0 1 2
62 Amplifiers From 1 Wafer Lot
VDD± = ±2.5 V
P Package
TA = 25°C to 85°C
†For all curves where VDD = 5 V, all loads are referenced to 2.5 V. For all curves where VDD = 3 V, all loads are referenced to 1.5 V.
SGLS217B − NOVEMBER 2003 − REVISED JUNE 2006
16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 10
DISTRIBUTION OF TLV2254 INPUT OFFSET
VOLTAGE TEMPERATURE COEFFICIENT
Percentage of Amplifiers − %
αVIO − Temperature Coefficient
of Input Offset Voltage − µV/°C
10
5
0
20
15
25
−2 −1 0 1 2
62 Amplifiers From 1 Wafer Lot
VDD± = ±1.5 V
P Package
TA = 25°C to 85°C
Figure 11
DISTRIBUTION OF TLV2254 INPUT OFFSET
VOLTAGE TEMPERATURE COEFFICIENT
Percentage of Amplifiers − %
αVIO − Temperature Coefficient
of Input Offset Voltage − µV/°C
10
5
0
20
15
25
−2 −1 0 1 2
62 Amplifiers From 1 Wafer Lot
VDD± = ±2.5 V
P Package
TA = 25°C to 85°C
Figure 12
IIB and IIO − Input Bias and Input Offset Currents − pA
INPUT BIAS AND INPUT OFFSET CURRENTS†
vs
FREE-AIR TEMPERATURE
IIB IIO
TA − Free-Air Temperature − °C
20
15
25 45 65
25
30
35
85
IIB IIO
10
5
0105 125
VDD± = ±2.5 V
VIC = 0
VO = 0
RS = 50 Ω
Figure 13
0
2
1 1.5 2 2.5
− Input Voltage − V
1
0.5
1.5
INPUT VOLTAGE
vs
SUPPLY VOLTAGE
2.5
3 3.5 4
−0.5
−1
−1.5
−2
−2.5
RS = 50 Ω
TA = 25°C
| VIO | ≤5 mV
ÁÁ
ÁÁ
VI
| VDD± | − Supply Voltage − V
†Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
SGLS217B − NOVEMBER 2003 − REVISED JUNE 2006
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 14
− Input Voltage − V
INPUT VOLTAGE†‡
vs
FREE-AIR TEMPERATURE
ÁÁ
VI
TA − Free-Air Temperature − °C
2
1
0
3
4
5
−1
−55 −35 −15 5 25 45 65 85
| VIO | ≤5 mV
VDD = 5 V
105 125
Figure 15
− High-Level Output Voltage − V
HIGH-LEVEL OUTPUT VOLTAGE†‡
vs
HIGH-LEVEL OUTPUT CURRENT
ÁÁ
ÁÁ
ÁÁ
VOH
| IOH | − High-Level Output Current − µA
2
1.5
1
00 200 400
2.5
3
600 800
VDD = 3 V
TA = −40°C
TA = 25°C
TA = 85°C
0.5
TA = 125°C
Figure 16
0.6
0.4
0.2
00123
− Low-Level Output Voltage − V
0.8
1
LOW-LEVEL OUTPUT VOLTAGE‡
vs
LOW-LEVEL OUTPUT CURRENT
1.2
45
ÁÁ
ÁÁ
VOL
IOL − Low-Level Output Current − mA
VDD = 3 V
TA = 25°C
VIC = 0
VIC = 0.75 V
VIC = 1.5 V
Figure 17
− Low-Level Output Voltage − V
LOW-LEVEL OUTPUT VOLTAGE†‡
vs
LOW-LEVEL OUTPUT CURRENT
ÁÁ
ÁÁ
VOL
IOL − Low-Level Output Current − mA
0.4
0.2
1.2
0012 3
0.8
0.6
1
1.4
45
TA = 85°C
TA = − 40°C
TA = 25°C
TA = 125°C
VDD = 3 V
VIC = 1.5 V
†Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
‡For all curves where VDD = 5 V, all loads are referenced to 2.5 V. For all curves where VDD = 3 V, all loads are referenced to 1.5 V.
SGLS217B − NOVEMBER 2003 − REVISED JUNE 2006
18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 18
− High-Level Output Voltage − V
HIGH-LEVEL OUTPUT VOLTAGE†‡
vs
HIGH-LEVEL OUTPUT CURRENT
ÁÁ
ÁÁ
VOH
| IOH | − High-Level Output Current − µA
3
2
1
00 200 400
4
5
600 800
VDD = 5 V
TA = −40°C
TA = 25°C
TA = 125°C
TA = 85°C
Figure 19
− Low-Level Output Voltage − V
LOW-LEVEL OUTPUT VOLTAGE†‡
vs
LOW-LEVEL OUTPUT CURRENT
ÁÁ
ÁÁ
VOL
IOL − Low-Level Output Current − mA
0.6
0.4
0.2
001 2 3
1
1.2
1.4
456
0.8
VDD = 5 V
VIC = 2.5 V
TA = −40°C
TA = 85°C
TA = 25°C
TA = 125°C
Figure 20
− Maximum Peak-to-Peak Output Voltage − V
f − Frequency − Hz
MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE‡
vs
FREQUENCY
ÁÁ
ÁÁ
ÁÁ
VO(PP)
4
2
1
5
3
0102103104105
RI = 50 kΩ
TA = 25°C
VDD = 5 V
VDD = 3 V
Figure 21
− Short-Circuit Output Current − mA
SHORT-CIRCUIT OUTPUT CURRENT
vs
SUPPLY VOLTAGE
IOS
VDD − Supply Voltage − V
5
3
1
2345
7
8
10
678
9
6
4
2
0
−1
VID = −100 mV
VID = 100 mV
VO = VDD/2
TA = 25°C
VIC = VDD/2
†Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
‡For all curves where VDD = 5 V, all loads are referenced to 2.5 V. For all curves where VDD = 3 V, all loads are referenced to 1.5 V.
SGLS217B − NOVEMBER 2003 − REVISED JUNE 2006
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 22
− Short-Circuit Output Current − mA
SHORT-CIRCUIT OUTPUT CURRENT†
vs
FREE-AIR TEMPERATURE
IOS
TA − Free-Air Temperature − °C
11
10
9
8
7
6
5
4
3
2
1
0
−1 −50 −25 0 25 50 75 100
VID = −100 mV
VID = 100 mV
VO = 2.5 V
VDD = ±5 V
−75 125
Figure 23
0
800
0 0.5 1 1.5
− Differential Input Voltage −
400
200
600
DIFFERENTIAL INPUT VOLTAGE‡
vs
OUTPUT VOLTAGE
1000
2 2.5 3
−200
−400
−600
−800
−1000
VDD = 3 V
RI = 50 kΩ
VIC = 1.5 V
TA = 25°C
VID Vµ
VO − Output Voltage − V
Figure 24
0
800
01 3
− Differential Input Voltage −
400
200
600
DIFFERENTIAL INPUT VOLTAGE‡
vs
OUTPUT VOLTAGE
1000
245
−200
−400
−600
−800
−1000
VID Vµ
VO − Output Voltage − V
VDD = 5 V
VIC = 2.5 V
RL = 50 kΩ
TA = 25°C
Figure 25
DIFFERENTIAL VOLTAGE AMPLIFICATION†‡
vs
LOAD RESISTANCE
RL − Load Resistance − kΩ
− Differential Voltage Amplification − V/mV
ÁÁ
ÁÁ
AVD
110
1102103
102
101
1
103
104VO(PP) = 2 V
TA = 25°C
VDD = 5 V
VDD = 3 V
†Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
‡For all curves where VDD = 5 V, all loads are referenced to 2.5 V. For all curves where VDD = 3 V, all loads are referenced to 1.5 V.
SGLS217B − NOVEMBER 2003 − REVISED JUNE 2006
20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
om − Phase Margin
φm
f − Frequency − Hz
LARGE-SIGNAL DIFFERENTIAL VOLTAGE†
AMPLIFICATION AND PHASE MARGIN
vs
FREQUENCY
AVD − Large-Signal Differential
ÁÁ
ÁÁ
ÁÁ
AVD
Voltage Amplification − dB
20
80
60
40
0
−20
−40
103104105106107
180°
135°
90°
45°
0°
−45°
−90°
Gain
VDD = 5 V
RL = 50 kΩ
CL= 100 pF
TA = 25°C
Phase Margin
Figure 26
om − Phase Margin
φm
f − Frequency − Hz
LARGE-SIGNAL DIFFERENTIAL VOLTAGE†
AMPLIFICATION AND PHASE MARGIN
vs
FREQUENCY
AVD − Large-Signal Differential
ÁÁ
ÁÁ
ÁÁ
AVD
Voltage Amplification − dB
20
80
60
40
0
−20
−40
103104105106107
180°
135°
90°
45°
0°
−45°
−90°
Gain
VDD = 3 V
RL= 50 kΩ
CL= 100 pF
TA = 25°C
Phase Margin
Figure 27
†For all curves where VDD = 5 V, all loads are referenced to 2.5 V. For all curves where VDD = 3 V, all loads are referenced to 1.5 V.
SGLS217B − NOVEMBER 2003 − REVISED JUNE 2006
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 28
LARGE-SIGNAL DIFFERENTIAL†‡
VOLTAGE AMPLIFICATION
vs
FREE-AIR TEMPERATURE
TA − Free-Air Temperature − °C
− Large-Signal Differential Voltage
AVD Amplification − V/mV
−50 −25 0 25 50 75 100
RL = 50 kΩ
RL = 1 MΩ
104
103
102
101
VDD = 3 V
VIC = 1.5 V
VO = 0.5 V to 2.5 V
−75 125
Figure 29
LARGE-SIGNAL DIFFERENTIAL†‡
VOLTAGE AMPLIFICATION
vs
FREE-AIR TEMPERATURE
TA − Free-Air Temperature − °C
− Large-Signal Differential Voltage
AVD Amplification − V/mV
−50 −25 0 25 50 75 100 125
VDD = 5 V
VIC = 2.5 V
VO = 1 V to 4 V
RL = 50 kΩ
RL = 1 MΩ
104
103
102
101
−75
Figure 30
− Output Impedance −
f− Frequency − Hz
OUTPUT IMPEDANCE‡
vs
FREQUENCY
Ω
zo
10
1
0.1
1000
100
102103104105106
AV = 100
AV = 10
AV = 1
VDD = 3 V
TA = 25°C
Figure 31
− Output Impedance −
f− Frequency − Hz
OUTPUT IMPEDANCE‡
vs
FREQUENCY
Ω
zo
10
1
0.1
1000
100
102103104105106
AV = 100
AV = 10
AV = 1
VDD = 5 V
TA = 25°C
†Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
‡For all curves where VDD = 5 V, all loads are referenced to 2.5 V. For all curves where VDD = 3 V, all loads are referenced to 1.5 V.
SGLS217B − NOVEMBER 2003 − REVISED JUNE 2006
22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 32
CMRR − Common-Mode Rejection Ratio − dB
f − Frequency − Hz
COMMON-MODE REJECTION RATIO†
vs
FREQUENCY
80
40
20
0
100
60
101102103104105106
VDD = 5 V
VIC = 2.5 V
VDD = 3 V
VIC = 1.5 V
TA = 25°C
Figure 33
CMMR − Common-Mode Rejection Ratio − dB
COMMON-MODE REJECTION RATIO†‡
vs
FREE-AIR TEMPERATURE
TA − Free-Air Temperature − °C
86
82
80
92
84
90
88
94
VDD = 5 V
VDD = 3 V
− 50 − 25 0 25 50 75 100− 75 125
Figure 34
− Supply-Voltage Rejection Ratio − dB
f − Frequency − Hz
SUPPLY-VOLTAGE REJECTION RATIO†
vs
FREQUENCY
Á
Á
Á
kSVR
60
40
20
100
80
0
−20
kSVR−
kSVR+
101102103104105106
VDD = 3 V
TA = 25°C
Figure 35
− Supply-Voltage Rejection Ratio − dB
f − Frequency − Hz
SUPPLY-VOLTAGE REJECTION RATIO†
vs
FREQUENCY
ÁÁ
ÁÁ
ÁÁ
kSVR
100
80
60
40
20
0
−20
101102103104105106
VDD = 5 V
TA = 25°C
kSVR−
kSVR+
‡Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
†For all curves where VDD = 5 V, all loads are referenced to 2.5 V. For all curves where VDD = 3 V, all loads are referenced to 1.5 V.
SGLS217B − NOVEMBER 2003 − REVISED JUNE 2006
23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 36
− Supply-Voltage Rejection Ratio − dB
SUPPLY-VOLTAGE REJECTION RATIO†
vs
FREE-AIR TEMPERATURE
ÁÁ
ÁÁ
kSVR
TA − Free-Air Temperature − °C
100
95
90
105
110
−50 −25 0 25 50 75 100
VDD = 2.7 V to 8 V
VIC = VO = VDD /2
125−75
Figure 37
− Supply Current − Aµ
ÁÁ
ÁÁ
IDD
60
40
20
0012345
80
100
120
678
VDD − Supply Voltage − V
VO = 0
No Load
TA = 25°C
TA = 85°C
TA = −40°C
TLV2252
SUPPLY CURRENT†
vs
SUPPLY VOLTAGE
Figure 38
− Supply Current − Aµ
ÁÁ
ÁÁ
ÁÁ
IDD
120
80
40
0012345
160
200
240
678
| VDD± | − Supply Voltage − V
VO = 0
No Load
TA = 25°C
TA = 85°C
TA = −40°C
TLV2254
SUPPLY CURRENT†
vs
SUPPLY VOLTAGE
Figure 39
SR − Slew Rate −
SLEW RATE‡
vs
LOAD CAPACITANCE
CL − Load Capacitance − pF
sµ
V/
0.16
0.08
0.04
0
0.2
0.12
101102103104
VDD = 5 V
AV = −1
TA = 25°C
SR−
0.18
0.14
0.1
0.06
0.02
SR+
†Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
‡For all curves where VDD = 5 V, all loads are referenced to 2.5 V. For all curves where VDD = 3 V, all loads are referenced to 1.5 V.
SGLS217B − NOVEMBER 2003 − REVISED JUNE 2006
24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 40
SR − Slew Rate −
SLEW RATE†‡
vs
FREE-AIR TEMPERATURE
sµ
V/
TA − Free-Air Temperature − °C
0.08
0.04
0
0.12
0.16
0.2
−50 −25 0 25 50 75 100
SR−
SR+
VDD = 5 V
RL = 50 kΩ
CL = 100 pF
AV = 1
−75 125
Figure 41
− Output Voltage − V
INVERTING LARGE-SIGNAL PULSE
RESPONSE†
VO
t − Time − µs
1.5
1
0.5
00 102030405060
2
2.5
3
70 80 90 100
AV = −1
TA = 25°C
VDD = 3 V
RL = 50 kΩ
CL = 100 pF
Figure 42
INVERTING LARGE-SIGNAL PULSE
RESPONSE†
t − Time − µs
− Output Voltage − V
VO
2
1
00 102030405060
3
4
5
70 80 90 100
VDD = 5 V
RL = 50 kΩ
CL = 100 pF
AV = −1
TA = 25°C
Figure 43
VOLTAGE-FOLLOWER LARGE-SIGNAL
PULSE RESPONSE†
− Output Voltage − V
VO
t − Time − µs
1.5
1
0.5
00 102030405060
2
2.5
3
70 80 90 100
AV = 1
TA = 25°C
VDD = 3 V
RL = 50 kΩ
CL = 100 pF
†Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
‡For all curves where VDD = 5 V, all loads are referenced to 2.5 V. For all curves where VDD = 3 V, all loads are referenced to 1.5 V.
SGLS217B − NOVEMBER 2003 − REVISED JUNE 2006
25
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 44
VOLTAGE-FOLLOWER LARGE-SIGNAL
PULSE RESPONSE†
− Output Voltage − V
VO
t − Time − µs
2
1
00 102030405060
3
4
5
70 80 90 100
VDD = 5 V
RL = 50 kΩ
CL = 100 pF
AV = 1
TA = 25°C
Figure 45
INVERTING SMALL-SIGNAL
PULSE RESPONSE†
− Output Voltage − V
VO
t − Time − µs
0.7
0.65
0.9
0.60102030
0.8
0.75
0.85
0.95
40 50
VDD = 3 V
RL = 50 kΩ
CL = 100 pF
AV = −1
TA = 25°C
Figure 46
VO − Output Voltage − V
INVERTING SMALL-SIGNAL
PULSE RESPONSE†
VO
t − Time − µs
2.5
2.45
2.4 0102030
2.55
2.6
2.65
40 50
VDD = 5 V
RL = 50 kΩ
CL = 100 pF
AV = −1
TA = 25°C
Figure 47
VOLTAGE-FOLLOWER SMALL-SIGNAL
PULSE RESPONSE†
VO − Output Voltage − V
VO
t − Time − µs
0.8
0.75
0.6 0102030
0.85
0.9
0.95
40 50
0.7
0.65
VDD = 3 V
RL = 50 kΩ
CL = 100 pF
AV = 1
TA = 25°C
†For all curves where VDD = 5 V, all loads are referenced to 2.5 V. For all curves where VDD = 3 V, all loads are referenced to 1.5 V.
SGLS217B − NOVEMBER 2003 − REVISED JUNE 2006
26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 48
VOLTAGE-FOLLOWER SMALL-SIGNAL
PULSE RESPONSE†
VO − Output Voltage − V
VO
t − Time − µs
2.5
2.45
2.4 0102030
2.55
2.6
2.65
40 50
VDD = 5 V
RL = 50 kΩ
CL = 100 pF
AV = 1
TA = 25°C
Figure 49
− Equivalent Input Noise Voltage −
f − Frequency − Hz
EQUIVALENT INPUT NOISE VOLTAGE†
vs
FREQUENCY
VnnV/ Hz
40
30
20
0
60
50
10
101102103104
VDD = 3 V
RS = 20 Ω
TA = 25°C
Figure 50
− Equivalent Input Noise Voltage −
f − Frequency − Hz
EQUIVALENT INPUT NOISE VOLTAGE†
vs
FREQUENCY
VnnV/ Hz
40
20
10
0
60
30
50
101102103104
VDD = 5 V
RS = 20 Ω
TA = 25°C
Figure 51
Noise Voltage − nV
t − Time − s
INPUT NOISE VOLTAGE OVER
A 10-s PERIOD†
0246
0
750
1000
810
500
−250
−500
−750
−1000
250
VDD = 5 V
f = 0.1 Hz to 10 Hz
TA = 25°C
†For all curves where VDD = 5 V, all loads are referenced to 2.5 V. For all curves where VDD = 3 V, all loads are referenced to 1.5 V.
SGLS217B − NOVEMBER 2003 − REVISED JUNE 2006
27
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 52
Integrated Noise Voltage −
f − Frequency − Hz
INTEGRATED NOISE VOLTAGE†
vs
FREQUENCY
Vµ
0.1
1
10
100
110
1102103104105
Calculated Using Ideal Pass-Band Filter
Low Frequency = 1 Hz
TA = 25°C
Figure 53
THD + N − Total Harmonic Distortion Plus Noise − %
f − Frequency − Hz
TOTAL HARMONIC DISTORTION PLUS NOISE†
vs
FREQUENCY
0.01
1
0.001
101102103104105
AV = 10
AV = 1 VDD = 5 V
RL = 50 kΩ
TA = 25°C
0.1
AV = 100
Figure 54
Gain-Bandwidth Product − kHz
GAIN-BANDWIDTH PRODUCT
vs
SUPPLY VOLTAGE
VDD − Supply Voltage − V
200
190
180
170 0235
210
220
78
146
Figure 55
Gain-Bandwidth Product − kHz
GAIN-BANDWIDTH PRODUCT†‡
vs
FREE-AIR TEMPERATURE
TA − Free-Air Temperature − °C
220
140
100
260
300
−50 −25 0 25 50 10075
180
VDD = 5 V
f = 10 kHz
RL = 50 kHz
CL = 100 pF
125−75
†For all curves where VDD = 5 V, all loads are referenced to 2.5 V. For all curves where VDD = 3 V, all loads are referenced to 1.5 V.
SGLS217B − NOVEMBER 2003 − REVISED JUNE 2006
28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 56
om − Phase Margin
PHASE MARGIN
vs
LOAD CAPACITANCE
CL − Load Capacitance − pF
m
φ
101102103104
75°
60°
45°
30°
15°
0°
Rnull = 200 Ω
Rnull = 500 Ω
Rnull = 50 Ω
Rnull = 0
TA = 25°C
Rnull = 100 Ω
Rnull = 10 Ω
50 kΩ
50 kΩ
VDD−
VDD+ Rnull
CL
VI+
−
Figure 57
Gain Margin − dB
GAIN MARGIN
vs
LOAD CAPACITANCE
CL − Load Capacitance − pF
20
10
5
0
15
101102103105
Rnull = 100 Ω
TA = 25°C
Rnull = 50 Ω
104
Rnull = 500 Ω
Rnull = 200 Ω
Rnull = 0
Rnull = 10 Ω
Figure 58
− Unity-Gain Bandwidth − kHz
UNITY-GAIN BANDWIDTH
vs
LOAD CAPACITANCE
CL − Load Capacitance − pF
ÁÁ
ÁÁ
B1
150
25
100
0
200
125
175
50
75
10110210310410
5
TA = 25°C
†See application information
Figure 59
Overestimation of Phase Margin
OVERESTIMATION OF PHASE MARGIN
†
vs
LOAD CAPACITANCE
CL − Load Capacitance − pF
15
10
5
0
20
25
101102103104105
TA = 25°C
Rnull = 100 Ω
Rnull = 50 Ω
Rnull = 10 Ω
Rnull = 500 Ω
Rnull = 200 Ω
‡Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
†For all curves where VDD = 5 V, all loads are referenced to 2.5 V. For all curves where VDD = 3 V, all loads are referenced to 1.5 V.
SGLS217B − NOVEMBER 2003 − REVISED JUNE 2006
29
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
driving large capacitive loads
The TLV2252 is designed to drive larger capacitive loads than most CMOS operational amplifiers. Figure 56
and Figure 57 illustrate its ability to drive loads up to 1000 pF while maintaining good gain and phase margins
(Rnull = 0).
A smaller series resistor (Rnull) at the output of the device (see Figure 60) improves the gain and phase margins
when driving large capacitive loads. Figure 55 and Figure 56 show the effects of adding series resistances of
10 Ω, 50 Ω, 100 Ω, 200 Ω, and 500 Ω. The addition of this series resistor has two ef fects – the first adds a zero
to the transfer function and the second reduces the frequency of the pole associated with the output load in the
transfer function.
The zero introduced to the transfer function is equal to the series resistance times the load capacitance. To
calculate the improvement in phase margin, equation 1 can be used.
∆φm1 +tan–1 ǒ2×π×UGBW×Rnull ×CLǓ
∆φm1
UGBW
Rnull
CL
(1)
Where : = improvement in phase margin
= unity-gain bandwidth frequency
= output series resistance
= load capacitance
The unity-gain bandwidth (UGBW) frequency decreases as the capacitive load increases (see Figure 58). To
use equation 1, UGBW must be approximated from Figure 58.
Using equation 1 alone overestimates the improvement in phase margin as illustrated in Figure 59. The
overestimation is caused by the decrease in the frequency of the pole associated with the load, providing
additional phase shift and reducing the overall improvement in phase margin.
Using Figure 60, with equation 1 enables the designer to choose the appropriate output series resistance to
optimize the design of circuits driving large capacitance loads.
50 kΩ
50 kΩ
VDD−/GND
VDD+
Rnull
CL
VI+
−
Figure 60. Series-Resistance Circuit
SGLS217B − NOVEMBER 2003 − REVISED JUNE 2006
30 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
macromodel information
Macromodel information provided was derived using Microsim Parts, the model generation software used
with Microsim PSpice. The Boyle macromodel (see Note 5) and subcircuit in Figure 61 are generated using
the TLV2252 typical electrical and operating characteristics at TA = 25°C. Using this information, output
simulations of the following key parameters can be generated to a tolerance of 20% (in most cases):
DMaximum positive output voltage swing
DMaximum negative output voltage swing
DSlew rate
DQuiescent power dissipation
DInput bias current
DOpen-loop voltage amplification
DUnity-gain frequency
DCommon-mode rejection ratio
DPhase margin
DDC output resistance
DAC output resistance
DShort-circuit output current limit
NOTE 4: G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Integrated Circuit Operational Amplifiers,” IEEE Journal
of Solid-State Circuits, SC-9, 353 (1974).
OUT
+
−
+
−
+
−
+
−
+
−
+
−
+
−+
−
+−
.SUBCKT TLV225x 1 2 3 4 5
C1 11 12 6.369E−12
C2 6 7 25.00E−12
DC 5 53 DX
DE 54 5 DX
DLP 90 91 DX
DLN 92 90 DX
DP 4 3 DX
EGND 99 0 POLY (2) (3,0) (4,0) 0 .5 .5
FB 7 99 POLY (5) VB VC VE VLP
+ VLN 0 57.62E6 −60E6 60E6 60E6 −60E6
GA 6 0 11 12 26.86E−6
GCM 0 6 10 99 2.686E−9
ISS 3 10 DC 3.1E−6
HLIM 90 0 VLIM 1K
J1 11 2 10 JX
J2 12 1 10 JX
R2 6 9 100.0E3
RD1 60 11 37.23E3
RD2 60 12 37.23E3
R01 8 5 84
R02 7 99 84
RP 3 4 71.43E3
RSS 10 99 64.52E6
VAD 60 4 −.5
VB 9 0 DC 0
VC 3 53 DC .605
VE 54 4 DC .605
VLIM 7 8 DC 0
VLP 91 0 DC −0.235
VLN 0 92 DC 7.5
.MODEL DX D (IS=800.0E−18)
.MODEL JX PJF (IS=500.0E−15 BETA=139E−6
+ VTO=−.05)
.ENDS
VCC+
RP
IN − 2
IN+ 1
VCC−
VAD
RD1
11
J1 J2
10
RSS ISS
3
12
RD2
60
VE
54 DE
DP
VC
DC
4
C1
53
R2 6
9
EGND
VB
FB
C2
GCM GA VLIM
8
5RO1
RO2
HLIM
90 DLP
91
DLN
92
VLNVLP
99
7
Figure 61. Boyle Macromodel and Subcircuit
PSpice and Parts are trademarks of MicroSim Corporation.
PACKAGE OPTION ADDENDUM
www.ti.com 17-Dec-2015
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TLV2252AQDREP ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 2252AE
TLV2254AQDREP ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 TLV2254AEP
V62/04651-02UE ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 2252AE
V62/04651-04XE ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 TLV2254AEP
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
PACKAGE OPTION ADDENDUM
www.ti.com 17-Dec-2015
Addendum-Page 2
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TLV2252-EP, TLV2252A-EP, TLV2254-EP, TLV2254A-EP :
•Catalog: TLV2252, TLV2252A, TLV2254, TLV2254A
•Automotive: TLV2252-Q1, TLV2252A-Q1, TLV2254-Q1, TLV2254A-Q1
•Military: TLV2252M, TLV2252AM, TLV2254M, TLV2254AM
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•Military - QML certified for Military and Defense Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TLV2252AQDREP SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TLV2254AQDREP SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Dec-2015
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLV2252AQDREP SOIC D 8 2500 367.0 367.0 35.0
TLV2254AQDREP SOIC D 14 2500 333.2 345.9 28.6
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Dec-2015
Pack Materials-Page 2
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