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QSFP28 Optical Transceiver — Up to 2 km reach for 100G FEC-enabled systems
www.lumentum.com 3
Section 1 Functional Description
The Lumentum 100G QFP28 CWDM4 optical transceiver is a full
duplex device with both transmit and receive functions contained
in a single module. The optical signals are multiplexed to a
single-mode ber through an industry standard LC connector.
The module provides a high speed link at an aggregated signaling
rate of 103.125 Gbps. It is compliant with: 100G CWDM4 MSA
Technical Specication Rev 1.0 and the IEEE 802.3bm CAUI-4
chip-to-module electrical specications at 103.125 Gbps. The
two-wire management interface complies with SFF-8636. The
transceiver mechanical design complies with SFF-8661 and the
base electrical design complies with SFF-8679. A block diagram is
shown in Figure 1.
IntL
LPMode
Monitoring&
Control
2
-Wire SCL
,SDA
ResetL
ModselL
ModPresL
LDD
LDD
LDD
LDD
CDR/
Limiting
Amplier
CDR/
Equalizer
38-pin Connector
TIA
TIA
TIA
TIA
Vcc_Tx
Vcc_Rx
Vcc1
Power
Supplies
Optical
Mux
Duplex LC Connector
Optical
DeMux
Figure 1. Lumentum QSFP28 CWDM4 Optical Transceiver functional
block diagram
Transmitter
The transmitter path converts four lanes of serial NRZ electrical
data from line rate of 25.78 Gbps to a standard compliant optical
signal. Each signal path, accepts a 100 differential 100 mV
peak-to-peak to 900 mV peak-to-peak electrical signal on TDxn
and TDxp pins. Inside the module, each differential pair of electric
signals is input to an equalizer and then to a CDR (clock- data
recovery) chip. The recovered and retimed signals are then
passed to a laser driver which transforms the small swing voltage
to an output modulation that drives an un-cooled EML laser. The
laser drivers control four EMLs with center wavelengths of 1271
nm, 1291 nm, 1311 nm and 1331 nm, respectively. The optical
signals from the four lasers are optically multiplexed and coupled
to single-mode optical ber through an industry standard LC
optical connector. The optical signals are engineered to meet the
CWDM4 MSA specications.
Receiver
The receiver takes incoming combined four lanes of DC balanced
CWDM NRZ optical data from line rate of 25.78 Gbps through an
industry standard LC optical connector. The four incoming
wavelengths are separated by an optical demultiplexer into four
separated channels. Each output is coupled to a PIN
photodetector. The electrical currents from each PIN
photodetector are converted to a voltage in a high-gain
transimpedance amplier. The electrical output is recovered and
retimed by the CDR chip. The four lanes of reshaped electrical
signals are output on the RDxp and RDxn pins as a 100
differential CAUI-4 chip-to-module signals.
Low-Speed Signaling
The Lumentum 100G QSFP28 CWDM4 Optical Transceiver has
several low-speed interface connections including a 2-wire serial
interface (SCL and SDA). These connections include; Low Power
Mode (LPMode), Module Select (ModSelL), Interrupt (IntL), Module
Present (ModPrsL) and Reset (ResetL) as shown in Figure 1.
ModSelL: The ModSelL is an input pin. When held low by the
host, the module responds to 2-wire serial communication
commands. The ModSelL allows the use of multiple QSFP28
modules on a single 2-wire interface bus. When the ModSelL is
“High”, the module does not respond to or acknowledge any
2-wire interface communication from the host.
In order to avoid conflicts, the host system shall not attempt
2-wire interface communications within the ModSelL de-assert
time after any QSFP28 module is deselected. Similarly the host
must wait for at least the ModSelL assert period of time before
communicating with a newly selected module. The assertion and
de-assertion periods of different modules may overlap as long as
the above timing requirements are met.
ResetL: The ResetL pin is pulled up to Vcc inside the QSFP28
module. A low level on the ResetL pin for longer than the
minimum pulse length (t_Reset_init) initiates a complete module
reset, returning all user module settings to their default state.
Module Reset Assert Time (t_init) starts upon the rising edge
after the low level on the ResetL pin is released. During the
execution of a reset (t_init) the host shall disregard all status bits
until the module indicates a completion of the reset interrupt. The
module indicates this by posting an IntL signal with the Data_
Not_Ready bit negated. Note that on power up (including hot
insertion) the module will post this completion of reset interrupt
without requiring a reset.
LPMode: : The LPMode pin is pulled up to Vcc inside the QSFP28
module. This function is affected by the LPMode pin and the
combination of the Power_over-ride and Power_set software
control bits (Address A0h, byte 93, bits 0,1).
The module has two modes: a low power mode and a high power
mode. The high power mode operates in one of the four power
classes.