TOSHIBA TCIOA35N/F TENTATIVE TOSHIBA CMOS DIGITAL INTEGRATED CIRCUITS SILICON MONOLITHIC TC9SOA35N, TC90A35F NICAM /iGR AUDIO SIGNAL PROCESSORS These LSIs are designed to decode PCM and FM aural TCOOA35N signats in UK sound multiplex broadcasts (NICAM728). In addition, they also can decode IGR sound multiplex broadcasts. The QPSK modulating signal in UK sound multiplex broadcasts are capable of doing digital QPSK demodulation and PCM decoding, and also can demodulate 1-channel FM sound signal. (Simultaneous NICAM and FM outputs are not supported.) Using a digital PLL for QPSK demodulation and a digital SDIP64-P-750-1.78 OSC for FM demoduiation, these can modulate i, B/G and any carrier used, with a single crystal. In addition, they allow for significant reduction in external part counts and materialize adjustment-free operation. TC9O0A35F FEATURES Decodes NICAM sound. @ Decodes FM sound. Decodes 2-carrier FM (IGR) sound. OFP80-P-1420-0.80A Uses digital PLL and digital OSC for multicarrier capability. Weight * Uses digital BPF to provide BPF characteristics matched to OPE? 1450.0 DA ; Tea} each system. Contains digital emphasis circuit for FM and PCM, Interfaces with a microcomputer via the I?C bus. Uses AGC circuit to stabilize input signal levets. Operates with a single crystal (18.432 MHz). Greatly reduces part counts thanks to digital processing. Operates with a single SV power supply. Package : QFP8O or SDIP64 (*) These products are under development. Specifications are subject to change without notice. 98091 0EBA) @ TOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. itis the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or damage to property. in developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent products specifications. Alsc, please keep in mind the precautions and conditions set forth in the TOSHIBA Semicanductor Reliability Handbook, Sire products described in this document are subject to the foreign exchange and foreign trade laws. The information contained herein is presented only as a gulde for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual Property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intelectual property or other rights of TOSHIBA CORPORATION or others, @ The information contained herein is subject to change without notice.TOSHIBA BLOCK DIAGRAM TC90A35N/F FM /PCM Digital 1/F DIFO osei nt yas pum] | STEREC MPX FM DEMO PILOT Det. De-emphasis f= DATA I/F I AGC AID our bit DAC ROUT RAM SIF sir2 MPX EM DEMO PCM DECODER ~_ oscz QPSK DEMO Re WF CLOCK PLL xO [Xl APCFO APCFI ; =u SCL SDA 18.432 MHz w : AR WA,TC9OA35N/F TOSHIBA PIN CONNECTION (QFP80) TCOOA35F ON ON ON 9 D 2 3 2 2 S) 2 2 2) 2 2) q) 3 3) 9) S) 2 3 9 3) 3) D Td, LAO TSS, J3U, USS, inoy (SDIP64) (FY SS, GJ] cia Gy viva (Z] x04 (Rp ow (] oo Gy was 3] FD (ap ZO, (G] Wd (Gy itas (S] z1as (SI 1s (2] LNow (Gl ZNow (@) v2 (S] ainw er () O24 (S] ZS5p, (AJ saad (Gay dus (SJ aLvoa (2) vivaa 6 (B] vivaes G vivayu (By 13 (j] 279 (S] 0011 (B] tor. (Sh Ed, NSEVOGOL Ds vas 1asay wlSaL 1S 3 zisdi Wiss lad, 10d, ino 15S, 134, USS a ano wad, OvSS, swid 113M, Hide, avad, op JovId, ZNISIS 43uD LNIAIS IOVS Sn 1d)d Od) d Xdd, 1x ox X5S,, 2925) G5) G7 GB) 9 BD GN GD OOS OO OO OG OOD @ GOW VOIOWTOSHIBA TC9OA35N/F PIN CONNECTION (QFP80) PIN No. PIN NAME 1/0 FUNCTION 1 NC _ _ 2 NC _ 3 NC _ _ 4 Nc _ 5 AGCReEF ~__| AGC reference 6 SIFIN2 | SIF IN2 7 VDDAGC __|AGC-Vpp 8 AGCO 1/0 [AGC test 1/0 9 VDDAD ~~ _ |ADC-Vpp 10 VREFH |ADC bias pin H 11 VREFL __|ADC bias pin 1 12 BIAS |ADC bias pin 13 VsSAD |ADC-Vss 14 Vopr __| Power supply for R-channel sound output filter 15 RouUT O | R-channel sound output 16 VssR ~__|GND for R-channel sound output filter 17 VREE _|1-bit DAC reference power supply 18 VSS-L __| GND for L-channel sound output filter 19 LOUT O {L-channel sound output 20 Vppi __|Power supply for L-channef sound output filter 21 NC 22 NC 23 NC 24 Nc _ 25 Vpp1 _ | Digital power supply 1 26 TEST1 i Test pin 1 27 TEST2 | Test pin 2 28 TEST3 | Test pin 3 29 TEST4 [| Test pin 4 30 RESET | Reset pin 31 SDA 1/O jC bus data pin 32 SCL | {IC bus clock pin 33 Vss1 | Digital GND 34 DIFO O | Digital |/F output 35 DATA QO | External DAC data output 36 BCK O | External DAC shift clock output 37 LRCK O | External DAC L/R clock output 38 CKO O | External DAC clock output 39 FRM O | Frame sync signal output 40 CK1 QO {Carrier output a1 Nc 42 NC - TOSHIBA TCS90A35N/F PIN No. ; PIN NAME 1/0 FUNCTION 43 NC _ _ 44 Nc _ 45 Vpp2 ~ |Digital power supply 2 46 PCMFM | {Analog sound PCM/FM switch 47 SEL1 I Digital sound select input 1 48 SEL2 I Digital sound select input 2 49 ST O | Stereo mode sound output 50 MON1 oO Monaural mode sound output 1 51 MON2 | Monaural mode sound output 2 52 c4 O |C4 mode display output 53 MUTE! I Sound mute input 54 PMUTEO | PCM mute signal output 55 FMUTEO | FM mute signa! output 56 Vss2 | Digital GND 57 PERR O | Parity error output 58 SERR QO | Sync error output 59 DGATE QO | Data GATE signal output 60 DDATA O | Data output 61 Nc _ 62 NC 63 NC 64 NC 65 Vss3 _ |Digital GND 66 C3DATA O |C3 data output 67 RDATA O {QPSK demodulation signal output 68 RCLK O [Clock output (728 kHz) 69 MCLK O |Clock output (carrier frequency) 70 TIOO 1/0 | Test 1/0 71 T1014 [1/0 |Test 1/0 72 Vpp3 ~ [Digital power supply 3 73 Vssx |VCXO-GND 74 XO O | Crystal ascillatian output 75 Xl | Crystal oscillation input 76 VopX [VCXO-Vpp 77 APCFO O | APC filter output 78 APCFI I APC filter input 79 VSSAGC _|Vss-AGC 80 SIFING | SIF IN4TOSHIBA PIN CONNECTION (SDIP64) TCSO0A35N/F PIN No. j} PIN NAME 1/0 FUNCTION 1 VssXx _ | VCXO-GND 2 xO O |Crystal oscillation output 3 x! | Crystal oscillation input 4 VopXx |VCXO-Vop 5 APCFO O [APC filter output 6 APCFI I APC filter input 7 VssAGC __|Vss-AGC 8 SIFING | SIF IN1 9 AGCreEF |AGC reference 10 SIFIN2 | SIF IN2 1 VppaGe _|AGC-Vop 12 AGCO 1/0 | AGC test 1/0 13 VDDAD |ADC-Vpp 14 VREFH [ADC bias pin H 15 VREFL |ADC bias pin L 16 BIAS |ADC bias pin 17 VssAD |ADC-Ve5 18 Vpor __| Power supply for R-channel sound output filter 19 ROUT R-channel sound output 20 Vssr __|GND for R-channel sound output fitter 21 VREF __|1-bit DAC reference power supply 22 VS5sL _|GND for L-channel sound output filter 23 Lout | L-channef sound output 24 VDDL __| Power supply for L-channel sound output filter 25 Voo1 __| Digital power supply 1 26 TEST1 | Test pin 1 27 TEST2 | Test pin 2 28 TEST3 I Test pin 3 29 TEST4 i Test pin 4 30 RESET J Reset pin 31 SDA 1/0 |i? bus data pin 32 SCL | I?C bus clock pin 33 Vss1 | Digital GND 34 DIFO O | Digital |/F output 35 DATA O | External DAC data output 36 BCK O | External DAC shift clock output 37 LRCK O {External DAC L/R clock output 38 cKO O | External DAC clock output 39 FRM O |Frame sync signal output 40 CK1 | Carrier output 41 Vpp2 | Digital power supply 2 42 RCMFM | _|Analog sound PCM/FM switchTOSHIBA TC90A35N/F PIN No. | PIN NAME 1/0 FUNCTION 43 SEL1 i Digital sound select input 1 44 SEL2 | Digital sound select input 2 45 ST OQ |Stereo mode sound output 46 MONT O |Monaural mode sound output 1 47 MON2 |Monaural mode sound output 2 48 c4 QO |C4 mode display output a9 MUTEI | Sound mute input 50 PMUTEO | PCM mute signal output 51 FMUTEO | FM mute signal output 52 Vss2 - | Digital GND 53 PERR | Parity error output 54 SERR OQ | Sync error output 55 DGATE QO | Data GATE signal output 56 DDATA oO Data output 57 Vs553 | Digital GND 58 C3DATA QO {C3 data output 59 RDATA O | QPSK demodulation signal output 60 RCLK QO | Clock output (728 kHz) 61 MCLK O {Clock output (carrier frequency) 62 TINO 1/O |Test 1/0 63 TIO1 1/O |Test 1/0 64 Vpp3 _ | Digital power supply 3TOSHIBA TC90A35N/F MAXIMUM RATINGS (Ta = 25C) CHARACTERISTIC SYMBOL RATING UNIT Supply Voltage Vop Ves~Vs5 + 7.0 V Input Voltage VIN -0.3~Vpp + 0.3 Vv Power Dissipation Pp _ mW Storage Temperature Tstg ~55~125 C RECOMMENDED OPERATING CONDITIONS CHARACTERISTIC SYMBOL TEST CONDITION MIN. | TYP. | MAX. | UNIT Supply Voltage Vpb _ 4.75 5 | 5.25 Vv Input Voltage VIN _ 0 _ Vpp V Operating Temperature Topr _ -20 _ 75 * ELECTRICAL CHARACTERISTICS DC characteristics (Unless otherwise specified, Ta = 25C, Vpp = 5V) CHARACTERISTIC SYMBOL TEST CONDITION MIN. | TYP. | MAX. | UNIT Current Dissipation lec _ _ -{|- mA Current Dissipation lpp _ -|- mA Power Dissipation Pp _ _ _ mw High-level Input Voltage Vin _ 40); _ Vv Low-level Input Voltage VIL 1.0 Vv Hysteresis Width VH _ _ _ Vv High-level input Current WH _ - _ 10 | yA Low-level Input Current IIL ~10 , _ LA High-level Output Voltage VOHI _ _ _ _ Vv Low-level Output Voltage Vou1 _ _ V High-level Output Voltage VOH2 _ _ Vv Low-level Output Voltage VOLZ _ _ _ Vv AC characteristics (Unless otherwise specified, Ta = 25C, Vop = 5 V) CHARACTERISTIC SYMBOL TEST CONDITION MIN. | TYP. | MAX. | UNIT SCL Clock Frequency sc. [fscu = 1/TSCL 0 100 | kHz SCL High-level Duration tsH CL = 400 pF 4.0 _ _ us SCL Low-level Duration tsL CL = 400 pF 47 _ 1s Data Setup Time tos Ci = 400 pF 250 ns Data Hold Time tpH C_ = 400 pF 5.0 _ us Transfer Start Condition Hold Time tscH C_ = 400 pF 4.0 _ _ Bs Transfer End Condition Setup tecs C, = 400 pF 4? _ _ ys Time Data Transfer Cycle tBUF CL = 400 pF 47 _ us PC Rise Time tir CL = 400 pF 1.0 us I? Fall Time tf CL = 400 pF _ 300 ns [DA converter output level | DAC | { | | 347 Vp, ]TOSHIBA TC9OA35N/F AUDIO OUTPUT CHARACTERISTICS DAC Output level 3.4 Vp-p S/N (NICAM) dB S/N (FM) _ dB THP (NICAM) oe dB THD (FM) _ dB Crosstalk _ dB Channel Separation _ _ dB SIF INPUT WAVEFORM SIF Maximum Input Level _ Vp-p SIF Minimum Input Level Vp-p AGC Range dB Input Frequency Range _ MHz Input Capacitance _ _ pF Input Impedance _ 2 . -7 dB B/G RM/NICAM Level Ratio ~70 = qB FM1/FM2 Level Ratio 7 dB D/K FM / visual Signal Ratio dB Maximum FM Deviation _ THD < 1% PILOT SIGNAL Pilot Signal Modulation Ratio _ _ % Pilot Signal Level _ _ C/N _ _ d8 DIGITAL DEEMPHAS!S | Characteristic Error = dB DIGITAL FILTER Passband Ripple _ dB Passband _ _ kHz Attenuation _ dBTOSHIBA TC90A35N/F Specifications of crystal and varactor Crystal Dai-Shinku AT-49 Frequency 18.432 MHz Frequency deviation 20 * 10-S at 25C 3C Equivalent resistance 40 (1 (max.) Storage temperature range - 40~85C Operating temperature range -10~70C Temperature characteristic +20 x 10-(- 10~70C) Load capacitance 10.0 pF + 0.5 pF Drive Level 10 wW t 2 pW Shunt Capacitance 7.0 pF (max.) Insulation resistance 500 0 (min.)/100 V DC Vibration type Basic wave Varactor Hitachi HVU17 10TOSHIBA TC9OA35N/F FUNCTIONS (1) Outline 1. input block Incorporates an MPX circuit which selects one of the two input signals, an AGC circuit, and an 8- bit AD converter. Digital QPSK demodulation block Demodulates AD-converted QPSK modulation signal to PCM data. Multi-suppert system that modulates any carrier, in addition to | and B/G by digital PLL. Operates differentials and converts between parallel and serial. Use an 18.432 MHz crystal. At the same time as QPSK demodulation, can perform FM demodulation for a channel. Output from the DA converter is one of the following : (1) NICAM (two channels), (2) IGR (two channels), and (3) FM monaural (one channel). Simultaneous output of NICAM and FM monaural is not possible. _ PCM decoder block Generates digital sound data which are passed to the DA converter from the QPSK demodulation digital data. Also, decodes sound data and selects sound output, . Digital FM demodulation block Demodulates AD-converted FM modulated signal using a digital oscillator and generates digital sound data which are passed to the DA converter. With an FM demodulator which uses a digital oscillator, demodulates any carrier, such as two-carrier FM multiplex broadcasting. SW and matrix block Incorporates a switch for PCM/FM and a matrix for two-carrier FM multiplex broadcasting. Digital deemphasis block Incorporates a digital deemphasis circuit for FM and PCM. The circuit processes signals in binaseband form. Digital output block Outputs digital data conforming to JEC958. Output sound data are those after digital deemphasis. (2) Description by Block 1, SIF selector circuit Switches between two inputs, SIFIN1 and SIFIN2. I2C bus is used for switching. . AGC circuit Absorbs level fluctuations in the input signal selected by the SIF selector circuit. Can automatically control gain of signals whose input level is *** to *** MVp-p- . ADC circuit AD-converts the input signal selected by the SIF selector circuit in units of 8 bits. 11TOSHIBA TC90A35N/F 4. OSC circuit Generates a carrier frequency corresponding to that used by broadcasters in various countries. I? bus is used to set the carrier frequency. 5. Data playback circuit Calculates data differentials, converts between parallel and serial, plays back data, and generates 5.824 MHz and 728 kHz clocks in sync with data. 6. Syne circuit Detects an 8-bit sync pattern (Frame Alignment Ward, FAW) from the QPSK demodulation signal output by the data playback circuit. Checks the sync patterns are consecutive using the fact that one frame consists of 728 bits. Sync protection starts after two consecutive frames are in sync, when sync status is entered, and lasts until after six consecutive frames are out of sync, when async status is entered. Once FAW sync is established, perform sync on 16 frames using the CO bit in the control bits. CO sync protection starts after two consecutive CO frames are in sync, when sync status is entered, and lasts until after four consecutive CO frames are out of sync, when async status is entered. During async, Low level is output to SERR (TCIOA35F : pin 58, TC90A35N : pin 54) 7, Descramble circuit Operates the built-in PN code generator in syne with the frame using the frame syne pulse from the syne circuit and eliminates the PN code in the QPSK demodulation signal. For PN scramble broadcasting, switch the display pin to the decode pin. Switch using DPSL at |?c bus address B4HEX, subaddress O4HEX. For scramble broadcasting, set the FAW initial value using the [?c bus. 8. Timing generator circuit Outputs timing signals which are in syne using the frame sync pulse from the sync signal. 9. Control bit detector circuit Performs majority decision on the playback signal from the descramble circuit in units of 16 frames and outputs the control bits. Thus, data are updated every 16 frames. The detected control bits are decoded and output to C4 (TCOOA35F : pin 52, TC90A35N : pin 48), MONQ2 (TCSOA35F : pin 51, TCSOA35N : pin 47), MONO1 (TC9OA35F : pin 50, TCSQA35N : pin 46), and ST (TC90A35F : pin 49, TCIOASSN : pin 45). 10.Range bit detector circuit Detects by multiple decisions the range bit and the control information bit multiplexed with the parity bit. 11.Parlty detector circuit Using the range bit and the control information bit detected by the range bit detector circuit, eliminates the range bit and the control information bit multiplexed with the parity bit and checks the parity. 12TOSHIBA TCS90A35N/F 12.10 14-bit stretch circuit According to the range bit detected by the range bit detector circuit, stretches the 10-bit data to 14-bit. Adds 00 in the lower two bits and treats the data as 16-bit. 13.Error interpolation circuit If an error is detected by the parity detector circuit, performs data interpolation. For a single error, performs mean interpolation; for consecutive errors, holds the previous value. 14.NICAM output selector circuit If a received signal is monaural, two-channel, output to the digital filter can be selected using SEL1 and SEL2 at I?C bus address B4HEX and subaddress OOHEX, or external pin SEL1 (TCSOA35F : 47, TCS0A35N : pin 35) and external pin SEL2 (TC9DA35F : 48, TC9O0A35N : pin 36). Because the control signals are OR-ed internally, when the [?C bus is used, connecting external pins SEL1 and SEL2 to DGND selects output to the digital filter. When external pins are used, connecting SCL (TC90A35F : pin 32, TCIDA35N : pin 32) and SDA (TC90A35F : pin 31, TCSOA35N : pin 31) to BVpp makes the selection. If both control signals are set to High level, display output disappears, muting the digital sound output. 15.Muting circuit (1) PCM muting circuit The muting circuit outputs High level to PMUTE (TC9OA35FN ;: pin 54, TCSOA35N : pin 50). @ When a sync error occurs. @ When parity errors occur more than the specified number of times during the specified decision duration (approx. 0.55). At this time, it takes seven frames until a sync error occurs. If digital mute is not in use, fix MUTE! to Low level. Switch the mute threshold value using THLO to THL7 at I?C bus address B4HEX and subaddress O1HEX. Set the mute duration using CYLCEO to CYLCE4 at I2C bus address B4HEX and subaddress O2HEX. When mute is on, High level is output to PMUTEO (TC90A35F : pin 54, TC9OA35N ; pin 50). tn the muting circuit, PMUTEO (TC90A35F : pin 54, TC9O0A35N : pin 50), FMUTEO (TCSOA35F : pin 55, TC9OA35N ; pin 51), and MUTE! (TC9OA35F : pin 53, TCOQA35N : pin 49) are OR-ed. Setting the MUTEI pin to High level triggers mute regardless of errors. If the MUTEI pin is not used, connect it to digital GND. (2) FM muting circuit When the circuit is in the following condition, the muting circuit mutes the sound output. During muting, High level is output to FMUTEO (TC90A35F : pin 55, TC90A35N : 51). @ When the FM carrier cannot be detected. 13TOSHIBA TCOOA35N/F 16.1? Bus Control Circuit Extracting control bits, selecting output, or setting the operating mode is performed via the I2 bus, which is an asynchronous serial interface. A register is selected using an 8-bit address and an 8-bit subaddress which data are sent to or received from. Data are transferred from SDA in syne with the SCL clock, The contents of a register are initialized to OOHEX by inputting Low level to RESET (TC9OA35F : pin 30, TC90A35N : pin 30). Data written to a register are retained until the next data are written. (Note) After power on, set the RESET pin to Low level, then initialize before use. 17. Digital Deemphasis Circuit (1) NICAM deemphasis circuit Digitally deemphasizes digital sound signals which are digitally demodulated according to ITU-T Recommendation J.17 characteristics. The gain error is (0.25dB or below. This circuit can be turned on or off. Switching is done using NIEMP1 and NIEMP2 at I?C bus address B4HEX and subaddress 42HEX. (2) FM deemphasis circuit Deemphasizes digitally demodulated FM sound signals. This circuit can be turned on or off. Switching is done using FMEMP1 and FMEMP2 at [C bus address B4HEX and subaddress 41HEX. 14TOSHIBA TC90A35N/F I? REGISTERS SUBADDRESS NAME DIFO Digital interface output switch FMSEL FM/NICAM auto select switch OOHEX FMPCM FM/PCM (NICAM) output select ERM Muting circuit control SEL1 Sound output main sound /sub sound switch 1 SEL2 Sound output main sound /sub sound switch 2 THL? Mute level threshold value switch 7 THL6 Mute level threshold value switch 6 THLS Mute level threshold value switch 5 O1HEX THL4 Mute level threshold value switch 4 THL3 Mute level threshold value switch 3 THL2 Mute level threshold value switch 2 THL1 Mute level threshold value switch 1 THLO Mute level threshold value switch 0 CYCLES Error detection duration setting 4 CYCLES Error detection duration setting 3 O2HEX CYCLE2 Error detection duration setting 2_ CYCLE1 Error detection duration setting 1 CYCLEO Error detection duration setting 0. lISBUS Data timing 1-bit shift O3HEX LRCLCREV | Inverts LRCLC polarity. PNDIN Supports PN scramble. FAW? FAW scramble broadcasting initial value setting 7 FAWE FAW scramble broadcasting initial value setting 6 FAWS FAW scramble broadcasting initial value setting 5 OB8HEX FAW4 FAW scramble broadcasting initial value setting 4 FAW3 FAW scramble broadcasting initial value setting 3 FAW2 FAW scramble broadcasting initial value setting 2 FAW1 FAW scramble broadcasting initial value setting 1 FAWO FAW scramble broadcasting initial value setting 0 OSPMUTE |Sound mute OSHEX SIFSEL | SIFIN1/SIFIND select PILOT? Pilot detection threshold vale setting 7 PILOT6 Pilot detection threshold vale setting 6 PILOTS Pilot detection threshold vale setting 5 OAHEX PILOT4 Pilot detection threshold vale setting 4 PILOT3 Pilot detection threshold vale setting 3 PILOT2 Pilot detection threshold vale setting 2 PILOT1 Pilot detection threshold vale setting 1 PILOTO Pilot detection threshold vale setting 0 15TOSHIBA TC9OA35N/E * REGISTERS SUBADDRESS NAME LVLO Pilot level setting data 0 LVL1 Pilot level setting data 1 LVL2 Pilot level setting data 2 LVL3 Pilot level setting data 3 OCHEX LVL4 Pilot level setting data 4 LVL5 Pilot level setting data 5 LVL6 Pilot level setting data 6 LVL? Pilot level setting data 7 LVL8 FM1 level setting data 8 LVLS FM1 level setting data 9 LVL10 FM1 level setting data 10 ODHEX LVL11 FM 1 tevel setting data 11 LVL12 FM1 level setting data 12 LVLi3 FM1 level setting data 13 LVL14 FM1 level setting data 14 LVL15 FM1 level setting data 15 LVL16 FM2 level setting data 16 LVL17 FM2 level setting data 17 LVL18 FMe2 level setting data 18 OEHEX LVL19 FM2 level setting data 19 LVL20 FM2 level setting data 20 LVL21 FM2 level setting data 21 LVL22 FM2 level setting data 22 LVL23 FM2 level setting data 23 LVL24 NICAM level data setting data 24 LVL25 NICAM level data setting data 25 LVL26 NICAM level data setting data 26 OFHEX LVL2? NICAM level data setting data 27 LVL28 NICAM level data setting data 28 LVL29 NICAM levei data setting data 29 LVL30 NICAM level data setting data 30 LVL31 NICAM level data setting data 31 OSC23 OSC2 oscillation frequency switch 3 OSC22 OSC2 oscillation frequency switch 2 OSC21 OSC2 oscillation frequency switch 1 40HEX 0$C13 OSC1 oscillation frequency switch 3 OSC12 OSC1 oscillation frequency switch 2 OSC11 OSC1 oscillation frequency switch 1 DEMMOD2 | Demodulator circuit operation select 2 DEMMOD1 | Demodulator circuit Operation select 1 16TOSHIBA IC REGISTERS TC9OA35N/F SUBADDRESS NAME FMST2 FM stereo matrix select 2 FMST1 FM stereo matrix select 1 FMEMP2 FM emphasis setting 2 FMEMP1 FM emphasis setting 1 ATHEX PILOT2 Pilot carrier frequency setting 2 PILOT1 Pilot carrier frequency setting 1 FMDEV2 FM deviation setting 2 FMDEV1 FM deviation setting 1 ROLOF1 Rolloff filter characteristic switch 1 AQHEX ROLOF2 Rolloff filter characteristic switch 2 NIEMP1 NICAM emphasis characteristic switch 1 NIEMP2 NICAM emphasis characteristic switch 2 SYSSEL4 Receive mode select 4 SYSSEL3 Receive mode select 3 44HEX SYSSEL2 Receive mode select 2 SYSSEL1 Receive mode select 1 17TOSHIBA TCOOA35N/F Description of IC bus registers After power on, the values of the I?C bus registers are undefined. Thus, perform reset after power on. The initial value after reset is NICAM-1 mode. Write register (B4HEX) Subaddress OOHEX MSB LSB 0 DIFO 0 FMSEL | PCMFM ERM SEL2 SEL1 DIFO : Digital interface output switch 0 : Digital output off t : Digital output on setting DIFO to 1 and setting SIGONO and SIGON1 at subaddress OBHEX output digital signal from DIFO (TC9OA35F : pin 34, TCODA35N : pin 34). FMSEL : C4 auto select switch 0 : Auto select 1: PCM/FM selected by FMPCM register Among control bits transmitted by NICAM, C4 is set to 1 when the contents of NICAM sound are the same as those transferred by FM sound. When C4 = 1, switches between automatic NICAM output (auto select) or selection (PCM /FM) by the FMPCM register. FMPCM : FM/PCM (NICAM) output select 0: FM 1: PCM (NICAM) (Note) FMPCM of the [? bus register and external pin PCMFM (TC90A35F : pin 46, TCSOA35N : pin 34) are OR-ed internally. Thus, when external pin PCMFM is not used, connect to digital GND. ERM : Muting circuit control 0 : Uses muting circuit. 1 : Does not use muting circuit. TCSOA35N and TCSQA35N incorporate a muting circuit, which uses error frequency detection. This bit selects whether the muting circuit is used or not. For how to set the muting circuit, see subaddresses O1HEX and 02HEX. SEL1, SEL2 : Sound select Determines the sound mode. Depending on the type of broadcast being received (FIM or NICAM) and the broadcast mode (stereo, monaural, two-channel monaural), the following sound is selected. External pins SEL1 (TC9OA35F : pin 47, TCODA3S5N : pin 48} and SEL2 (TC9OA35F : pin 48, TCSOA35N : pin 47) can also control the sound selection. 18TOSHIBA TC90A35N/F (Note) SEL1 and SEL2 of the I? bus and external pins SEL1 and SEL2 are internally OR-ed. Therefore, if the external pins are not used, connect these pins to digital GND. FM mode FM stereo mode 00: Stereo 01: Stereo 10: Stereo 11: Not selected (no sound output) MODE SOUND SELECTED SOUND OUTPUT L1 SEL2 0 0 Stereo i] 1 1 1 0 1 Two-channel monaural mode 00: Main sound 01: Sub sound 10: Main sound/sub sound 11: Not selected (no sound output) MODE SOUND SELECTED SOUND OUTPUT SEL1 SEL2 L R M 0 0 M1 M1 Monee al 3 a e 1 0 M2 M2 1 1 Mute Mute FM monaural mode 00: Monaural 01: Monaural 10: Monaural 11: Not selected (no sound output) MODE SOUND SELECTED SOUND OUTPUT SEL1 SEL2 L RK. 0 0 M M Monaural 0 1 M M 1 0 M M 1 1 Mute Mute NICAM stereo mode The control bits in the table below are bits sent together with sound da ta in NICAM broadcasting. The decoder determines the mode by detecting the control bit. 19TOSHIBA MODE SOUND SELECTED SOUND OUTPUT SEL1 SEL2 L R Stereo 0 0 i R Control Bit 0 1 L R cl | C2} C3 | C4 1 0 L R 0 0 Oo 10/1 1 1 Mute Mute MODE SOUND SELECTED SOUND OUTPUT Monaural SELt SEL2 L R Tweo-channel 0 0 M1 M1 Control Bit 0 1 M2 M2 c1 | c2 | c3 | c4 1 0 M1 M2 0 1 0 /O/1 1 1 Mute Mute MODE SOUND SELECTED SOUND OUTPUT SEL1 SEL2 L R Monaural + Data 0 0 Mute Mute Control Bit 0 1 Mute Mute C1 {; c2 | c3 | c4 1 0 Mute Mute 1 0 0 10/1 1 1 M M Data Control Bit c1 | c2 | c3 | ca 1 1 0 /O/1 SOUND SELECTED SEL1 SEL2 0 0 0 1 1 SOUND OUTPUT L R FM FM FM FM FM FM FM MODE SOUND SELECTED SOUND OUTPUT SEL1 SEL2 L R Others 6 0 FM FM Control Bit 0 1 FM FM 1 | C2 | c3 | C4 1 0 FM FM x x QO |0/1 1 1 FM FM Subaddress 01HEX MSB LSB THL? THL6 THLS THL4 THL3 THL2 THL1 THLO TC90A35N/F 20TOSHIBA TC9OA35N/F THL? to THLO : Mute levei threshold value Set values ; 00 to FF {1 to 256 samples) This register is used to set tevel where mute is applied. Combining the set mute threshold value and the set mute duration at subaddress O2HEX can set mute- on status to any error detection duration and error frequency. The muting circuit has ON/OFF hysteresis as shown below. When a parity error occurs to (set value x 2) samples, mute turns on, When errors return to (set value x 1), mute turns off. * 1 frame = 64 samples = 1/728s Mute on Mute off N 2N (error occurrence level) Subaddress O2HEX MSB LSB 0 0 0 CYCLE4 | CYCLE3 | CYCLE2 | CYCLE1 | CYCLEO CYCLE4 to CYCLEO : Set error detection duration. Set values : 00 to 1F (0 to 31 super frames*) 1 super frame = 10 frames = 16 x (1/728)s This register is used to set the error detection duration for mute. If a parity error at the level set at subaddress O1HEX is detected during the set duration, mute turns on. Subaddress O3HEX MSB LSB IISBUS | LRCLKREV| PNDIN 0 0 0 0 0 ISBUS ; Data timing 1-bit shift LRCLKREV : Inverts polarity of LRCLK. PNDIN : Supports PN scrambie. Set the functions of external pins TIOO (TCOOAS5F : pin 70, TC9DA35N : pin 58) and TIO1 (TC9OA35F : pin 71, TC9O0A35N : pin 59) as follows: TIOO = CWCLOCK TIO1 = CWDATA 21TOSHIBA TC90A35N/F Subaddress OSHEX MSB LSB FAW? FAW6 FAWS5 FAW4 FAW3 FAW2 FAW1 FAWO FAW? to FAWO : Set the FAW scramble broadcasting initial value. When receiving FAW scramble broadcasting, set the initial value in this register. (Note) After the IC is reset 01001110" which is the NICAM broadcasting specification, is set as the initial value. Note that if the register is accessed, the value is altered and remains altered unless "01001110" is set again (decoding becomes impossible). Do not access the register unless necessary. Subaddress OOHEX MSB LSB DSPCMUTE 0 0 0) 0 0 SIFSEL 0 DSPCMUTE : Sound mute Q : Normal 1: Mute Applies mute to sound output. Valid for both NICAM and FM sounds. For mute when an NICAM or FM error occurs, see subaddresses 01 and O2HEX. SIFSEL : Selects SIFIN1 or SIFIN2. QO: SIFIN1 1: SIFIN2 Selects input to SIFIN] (TC90A35F : pin 80, TCIJAI5N : pin 8) or SIFIN2 (TCO0A35F : pin 6, TC9OA35N : pin 10). Subaddress OA HEX MSB LSB PILOTH7 | PILOTH6 | PILOTHS | PILOTH4 | PILOTH3 | PILOTH2 | PILOTH1 | PILOTHO PILOTH7 to PILOTHO : Set pilot detection threshold value. Subaddress OB HEX M5B LSB SIGONO | SIGON1 SIGONO : External DAC signal output 0 0 : Does not use digital interface. 1: Uses digital interface. SIGON1 : External DAC signal output 1 0 : Does not use digital interface. 1: Uses digital interface. When using a digital interface, set both SIGONO and SIGON1 to 1 and DIRO at subaddress QOHEX to 1. 22TOSHIBA Subaddress 0C HEX MSB LSB LVLO LVL1 LVL2 LVL3 LVL4 LVL5 LVL6 LVL7 LVLO to LVL? : Set pilot level data 1 Subaddress OD HEX MSB LSB LVL8 LVL9 LVL10 LVL11 LVL12 LVL13 LVL14 LVL15 LVL8 to LVL15 : Set FM1 level data. Set an FM1 detection threshold value. Subaddress OE HEX MS5B LSB LVL16 LVL17 LVL18 LVL19 LVL20 LVL21 LVL22 LVL23 LVL16 to LVL23 : Set FM2 level data. Set an FM2 detection threshold value. Subaddress OF HEX MSB LSB LVL24 LVL25 LVL26 LVL27 LVL28 LVL29 LVL30 LVL31 LVL24 to LVL31 : Set NICAM fevel data. Set a NICAM detection threshold value. Subaddress 40 HEX MSB LSB OSC23 OS$C22 OSc21 O$C13 OSC12 OSC11_ | DEMMOD2 | DEMMOD1 OSC23 to OSC21 : Set the oscillation frequency of internal oscillator 2. 000 6.552 MHz 100 5.85 MHz 010 5.74MHz 110 6.74 MHz 001 4.74MHz OSC13 to OSC11 : Set the oscillation frequency of internal oscillator 1. 000 6.0 MHz 100 5.5 MHz 010 6.5 MHz 110 4.5 MHz TC90A35N/F 23TOSHIBA TC90A35N/F DEMMOD : Selects the demodulator circuit operation. 00 : NICAM + FM 10 : FM + FM (two-carrier FM) 01, 11: FM (monaural) (Note) When NICAM + FM mode is selected by setting DEMMOD to 00, FM and NICAM are decoded internally but cannot be output simultaneously. Subaddress 41HEX FM decoder setting switch MSB LSB FMST2 FMST1 | FMEMP1 | FMEMP1| PILOT2 PILOT1 | FMDEV2 | FMDEV1 FMST2, FMST1 : Set FM stereo matrix. 00: L/R 10 : L+R/2R Ol: L+R/L=-R FMEMP2, FMEMP1 : Set FM emphasis. 00 : 50 zs 10: 75 us 01 : Bypasses the emphasis circuit. PILOT2, PILOT1 : Set pilot carrier in two-carrier FM mode. 00 : IGR FMDEV1, FMDEV2 : Set FM deviation. FMDEV2, FMDEV1 00 : 50kHz 10 : 30kHz OT : 25 kHz Subaddress 42HEX NICAM decoder setting switch MSB LSB ROLOF1 | ROLOF2 | NIEMP1 | NIEMP2 0 0 0 0 The TCS9O0A35F and TCIOA35N incorporate a NICAM rolioff filter and deemphasis circuit. ROLOF1, 2 : Switch rolloff filter characteristics. 00 ; 100% (I) 10 : 40% (B/G) NIEMP1, 2 : 00 : J. 17(+6dB) O1 : J. 17 10 : Bypasses the deemphasis circuit 24TOSHIBA Subaddress 44HEX MSB L358 SYSSEL4 SYSSEL3 SYSSEL2 SYSSEL1 0 SCANPRD2 SCANPRD1 SYSEL4 to SYSEL1 : Select receive mode oo00 : NICAM | 0001 : NICAM B/G 0010 : IGR (two-carrier FM) 0100 : NICAM D/K 0101 : FM B/G 0110 : FMI | 0111 : FM D/K 1000 : External setting mode Preset mode Manual setting mode TC90A35N/F To support different broadcasting modes, the TC90A35F/N contains in internal ROM parameters such as oscillation frequencies, pilot carrier frequencies, FM emphasis characteristics, FM deviations, and NICAM emphasis characteristics. Setting SYSSEL determines the combination of parameters used to read data. Combinations of parameters are as shown in the table below. The initial value after reset is SYSSEL = 0000. Osc! Osc2 FM PILOT FM = | rottorr| SYSSEL | CONTENTS {| MODE |OSCILLATION| OSCILLATION | DEVE MATRIX SIGNAL EMPHASIS RATIO FREQUENCY | FREQUENCY | ATIONS MODE 0000 |NICAM-| |FM+NICAM] 6.0MHz 6.552 MHz | 50 kHz 50 ps 100% | 0001 | NICAM-B/G |FM+NICAM] 5.5MHz 5.85 MHz | 50 kHz _ 50 ys 40% _ 0010 |1GR FM + FM 5.5 MHz 9.7421875 MHz | 30 kHz | 54.6875 kHz 50 us _ L+R/2R 0100 |NICAM-D/K|FMsNICAM| 6.5MHz 5.85 MHz | 50kHz 50 ys _ 0101 |FM-B/G {FM 5.5 MHz _ 50 kHz _ 50 us ~ _ 0110 FRA-I| FM 6.0 MHz _ 50 kHz ~ 50 us _ _ 0111 |FM-D/K lFM 6.5 MHz _ 50 kHz = 50 us Setting of actual receive modes 1. Preset mode (mode which can be set by SYSSEL) Parameters can be determined at subaddresses 40HEX to 42HEX. However, normally, all the parameters can be set using SYSSEL at subaddress 44HEX only. After the IC is reset, set the desired receive mode in SYSSEL. 2. Manual setting mode (mode which cannot be set by SYSSEL) To change some SYSSEL parameters, overwrite using the iC bus after the mode is set in SYSSEL. (1) Set SYSSEL at 44HEX. (2) Set the parameters to be changed at 40HEX to 42HEX. (3) Set 1000 in SYSSEL and transmit the coefficients. (Note) When the parameters at 40HEX to 42HEX are changed, TYSSEL = 10000 must be set. Otherwise, coefficients will not be transmitted to their destinations. 25TOSHIBA TC9OA35F, TCIOA35N address B5HEX (read register) TC9OA35N/F READ SIGNAL ORDER NAME FUNCTION DESCRIPTION 1 C1 2 C2 Control bits Indicate the control bits to be transmitted in 3 C3 NICAM broadcast mode. 4 c4 5 SERR Sync error Set to 1 when a sync error occurs. 6 PMUTEO_ | NICAM mute signal Set to 1 when mute is applied to NICAM. 7 cIB1 information bit 8 CIB2 Information bit Indicates the detection result for the mode . specified by subaddress 44HEX (SYSSEL). For 9 LDET _| Level detection result example, when SYSSEL = 0000 (NICAM-1) is set, detecting FM and NICAM results in LDET = 1. 10 FMMUTEO |FM mute signal Set to 1 when mute is applied to FM. . . Indicate IGR mode detection result. " PLT2 Pilot signal 2 PLT2 : PLT! = 0:0 = MONO . . PLT2 : PLT1 = 1:0 = 2ch MONO 12 PLT Pilot signal 1 PLT2 : PLT1 = 0: 1 = STEREO 13 SYSSEL3 Indicate FM + NICAM or FM receive mode. 14 SYSSEL2 SYSSEL3 : SYSSELZ ; SYSSEL1 : SYSSELO = Receive mode 0000 = NICAM |, 0001 = NICAM B/G, 0010 = IGR, 15 SYSSEL1 0100 = NICAM D/K, 0101 = FM B/G, 0110 = EM |, 16 SYSSELO 0111 = FM O/K 7 LVLDTO 18 LVLDT1 19 LVLOT2 | = FM 17 level detection data | Indicate FM1 detection result. 22 LVLDT5 23 LVLDT6 24 LVLDT?7 25 -LVLOTB 26 LVLDT9 27 LVLDT10 . ot FM 2 level detection data | Indicate FM2 detection result. 30 LVLDT13 31 LVLDT14 32 LVLDT15 33 LVLDT16 34 LVLDT17 35 LVLDT18 = woe wae level detection Indicate NICAM detection result. 38 LVLDT21 39 LVLDT22 40 LVLDT23 26TOSHIBA TC90A35N/F Description of |?C bus functions The TCSOA35F/N uses IC bus specifications (Philips bus specifications} as the interface for controlling operation. The |?C bus specifications are designed to transfer data between ICs using a common serial bus. Both TC90A35F and TCSOA35N are designed so that they can operate on an I2C bus. 1. Outline The I?C bus consists of two lines, SCL and SDA. Data are transferred on the SDA line in units of 8 bits in sync with the clock of the SCL line. Transfer start and end are controlled by changing SDA when the SCL line is High level. Acknowledge is defined in units of bytes, thus a 1-bit acknowledge is sent after 8-bit data are transferred, The fC bus assumes multimasters but the TCSOA35F/.N supports only a slave function. Therefore, data are transferred at a point between the master and the slave (in this case, TCSOOA3SF/N). Transfer start, end, slave selection, and operating mode are all controlled by the then master. Therefore, the SCL line is always controlled by the master and the slave (TC90A35F /N) is set to input. The SDA line is bidirectional. Input/ output is switched by a register of the slave (TC90A35F/ N). The SCL is driven by the master. The SDA line is driven by an open drain from the master or TC90A35F/N and pulled up by a pull-up resistor. The master must control transfer (eg, switch input/output of SDA line) by the operating mode (read /write) of the slave address (TC90A35F /N). 2. Address The I?C bus allocates two 8-bit addresses to a slave. As the list of IC bus registers shows, B4HEX is assigned as the write address, BSHEX as the read address. An 8-bit subaddress is also set. To control TCOOA35F/N, data are sent/received by specifying an address and a subaddress. 3. Data Block The I? bus can transfer any number of bytes in units of 8 bits. With the TC9OA35F/N, as the list of ?C bus registers shows, 8 bits are transferred for BAHEX or BSHEX. All the TCIOA35F/N registers are static, so the previous values are retained until the next update. The slave registers are undefined after power on. Always input Low level to the RESET pin (TCSOA3SN : pin 30, TCIDA35F : pin 30) and initialize to OOHEX. 4. Transfer Sequence 4.1 Transfer Start and End Data are transferred in syne with the SCL line. in standby mode, both SDL and SDA lines are left at high impedance. Because both lines are pulled up, they are High level. Data transfer starts when the SDA line changes from High to Low while the SCL line is at High level and ends when the SDA line changes from Low to High while the SCL line is at High level. There are no such sequences during data transfer duration (see sequences 1 and 2). 27TOSHIBA TC9OA35N/F 4.2 SCL Line and SDA Line Timing The SDA line data must be valid between the SCL line rising and falling. To make sure data are valid, the transmitting side should output data to the SDA line after checking that the SCL line changes from High to Low level. Due to this restriction, there are no start and end sequences during data transfer. 4.3 Acknowledge When 8-bit data are correctly received in the write register, the TC90A35F/N sets the SDA line to Low level. When the master detects this, it knows that data are received correctly. If acknowledge remains at High level, data are not received correctly. Then, the master must retransmit the data. 4.4 Data Transfer Order The polarity of the SDA line is positive. Data are transferred from the MSB to the LSB of the address, then the MSB to the LSB of the data. 45 Data Transmit/Receive Switch Timing To receive acknowledge after transfer of 8 bits, the master sets the SDA line to high impedance after the SCL line falls after outputting an 8-bit address. The TCSO0A35F/N outputs acknowledge to the SDA line in sync with the fall of the SCL line. The SDA line returns to high impedance after the SCL line falls after outputting acknowledge. 2C bus control example After power on, the master sets the SCL and SDA lines to high impedance. Then, the TC90A35F/N inputs Low level to RESET to initialize the IC, Low level can be input to RESET using an external RC or by a pulse from the microcomputer. At this time, the TC90A35F/N can be controlled externally and the write register at address B4HEX is initialized to OOHEX., Here, for slave registers whose initial settings you want to change, send the initial data. For example, to select NICAM-B/G at automatic system setting, send data 01HEX to subaddress 44HEX. Using this as an example, transfer is described in more detail. First, output High level to the SCL and SDA lines. Then, to start transfer, set the SDA line to Low level, then the SCL line to Low level. Next, send the address. Transfer starts from the MSB. As a data string for address B4HEX, send 10410100 {transfer starting from the MSB). For the first bit transfer, set the SDA line to High level, the SCL line to High level, then return to Low level. Then, in sync with the SCL line, change the SDA line to Low level, High level, High level, Low level, High level, Low level, then Low level, transfer the 8-bit address, change the SCL line to High level and confirm that acknowledge is Low level. After confirmation, change the SCL line to Low level then proceed from transfer of the address to transfer of the subaddress. 28TOSHIBA TC90A35N/F To transfer the subaddress, start from the MSB. As a data string for subaddress B4HEX, send 01000100 (transfer starting from the MSB). For the first bit transfer, set the SDA line to Low level, the SCL line to High level, then return to Low level. Then, in sync with the SCL line, change the SDA line to High level, Low level, Low level, Low level, High level, Low level, then Low level, transfer the 8-bit subaddress, change the SCL line to High level and confirm that acknowledge is Low level. After confirmation, change the SCL line to Low level then proceed from transfer of the subaddress to transfer of data. The data string at 01HEX is 00000001. In sync with the SCL line, change the SDA line to Low level, Low levei, Low level, Low level, Low level, Low level, Low level, then High level, transfer the 8-bit data. When transfer of the 8-bit data is complete, change the SCL line to High level and confirm that acknowledge is Low level. After confirmation, change the SCL line to Low level. Finally, to end the transfer, as the end sequence, change the SDA line to Low level, the SCL line to High level, then the SDA line to High levei. After that, set both SDA and SCL lines to high impedance. This ends the transfer. When transferring to another register, apply the same procedure with a different subaddress and data string. 29TOSHIBA TCSOA35N/F ?C bus transfer sequences 1. Transfer start sequence UU Address Data 1 8 ACK 1 SDA (bidirectional) 2. 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ISSaq, 0, Is} 2 PcelTea cao Serpe? Lou ' o oy OAZ Lt == j ite az viva 00u. Jo18! dou 208 3D; or vive Isla L we ais | oon ous OM xr 1b]o lat x 02 [O{9} a on Yvivau li ol Pela 5 I wad viva 6 wu fol, 2 2 2 Zz = 9 sss, bolla ba S 2 aoa z x = ee ew uw 2 S A Roe of So FF Fezendk pa kh Fee ce =o ew 47 5 8 ese 7 6 OK SF a om Oe zm mD eG) OD GD BY GD @) v ey @ ey . ey * ZAL| Edt] od] San Sal} Za] 213-4 a oO q Gg oo FFE 1 uw oo nal 2gf484 S555 reba & ba a1 11 "SSE ce ze Soo Spock tooo [oro] [a-o-o] @ eer loco $m $s $2 Se cZ= x 3s 938 O75 F575 | AGS 575 Fae am) et | oo -mm a [ "3 mb a = a = oo =~ = > N we a wn Lal a (4SEVO6DL) LINDHID 1531 4O FIdWXaEXAMPLE OF TEST CIRCUIT (TC90A35N) Vss1 = Vop1 100 5V C23CE1 Vop3 wokdver Xl xO TIO1 27 C1 1 2 100 xl TICO MCLK VpDXx APCFO RCLK APCFI ROATA BF 39k VSSAGC C3IDATA #1 SIFING Vs53 C3IDATA ODATA OGATE AGCREF DDATA 48 SIFIN2 DGATE 1kQ Vppacc SERR RV7 1 AGCO PERR R16 1 Vopap Vss2 04 03 FMUTEO FMUTEO PMUTEO MUTE] VREFH 03 VREFL PMUTEO I7 13 O3 BIAS MUTEL Vesap PC QOARSN a c14 CE? C17 of 5 Vepr MON2 rear'4 R13 kD R12 = o a Rch ROUT GND Vsr ST VREF SEL2 GND Vssi SEL1 Leh Lour POM /FM C22CEt w i+ VDDL Vopz Vpp1 cK 16 cK1 FRM TESTI TESTI TEST2 cko LRCK BCK DATA DIFO TEST2 TEST3 TESTS TEST4 TEST4 RESET RESET DATA SDA DIFO so sc SCL Vgs1 Vss2 Vpp2 TCOOA35N/F - 32EE d/NSEVOBIL Ww1 OND ORS Ye aS #f | s35 eel, # pp stom os os yt oo 2550 Dd Le b eat ela? Ss = = wt, {02> #1 Hol "Ss rs E01 f io = > . 4 LSSA S| rol ass [fie |S R alalala A Ia bd 4 H? OL 7 | F7o elalei? of a FORT we zadn Dx] ad 2 ft. a* Pi od te,! "s aD Fa rz Pa sjsajzle * sEhle wl f+ # a7 Bia] = td} a wiles /3]s|e2 el |e f 2 239 Lae, E gi 9 813 Pt J HTOL AS cory won [213 f id 6 4) 4D CD HG OMAN MOMMOOMODOMOAMG a z z z Zs < <= = zm < =< @ << = = tw r 2 z z or se aagereegesgeprag ke 2 RR RRR rc i I= 7 FB 2 z Ss 2 nw Gi L eat E lad, NISIS 7 G4 usa FOVSSA ww of a te 9 sy 8 evo rs Idd a zusal met * sot f= ELSaL Osd tor = p1S3l xad, nt 3 Lasav x and w a oo! = |01 ox on Pat vas = Wy SL 9S ly aan DIO TDs xSS4, o A4SEVO6DL ISSA fad, 7 ton aa Ez a AZ DN #De wivay yivaes B ESSA 2 o2 = og o c z= 2 << 2 ww & OG a a aw m m > a mm m mw z zl 4 =a _ o on = om Pp &> &) G9 9 ED G9 ED &) zz bol -_s -ot up a Fe (USEV06DL) IIMWYXI LINDHID UonenjddyAPPLICATION CIRCUIT EXAMPLE (TC9S0A35N) Vssi = Vt 100 av 104 Vop3 100k * xO TIO1 27 1 100 xl TIO Vppx MCLK APCFO RCLK APCFI RDATA, 103] 0.07 uF 39k Vssacc C3DATA SIFING Vg3 AGCREF DDATA SIFIN2 DGATE 103 30 Vooacc SERR * Varactor : Hitachi HVU17 AGCO PERR Vooap Vss2 VREFH FMUTEO VREFL PMUTEO BIAS MUTE! TCIOA35N Vssap ca Vpor Reh ROUT GND Vssr VREF GND Vssi ich LOUT VooL Yoo TEST! TEST2 TESTS LRCK TESTa BCK RESET DATA SDA SCL Micro- computer Vss2 Vpp2 TCOOAISN/F 34TOSHIBA TC9SOA35N/F OUTLINE DRAWING SDIPG4-P-750-1.78 Unit : mm 3 84 33 * GOO meee ooops o 17.840.2 [18.05] 33 #9 So Sea oh Soe So ee q 1 32 S 58.0MAX $7.5+0.2 _ 7 : ar Sy I x wo i 1 | z in - o 1.040.1 0.4610.1 D1aG F 1.481 Tre [1.778 Weight : 8.859 (Typ.) 35TOSHIBA TC9OA35N/F OUTLINE DRAWING QFP80-P-1420-0.80A Unit : mm iy] r| 3 No 0.2+0,1 A 0.15 +05 Weight : 1.6g (Typ.) 36/E