6.5 V, 1 A, Ultralow Noise, High PSRR,
Fast Transient Response CMOS LDO
Data Sheet
ADM7171
Rev. C Document Feedback
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FEATURES
Input voltage range: 2.3 V to 6.5 V
Maximum load current: 1 A
Low noise: 5 µV rms independent of output voltage at
100 Hz to 100 kHz
Fast transient response: 1.5 μs for 1 mA to 500 mA load step
60 dB PSRR at 100 kHz
Low dropout voltage: 42 mV at 500 mA load, VOUT = 3 V
Initial accuracy: −0.5% (minimum), +1% (maximum)
Accuracy over line, load, and temperature: ±1.5%
Quiescent current, IGND = 0.7 mA with no load
Low shutdown current: 0.25 μA at VIN = 5 V
Stable with small 4.7 µF ceramic output capacitor
Adjustable and fixed output voltage options: 1.2 V to 5.0 V
Adjustable output from 1.2 V to VIN − VDO
Precision enable
Adjustable soft start
8-lead, 3 mm × 3 mm LFCSP package
Supported by ADIsimPower tool
APPLICATIONS
Regulation to noise sensitive applications: ADC and DAC
circuits, precision amplifiers, PLLs/VCOs, and clocking ICs
Communications and infrastructure
Medical and healthcare
Industrial and instrumentation
GENERAL DESCRIPTION
The ADM7171 is a CMOS, low dropout linear regulator (LDO)
that operates from 2.3 V to 6.5 V and provides up to 1 A of output
current. This high output current LDO is ideal for regulation of
high performance analog and mixed signal circuits operating
from 6 V down to 1.2 V rails. Using an advanced proprietary
architecture, the device provides high power supply rejection and
low noise, and achieves excellent line and load transient response
with just a small 4.7 µF ceramic output capacitor. Load transient
response is typically 1.5 μs for a 1 mA to 500 mA load step.
The ADM7171 is available in 17 fixed output voltage options.
The following voltages are available from stock: 1.3 V, 1.8 V,
2.5 V, 3.0 V, 3.3 V, 4.2 V, and 5.0 V. Additional voltages that are
available by special order are: 1.5 V, 1.85 V, 2.0 V, 2.2 V, 2.7 V,
2.75 V, 2.8 V, 2.85 V, 3.8 V, and 4.6 V. An adjustable version is
also available that allows output voltages that range from 1.2 V
to VIN − VDO with an external feedback divider.
Inrush current can be controlled by adjusting the start-up time
via the soft start pin. The typical start-up time with a 1 nF soft
start capacitor is 1.0 ms.
TYPICAL APPLICATION CIRCUIT
Figure 1. ADM7171 with Fixed Output Voltage, 3.3 V
The ADM7171 regulator output noise is 5 μV rms independent
of the output voltage. The ADM7171 is available in an 8-lead,
3 mm × 3 mm LFCSP, making it not only a very compact solution,
but also providing excellent thermal performance for applications
requiring up to 1 A of output current in a small, low profile
footprint.
Figure 2. Transient Response (Trace 2), 1 mA to 500 mA Load Step in 400 ns (Trace 1)
Table 1. Related Devices
Device Input Voltage Output Current Package
ADM7170 2.3 V to 6.5 V 500 mA 8-lead LFCSP
ADM7172 2.3 V to 6.5 V 2 A 8-lead LFCSP
VOUT
SENSE
SS
VIN
EN
ADM7171
GND
VIN VOUT
C
SS
1nF
C
IN
4.7µF C
OUT
4.7µF
OFF
ON
V
IN
= 5V V
OUT
= 3.3V
12298-001
12298-002
CH1 200mA Ω
BW
CH2 10mV
BW
M400ns A CH3 100mV
T 0.40%
1
2
T
ADM7171 Data Sheet
Rev. C | Page 2 of 23
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Typical Application Circuit ............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Input and Output Capacitor, Recommended Specifications .. 4
Absolute Maximum Ratings ............................................................ 5
Thermal Data ................................................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution .................................................................................. 5
Pin Configuration and Function Descriptions ............................. 6
Typical Performance Characteristics ............................................. 7
Theory of Operation ...................................................................... 16
Applications Information .............................................................. 17
ADIsimPower Design Tool ....................................................... 17
Capacitor Selection .................................................................... 17
Programmable Precision Enable ................................................. 18
Undervoltage Lockout ............................................................... 18
Soft Start ....................................................................................... 18
Noise Reduction of the ADM7171 in Adjustable Mode ........... 19
Current-Limit and Thermal Overload Protection ................. 19
Thermal Considerations ............................................................ 20
Typical Applications Circuits .................................................... 21
Printed Circuit Board Layout Considerations ............................ 22
Outline Dimensions ....................................................................... 23
Ordering Guide .......................................................................... 23
REVISION HISTORY
8/15—Rev. B to Rev. C
Changes to Soft Start Section ........................................................ 19
Added Effect of Noise Reduction on Start-Up Time Section ... 19
12/14—Rev. A to Rev. B
Changes to Figure 2 .......................................................................... 1
Changes to Figure 48 to Figure 51 ................................................ 14
Changes to Figure 52 to Figure 53 ................................................ 15
Changes to Figure 56 ...................................................................... 17
8/14—Rev. 0 to Rev. A
Changes to Ordering Guide .......................................................... 23
7/14—Revision 0: Initial Version
Data Sheet ADM7171
Rev. C | Page 3 of 23
SPECIFICATIONS
VIN = (VOUT + 0.5 V) or 2.3 V (whichever is greater), EN = VIN, ILOAD = 10 mA, CIN = COUT = 4.7 µ F, TA = 25°C for typical specifications,
TJ = −40°C to +125°C for minimum/maximum specifications, unless otherwise noted.
Table 2.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
INPUT VOLTAGE RANGE VIN 2.3 6.5 V
LOAD CURRENT ILOAD 1 A
OPERATING SUPPLY CURRENT IGND ILOAD = 0 µA 0.7 2.0 mA
ILOAD = 1 A 4.0 6.3 mA
SHUTDOWN CURRENT IGND-SD EN = GND, VIN = 5 V 0.25 3.8 µA
OUTPUT VOLTAGE ACCURACY
Fixed Output Voltage Accuracy VOUT ILOAD = 10 mA, TJ = 25°C −0.5 +1 %
100 μA< ILOAD < 1A VIN = (VOUT + 0.5V) to 6.5 V −1.5 +1.5 %
Adjustable Output Voltage
Accuracy
VSENSE ILOAD = 10 mA 1.194 1.200 1.212 V
10 mA < ILOAD < 2 A, VIN = (VOUT + 0.5 V) to 6.5 V 1.182 1.218 V
REGULATION
Line ∆VOUT/∆VIN VIN = (VOUT + 0.5 V) to 6.5 V −0.1 +0.1 %/V
Load ∆VOUT/∆ILOAD ILOAD = 100 μA to 1 A 0.1 0.4 %/A
SENSE INPUT BIAS CURRENT SENSEI-BIAS 100 μA< ILOAD < 1 A, VIN = (VOUT + 0.5 V) to 6.5 V 1 nA
DROPOUT VOLTAGE1 VDROPOUT ILOAD = 500 mA, VOUT = 3 V 42 70 mV
ILOAD = 1 A, VOUT = 3 V 84 135 mV
OUTPUT NOISE OUTNOISE 10 Hz to 100 kHz, all fixed output voltages 6 µV rms
100 Hz to 100 kHz, all fixed output voltages 5 µV rms
Noise Spectral Density 100 Hz, all fixed output voltages 110 nV/√Hz
1 kHz, all fixed output voltages 40 nV/√Hz
10 kHz, all fixed output voltages
20
nV/√Hz
100 kHz, all fixed output voltages
12
nV/√Hz
POWER SUPPLY REJECTION RATIO PSRR 100 kHz, VIN = 4.0 V, VOUT = 3 V, ILOAD = 1 A, CSS = 0 nF 60 dB
100 kHz, VIN = 3.5 V, VOUT = 3 V, ILOAD = 1 A, CSS = 0 nF 53 dB
100 kHz, VIN = 3.3 V, VOUT = 3 V, ILOAD = 1 A, CSS = 0 nF 42 dB
1 MHz, VIN = 4.0 V, VOUT = 3 V, ILOAD = 1 A, CSS = 0 nF 31 dB
1 MHz, VIN = 3.5 V, VOUT = 3 V, ILOAD = 1 A, CSS = 0 nF 30 dB
1 MHz, VIN = 3.3 V, VOUT = 3 V, ILOAD = 1 A, CSS = 0 nF 20 dB
TRANSIENT LOAD RESPONSE tTR-REC Time for output voltage to settle within ±VSETTLE
from VDEV for a 1 mA to 500 mA load step, load step
rise time = 400 ns
1.5 μs
VDEV Output voltage deviation due to 1 mA to 500 mA load
step
35 mV
VSETTLE Output voltage deviation after transient load response
time (tTR-REC) has passed, VOUT = 5 V, COUT = 4.7 µF
0.1 %
START-UP TIME
2
t
START-UP
V
OUT
= 5 V, C
SS
= 0 nF
380
µs
VOUT = 5 V, CSS = 1 nF 1.0 ms
SOFT START CURRENT
I
SS
V
IN
= 5 V
0.5
1
1.5
µA
CURRENT-LIMIT THRESHOLD3 ILIMIT 1.3 2.1 2.7 A
VOUT PULL-DOWN RESISTANCE VOUT-PULL EN = 0 V, VOUT = 1 V 11 kΩ
THERMAL SHUTDOWN
Thermal Shutdown Threshold
TS
SD
T
J
rising
150
°C
Thermal Shutdown Hysteresis TSSD-HYS 15 °C
UNDERVOLTAGE THRESHOLDS
Input Voltage Rising UVLORISE 2.28 V
Input Voltage Falling UVLOFAL L 1.94 V
Hysteresis UVLOHYS 200 mV
ADM7171 Data Sheet
Rev. C | Page 4 of 23
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
EN INPUT STANDBY 2.3 V ≤ VIN ≤ 6.5 V
EN Input Logic High ENSTBY-HIGH 1.1 V
EN Input Logic Low ENSTBY-LOW 0.4 V
EN Input Logic Hysteresis ENSTBY-HYS 80 mV
EN INPUT PRECISION 2.3 V ≤ VIN ≤ 6.5 V
EN Input Logic High ENHIGH 1.11 1.2 1.27 V
EN Input Logic Low ENLOW 1.01 1.1 1.16 V
EN Input Logic Hysteresis ENHYS 100 mV
EN Input Leakage Current IEN-LKG EN = VIN or GND 0.1 1.0 µA
EN Input Delay Time TIEN-DLY From EN rising from 0 V to VIN to 0.1 V × VOUT 130 μs
1 Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. Dropout applies only for output
voltages greater than 2.3 V.
2 Start-up time is defined as the time between the rising edge of EN to VOUT being at 90% of its nominal value.
3 Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 5.0 V
output voltage is defined as the current that causes the output voltage to drop to 90% of 5.0 V, or 4.5 V.
INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS
Table 3.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
MINIMUM INPUT AND OUTPUT CAPACITANCE1 CMIN TA = −40°C to +125°C 3.3 µF
CAPACITOR ESR RESR TA = −40°C to +125°C 0.001 0.05 Ω
1 Ensure that the minimum input and output capacitance is greater than 3.3 μF over the full range of operating conditions. The full range of operating conditions in the
application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended;
Y5V and Z5U capacitors are not recommended for use with any LDO.
Data Sheet ADM7171
Rev. C | Page 5 of 23
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter Rating
VIN to GND −0.3 V to +7 V
VOUT to GND −0.3 V to VIN
EN to GND −0.3 V to +7 V
SS to GND −0.3 V to VIN
SENSE to GND −0.3 V to +7 V
Storage Temperature Range −65°C to +150°C
Operating Junction Temperature Range −40°C to +125°C
Soldering Conditions JEDEC J-STD-020
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL DATA
Absolute maximum ratings apply individually only, not in
combination. The ADM7171 can be damaged when the
junction temperature limits are exceeded. Monitoring ambient
temperature does not guarantee that TJ is within the specified
temperature limits. In applications with high power dissipation
and poor thermal resistance, the maximum ambient
temperature may need to be derated.
In applications with moderate power dissipation and low
printed circuit board (PCB) thermal resistance, the maximum
ambient temperature can exceed the maximum limit provided
that the junction temperature is within specification limits. The
junction temperature (TJ) of the device is dependent on the
ambient temperature (TA), the power dissipation of the device
(PD), and the junction-to-ambient thermal resistance of the
package (θJA).
Maximum junction temperature (TJ) is calculated from the
ambient temperature (TA) and power dissipation (PD) using the
formula
TJ = TA + (PD × θJA)
Junction-to-ambient thermal resistance (θJA) of the package is
based on modeling and calculation using a 4-layer board. The
junction-to-ambient thermal resistance is highly dependent on
the application and board layout. In applications where high
maximum power dissipation exists, close attention to thermal
board design is required. The value of θJA may vary, depending on
PCB material, layout, and environmental conditions. The
specified values of θJA are based on a 4-layer, 4 in. × 3 in. circuit
board. See JESD51-7 and JESD51-9 for detailed information on
the board construction. For additional information, see the
AN-617 Application Note, Wafer Level Chip Scale Package,
available at www.analog.com.
ΨJB is the junction-to-board thermal characterization parameter
with units of °C/W. ΨJB of the package is based on modeling and
calculation using a 4-layer board. The JESD51-12, Guidelines for
Reporting and Using Electronic Package Thermal Information,
states that thermal characterization parameters are not the same
as thermal resistances. ΨJB measures the component power
flowing through multiple thermal paths rather than a single
path as in thermal resistance, θJB. Therefore, ΨJB thermal paths
include convection from the top of the package as well as
radiation from the package, factors that make ΨJB more useful
in real-world applications. Maximum junction temperature (TJ)
is calculated from the board temperature (TB) and power
dissipation (PD) using the formula
TJ = TB + (PD × ΨJB)
See JESD51-8 and JESD51-12 for more detailed information
about ΨJB.
THERMAL RESISTANCE
θJA, θJC, and ΨJB are specified for the worst-case conditions, that
is, a device soldered in a circuit board for surface-mount
packages.
Table 5. Thermal Resistance
Package Type θJA θ
JC Ψ
JB Unit
8-Lead LFCSP 36.4 23.5 13.3 °C/W
ESD CAUTION
ADM7171 Data Sheet
Rev. C | Page 6 of 23
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 3. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Description
1 VOUT Regulated Output Voltage. Bypass this pin to GND with a 4.7 µF or greater capacitor.
2 VOUT Regulated Output Voltage. This pin is internally connected to Pin 1.
3 SENSE Sense Input. Connect this pin as close as possible to the load for best load regulation. Use an external
resistor divider to set the output voltage higher than the fixed output voltage.
4 SS Soft Start. A 1 nF external capacitor connected to SS results in a 1.0 ms start-up time.
5 EN Regulator Enable. Drive EN high to turn on the regulator; drive EN low to turn off the regulator. For
automatic startup, connect EN to VIN (Pin 7 or Pin 8).
6
GND
Ground.
7
VIN
Regulator Input Supply. Bypass this pin to GND with a 4.7 µF or greater capacitor.
8 VIN Regulator Input Supply. This pin is internally connected to Pin 7.
9 EP Exposed Pad. The exposed pad is on the bottom of the package. The exposed pad enhances thermal
performance and is electrically connected to GND inside the package. Connect the exposed pad to the
ground plane on the board to ensure proper operation.
3SENSE
4SS
1VOUT
2VOUT
6GND
5 EN
8 VIN
7 VIN
NOTES
1. THE EX P OSE D P AD E NHANCE S THERMAL PE RFORM ANCE
AND IS E LECTRI CALLY CONNECTED T O G ND INSIDE T HE
PACKAGE . CO NNE CT T HE E X P OSED P AD TO THE G ROUND
PL ANE ON T HE BOARD T O ENSURE P ROPE R OPERATI ON.
ADM7171
TOP VIEW
(No t t o Scal e)
12298-003
Data Sheet ADM7171
Rev. C | Page 7 of 23
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 5.5 V, VOUT = 5 V, I LOAD = 10 mA, CIN = COUT = 4.7 µF, TA = 25°C, unless otherwise noted.
Figure 4. Output Voltage (VOUT) vs. Junction Temperature
Figure 5. Output Voltage (VOUT) vs. Load Current (ILOAD)
Figure 6. Output Voltage (VOUT) vs. Input Voltage (VIN)
Figure 7. Ground Current vs. Junction Temperature
Figure 8. Ground Current vs. Load Current (ILOAD)
Figure 9. Ground Current vs. Input Voltage (VIN)
VOUT (V)
JUNCTION TEM P E RATURE (°C) 1258525–5–40
4.90
4.92
4.94
4.96
4.98
5.00
5.02
5.04
5.06
5.08
5.10
ILOAD = 100µA
ILOAD = 10mA
ILOAD = 100mA
ILOAD = 500mA
ILOAD = 1000mA
12298-004
V
OUT
(V)
I
LOAD
(mA) 10001001010.1
4.95
4.96
4.97
4.98
4.99
5.00
5.01
5.02
5.03
5.04
5.05
12298-005
V
OUT
(V)
V
IN
(V) 6.66.46.26.05.85.65.4
4.95
4.96
4.97
4.98
4.99
5.00
5.01
5.02
5.03
5.04
5.05
I
LOAD
= 100µA
I
LOAD
= 10mA
I
LOAD
= 100mA
I
LOAD
= 500mA
I
LOAD
= 1000mA
12298-006
GRO UND CURRE NT (mA)
JUNCTION TEM P E RATURE (°C) 1258525–5–40
0
7
6
5
4
3
2
1
ILOAD = 100µA
ILOAD = 10mA
ILOAD = 100mA
ILOAD = 500mA
ILOAD = 1000mA
12298-007
GRO UND CURRE NT (mA)
I
LOAD
(mA) 10001001010.1
0
7
6
5
4
3
2
1
12298-008
GRO UND CURRE NT (mA)
V
IN
(V)
0
1
2
3
4
5
7
6
6.56.36.15.9
5.75.5
I
LOAD
= 100µA
I
LOAD
= 10mA
I
LOAD
= 100mA
I
LOAD
= 500mA
I
LOAD
= 1000mA
12298-009
ADM7171 Data Sheet
Rev. C | Page 8 of 23
Figure 10. Shutdown Current vs. Temperature at Various Input Voltages
Figure 11. Dropout Voltage vs. Load Current (ILOAD), VOUT = 5 V
Figure 12. Output Voltage (VOUT) vs. Input Voltage (VIN) in Dropout, VOUT = 5 V
Figure 13. Ground Current vs. Input Voltage (VIN) in Dropout, VOUT = 5 V
Figure 14. Output Voltage (VOUT) vs. Junction Temperature, VOUT = 3 V
Figure 15. Output Voltage (VOUT) vs. Load Current (ILOAD), VOUT = 3 V
SHUT DO WN CURRENT (µ A)
TEMPERATURE (°C)
0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
–50 –25 025 50 75 100 125
V
IN
= 2.3V
V
IN
= 2.5V
V
IN
= 3.5V
V
IN
= 4.0V
V
IN
= 5.0V
V
IN
= 6.5V
12298-010
DROPOUT VOLTAGE (mV)
I
LOAD
(mA) 1000100101
0
20
40
60
80
100
140
120
12298-011
V
OUT
(V)
V
IN
(V) 5.45.35.25.15.04.94.7 4.8
4.60
4.65
4.70
4.75
4.80
4.85
4.90
4.95
5.00
5.05
5.10
I
LOAD
=5mA
I
LOAD
=10mA
I
LOAD
=100mA
I
LOAD
=500mA
I
LOAD
=1000mA
12298-012
GRO UND CURRE NT (mA)
V
IN
(V) 5.45.35.25.15.04.94.7 4.8
0
40
35
30
25
20
15
10
5
I
LOAD
= 5mA
I
LOAD
= 10mA
I
LOAD
= 100mA
I
LOAD
= 500mA
I
LOAD
= 1000mA
12298-013
VOUT (V)
JUNCTION TEM P E RATURE (°C) 1258525–5–40
2.95
3.05
3.04
3.03
3.02
3.01
3.00
2.99
2.98
2.97
2.96
ILOAD = 100µA
ILOAD = 10mA
ILOAD = 100mA
ILOAD = 500mA
ILOAD = 1000mA
12298-014
V
OUT
(V)
I
LOAD
(mA) 10001001010.1
2.95
3.05
3.04
3.03
3.02
3.01
3.00
2.99
2.98
2.97
2.96
12298-015
Data Sheet ADM7171
Rev. C | Page 9 of 23
Figure 16. Output Voltage (VOUT) vs. Input Voltage(VIN), VOUT = 3 V
Figure 17. Ground Current vs. Junction Temperature, VOUT = 3 V
Figure 18. Ground Current vs. Load Current (ILOAD), VOUT = 3 V
Figure 19. Ground Current vs. Input Voltage (VIN), VOUT = 3 V
Figure 20. Dropout Voltage vs. Load Current (ILOAD), VOUT = 3 V
Figure 21. Output Voltage (VOUT) vs. Input Voltage (VIN) in Dropout, VOUT = 3 V
V
OUT
(V)
V
IN
(V) 6.66.25.85.45.04.64.23.83.4
2.95
3.05
3.04
3.03
3.02
3.01
3.00
2.99
2.98
2.97
2.96
I
LOAD
= 100µA
I
LOAD
= 10mA
I
LOAD
= 100mA
I
LOAD
= 500mA
I
LOAD
= 1000mA
12298-016
GRO UND CURRE NT (mA)
JUNCTION TEM P E RATURE (°C) 1258525–5–40
0
7
6
5
4
3
2
1
ILOAD = 100µA
ILOAD = 10mA
ILOAD = 100mA
ILOAD = 500mA
ILOAD = 1000mA
12298-017
GRO UND CURRE NT (mA)
I
LOAD
(mA) 10001001010.1
0
1
2
3
4
5
6
7
12298-018
GRO UND CURRE NT (mA)
V
IN
(V) 6.66.25.85.45.04.64.23.83.4
0
7
6
5
4
3
2
1
I
LOAD
= 100µA
I
LOAD
= 10mA
I
LOAD
= 100mA
I
LOAD
= 500mA
I
LOAD
= 1000mA
12298-019
DROPOUT VOLTAGE (mV)
I
LOAD
(mA) 1000100101
0
180
160
140
120
100
80
60
40
20
12298-020
V
OUT
(V)
V
IN
(V) 3.43.2 3.33.13.02.92.82.7
2.50
3.05
3.00
2.95
2.90
2.85
2.80
2.75
2.70
2.65
2.60
2.55
I
LOAD
=5mA
I
LOAD
= 10mA
I
LOAD
=100mA
I
LOAD
=500mA
I
LOAD
= 1000mA
12298-021
ADM7171 Data Sheet
Rev. C | Page 10 of 23
Figure 22. Ground Current vs. Input Voltage (VIN) in Dropout, VOUT = 3 V
Figure 23. Output Voltage (VOUT) vs. Junction Temperature,
Adjustable Version, VOUT = 1.2 V
Figure 24. Output Voltage (VOUT) vs. Load Current (ILOAD), Adjustable Version,
VOUT = 1.2 V
Figure 25. Output Voltage (VOUT) vs. Input Voltage (VIN), Adjustable Version,
VOUT = 1.2 V
Figure 26. Ground Current vs. Junction Temperature, Adjustable Version,
VOUT = 1.2 V
Figure 27. Ground Current vs. Load Current (ILOAD), Adjustable Version,
VOUT = 1.2 V
GRO UND CURRE NT (mA)
V
IN
(V) 3.43.2 3.33.13.02.92.82.7
0
16
14
12
10
8
6
4
2
I
LOAD
= 5mA
I
LOAD
= 10mA
I
LOAD
= 100mA
I
LOAD
= 500mA
I
LOAD
= 1000mA
12298-022
VOUT (V)
JUNCTION TEM P E RATURE (°C) 1258525–5–40
1.16
1.24
1.22
1.20
1.18
1.23
1.21
1.19
1.17
ILOAD = 100µA
ILOAD = 10mA
ILOAD = 100mA
ILOAD = 500mA
ILOAD = 1000mA
12298-023
V
OUT
(V)
I
LOAD
(mA) 10001001010.1
1.16
1.24
1.22
1.20
1.18
1.23
1.21
1.19
1.17
12298-024
V
OUT
(V)
V
IN
(V) 6.52.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
1.16
1.24
1.22
1.20
1.18
1.23
1.21
1.19
1.17
I
LOAD
= 100µA
I
LOAD
= 10mA
I
LOAD
= 100mA
I
LOAD
= 500mA
I
LOAD
= 1000mA
12298-025
GRO UND CURRE NT (mA)
JUNCTION TEM P E RATURE (°C) 1258525–5–40
0
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
ILOAD = 100µA
ILOAD = 10mA
ILOAD = 100mA
ILOAD = 500mA
ILOAD = 1000mA
12298-026
GRO UND CURRE NT (mA)
I
LOAD
(mA) 10001001010.1
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
12298-027
Data Sheet ADM7171
Rev. C | Page 11 of 23
Figure 28. Ground Current vs. Input Voltage (VIN), Adjustable Version,
VOUT = 1.2 V
Figure 29. Soft Start Current vs. Temperature, Different Input Voltages,
VOUT = 5 V
Figure 30. Power Supply Rejection Ratio (PSRR) vs. Frequency, VOUT = 3 V,
1 A Load Current, Various Headroom Voltages
Figure 31. Power Supply Rejection Ratio (PSRR) vs. Headroom, VOUT = 3 V,
1 A Load Current, Different Frequencies
Figure 32. Power Supply Rejection Ratio (PSRR) vs. Frequency, 800 mV
Headroom, VOUT = 3 V
Figure 33. Power Supply Rejection Ratio (PSRR) vs. Frequency, 400 mV
Headroom, VOUT = 3 V
GRO UND CURRE NT (mA)
V
IN
(V) 6.52.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5 I
LOAD
= 100µA
I
LOAD
= 10mA
I
LOAD
= 100mA
I
LOAD
= 500mA
I
LOAD
= 1000mA
12298-028
SS CURRENT (µA)
TEMPERATURE (°C) 1258525–5–40
0.8
0.9
1.0
1.1
1.2 VIN = 3.0V
VIN = 4.0V
VIN = 5.0V
VIN = 6.0V
VIN = 6.5V
12298-029
PSRR ( dB)
FRE Q UE NCY ( Hz ) 10M110 100 1k 10k 100k 1M
–100
–80
–60
–40
–20
0
800mV
700mV
600mV
500mV
400mV
300mV
200mV
160mV
100mV
12298-030
PSRR ( dB)
HEADROOM ( V ) 0.8
0.70.60.50.40.30.20.10
–100
–80
–60
–40
–20
0
10Hz
100Hz
1kHz
10kHz
100kHz
1MHz
10MHz
12298-031
PSRR ( dB)
FRE Q UE NCY ( Hz ) 10M110 100 1k 10k 100k 1M
–100
–80
–60
–40
–20
0
12298-032
I
LOAD
= 100mA
I
LOAD
= 200mA
I
LOAD
= 500mA
I
LOAD
= 1A
PSRR ( dB)
FRE Q UE NCY ( Hz ) 10M110 100 1k 10k 100k 1M
–100
–80
–60
–40
–20
0
12298-033
I
LOAD
= 100mA
I
LOAD
= 200mA
I
LOAD
= 500mA
I
LOAD
= 1A
ADM7171 Data Sheet
Rev. C | Page 12 of 23
Figure 34. Power Supply Rejection Ratio (PSRR) vs. Frequency, 300 mV
Headroom, VOUT = 3 V
Figure 35. Power Supply Rejection Ratio (PSRR) vs. Frequency, VOUT = 5 V,
1 A Load Current, Various Headroom Voltages
Figure 36. Power Supply Rejection Ratio (PSRR) vs. Headroom, VOUT = 5 V,
1 A Load Current, Different Frequencies
Figure 37. Power Supply Rejection Ratio (PSRR) vs. Frequency, 800 mV
Headroom, VOUT = 5 V
Figure 38. Power Supply Rejection Ratio (PSRR) vs. Frequency, 400 mV
Headroom, VOUT = 5 V
Figure 39. Power Supply Rejection Ratio (PSRR) vs. Frequency, 300 mV
Headroom, VOUT = 5 V
PSRR ( dB)
FRE Q UE NCY ( Hz ) 10M110 100 1k 10k 100k 1M
–100
–80
–60
–40
–20
0
12298-034
I
LOAD
= 100mA
I
LOAD
= 200mA
I
LOAD
= 500mA
I
LOAD
= 1A
PSRR ( dB)
FRE Q UE NCY ( Hz ) 10M110 100 1k 10k 100k 1M
–100
–80
–60
–40
–20
0
800mV
700mV
600mV
500mV
400mV
300mV
200mV
150mV
12298-035
PSRR ( dB)
HEADROOM ( V ) 0.800.70.60.50.40.30.20.1
–100
–80
–60
–40
–20
0
10Hz
100Hz
1kHz
10kHz
100kHz
1MHz
10MHz
12298-036
PSRR ( dB)
FRE Q UE NCY ( Hz ) 10M110 100 1k 10k 100k 1M
–100
–80
–60
–40
–20
0
12298-037
I
LOAD
= 100mA
I
LOAD
= 200mA
I
LOAD
= 500mA
I
LOAD
= 1A
PSRR ( dB)
FRE Q UE NCY ( Hz ) 10M110 100 1k 10k 100k 1M
–100
–80
–60
–40
–20
0
12298-038
I
LOAD
= 100mA
I
LOAD
= 200mA
I
LOAD
= 500mA
I
LOAD
= 1A
PSRR ( dB)
FRE Q UE NCY ( Hz ) 10M
110 100 1k 10k 100k 1M
–100
–80
–60
–40
–20
0
12298-039
I
LOAD
= 100mA
I
LOAD
= 200mA
I
LOAD
= 500mA
I
LOAD
= 1A
Data Sheet ADM7171
Rev. C | Page 13 of 23
Figure 40. RMS Output Noise vs. Load Current (ILOAD), Adjustable Version,
VOUT = 1.2 V
Figure 41. RMS Output Noise vs. Load Current (ILOAD), VOUT = 3 V
Figure 42. RMS Output Noise vs. Load Current (ILOAD), VOUT = 5 V
Figure 43. RMS Output Noise vs. Output Voltage,
Load Current = 100 mA
Figure 44. Output Noise Spectral Density, Adjustable Version, VOUT = 1.2 V
Figure 45. Output Noise Spectral Density, VOUT = 3 V
NOI S E ( µV rms)
I
LOAD
(mA) 10000110 100 1000
0
2
4
6
8
10
1
3
5
7
910Hz T O 100kHz
100Hz T O 100kHz
12298-040
NOI S E ( µV rms)
I
LOAD
(mA) 10000110 100 1000
0
2
4
6
8
10
1
3
5
7
910Hz T O 100kHz
100Hz T O 100kHz
12298-041
NOI S E ( µV rms)
I
LOAD
(mA) 10000110 100 1000
0
2
4
6
8
10
1
3
5
7
910Hz T O 100kHz
100Hz T O 100kHz
12298-042
NOI S E ( µV rms)
OUTPUT VOLTAGE (V) 5.04.6
4.23.83.43.02.62.21.81.41.0
0
2
4
6
8
10
1
3
5
7
910Hz T O 100kHz
100Hz T O 100kHz
12298-043
NOISE SPECTRAL DENSITY (nV/√Hz)
FRE Q UE NCY ( Hz ) 10M110 100 1k 10k 100k 1M
1
10
100
1k
10k
100k I
LOAD
= 1mA
I
LOAD
= 10mA
I
LOAD
= 100mA
I
LOAD
= 500mA
I
LOAD
= 1.0A
12298-044
NOISE SPECTRAL DENSITY (nV/√Hz)
FRE Q UE NCY ( Hz ) 10M110 100 1k 10k 100k 1M
1
10
100
1k
10k
100k I
LOAD
= 1mA
I
LOAD
= 10mA
I
LOAD
= 100mA
I
LOAD
= 500mA
I
LOAD
= 1.0A
12298-045
ADM7171 Data Sheet
Rev. C | Page 14 of 23
Figure 46. Output Noise Spectral Density, VOUT = 5 V
Figure 47. Output Noise Spectral Density, Different Output Voltages,
Load Current = 100 mA
Figure 48. Load Transient Response, ILOAD = 10 mA to 1 A,
VOUT = 5 V, VIN = 5.5 V, CH1 = ILOAD, CH2 = VOUT
Figure 49. Load Transient Response, ILOAD = 10 mA to 500 mA,
VOUT = 5 V, VIN = 5.5 V, CH1= ILOAD, CH2 = VOUT
Figure 50. Load Transient Response, ILOAD = 10 mA to 1 A,
Adjustable Version, VOUT = 1.2 V, VIN = 2.5 V, CH1 = ILOAD, CH2 = VOUT
Figure 51. Load Transient Response, ILOAD = 10 mA to 500 mA,
Adjustable Version, VOUT = 1.2 V, VIN = 2.5 V, CH1 = ILOAD, CH2 = VOUT
NOISE SPECTRAL DENSITY (nV/√Hz)
FRE Q UE NCY ( Hz ) 10M110 100 1k 10k 100k 1M
1
10
100
1k
10k
100k I
LOAD
= 1mA
I
LOAD
= 10mA
I
LOAD
= 100mA
I
LOAD
= 500mA
I
LOAD
= 1.0A
12298-046
NOISE SPECTRAL DENSITY (nV/√Hz)
FRE Q UE NCY ( Hz ) 10M110 100 1k 10k 100k 1M
1
10
100
1k
10k
100k 5.0V
3.0V
1.2V
12298-047
12298-048
CH1 500mA Ω
BW
CH2 20mV
BW
M4.0µs A CH1 570mA
T 10.4%
1
2
T
12298-049
CH1 200mA Ω
BW
CH2 10mV
BW
M4.0µs A CH1 124mA
T 10.6%
T
1
2
12298-050
CH1 500mA Ω
BW
CH2 20mV
BW
M1.0µs A CH1 530mA
T 10.8%
T
1
2
12298-051
CH1 200mA Ω
BW
CH2 10mV
BW
M2.0µs A CH1 160mA
T 9.8%
T
1
2
Data Sheet ADM7171
Rev. C | Page 15 of 23
Figure 52. Line Transient Response, 6 V to 6.5 V, ILOAD = 1 A,
VOUT = 5 V, CH1 = VIN, CH2 = VOUT
Figure 53. Line Transient Response, 2.5 V to 3 V, ILOAD = 1 A,
Adjustable Version, VOUT = 1.2 V, CH1 = VIN, CH2 = VOUT
12298-052
CH1 500mV
BW
CH2 2.0mV
BW
M4.0µs A CH3 –300mV
T 9.8%
T
1
2
12298-053
CH1 500mV
BW
CH2 2.0mV
BW
M4.0µs A CH3 360mV
T 9.8%
T
1
2
ADM7171 Data Sheet
Rev. C | Page 16 of 23
THEORY OF OPERATION
The ADM7171 is a low quiescent current, low dropout linear
regulator that operates from 2.3 V to 6.5 V and provides up to
1 A of load current. Drawing a low 4.0 mA of quiescent current
(typical) at full load makes the ADM7171 ideal for portable
equipment. Typical shutdown current consumption is 0.25 μA
at room temperature.
Optimized for use with small 4.7 µF ceramic capacitors, the
ADM7171 provides excellent transient performance.
Figure 54. Internal Block Diagram
Internally, the ADM7171 consists of a reference, an error
amplifier, a feedback voltage divider, and a PMOS pass transistor.
Output current is delivered via the PMOS pass device, which is
controlled by the error amplifier. The error amplifier compares
the reference voltage with the feedback voltage from the output
and amplifies the difference. When the feedback voltage is
lower than the reference voltage, the gate of the PMOS device is
pulled lower, allowing more current to pass and increasing the
output voltage. When the feedback voltage is higher than the
reference voltage, the gate of the PMOS device is pulled higher,
allowing less current to pass and decreasing the output voltage.
The ADM7171 is available in 17 fixed output voltage options,
ranging from 1.2 V t o 5 V. T h e ADM7171 architecture allows
any fixed output voltage to be set to a higher voltage with an
external voltage divider. For example, a fixed 5 V output
ADM7171 can be set to a 6 V output according to the following
equation:
VOUT = 5 V(1 + R1/R2)
Figure 55. Typical Adjustable Output Voltage Application Schematic
Use a value of less than 200 kΩ for R2 to minimize errors in the
output voltage caused by the SENSE pin input current. For
example, when R1 and R2 each equal 200 kΩ and the default
output voltage is 1.2 V, the adjusted output voltage is 2.4 V. The
output voltage error introduced by the SENSE pin input current is
0.1 mV or 0.004%, assuming a typical SENSE pin input bias
current of 1 nA at 25°C.
The ADM7171 uses the EN pin to enable and disable the VOUT
pins under normal operating conditions. When EN is high,
VOUT turns on, when EN is low, VOUT turns off. For automatic
startup, tie EN to VIN (Pin 7 or Pin 8).
VOUT
SENSE
SS
GND CURRENT-LIMIT,
THERMAL
PROTECT
SOFT START
REFERENCE
SHUTDOWN
EN
VIN
12298-056
VOUT
SENSE
VIN
ADM7171
GND
VIN VOUT
SS C
SS
1nF
C
IN
4.7µF C
OUT
4.7µF
EN
OFF
ON
V
IN
= 6.5V V
OUT
= 6.0V
R1
2kΩ
R2
10kΩ
12298-057
Data Sheet ADM7171
Rev. C | Page 17 of 23
APPLICATIONS INFORMATION
ADIsimPOWER DESIGN TOOL
The ADM7171 is supported by the ADIsimPower™ design tool
set. ADIsimPower is a collection of tools that produce complete
power designs optimized for a specific design goal. The tools
enable the user to generate a full schematic, bill of materials,
and calculate performance in minutes. ADIsimPower can
optimize designs for cost, area, efficiency, and parts count,
taking into consideration the operating conditions and
limitations of the IC and all real external components. For more
information about, and to obtain ADIsimPower design tools,
visit www.analog.com/ADIsimPower.
CAPACITOR SELECTION
Multilayer ceramic capacitors (MLCC) combine small size, low
effective series resistance (ESR), low ESL, and wide operating
temperature range, making them an ideal choice for bypass
capacitors. They are not without limitations, however.
Depending on the dielectric material, the capacitance can vary
dramatically with temperature, dc bias, and ac signal level.
Therefore, selecting the proper capacitor results in the best
circuit performance.
Output Capacitor
The ADM7171 is designed for operation with small, space-
saving ceramic capacitors but functions with most commonly
used capacitors as long as care is taken with regard to the ESR
value. The ESR of the output capacitor affects the stability of the
LDO control loop. A minimum of 4.7 µF capacitance with an
ESR of 0.05 Ω or less is recommended to ensure the stability of the
ADM7171. Transient response to changes in load current is also
affected by output capacitance. Using a larger value of output
capacitance improves the transient response of the ADM7171 to
large changes in load current. Figure 56 shows the transient
responses for an output capacitance value of 4.7 µ F.
Figure 56. Output Transient Response, VOUT = 5 V, COUT = 4.7 µF
Input Bypass Capacitor
Connecting a 4.7 µF capacitor from VIN to GND reduces the
circuit sensitivity to PCB layout, especially when long input
traces or a high source impedance is encountered. If greater
than 4.7 µF of output capacitance is required, increase the input
capacitor to match it.
Input and Output Capacitor Properties
Any good quality ceramic capacitors can be used with the
ADM7171 if they meet the minimum capacitance and
maximum ESR requirements. Ceramic capacitors are manufac-
tured with a variety of dielectrics, each with different behavior
over temperature and applied voltage. Capacitors require a
dielectric adequate to ensure the minimum capacitance over
the necessary temperature range and dc bias conditions. X5R
or X7R dielectrics with a voltage rating of 6.3 V to 100 V are
recommended. Y5V and Z5U dielectrics are not recommended,
due to their poor temperature and dc bias characteristics.
Figure 57 depicts the capacitance vs. dc bias voltage of a 0805,
4.7 µF, 16 V, X5R capacitor. The voltage stability of a capacitor is
strongly influenced by the capacitor size and voltage rating. In
general, a capacitor in a larger package or higher voltage rating
exhibits better stability. The temperature variation of the X5R
dielectric is ~±15% over the −40°C to +85°C temperature range
and is not a function of package or voltage rating.
Figure 57. Capacitance vs. DC Bias Voltage
Use Equation 1 to determine the worst-case capacitance accounting
for capacitor variation over temperature, component tolerance,
and voltage.
CEFF = CBIAS × (1 − TEMPCO) × (1 − TOL) (1)
where:
CBIAS is the effective capacitance at the operating voltage.
TEMPCO is the worst-case capacitor temperature coefficient.
TOL is the worst-case component tolerance.
In this example, the worst-case temperature coefficient (TEMPCO)
over −40°C to +85°C is assumed to be 15% for an X5R dielectric.
12298-058
CH1 500mA
BW
CH2 20mV
BW
M4.0µs A CH1 570mA
T 10.4%
T
1
2
CAPACITANCE ( µF)
DC BIAS V OL TAG E ( V ) 20181614121086420
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
12298-059
ADM7171 Data Sheet
Rev. C | Page 18 of 23
The tolerance of the capacitor (TOL) is assumed to be 10%, and
CBIAS is 4.35 μF at 3.0 V, as shown in Figure 57.
Substituting these values in Equation 1 yields
CEFF = 4.35 μF × (1 − 0.15) × (1 − 0.1) = 3.33 μF
Therefore, the capacitor chosen in this example meets the
minimum capacitance requirement of the LDO over temper-
ature and tolerance at the chosen output voltage of 3.0 V.
To guarantee the performance of the ADM7171, it is imperative
that the effects of dc bias, temperature, and tolerances on the
behavior of the capacitors be evaluated for each application.
PROGRAMMABLE PRECISION ENABLE
The ADM7171 uses the EN pin to enable and disable the VOUT
pins under normal operating conditions. As shown in Figure 58,
when a rising voltage on EN crosses the upper threshold,
typically 1.2 V, VOUT turns on. When a falling voltage on EN
crosses the lower threshold, typically 1.1 V, VOUT turns off. The
hysteresis of the EN threshold is approximately 100 m V.
Figure 58. Typical VOUT Response to EN Pin Operation
The upper and lower thresholds are user programmable and can
be set higher than the nominal 1.2 V threshold by using two
resistors. The resistance values, REN1 and REN2, can be
determined from
REN1 = REN2 × (VIN − 1.2 V)/1.2 V
where:
REN2 is nominally 10 kΩ to 100 kΩ.
VIN is the desired turn-on voltage.
The hysteresis voltage increases by the factor
(REN1 + REN2)/REN1
For the example shown in Figure 59, the enable threshold is
3.6 V with a hysteresis of 300 m V.
Figure 59. Typical EN Pin Voltage Divider
Figure 58 shows the typical hysteresis of the EN pin. This
prevents on/off oscillations that can occur due to noise
on the EN pin as it passes through the threshold points.
UNDERVOLTAGE LOCKOUT
The ADM7171 also incorporates an internal undervoltage
lockout circuit to disable the output voltage when the input
voltage is less than the minimum input voltage rating of the
regulator. The upper and lower thresholds are internally fixed
with about 200 mV of hysteresis. This hysteresis prevents on/off
oscillations that can occur when caused by noise on the input
voltage as it passes through the threshold points.
SOFT START
The ADM7171 uses an internal soft start (SS pin open) to limit the
inrush current when the output is enabled. The start-up time for
the 5.0 V option is approximately 380 μs from the time the EN
active threshold is crossed to when the output reaches 90% of its
final value. As shown in Figure 60, the start-up time is nearly
independent of the output voltage setting.
Figure 60. Typical Start-Up Behavior
VOUT (V)
VEN (V) 1.301.251.201.151.101.051.00
0
0.5
1.0
1.5
2.0
2.5
3.0
12298-060
VOUT
SENSE
VIN
EN
ADM7171
GND
CIN
4.7µF COUT
4.7µF
OFF
ON
VOUT = 5. 0V
VIN = 6.0V
REN1
200kΩ
REN2
100kΩ
12298-061
VOUT
VIN
VOUT (V)
TIME (ms) 1.00.90.80.70.60.50.40.30.20.10
0
0.5
1.0
2.0
3.0
4.0
5.0
1.5
2.5
3.5
4.5 VEN
2.5V
3.0V
5.0V
12298-062
Data Sheet ADM7171
Rev. C | Page 19 of 23
An external capacitor connected to the SS pin determines the
soft start time. The SS pin can be left open for a typical 380 μs
start-up time. Do not ground this pin. When an external soft
start capacitor is used, the soft start time is determined by the
following equation:
SSTIME (sec) = tSTART-UP at 0 nF + (0.6 × CSS)/ISS
where:
tSTART-UP at 0 nF is the start-up time at CSS = 0 nF (typically 380 μs).
CSS is the soft start capacitor (F).
ISS is the soft start current (typically 1 μA).
Figure 61. Typical Soft Start Behavior, Different CSS Values
NOISE REDUCTION OF THE ADM7171 IN
ADJUSTABLE MODE
The ultralow output noise of the ADM7171 is achieved by
keeping the LDO error amplifier in unity gain and setting the
reference voltage equal to the output voltage. This architecture
does not work for an adjustable output voltage LDO in the
conventional sense. However, the ADM7171 architecture allows
any fixed output voltage to be set to a higher voltage with an
external voltage divider. For example, the adjustable (1.2 V in
unity gain) output ADM7171 can be set to a 6 V output
according to the following equation:
VOUT = 1.2 V(1 + R1/R2)
The disadvantage of using the ADM7171 in this manner is that
the output voltage noise is proportional to the output voltage.
Therefore, it is best to choose a fixed output voltage that is close
to the target voltage to minimize the increase in output noise.
The adjustable LDO circuit can be modified to reduce the
output voltage noise to levels close to that of the fixed output
ADM7171. The circuit shown in Figure 62 adds two additional
components to the output voltage setting resistor divider. CNR
and RNR are added in parallel with RFB1 to reduce the ac gain of
the error amplifier. RNR is chosen to be small with respect to
RFB2. If RNR is 1% to 10% of the value of RFB2, the minimum ac
gain of the error amplifier is approximately 0.1 dB to 0.8 dB.
The actual gain is determined by the parallel combination of
RNR and RFB1. This ensures that the error amplifier always
operates at slightly greater than unity gain.
CNR is chosen by setting the reactance of CNR equal to RFB1 −
RNR at a frequency between 0.5 Hz and 10 Hz. This sets the
frequency where the ac gain of the error amplifier is 3 dB
less than its dc gain.
Figure 62. Noise Reduction Modification
Assuming the noise of a fixed output LDO is approximately
5 μV, i d e nt i f y t he noise of the adjustable LDO by using the
following formula:
Noise = 5 μV × (RPAR + RFB2)/RFB2
where RPAR is the parallel combination of RFB1 and RNR.
Based on the component values shown in Figure 62, the
ADM7171 has the following characteristics:
• DC gain of 5 (14 dB)
• 3 dB roll-off frequency of 0.8 Hz
• High frequency ac gain of 1.09 (0.75 dB)
• Noise reduction factor of 4.42 (12.91 dB)
• RMS noise of the adjustable LDO without noise reduction
of 25 µV rms
• RMS noise of the adjustable LDO with noise reduction
(assuming 5 µV rms for fixed voltage option) of 5.5 µV rms
EFFECT OF NOISE REDUCTION ON START-UP TIME
The start-up time of the ADM7171 is affected by the noise
reduction network and must be considered in applications
wherein power supply sequencing is critical.
The noise reduction circuit adds a pole in the feedback loop
that slows down the start-up time. The start-up time for an
adjustable model with a noise reduction network can be
approximated using the following equation:
SSNRTIME (sec) = 5.5 × CNR × (RNR + RFB1)
For a CNR, RNR, and RFB1 combination of 1 µ F, 5 kΩ, and 200 kΩ,
respectively, as shown in Figure 62, the start-up time is
approximately 1.1 seconds. When SSNRTIME is greater than
SSTIME, it dictates the length of the start-up time instead of the
soft start capacitor.
CURRENT-LIMIT AND THERMAL OVERLOAD
PROTECTION
The ADM7171 is protected against damage due to excessive
power dissipation by current-limit and thermal overload
protection circuits. The ADM7171 is designed to current limit
when the output load reaches 3 A (typical). When the output
load exceeds 3 A, the output voltage is reduced to maintain a
constant current limit.
VOUT (V)
TIME (ms) 109876543210
0
0.5
1.0
2.0
3.0
3.5
1.5
2.5
VEN
NO CSS
1nF
4.7nF
10nF
12298-063
VOUT
SENSE
VIN
ADM7171
GND
VIN VOUT
SS C
SS
1nF
C
IN
4.7µF C
OUT
4.7µF
C
NR
1µF
EN
OFF
ON
V
IN
= 6.5V V
OUT
= 6.0V
R
FB1
200kΩ
R
FB2
50kΩ
R
NR
5kΩ
12298-064
ADM7171 Data Sheet
Rev. C | Page 20 of 23
Thermal overload protection is included, which limits the
junction temperature to a maximum of 150°C (typical). Under
extreme conditions (that is, high ambient temperature and/or
high power dissipation) when the junction temperature starts to
rise above 150°C, the output is turned off, reducing the output
current to zero. When the junction temperature drops below
135°C, the output is turned on again, and the output current is
restored to its operating value.
Consider the case where a hard short from VOUT to ground
occurs. At first, the ADM7171 current limits, so that only 3 A is
conducted into the short. If self heating of the junction is great
enough to cause its temperature to rise above 150°C, thermal
shutdown activates, turning off the output and reducing the output
current to zero. As the junction temperature cools and drops
below 135°C, the output turns on and conducts 3 A into the
short, again causing the junction temperature to rise above
150°C. This thermal oscillation between 135°C and 150°C
causes a current oscillation between 3 A and 0 mA that
continues for as long as the short remains at the output.
Current-limit and thermal limit protections are intended to
protect the device against accidental overload conditions. For
reliable operation, device power dissipation must be externally
limited so that the junction temperature does not exceed 125°C.
THERMAL CONSIDERATIONS
In applications with low input-to-output voltage differential, the
ADM7171 does not dissipate much heat. However, in applications
with high ambient temperature and/or high input voltage, the
heat dissipated in the package may become large enough that
it causes the junction temperature of the die to exceed the
maximum junction temperature of 125°C.
When the junction temperature exceeds 150°C, the converter
enters thermal shutdown. It recovers only after the junction
temperature has decreased below 135°C to prevent any permanent
damage. Therefore, thermal analysis for the chosen application
is very important to guarantee reliable performance over all
conditions. The junction temperature of the die is the sum of
the ambient temperature of the environment and the tempera-
ture rise of the package due to the power dissipation, as shown
in Equation 2.
To guarantee reliable operation, the junction temperature of
the ADM7171 must not exceed 125°C. To ensure that the
junction temperature stays below this maximum value, the
user must be aware of the parameters that contribute to
junction temperature changes. These parameters include
ambient temperature, power dissipation in the power device,
and thermal resistances between the junction and ambient air
(θJA). The θJA number is dependent on the package assembly
compounds that are used and the amount of copper used to
solder the package GND pin to the PCB.
Table 7 shows typical θJA values of the 8-lead LFCSP package for
various PCB copper sizes. The typical value of ΨJB is 15.1°C/W for
the 8-lead LFCSP package.
Table 7. Typical θJA Values
Copper Size (mm2) θJA (°C/W) of LFCSP
251 165.1
100 125.8
500 68.1
1000 56.4
6400 42.1
1 Device soldered to minimum size pin traces.
The junction temperature of the ADM7171 is calculated from
the following equation:
TJ = TA + (PD × θJA) (2)
where:
TA is the ambient temperature.
PD is the power dissipation in the die, given by
PD = [(VIN − VOUT) × ILOAD] + (VIN × IGND) (3)
where:
ILOAD is the load current.
IGND is the ground current.
VIN and VOUT are the input and output voltages, respectively.
Power dissipation due to ground current is quite small and can
be ignored. Therefore, the junction temperature equation
simplifies to the following:
TJ = TA + (((VIN − VOUT) × ILOAD) × θJA) (4)
As shown in Equation 4, for a given ambient temperature, input-
to-output voltage differential, and continuous load current, a
minimum copper size requirement exists for the PCB to ensure
that the junction temperature does not rise above 125°C. Figure 63
to Figure 65 show junction temperature calculations for differ-
ent ambient temperatures, power dissipation, and areas of PCB
copper.
Figure 63. LFCSP, TA = 25°C
JUNCTION TEM P E RATURE (°C)
TOTAL POWER DISSIPATION (W)
6400mm
2
500mm
2
25mm
2
T
J
MAX
25
35
45
55
65
75
85
95
105
115
125
135
145
155
00.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
12298-065
Data Sheet ADM7171
Rev. C | Page 21 of 23
Figure 64. LFCSP, TA = 50°C
Figure 65. LFCSP, TA = 85°C
In the case where the board temperature is known, use the
thermal characterization parameter, ΨJB, to estimate the
junction temperature rise. Maximum junction temperature (TJ)
is calculated from the board temperature (TB) and power
dissipation (PD) using the following formula:
TJ = TB + (PD × ΨJB) (5)
Figure 66. LFCSP Power Dissipation for Various Board Temperatures
TYPICAL APPLICATIONS CIRCUITS
Figure 67. Clock Driver Power
Figure 68. RF PLL/VCO Power
JUNCTION TEM P E RATURE (°C)
TOTAL POWER DISSIPATION (W)
1.8 2.0 2.2 2.41.61.41.21.00.80.60.40.20
50
60
70
80
90
100
110
120
140
160
130
150
6400mm
2
500mm
2
25mm
2
T
J
MAX
12298-066
JUNCTION TEM P E RATURE (°C)
TOTAL POWER DISSIPATION (W) 1.50.8 0.9 1.0 1.1 1.2 1.3 1.40.70.60.50.40.30.20.10
65
75
85
95
105
115
125
135
155
145
6400mm2
500mm2
25mm2
TJ MAX
12298-067
JUNCTION TEM P E RATURE (°C)
TOTAL POWER DISSIPATION (W) 9876543210
0
160
140
120
100
80
60
40
20
T
B
= 25° C
T
B
= 50° C
T
B
= 65° C
T
B
= 85° C
T
J
MAX
12298-068
ADM7171
6.5V, 1A
LDO
4V T O 6.5V 3.3V HIGH
SPEED
CLOCK
DRIVER
12298-070
ADM7171
6.5V, 1A
LDO
4V T O 6.5V 3.3V V
VCO
ADM7171
6.5V, 1A
LDO
3.3V A
VDD
D
VDD ADF4350
12298-071
ADM7171 Data Sheet
Rev. C | Page 22 of 23
PRINTED CIRCUIT BOARD LAYOUT CONSIDERATIONS
Heat dissipation from the package can be improved by increasing
the amount of copper attached to the pins of the ADM7171.
However, as listed in Table 7, a point of diminishing returns
is eventually reached, beyond which an increase in the copper
size does not yield significant heat dissipation benefits.
Place the input capacitor as close as possible to the VIN and
GND pins. Place the output capacitor as close as possible to the
VOUT and GND pins. Use of 0805 or 1206 size capacitors and
resistors achieves the smallest possible footprint solution on
boards where area is limited.
Figure 69. Example LFCSP PCB Layout
12298-069
Data Sheet ADM7171
Rev. C | Page 23 of 23
OUTLINE DIMENSIONS
Figure 70. 8-Lead Lead Frame Chip Scale Package [LFCSP_WD]
3 mm × 3 mm Body, Very Very Thin, Dual Lead
(CP-8-21)
Dimensions shown in millimeters
ORDERING GUIDE
Model4F
1 Temperature Range Output Voltage (V)5F
2,
6F
3 Package Description Package Option Branding
ADM7171ACPZ-1.3-R7 −40°C to +125°C 1.3 8-Lead LFCSP_WD CP-8-21 LPX
ADM7171ACPZ-1.8-R7 −40°C to +125°C 1.8 8-Lead LFCSP_WD CP-8-21 LPY
ADM7171ACPZ-2.5-R7 −40°C to +125°C 2.5 8-Lead LFCSP_WD CP-8-21 LR3
ADM7171ACPZ-3.0-R7 −40°C to +125°C 3.0 8-Lead LFCSP_WD CP-8-21 LPZ
ADM7171ACPZ-3.3-R7 −40°C to +125°C 3.3 8-Lead LFCSP_WD CP-8-21 LQ0
ADM7171ACPZ-4.2-R7 −40°C to +125°C 4.2 8-Lead LFCSP_WD CP-8-21 LQX
ADM7171ACPZ-5.0-R7 −40°C to +125°C 5.0 8-Lead LFCSP_WD CP-8-21 LQ1
ADM7171ACPZ-R7 −40°C to +125°C Adjustable (1.2 V) 8-Lead LFCSP_WD CP-8-21 LQ2
ADM7171ACPZ-R2 −40°C to +125°C Adjustable (1.2 V) 8-Lead LFCSP_WD CP-8-21 LQ2
ADM7171CP-EVALZ Evaluation Board
1 Z = RoHS Compliant Part.
2 For additional voltage options, contact a local Analog Devices, Inc., sales or distribution representative.
3 The evaluation board is preconfigured with an adjustable voltage (1.2 V) preset to a 3.0 V ADM7171.
2.54
2.44
2.34
0.50
0.40
0.30
TOP VIEW
8
1
5
4
0.30
0.25
0.20
BOTTOM VIEW
PIN 1 IN DEX
AREA
SEATING
PLANE
0.80
0.75
0.70
1.70
1.60
1.50
0.203 REF
0.20 MI N
0.05 MAX
0.02 NOM
0.50 BSC
EXPOSED
PAD
PIN 1
INDICATOR
(R 0.20)
FOR PROPE R CONNE C TI ON OF
THE EXPOSED PAD, REFER TO
THE P I N CO N F I GURAT IO N AND
FUNC TI ON DESCRIPTIONS
SECTION OF T HIS DATA SHEET.
12-03-2013-A
PKG-004371
3.10
3.00 S Q
2.90
©2014–2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D12298-0-8/15(C)
