LMP91002 www.ti.com SNIS163A - APRIL 2012 - REVISED MARCH 2013 LMP91002 Sensor AFE System: Configurable AFE Potentiostat for Low-Power Chemical Sensing Applications Check for Samples: LMP91002 FEATURES DESCRIPTION * * * * * The LMP91002 is a programmable Analog Front End (AFE) for use in micro-power electrochemical sensing applications. It provides a complete signal path solution between a not biased gas sensor and a microcontroller generating an output voltage proportional to the cell current. The LMP91002's programmability enables it support not biased electrochemical gas sensor with a single design. The LMP91002 supports gas sensitivities over a range of 0.5 nA/ppm to 9500 nA/ppm. It also allows for an easy conversion of current ranges from 5A to 750A full scale. The LMP91002's transimpedance amplifier (TIA) gain is programmable through the I2C interface. The I2C interface can also be used for sensor diagnostics. The LMP91002 is optimized for micropower applications and operates over a voltage range of 2.7V to 3.6V. The total current consumption can be less than 10A. Further power savings are possible by switching off the TIA amplifier and shorting the reference electrode to the working electrode with an internal switch. 1 * * * * * * * * Typical Values, TA = 25C Supply Voltage 2.7 V to 3.6 V Supply Current (Average Over Time) <10 A Cell Conditioning Current Up to 10 mA Reference Electrode Bias Current (85C) 900pA (Max) Output Drive Current 750A Complete Potentiostat Circuit to Interface to Most Not Biased Gas Sensors Low Bias Voltage Drift Programmable TIA Gain 2.75k to 350k I2C Compatible Digital Interface Ambient Operating Temperature -40C to 85C Package 14 pin WSON Supported by Webench Sensor AFE Designer APPLICATIONS * * * Gas Detector Amperometric Applications Electrochemical Blood Glucose Meter Typical Application VDD VREF SCL LMP91002 3-Lead Electrochemical Cell + CE A1 DIAGNOSTIC VREF DIVIDER I2C INTERFACE AND CONTROL REGISTERS SDA MSP430 MENB - CE RE RE DGND WE + WE - RLoad VOUT TIA RTIA C1 C2 AGND Figure 1. AFE Gas Detector 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2012-2013, Texas Instruments Incorporated LMP91002 SNIS163A - APRIL 2012 - REVISED MARCH 2013 www.ti.com Connection Diagram DGND 1 14 CE MENB RE SCL WE SDA VREF DAP NC C1 VDD C2 AGND 7 8 VOUT Figure 2. 14-Pin WSON - Top View See Package Number NHL0014B PIN DESCRIPTIONS Pin Name Description 1 DGND Connect to ground 2 MENB Module Enable, Active Low 3 SCL Clock signal for I2C compatible interface 4 SDA Data for I2C compatible interface 5 NC 6 VDD Not Internally Connected 7 AGND Ground 8 VOUT Analog Output Supply Voltage 9 C2 External filter connector (Filter between C1 and C2) 10 C1 External filter connector (Filter between C1 and C2) 11 VREF 12 WE Working Electrode. Output to drive the Working Electrode of the chemical sensor 13 RE Reference Electrode. Input to drive Counter Electrode of the chemical sensor 14 CE Counter Electrode. Output to drive Counter Electrode of the chemical sensor DAP Voltage Reference input Connect to AGND These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 2 Submit Documentation Feedback Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: LMP91002 LMP91002 www.ti.com SNIS163A - APRIL 2012 - REVISED MARCH 2013 Absolute Maximum Ratings (1) (2) (3) Human Body Model ESD Tolerance (4) 2kV Charge-Device Model 1kV Machine Model 200V Voltage between any two pins 6.0V Current through VDD or VSS 50mA Current sunk and sourced by CE pin 10mA Current out of other pins (5) 5mA Storage Temperature Range -65C to 150C Junction Temperature (6) (1) (2) (3) (4) (5) (6) 150C "Absolute Maximum Ratings" indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Operating Ratings is not implied. Operating Ratings indicate conditions at which the device is functional and the device should not be operated beyond such conditions. For soldering specifications, see www.ti.com/lit/SNOA549. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of JEDEC) Field- Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC). All non-power pins of this device are protected against ESD by snapback devices. Voltage at such pins will rise beyond absmax if current is forced into pin. The maximum power dissipation is a function of TJ(MAX), JA, and the ambient temperature, TA. The maximum allowable power dissipation at any ambient temperature is PDMAX = (TJ(MAX) - TA)/ JA All numbers apply for packages soldered directly onto a PC board. Operating Ratings (1) Supply Voltage VS = (VDD - AGND) 2.7V to 3.6V Temperature Range (2) Package Thermal Resistance (2) (1) (2) -40C to 85C 14-Pin WSON (JA) 44 C/W "Absolute Maximum Ratings" indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Operating Ratings is not implied. Operating Ratings indicate conditions at which the device is functional and the device should not be operated beyond such conditions. The maximum power dissipation is a function of TJ(MAX), JA, and the ambient temperature, TA. The maximum allowable power dissipation at any ambient temperature is PDMAX = (TJ(MAX) - TA)/ JA All numbers apply for packages soldered directly onto a PC board. Submit Documentation Feedback Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: LMP91002 3 LMP91002 SNIS163A - APRIL 2012 - REVISED MARCH 2013 www.ti.com Electrical Characteristics (1) Unless otherwise specified, all limits ensured for TA = 25C, VS= (VDD - AGND), VS= 3.3V and AGND = DGND = 0V, VREF = 2.5V, Internal Zero = 20% VREF. Boldface limits apply at the temperature extremes. Symbol Typ (3) Max (2) 3-lead amperometric cell mode MODECN = 0x03 10 15 13.5 Standby mode MODECN = 0x02 6.5 10 8 Deep Sleep mode MODECN = 0x00 0.6 1 0.85 Parameter Min (2) Conditions Units Power Supply Specification IS Supply Current A Potentiostat IRE Input bias current at RE pin Minimum operating current capability ICE Minimum charging capability (4) VDD=2.7V; Internal Zero 50% VDD -90 -800 90 800 VDD=3.6V; Internal Zero 50% VDD -90 -900 90 900 sink 750 source 750 sink 10 source 10 AOL_A1 Open loop voltage gain of control loop op amp (A1) 300mVVCEVs-300mV, -750AICE750A en_RW Low Frequency integrated noise between RE pin and WE pin 0.1Hz to 10Hz (5) VOS_RW WE Voltage Offset referred to RE 104 pA A mA 120 dB 3.4 Vpp 0% VREF, Internal Zero=20% VREF 0% VREF, Internal Zero=50% VREF -550 550 V -4 4 V/C 0% VREF, Internal Zero=67% VREF 0% VREF, Internal Zero=20% VREF TcVOS_RW WE Voltage Offset Drift referred to RE from -40C to 85C (6) 0% VREF, Internal Zero=50% VREF 0% VREF, Internal Zero=67% VREF Transimpedance gain accuracy Linearity TIA_GAIN Programmable TIA Gains (1) (2) (3) (4) (5) (6) 4 5 % 0.05 % 7 programmable gain resistors 2.75 3.5 7 14 35 120 350 Maximum external gain resistor 350 k Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No ensured specification of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. Absolute Maximum Ratings indicate junction temperature limits beyond which the device may be permanently degraded, either mechanically or electrically. Limits are 100% production tested at 25C. Limits over the operating temperature range are ensured through correlations using statistical quality control (SQC) method. Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production material. At such currents no accuracy of the output voltage can be expected. This parameter includes both A1 and TIA's noise contribution. Offset voltage temperature drift is determined by dividing the change in VOS at the temperature extremes by the total temperature change.Starting from the measured voltage offset at temperature T1 (VOS_RW(T1)), the voltage offset at temperature T2 (VOS_RW(T2)) is calculated according the following formula: VOS_RW(T2)=VOS_RW(T1)+ABS(T2-T1)* TcVOS_RW. Submit Documentation Feedback Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: LMP91002 LMP91002 www.ti.com SNIS163A - APRIL 2012 - REVISED MARCH 2013 Electrical Characteristics(1) (continued) Unless otherwise specified, all limits ensured for TA = 25C, VS= (VDD - AGND), VS= 3.3V and AGND = DGND = 0V, VREF = 2.5V, Internal Zero = 20% VREF. Boldface limits apply at the temperature extremes. Symbol TIA_ZV Parameter Min (2) Conditions 3 programmable percentages of VREF 20 50 67 3 programmable percentages of VDD 20 50 67 Internal zero voltage Internal zero voltage Accuracy RL Typ (3) Max (2) Units % 0.04 % Load Resistor 10 Load accuracy 5 % 110 dB Internal zero 20% VREF PSRR Power Supply Rejection Ratio at RE pin 2.7 VDD5.25V Internal zero 50% VREF 80 Internal zero 67% VREF External reference specification (7) VREF (7) External Voltage reference range 1.5 VDD Input impedance V 10 M In case of external reference connected, the noise of the reference has to be added. I2C Interface (1) Unless otherwise specified, all limits ensured for at TA = 25C, VS=(VDD - AGND), 2.7V <VS< 3.6V and AGND = DGND =0V, VREF= 2.5V. Boldface limits apply at the temperature extremes Symbol Parameter VIH Input High Voltage VIL Input Low Voltage VOL Output Low Voltage Conditions (1) (2) (3) (4) Typ (3) Max (2) Units 0.7*VDD V IOUT=3mA Hysteresis (4) CIN Min (2) 0.3*VDD V 0.4 V 0.1*VDD Input Capacitance on all digital pins V 0.5 pF Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No ensured specification of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. Absolute Maximum Ratings indicate junction temperature limits beyond which the device may be permanently degraded, either mechanically or electrically. Limits are 100% production tested at 25C. Limits over the operating temperature range are ensured through correlations using statistical quality control (SQC) method. Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production material. This parameter is specified by design or characterization. Submit Documentation Feedback Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: LMP91002 5 LMP91002 SNIS163A - APRIL 2012 - REVISED MARCH 2013 www.ti.com Timing Characteristics (1) Unless otherwise specified, all limits ensured for TA = 25C, VS= (VDD - AGND), VS= 3.3V and AGND = DGND = 0V, VREF = 2.5V, Internal Zero= 20% VREF. Boldface limits apply at the temperature extremes. Refer to timing diagram in Figure 3. Symbol Parameter Conditions Min Typ Max Units 100 kHz fSCL Clock Frequency 10 tLOW Clock Low Time 4.7 s tHIGH Clock High Time 4.0 s 4.0 s After this period, the first clock pulse is generated tHD;STA Data valid tSU;STA Set-up time for a repeated START condition 4.7 s tHD;DAT Data hold time (2) 0 ns tSU;DAT Data Setup time 250 ns (3) IL 3mA, CL 400pF tf SDA fall time tSU;STO Set-up time for STOP condition 4.0 250 s tBUF Bus free time between a STOP and START condition 4.7 s tVD;DAT Data valid time 3.45 s tVD;ACK Data valid acknowledge time 3.45 s tSP Pulse width of spikes that must be suppressed by the input filter (3) 50 ns t_timeout SCL and SDA Timeout 25 100 ms tEN;START I2C Interface Enabling 600 ns 2 ns tEN;STOP I C Interface Disabling 600 ns tEN;HIGH time between consecutive I2C interface enabling and disabling 600 ns (1) (2) (3) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No ensured specification of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. Absolute Maximum Ratings indicate junction temperature limits beyond which the device may be permanently degraded, either mechanically or electrically. LMP91002 provides an internal 300ns minimum hold time to bridge the undefined region of the falling edge of SCL. This parameter is specified by design or characterization. Timing Diagram MENB 70% 30% tEN;START tEN;HIGH tEN;STOP 70% SDA 30% tf tVD;DAT tLOW tBUF tHD;STA tSP SCL 70% 30% tSU;STA tHD;STA tHIGH tHD;DAT START 1/fSCL tSU;STO tSU;DAT tVD;ACK STOP REPEATED START START Figure 3. I2C Interface Timing Diagram 6 Submit Documentation Feedback Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: LMP91002 LMP91002 www.ti.com SNIS163A - APRIL 2012 - REVISED MARCH 2013 Typical Performance Characteristics Unless otherwise specified, TA = 25C, VS=(VDD - AGND), 2.7V <VS< 3.6V and AGND = DGND =0V, VREF= 2.5V. Input VOS_RW vs. temperature VDD = 2.7V VDD = 3.3V -120 -140 -160 -160 VOS ( V) -140 -180 -200 -220 -180 -200 -220 -240 -240 -260 -260 -280 -280 -300 -300 -50 -25 85C 25C -40C -120 0 25 50 75 TEMPERATURE (C) 100 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 SUPPLY VOLTAGE (V) IWE Step current response (rise) IWE Step current response (fall) IWE 2.75k 3.5k 7k 14k 35k 120k 350k NORMALIZED OUTPUT TIA (200mV/DIV) Figure 5. NORMALIZED OUTPUT (200mV/DIV) Figure 4. IWE(50 A/DIV) VOS ( V) Input VOS_RW vs. VDD -100 IWE 2.75k 3.5k 7k 14k 35k 120k 350k TIME (200 s/DIV) TIME (200 s/DIV) Figure 6. Figure 7. AC PSRR vs. Frequency Supply current vs. temperature (Deep Sleep Mode) 140 1.0 0.9 SUPPLY CURRENT ( A) 130 PSRR (dB) IWE(50 A/DIV) -100 120 110 100 90 VDD = 2.7V VDD = 3.3V 0.8 0.7 0.6 0.5 0.4 0.3 0.2 80 0.1 10 100 1k 10k FREQUENCY (Hz) 100k Figure 8. -50 -25 0 25 50 TEMPERATURE (C) 75 100 Figure 9. Submit Documentation Feedback Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: LMP91002 7 LMP91002 SNIS163A - APRIL 2012 - REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) Unless otherwise specified, TA = 25C, VS=(VDD - AGND), 2.7V <VS< 3.6V and AGND = DGND =0V, VREF= 2.5V. Supply current vs. VDD (Deep Sleep Mode) SUPPLY CURRENT ( A) 0.9 7.50 85C 25C -40C 0.8 0.7 0.6 0.5 0.4 0.3 7.00 6.75 6.50 6.25 6.00 0.2 5.75 0.1 5.50 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 SUPPLY VOLTAGE (V) SUPPLY CURRENT ( A) 7.25 -50 -25 0 25 50 TEMPERATURE (C) Supply current vs. VDD (Standby Mode) Supply current vs. temperature (3-lead amperometric Mode) 11.0 85C 25C -40C VDD = 2.7V VDD = 3.3V VDD = 5V 10.8 6.75 6.50 6.25 6.00 10.6 10.4 10.2 10.0 9.8 9.6 9.4 5.75 9.2 5.50 9.0 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 SUPPLY VOLTAGE (V) -50 -25 0 25 50 75 TEMPERATURE (C) Figure 12. 0.1Hz to 10Hz noise 1.5 85C 25C -40C 1.0 10.6 10.4 EN_RW ( V) SUPPLY CURRENT ( A) 100 Figure 13. Supply current vs. VDD (3-lead amperometric Mode) 10.8 100 Figure 11. 7.00 11.0 75 Figure 10. SUPPLY CURRENT ( A) 7.50 VDD = 2.7V VDD = 3.3V 7.25 SUPPLY CURRENT ( A) 1.0 Supply current vs. temperature (Standby Mode) 10.2 10.0 9.8 9.6 9.4 0.5 0.0 -0.5 -1.0 9.2 9.0 -1.5 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 SUPPLY VOLTAGE (V) Figure 14. 8 0 1 2 3 4 5 6 TIME (s) 7 8 9 10 Figure 15. Submit Documentation Feedback Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: LMP91002 LMP91002 www.ti.com SNIS163A - APRIL 2012 - REVISED MARCH 2013 Typical Performance Characteristics (continued) Unless otherwise specified, TA = 25C, VS=(VDD - AGND), 2.7V <VS< 3.6V and AGND = DGND =0V, VREF= 2.5V. A VOUT step response 100 ppm to 400 ppm CO (CO gas sensor connected to LMP91002) 2.0 LMP91000 1.9 1.8 VOUT (V) 1.7 1.6 1.5 1.4 1.3 1.2 RTIA=35k , Rload=10 , 1.1 1.0 0 25 50 75 100 TIME (s) 125 150 Figure 16. Submit Documentation Feedback Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: LMP91002 9 LMP91002 SNIS163A - APRIL 2012 - REVISED MARCH 2013 www.ti.com Function Description GENERAL The LMP91002 is a programmable AFE for use in micropower chemical sensing applications. The LMP91002 is designed for 3-lead not biased gas sensors and for 2 leads galvanic cell. This device provides all of the functionality for detecting changes in gas concentration based on a delta current at the working electrode. The LMP91002 generates an output voltage proportional to the cell current. Transimpedance gain is user programmable through an I2C compatible interface from 2.75k to 350k making it easy to convert current ranges from 5A to 750A full scale. Optimized for micro-power applications, the LMP91002 AFE works over a voltage range of 2.7V to 3.6 V. The cell voltage is user selectable using the on board programmability. In addition, it is possible to connect an external transimpedance gain resistor. Depending on the configuration, total current consumption for the device can be less than 10A. For power savings, the transimpedance amplifier can be turned off and instead a load impedance equivalent to the TIA's inputs impedance is switched in. VDD VREF SCL LMP91002 3-Lead Electrochemical Cell + CE A1 DIAGNOSTIC I2C INTERFACE AND CONTROL REGISTERS VREF DIVIDER SDA MENB - CE RE RE DGND WE + WE - RLoad VOUT TIA RTIA C1 AGND C2 Figure 17. System Block Diagram POTENTIOSTAT CIRCUITRY The core of the LMP91002 is a potentiostat circuit. It consists of a differential input amplifier used to compare the potential between the working and reference electrodes to a zero bias potential.. The error signal is amplified and applied to the counter electrode (through the Control Amplifier - A1). Any changes in the impedance between the working and reference electrodes will cause a change in the voltage applied to the counter electrode, in order to maintain the constant voltage between working and reference electrodes. A Transimpedance Amplifier connected to the working electrode, is used to provide an output voltage that is proportional to the cell current. The working electrode is held at virtual ground (Internal ground) by the transimpedance amplifier. The potentiostat will compare the reference voltage to the desired bias potential and adjust the voltage at the counter electrode to maintain the proper working-to-reference voltage. Transimpedance amplifier The transimpedance amplifier (TIA in Figure 17) has 7 programmable internal gain resistors. This accommodates the full scale ranges of most existing sensors. Moreover an external gain resistor can be connected to the LMP91002 between C1 and C2 pins. The gain is set through the I2C interface. 10 Submit Documentation Feedback Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: LMP91002 LMP91002 www.ti.com SNIS163A - APRIL 2012 - REVISED MARCH 2013 Control amplifier The control amplifier (A1 op amp in Figure 17) provides initial charge to the sensor. A1 has the capability to drive up to 10mA into the sensor in order to to provide a fast initial conditioning. A1 is able to sink and source current according to the connected gas sensor (reducing or oxidizing gas sensor). It can be powered down to reduce system power consumption. However powering down A1 is not recommended, as it may take a long time for the sensor to recover from this situation. Internal zero The internal Zero is the voltage at the non-inverting pin of the TIA. The internal zero can be programmed to be either 67%, 50% or 20%, of the supply, or the external reference voltage. This provides both sufficient headroom for the counter electrode of the sensor to swing, in case of sudden changes in the gas concentration, and best use of the ADC's full scale input range. The Internal zero is provided through an internal voltage divider (Vref divider box in Figure 17). The divider is programmed through the I2C interface. I2C INTERFACE The I2C compatible interface operates in Standard mode (100kHz). Pull-up resistors or current sources are required on the SCL and SDA pins to pull them high when they are not being driven low. A logic zero is transmitted by driving the output low. A logic high is transmitted by releasing the output and allowing it to be pulled-up externally. The appropriate pull-up resistor values will depend upon the total bus capacitance and operating speed. The LMP91002 comes with a 7 bit bus fixed address: 1001 000. WRITE AND READ OPERATION In order to start any read or write operation with the LMP91002, MENB needs to be set low during the whole communication. Then the master generates a start condition by driving SDA from high to low while SCL is high. The start condition is always followed by a 7-bit slave address and a Read/Write bit. After these 8 bits have been transmitted by the master, SDA is released by the master and the LMP91002 either ACKs or NACKs the address. If the slave address matches, the LMP91002 ACKs the master. If the address doesn't match, the LMP91002 NACKs the master. For a write operation, the master follows the ACK by sending the 8-bit register address pointer. Then the LMP91002 ACKs the transfer by driving SDA low. Next, the master sends the 8-bit data to the LMP91002. Then the LMP91002 ACKs the transfer by driving SDA low. At this point the master should generate a stop condition and optionally set the MENB at logic high level (refer to Figure 20). A read operation requires the LMP91002 address pointer to be set first, also in this case the master needs setting at low logic level the MENB, then the master needs to write to the device and set the address pointer before reading from the desired register. This type of read requires a start, the slave address, a write bit, the address pointer, a Repeated Start (if appropriate), the slave address, and a read bit (refer to Figure 20). Following this sequence, the LMP91002 sends out the 8-bit data of the register. When just one LMP91002 is present on the I2C bus the MENB can be tied to ground (low logic level). Submit Documentation Feedback Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: LMP91002 11 LMP91002 SNIS163A - APRIL 2012 - REVISED MARCH 2013 www.ti.com MENB 1 9 1 9 SCL SDA A6 A5 A4 A3 A2 A1 A0 R/W D7 Ack by LMP91000 Start by Master Frame 1 Serial Bus Address Byte from Master MENB (continued) SCL (continued) 1 SDA (continued) D7 D6 D5 D4 D3 D2 D1 D0 Frame 2 Internal Address Register Byte from Master Ack by LMP91000 9 D6 D5 D4 D3 D2 D1 D0 Ack Stop by by Master LMP91000 Frame 3 Data Byte Figure 18. (a) Register write transaction MENB 1 9 1 9 SCL SDA A6 A5 A4 A3 A2 A1 A0 R/W Start by Master Frame 1 Serial Bus Address Byte from Master D7 Ack by LMP91000 D6 D5 D4 D3 D2 D1 Frame 2 Internal Address Register Byte from Master D0 Ack by LMP91000 Stop by Master Figure 19. (b) Pointer set transaction MENB 1 9 1 9 SCL SDA A6 A5 A4 A3 A2 A1 A0 R/W Start by Master Frame 1 Serial Bus Address Byte from Master D7 Ack by LMP91000 D6 D5 D4 D3 D2 D1 Frame 2 Data Byte from Slave D0 No Ack by Master Stop by Master (c) Register read transaction Figure 20. READ and WRITE transaction TIMEOUT FEATURE The timeout is a safety feature to avoid bus lockup situation. If SCL is stuck low for a time exceeding t_timeout, the LMP91002 will automatically reset its I2C interface. Also, in the case the LMP91002 hangs the SDA for a time exceeding t_timeout, the LMP91002's I2C interface will be reset so that the SDA line will be released. Since the SDA is an open-drain with an external resistor pull-up, this also avoids high power consumption when LMP91002 is driving the bus and the SCL is stopped. 12 Submit Documentation Feedback Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: LMP91002 LMP91002 www.ti.com SNIS163A - APRIL 2012 - REVISED MARCH 2013 REGISTERS The registers are used to configure the LMP91002. If writing to a reserved bit, user must write only 0. Readback value is unspecified and should be discarded. Table 1. Register Map Address Name Power on default Access Lockable? 0x00 STATUS 0x00 Read only N 0x01 R/W N Y 0x01 LOCK 0x02 through 0x09 RESERVED 0x10 TIACN 0x03 R/W 0x11 REFCN 0x20 R/W Y 0x12 MODECN 0x00 R/W N 0x13 through 0xFF RESERVED STATUS -- Status Register (address 0x00) The status bit is an indication of the LMP91002's power-on status. If its readback is "0", the LMP91002 is not ready to accept other I2C commands. Bit Name [7:1] RESERVED 0 STATUS Function Status of Device 0 Not Ready (default) 1 Ready LOCK -- Protection Register (address 0x01) The lock bit enables and disables the writing of the TIACN and the REFCN registers. In order to change the content of the TIACN and the REFCN registers the lock bit needs to be set to "0". Bit Name [7:1] RESERVED 0 LOCK Function Write protection 0 Registers 0x10, 0x11 in write mode 1 Registers 0x10, 0x11 in read only mode (default) TIACN -- TIA Control Register (address 0x10) The parameters in the TIA control register allow the configuration of the transimpedance gain (RTIA). Bit Name [7:5] RESERVED [4:2] TIA_GAIN [1:0] RESERVED Function RESERVED TIA feedback resistance selection 000 External resistance (default) 001 2.75k 010 3.5k 011 7k 100 14k 101 35k 110 120k 111 350k RESERVED Submit Documentation Feedback Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: LMP91002 13 LMP91002 SNIS163A - APRIL 2012 - REVISED MARCH 2013 www.ti.com REFCN -- Reference Control Register (address 0x11) The parameters in the Reference control register allow the configuration of the Internal zero, and Reference source. When the Reference source is external, the reference is provided by a reference voltage connected to the VREF pin. In this condition the Internal Zero is defined as a percentage of VREF voltage instead of the supply voltage. Bit Name 7 REF_SOURCE [6:5] INT_Z [4] RESERVED [3:0] DIAGNOSTIC Function Reference voltage source selection 0 Internal (default) 1 external Internal zero selection (Percentage of the source reference) 00 20% 01 50% (default) 10 67% RESERVED Diagnostic step (Percentage of the source reference) 0000 0% (default) 0001 1% MODECN -- Mode Control Register (address 0x12) The Parameters in the Mode register allow the configuration of the Operation Mode of the LMP91002. Bit Name 7 FET_SHORT Shorting FET feature 0 Disabled (default) 1 Enabled [6:3] RESERVED RESERVED OP_MODE Mode of Operation selection 000 Deep Sleep (default) 010 Standby 011 3-lead amperometric cell [2:0] 14 Function Submit Documentation Feedback Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: LMP91002 LMP91002 www.ti.com SNIS163A - APRIL 2012 - REVISED MARCH 2013 GAS SENSOR INTERFACE The LMP91002 supports both 3-lead and 2-lead gas sensors. Most of the toxic gas sensors are amperometric cells with 3 leads (Counter, Worker and Reference). These leads should be connected to the LMP91002 in the potentiostat topology. 3-lead Amperometric Cell In Potentiostat Configuration Most of the amperometric cell have 3 leads (Counter, Reference and Working electrodes). The interface of the 3lead gas sensor to the LMP91002 is straightforward, the leads of the gas sensor need to be connected to the namesake pins of the LMP91002. The LMP91002 is then configured in 3-lead amperometric cell mode; in this configuration the Control Amplifier (A1) is ON and provides the internal zero voltage and bias in case of biased gas sensor. The transimpedance amplifier (TIA) is ON, it converts the current generated by the gas sensor in a voltage, according to the transimpedance gain: Gain = RTIA If different gains are required, an external resistor can be connected between the pins C1 and C2. In this case the internal feedback resistor should be programmed to "external". The RLoad together with the output capacitance of the gas sensor acts as a low pass filter. VDD VREF SCL LMP91002 3-Lead Electrochemical Cell + CE A1 DIAGNOSTIC VREF DIVIDER I2C INTERFACE AND CONTROL REGISTERS SDA MENB - CE RE RE DGND WE + WE - RLoad VOUT TIA RTIA C1 C2 AGND Figure 21. 3-Lead Amperometric Cell Submit Documentation Feedback Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: LMP91002 15 LMP91002 SNIS163A - APRIL 2012 - REVISED MARCH 2013 www.ti.com 2-lead Galvanic Cell in Potentiostat Configuration When the LMP91002 is interfaced to a galvanic cell (for instance to an Oxygen gas sensor) referred to a reference, the Counter and the Reference pin of the LMP91002 are shorted together and connected to negative electrode of the galvanic cell. The positive electrode of the galvanic cell is then connected to the Working pin of the LMP91002. The LMP91002 is then configured in 3-lead amperometric cell mode (as for amperometric cell). In this configuration the Control Amplifier (A1) is ON and provides the internal zero voltage. The transimpedance amplifier (TIA) is also ON, it converts the current generated by the gas sensor in a voltage, according to the transimpedance gain: Gain= RTIA If different gains are required, an external resistor can be connected between the pins C1 and C2. In this case the internal feedback resistor should be programmed to "external". VDD VREF SCL LMP91002 2-Lead Sensor such as Oxygen CE + A1 VREF DIVIDER DIAGNOSTIC I2C INTERFACE AND CONTROL REGISTERS SDA MENB - VERE NC DGND VE+ WE + VOUT TIA - RLoad RTIA C1 C2 AGND Figure 22. 16 Submit Documentation Feedback Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: LMP91002 LMP91002 www.ti.com SNIS163A - APRIL 2012 - REVISED MARCH 2013 APPLICATION INFORMATION CONNECTION OF MORE THAN ONE LMP91002 TO THE I2C BUS The LMP91002 comes out with a unique and fixed I2C slave address. It is still possible to connect more than one LMP91002 to an I2C bus and select each device using the MENB pin. The MENB simply enables/disables the I2C communication of the LMP91002. When the MENB is at logic level low all the I2C communication is enabled, it is disabled when MENB is at high logic level. In a system based on a controller and more than one LMP91002 connected to the I2C bus, the I2C lines (SDA and SCL) are shared, while the MENB of each LMP91002 is connected to a dedicate GPIO port of the controller. The controller starts communication asserting one out of N MENB signals where N is the total number of LMP91002s connected to the I2C bus. Only the enabled device will acknowledge the I2C commands. After finishing communicating with this particular LMP91002, the microcontroller de-asserts the corresponding MENB and repeats the procedure for other LMP91002s. Figure 23 shows the typical connection when more than one LMP91002 is connected to the I2C bus. SCL GPIO N C SDA LMP91000 MENB SCL GPIO 3 GPIO 2 SDA MENB LMP91000 SDA SCL LMP91000 MENB SCL GPIO 1 SDA MENB LMP91000 SCL SDA Figure 23. More than one LMP91002 on I2C bus SMART GAS SENSOR ANALOG FRONT END The LMP91002 together with an external EEPROM represents the core of a SMART GAS SENSOR AFE. In the EEPROM it is possible to store the information related to the GAS sensor type, calibration and LMP91002's configuration (content of registers 10h, 11h, 12h). At startup the microcontroller reads the EEPROM's content and configures the LMP91002. A typical smart gas sensor AFE is shown in Figure 24. The connection of MENB to the hardware address pin A0 of the EEPROM allows the microcontroller to select the LMP91002 and its corresponding EEPROM when more than one smart gas sensor AFE is present on the I2C bus. Note: only EEPROM I2C addresses with A0=0 should be used in this configuration. Submit Documentation Feedback Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: LMP91002 17 LMP91002 SNIS163A - APRIL 2012 - REVISED MARCH 2013 www.ti.com SCL A0 SDA SCL MENB MENB SCL SDA I2C EEPROM LMP91000 SDA Figure 24. SMART GAS SENSOR AFE SMART GAS SENSOR AFES ON I2C BUS The connection of Smart gas sensor AFEs on the I2C bus is the natural extension of the previous concepts. Also in this case the microcontroller starts communication asserting 1 out of N MENB signals where N is the total number of smart gas sensor AFE connected to the I2C bus. Only one of the devices (either LMP91002 or its corresponding EEPROM) in the smart gas sensor AFE enabled will acknowledge the I2C commands. When the communication with this particular module ends, the microcontroller de-asserts the corresponding MENB and repeats the procedure for other modules. Figure 25 shows the typical connection when several smart gas sensor AFEs are connected to the I2C bus. SMART SENSOR AFE SMART SENSOR AFE GPIO 1 SCL SDA I2C EEPROM A0 SCL SDA LMP91000 MENB SCL SDA I2C EEPROM A0 SDA SCL LMP91000 MENB SDA A0 I2C EEPROM SCL SCL SDA MENB LMP91000 SMART SENSOR AFE GPIO 2 GPIO N C SCL SDA Figure 25. SMART GAS SENSOR AFEs on I2C bus POWER CONSUMPTION The LMP91002 is intended for use in portable devices, so the power consumption is as low as possible in order to ensure a long battery life. The total power consumption for the LMP91002 is below 10A @ 3.3v average over time, (this excludes any current drawn from any pin). A typical usage of the LMP91002 is in a portable gas detector and its power consumption is summarized in Table 2. This has the following assumptions: -Power On only happens a few times over life, so its power consumption can be ignored -Deep Sleep mode is not used -The system is used about 8 hours a day, and 16 hours a day it is in Standby mode. 18 Submit Documentation Feedback Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: LMP91002 LMP91002 www.ti.com SNIS163A - APRIL 2012 - REVISED MARCH 2013 This results in an average power consumption of approximately 7.8 A. This can potentially be further reduced, by using the Standby mode between gas measurements. It may even be possible, depending on the sensor used, to go into deep sleep for some time between measurements, further reducing the average power consumption. Table 2. Power Consumption Scenario Deep Sleep StandBy 3-Lead Amperometric Cell Total Current consumption (A) typical value 0.6 6.5 10 Time ON (%) 0 60 39 Average (A) 0 3.9 3.9 A1 OFF ON ON TIA OFF OFF ON I2C interface ON ON ON 7.8 Notes SENSOR TEST PROCEDURE The LMP91002 has all the hardware and programmability features to implement some test procedures. The purpose of the test procedure is to: a) test proper function of the sensor (status of health) b) test proper connection of the sensor to the LMP91002 The test procedure is very easy. The diagnostic block is user programmable through the digital interface. A step voltage can be applied by the end user to the positive input of A1. As a consequence a transient current will start flowing into the sensor (to charge its internal capacitance) and it will be detected by the TIA. If the current transient is not detected, either a sensor fault or a connection problem is present. The slope and the aspect of the transient response can also be used to detect sensor aging (for example, a cell that is drying and no longer efficiently conducts the current). After it is verified that the sensor is working properly, the LMP91002 needs to be reset to its original configuration. It is not required to observe the full transient in order to contain the testing time. All the needed information are included in the transient slopes (both edges). Figure 26 shows an example test procedure, a Carbon Monoxide sensor is connected to the LMP91002, a 25mVpp pulse is applied between Reference and Working pin. The following procedure shows how to implement the sensor test. Preliminary conditions: The LMP91002 is unlocked and it is in 3-Lead Amperometric Cell Mode 1. Put in the [3:0] bit of the register REFCN (0x11) the 0001b value, leaving the other bit unchanged. This operation will apply a potential (VRW) between RE and WE pin (VRE > VWE), VRW= 1% Source reference 2. Put in the [3:0] bit of the register REFCN (0x11) the 0000b value, leaving the other bit unchanged. This operation will remove the potential (VRW) between RE and WE pin (VRE > VWE), VRW= 0V. LMP91000 OUTPUT TEST PULSE INPUT PULSE (50mV/DIV) OUTPUT VOLTTAGE (500mV/DIV) The width of the pulse is simply the time between the two writing operation. TIME (25ms/DIV) Figure 26. TEST PROCEDURE EXAMPLE Submit Documentation Feedback Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: LMP91002 19 LMP91002 SNIS163A - APRIL 2012 - REVISED MARCH 2013 20 www.ti.com Submit Documentation Feedback Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: LMP91002 LMP91002 www.ti.com SNIS163A - APRIL 2012 - REVISED MARCH 2013 REVISION HISTORY Changes from Original (March 2013) to Revision A * Page Changed layout of National Data Sheet to TI format .......................................................................................................... 19 Submit Documentation Feedback Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: LMP91002 21 PACKAGE OPTION ADDENDUM www.ti.com 27-Mar-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (C) Top-Side Markings (3) (4) LMP91002SD/NOPB ACTIVE WSON NHL 14 1000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR L91002 LMP91002SDE/NOPB ACTIVE WSON NHL 14 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR L91002 LMP91002SDX/NOPB ACTIVE WSON NHL 14 4500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR L91002 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. 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Addendum-Page 1 Samples PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing LMP91002SD/NOPB WSON NHL 14 LMP91002SDE/NOPB WSON NHL LMP91002SDX/NOPB WSON NHL SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 14 250 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 14 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMP91002SD/NOPB WSON NHL 14 1000 213.0 191.0 55.0 LMP91002SDE/NOPB WSON NHL 14 250 213.0 191.0 55.0 LMP91002SDX/NOPB WSON NHL 14 4500 367.0 367.0 35.0 Pack Materials-Page 2 MECHANICAL DATA NHL0014B SDA14B (Rev A) www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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