UPD70F3237M1GJ(A)-UEN - Renesas Electronics

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Old Company Name in Catalogs and Other Documents

On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology

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April 1st, 2010

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Notice

1. All information included in this document is current as of the date this document is issued. Such information, however, is

subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please

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Printed in Europe

Document No. U17830EE1V0UM00

Date Published November 2005-NS CP(K)

User’s Manual

V850ES/Fx2

32-Bit Single-Chip Microcontroller

Hardware

PD703230(A)

PD70(F)3231(A)

PD703230(A1)

PD70(F)3231(A1)

PD703230(A2)

PD70(F)3231(A2)

PD70(F)3232(A)

PD70(F)3233(A)

PD70(F)3232(A1)

PD70(F)3233(A1)

PD70(F)3232(A2)

PD70(F)3233(A2)

PD70(F)3234(A)

PD70(F)3235(A)

PD70F3236(A)

PD70(F)3234(A1)

PD70(F)3235(A1)

PD70F3236(A1)

PD70(F)3234(A2)

PD70(F)3235(A2)

PD70F3236(A2)

PD70F3237(A)

PD70F3238(A)

PD70F3239(A)

PD70F3237(A1)

PD70F3238(A1)

PD70F3239(A1)

PD70F3237(A2)

PD70F3238(A2)

PD70F3239(A2)

2005

User’s Manual U17830EE1V0UM00

[MEMO]

User’s Manual U17830EE1V0UM00 3

VOLTAGE APPLICATION WAVEFORM AT INPUT PIN

Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the

CMOS device stays in the area between V

(MAX) and V

(MIN) due to noise, etc., the device may

malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,

and also in the transition period when the input level passes through the area between V

(MAX) and

(MIN).

HANDLING OF UNUSED INPUT PINS

Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is

possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS

devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed

high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to V

or GND

via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must

be judged separately for each device and according to related specifications governing the device.

PRECAUTION AGAINST ESD

A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and

ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as

much as possible, and quickly dissipate it when it has occurred. Environmental control must be

adequate. When it is dr y, a humidifier should be used. It is recommended to avoid using insulators that

easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static

container, static shielding bag or conductive material. All test and measurement tools including work

benches and floors should be grounded. The operator should be grounded using a wrist strap.

Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for

PW boards with mounted semiconductor devices.

STATUS BEFORE INITIALIZATION

Power-on does not necessarily define the initial status of a MOS device. Immediately after the power

source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does

not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the

reset signal is received. A reset operation must be executed immediately after power-on for devices

with reset functions.

INPUT OF SIGNAL DURING POWER OFF STATE

Do not input signals or an I/O pull-up power supply while the device is not powered. The current

injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and

the abnormal current that passes in the device at this time may cause degradation of internal elements.

Input of signals during the power off state must be judged separately for each device and according to

related specifications governing the device.

NOTES FOR CMOS DEVICES

User’s Manual U17830EE1V0UM00

The information in this document is current as of November, 2005. The information is subject to

change without notice. For actual design-in, refer to the latest publications of NEC Electronics data

sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not

all products and/or types are available in every country. Please check with an NEC Electronics sales

representative for availability and additional information.

No part of this document may be copied or reproduced in any form or by any means without the prior

written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may

appear in this document.

NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual

property rights of third parties by or arising from the use of NEC Electronics products listed in this document

or any other liability arising from the use of such products. No license, express, implied or otherwise, is

granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.

Descriptions of circuits, software and other related information in this document are provided for illustrative

purposes in semiconductor product operation and application examples. The incorporation of these

circuits, software and information in the design of a customer's equipment shall be done under the full

responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by

customers or third parties arising from the use of these circuits, software and information.

While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,

customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To

minimize risks of damage to property or injury (including death) to persons arising from defects in NEC

Electronics products, customers must incorporate sufficient safety measures in their design, such as

redundancy, fire-containment and anti-failure features.

NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and

"Specific".

The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-

designated "quality assurance program" for a specific application. The recommended applications of an NEC

Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of

each NEC Electronics product before using it in a particular application.

The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC

Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications

not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to

determine NEC Electronics' willingness to support a given application.

(Note)

•

M8E 02. 11-1

(1)

(2)

"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its

majority-owned subsidiaries.

"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as

defined above).

Computers, office equipment, communications equipment, test and measurement equipment, audio

and visual equipment, home electronic appliances, machine tools, personal electronic equipment

and industrial robots.

Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster

systems, anti-crime systems, safety equipment and medical equipment (not specifically designed

for life support).

Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life

support systems and medical equipment for life support, etc.

"Standard":

"Special":

"Specific":

User’s Manual U17830EE1V0UM00 5

Regional Information

• Device availability

• Ordering information

• Product release schedule

• Availability of related technical literature

• Development environment specifications (for example, specifications for third-party tools and

components, host computers, power plugs, AC supply voltages, and so forth)

• Network requirements

In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary

from country to country.

[GLOBAL SUPPORT]

http://www.necel.com/en/support/support.html

NEC Electronics America, Inc. (U.S.)

Santa Clara, California

Tel: 408-588-6000

800-366-9782

NEC Electronics Hong Kong Ltd.

Hong Kong

Tel: 2886-9318

NEC Electronics Hong Kong Ltd.

Seoul Branch

Seoul, Korea

Tel: 02-558-3737

NEC Electronics Shanghai Ltd.

Shanghai, P.R. China

Tel: 021-5888-5400

NEC Electronics Taiwan Ltd.

Taipei, Taiwan

Tel: 02-2719-2377

NEC Electronics Singapore Pte. Ltd.

Novena Square, Singapore

Tel: 6253-8311

J04.1

EC Electronics (Europe) GmbH

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Tel: 0211-65030

• Sucursal en España

Madrid, Spain

Tel: 091-504 27 87

Vélizy-Villacoublay, France

Tel: 01-30-67 58 00

• Succursale Française

• Filiale Italiana

Milano, Italy

Tel: 02-66 75 41

• Branch The Netherlands

Eindhoven, The Netherlands

Tel: 040-244 58 45

• Tyskland Filial

Taeby, Sweden

Tel: 08-63 80 820

• United Kingdom Branch

Milton Keynes, UK

Tel: 01908-691-133

Some information contained in this document may vary from country to country. Before using any NEC

Electronics product in your application, pIease contact the NEC Electronics office in your country to

obtain a list of authorized representatives and distributors. They will verify:

User’s Manual U17830EE1V0UM00

PREFACE

Readers For the whole document it shall be agreed that V850ES/Fx2 stands for V850ES/FE2,

V850ES/FF2, V850ES/FG2 and V850ES/FJ2.

This manual is intended for users who wish to understand the functions of the

V850ES/Fx2 and design application systems using these products.

The target products are as follows.

Purpose This manual is intended to give users an understanding of the har dware functions of the

V850ES/Fx2 shown in the Organization below.

Organization This manual is divided into two parts: Hardware (this manual) and Architecture (V850ES

Architecture User’s Manual).

Hardware Architecture

• Pin functions

• CPU function

• On-chip peripheral functions

• Flash memory programming

• Data types

• Register set

• Instruction format and instruction set

• Interrupts and exceptions

• Pipeline operation

How to Read This Manual It is assumed that the readers of this manual have general knowledge in the fields of

electrical engineering, logic circuits, and microcontrollers.

To understand the details of an instructio n function

→ Refer to the V850ES Architecture User’s Manual.

→ The name of the bit whose number is in angle brackets (< >) in the figure of the

→ Regarding the pin functions and Internal peripheral functions of products, please

read and change the products as follows.

→ ・µ PD703230 → µ PD70323 0(A), µ PD703230(A1), µ PD703230(A2)

→ ・µ PD70F3231 → µ PD70(F)3231(A), µ PD70(F)3231(A1), µ PD70(F)3231(A2)

→ ・µ PD70F3232 → µ PD70(F)3232(A), µ PD70(F)3232(A1), µ PD70(F)3232(A2)

→ ・µ PD70F3233 → µ PD70(F)3233(A), µ PD70(F)3233(A1), µ PD70(F)3233(A2)

→ ・µ PD70F3234 → µ PD70(F)3234(A), µ PD70(F)3235(A1), µ PD70(F)3234(A2)

→ ・µ PD70F3235 → µ PD70(F)3235(A), µ PD70(F)3235(A1), µ PD70(F)3235(A2)

→ ・µ PD70F3236 → µ PD70F3236(A), µ PD70F3236(A1), µ PD70F3236(A2)

→ ・µ PD70F3237 → µ PD70F3237(A), µ PD70F3237(A1), µ PD70F3237(A2)

→ ・µ PD70F3238 → µ PD70F3238(A), µ PD70F3238(A1), µ PD70F3238(A2)

→ ・µ PD70F3239 → µ PD70F3239(A), µ PD70F3239(A1), µ PD70F3239(A2)

To understand the overall functions of the V850ES/Fx2

→ Read this manual according to the CONTENTS. The mark shows major revised

points.

User’s Manual U17830EE1V0UM00 7

Conventions Data significance: Higher digits on the left and lower digits on the right

Active low representation: xxx (over score over pin or signal name)

Memory map address: Higher addresses on the top an d lower addresses on the botto m

Note: Footnote for item marked with Note in the text

Caution: Information requiring particular attention

Remark: Supplementary information

Numeric representation: Binary ... xxxx or xxxxB

Decimal ... xxxx

Hexadecimal ... xxxxH

Prefix indicating power of 2 (address space, memory capacity):

K (kilo): 210 = 1,024

M (mega): 220 = 1,0242

G (giga): 230 = 1,0243

Related Documents The related documents indicated in this publi cation may include preliminary versions.

However, preliminary versions are not marked as such.

Documents related to V850ES/Fx2 and sub series (V850ES/FE2, V850ES/FF2,

V850ES/FG2 and V850ES/FJ2)

Document Name Document No.

V850ES Architecture User’s Manual U15943E

V850ES/Fx2 Hard ware User’s Ma nual

U17830EE1V0UM00

V850ES/FE2 Data Sheet

U17834EE1V0DS00

V850ES/FG2 Data Sheet

U17832EE1V0DS00

V850ES/FF2 Data Sheet

U17833EE1V0DS00

V850ES/FJ2 Data Sheet

U17831EE1V0DS00

User’s Manual U17830EE1V0UM00

Documents related to development tools (user’s manuals)

Document Name Document No.

IE-V850ES-G1 (In-Circuit Emulator) U16313E

IE-703239-G1-EM1 (In-Circuit Emulator Option Board) SUD-FT-04-0105

Operation U16053E

C Language U16054E

PM plus U16055E

CA850 Ver. 2.70 C Compiler Package

Assembly Language U16042E

ID850 Ver. 2.51 Integrated Debugger Operation U16217E

Fundamental U13430E

Installation U13410E

RX850 Ver. 3.13 or Later Real-Time OS

Technical U13431E

Fundamental U13773E

Installation U13774E

RX850 Pro Ver. 3.15 Real-Time OS

Technical U13772E

RD850 Ver. 3.01 Task Debugger U13737E

RD850 Pro Ver. 3.01 Task Debugger U13916E

AZ850 Ver. 3.2 System Performance Analyzer U14410E

PG-FP4 Flash Memory Programmer U15260E

IE-V850E1-CD-NW(N-wire) U16647E

QB-V850ESFX2(IECUBE) ZUD-BD-04-0085

SM plus Ver1.00 System Simulation U16906J

User’s Manual U17830EE1V0UM00 9

CONTENTS

CHAPTER 1 INTRODUCTION .................................................................................................................19

1.1 General.......................................................................................................................................19

1.2 Product Development of V850ES/FE2, V850ES/FF2, V850ES/FG2, and V850ES/FJ2.........20

1.3 Features......................................................................................................................................21

1.4 Ordering Information ................................................................................................................23

1.5 Applications...............................................................................................................................26

1.6 Pin Configuration (Top View).................................... ...............................................................27

1.7 Function Block Configuration..................................................................................................33

1.7.1 Internal block diagram...................................................................................................................33

1.7.2 Internal units.................................................................................................................................38

CHAPTER 2 PIN FUNCTIONS................................................................................................................40

2.1 Pin Function List .......................................................................................................................40

2.1.1 V850ES/FE2.................................................................................................................................40

2.1.2 V850ES/FF2.................................................................................................................................45

2.1.3 V850ES/FG2.................................................................................................................................50

2.1.4 V850ES/FJ2..................................................................................................................................55

2.2 Pin Status (V850ES/FJ2)...........................................................................................................63

2.3 Description of Pin Functions ...................................................................................................64

2.3.1 V850ES/FE2.................................................................................................................................64

2.3.2 V850ES/FF2.................................................................................................................................71

2.3.3 V850ES/FG2.................................................................................................................................78

2.3.4 V850ES/FJ2..................................................................................................................................84

2.4 Pin I/O Circuit Types and Recommended Connection of Unused Pins ..............................94

2.4.1 V850ES/FE2.................................................................................................................................94

2.4.2 V850ES/FF2.................................................................................................................................96

2.4.3 V850ES/FG2.................................................................................................................................98

2.4.4 V850ES/FJ2................................................................................................................................100

2.5 Pin I/O Circuits.........................................................................................................................104

CHAPTER 3 CPU FUNCTIONS ............................................................................................................106

3.1 Features....................................................................................................................................106

3.2 CPU Register Set.....................................................................................................................107

3.2.1 Program register set ...................................................................................................................108

3.2.2 System register set.....................................................................................................................109

3.3 Operation Modes.....................................................................................................................115

3.4 Address Space.........................................................................................................................116

3.4.1 CPU address space....................................................................................................................116

3.4.2 Image..........................................................................................................................................117

3.4.3 Wraparound of CPU address space ...........................................................................................118

3.4.4 Memory map...............................................................................................................................119

3.4.5 Areas ..........................................................................................................................................121

3.4.6 Recommended use of address space.........................................................................................134

3.4.7 Peripheral I/O registers...............................................................................................................137

3.4.8 Programmable peripheral I/O register.........................................................................................176

3.4.9 Special registers .........................................................................................................................177

3.4.10 Cautions......................................................................................................................................181

User’s Manual U17830EE1V0UM00

CHAPTER 4 PORT FUNCTIONS......................................................................................................... 184

4.1 Features................................................................................................................................... 184

4.2 Basic Port Configuration ....................................................................................................... 184

4.2.1 Basic port configuration on V850ES/FE2....................................................................................184

4.2.2 Port configuration on V850ES/FF2..............................................................................................185

4.2.3 Port configuration on V850ES/FG2.............................................................................................186

4.2.4 Port configuration on V850ES/FJ2..............................................................................................187

4.3 Port Configuration.................................................................................................................. 188

4.3.1 Port 0 ..........................................................................................................................................194

4.3.2 Port 1 ..........................................................................................................................................201

4.3.3 Port 3 ..........................................................................................................................................206

4.3.4 Port 4 ..........................................................................................................................................216

4.3.5 Port 5 ..........................................................................................................................................219

4.3.6 Port 6 ..........................................................................................................................................226

4.3.7 Port 7 ..........................................................................................................................................236

4.3.8 Port 8 ..........................................................................................................................................239

4.3.9 Port 9 ..........................................................................................................................................244

4.3.10 Port 12 ........................................................................................................................................257

4.3.11 Port CD.......................................................................................................................................259

4.3.12 Port CM.......................................................................................................................................261

4.3.13 Port CS .......................................................................................................................................265

4.3.14 Port CT........................................................................................................................................269

4.3.15 Port DL........................................................................................................................................273

4.3.16 Port pins that function alternately as on-chip debug function......................................................278

4.3.17 Register settings to use port pins as alternate-function pins.......................................................279

4.3.18 Operation of port function............................................................................................................286

4.4 Cautions .................................................................................................................................. 287

4.4.1 Cautions of setting port pins........................................................................................................287

4.4.2 Cautions of bit manilulation instruction for port register (Pn).......................................................288

4.4.3 Cautions on on-chip debug pins..................................................................................................288

4.4.4 Cautions on P05/INTP2/DRST pin..............................................................................................288

CHAPTER 5 BUS CONTROL FUNCTION.......................................................................................... 289

5.1 Features................................................................................................................................... 289

5.2 Bus Control Pins..................................................................................................................... 290

5.2.1 Pin status when internal ROM, internal RAM, or on-chip peripheral I/O is accessed..................290

5.2.2 Pin status in each operation mode..............................................................................................290

5.3 Memory Block Function......................................................................................................... 291

5.3.1 Memory space.............................................................................................................................291

5.3.2 Chip select function.....................................................................................................................292

5.4 Bus Access ............................................................................................................................. 293

5.4.1 Number of clocks for access.......................................................................................................293

5.4.2 Bus size setting function .............................................................................................................293

5.4.3 Access according to bus size......................................................................................................294

5.5 Wait Function.......................................................................................................................... 300

5.5.1 Programmable wait function........................................................................................................300

5.5.2 External wait function..................................................................................................................301

5.5.3 Relationship between programmable wait and external wait.......................................................301

User’s Manual U17830EE1V0UM00 11

5.5.4 Programmable address wait function..........................................................................................302

5.6 Idle State Insertion Function..................................................................................................303

5.7 Bus Hold Function ..................................................................................................................304

5.7.1 Functional outline........................................................................................................................304

5.7.2 Bus hold procedure.....................................................................................................................305

5.7.3 Operation in power save mode...................................................................................................305

5.8 Bus Priority..............................................................................................................................306

5.9 Boundary Operation Conditions...................................... ......................................................306

5.9.1 Program space............................................................................................................................306

5.9.2 Data space..................................................................................................................................306

5.10 Bus Timing...............................................................................................................................307

5.10.1 Multiplexed bus...........................................................................................................................307

CHAPTER 6 CLOCK GENERATION FUNCTION...............................................................................313

6.1 Overview...................................................................................................................................313

6.2 Configuration...........................................................................................................................314

6.3 Control Registers ....................................................................................................................316

6.4 Operation..................................................................................................................................319

6.4.1 Operation of each clock..............................................................................................................319

6.4.2 Clock output function ..................................................................................................................320

6.5 PLL Function............................................................................................................................320

6.5.1 Overview.....................................................................................................................................320

6.5.2 Control registers..........................................................................................................................320

6.5.3 Usage .........................................................................................................................................323

CHAPTER 7 16-BIT TIMER/EVENT COUNTER P .............................................................................324

7.1 Features....................................................................................................................................324

7.2 Functional Outline...................................................................................................................324

7.3 Configuration...........................................................................................................................325

7.4 Control Registers ....................................................................................................................330

7.5 Operation..................................................................................................................................339

7.5.1 Anytime write and reload ............................................................................................................339

7.5.2 Interval timer mode (TPnMD2 to TPnMD0 = 000).......................................................................344

7.5.3 External event count mode (TPnMD2 to TPnMD0 = 001)...........................................................347

7.5.4 External trigger pulse mode (TPnMD2 to TPnMD0 = 010)..........................................................351

7.5.5 One-shot pulse mode (TPnMD2 to TPnMD0 = 011)...................................................................354

7.5.6 PWM mode (TPnMD2 to TPnMD0 = 100)...................................................................................357

7.5.7 Free-running mode (TPnMD2 to TPnMD0 = 101).......................................................................362

7.5.8 Pulse width measurement mode (TPnMD2 to TPnMD0 = 110)..................................................367

7.6 Timer Synchronized Operation Function..............................................................................369

7.7 Selector Function....................................................................................................................373

7.8 Cautions ...................................................................................................................................377

CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q.............................................................................380

8.1 Features....................................................................................................................................380

8.2 Functional Outline...................................................................................................................380

8.3 Configuration...........................................................................................................................381

8.4 Control Registers ....................................................................................................................388

User’s Manual U17830EE1V0UM00

8.5 Operation................................................................................................................................. 398

8.5.1 Anytime write and reload.............................................................................................................398

8.5.2 Interval timer mode (TQnMD2 to TQnMD0 = 000)......................................................................403

8.5.3 External event count mode (TQnMD2 to TQnMD0 = 001)..........................................................406

8.5.4 External trigger pulse mode (TQnMD2 to TQnMD0 = 010).........................................................410

8.5.5 One-shot pulse mode (TQnMD2 to TQnMD0 = 011)...................................................................413

8.5.6 PWM mode (TQnMD2 to TQnMD0 = 100)..................................................................................416

8.5.7 Free-running mode (TQnMD2 to TQnMD0 = 101) ...................................................................... 42"

8.5.8 Pulse width measurement mode (TQnMD2 to TQnMD0 = 110)..................................................422

8.5.9 Triangular wave PWM mode (TQnMD2 to TQnMD0 = 111)........................................................431

8.6 Timer Synchronized Operation Function............................................................................. 433

8.7 Cautions .................................................................................................................................. 437

CHAPTER 9 16-BIT INTERVAL TIMER M......................................................................................... 440

9.1 Features................................................................................................................................... 440

9.2 Configuration .......................................................................................................................... 441

9.3 Control Register...................................................................................................................... 443

9.4 Operation................................................................................................................................. 445

9.4.1 Interval timer mode .....................................................................................................................445

9.5 Cautions .................................................................................................................................. 446

CHAPTER 10 WATCH TIMER FUNCTIONS ...................................................................................... 447

10.1 Functions................................................................................................................................. 447

10.2 Configuration .......................................................................................................................... 449

10.3 Control Registers.................................................................................................................... 450

10.4 Operation................................................................................................................................. 452

10.4.1 Operation as watch timer ............................................................................................................452

10.4.2 Operation as interval timer..........................................................................................................452

10.4.3 Cautions......................................................................................................................................453

10.5 Prescaler 3............................................................................................................................... 454

10.5.1 Control registers..........................................................................................................................454

10.5.2 Generation of watch timer count clock........................................................................................455

CHAPTER 11 FUNCTIONS OF WATCHDOG TIMER 2................................................................... 456

11.1 Functions................................................................................................................................. 456

11.2 Configuration .......................................................................................................................... 457

11.3 Control Registers.................................................................................................................... 457

CHAPTER 12 A/D CONVERTER ......................................................................................................... 461

12.1 Overview.................................................................................................................................. 461

12.2 Functions................................................................................................................................. 461

12.3 Configuration .......................................................................................................................... 463

12.4 Control Registers.................................................................................................................... 464

12.5 Operation................................................................................................................................. 473

12.5.1 Basic operation ...........................................................................................................................473

12.5.2 Trigger mode...............................................................................................................................475

12.5.3 Operation mode ..........................................................................................................................477

12.5.4 Power-fail compare mode ...........................................................................................................481

User’s Manual U17830EE1V0UM00 13

12.6 Cautions ...................................................................................................................................486

12.7 How to Read A/D Converter Characteristics Table..............................................................491

CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE A (UARTA)..............................................495

13.1 Features....................................................................................................................................496

13.2 Configuration...........................................................................................................................497

13.2.1 Control registers..........................................................................................................................499

13.3 Control Registers ....................................................................................................................500

13.4 Interrupt Request Signals.......................................................................................................508

13.5 Operation..................................................................................................................................509

13.5.1 Data format.................................................................................................................................509

13.5.2 SBF transmission/reception format.............................................................................................510

13.5.3 SBF transmission........................................................................................................................512

13.5.4 SBF reception.............................................................................................................................513

13.5.5 UART transmission.....................................................................................................................514

13.5.6 Procedure of continuous transmission........................................................................................515

13.5.7 UART reception ..........................................................................................................................517

13.5.8 Reception errors .........................................................................................................................518

13.5.9 Types and operation of parity......................................................................................................520

13.5.10 Noise filter of receive data..........................................................................................................521

13.6 Dedicated Baud Rate Generator............................................................................................522

13.7 Cautions ...................................................................................................................................528

CHAPTER 14 3-WIRE SERIAL INTERFACE (CSIB).........................................................................529

14.1 Features....................................................................................................................................529

14.2 Configuration...........................................................................................................................530

14.3 Control Registers ....................................................................................................................533

14.4 Transfer Data Length Change Function................................................................................538

14.5 Interrupt Request Signals.......................................................................................................539

14.6 Operation..................................................................................................................................540

14.6.1 Single transfer mode (master mode, transmission/reception mode)...........................................540

14.6.2 Single transfer mode (master mode, reception mode)................................................................541

14.6.3 Continuous mode (master mode, transmission/reception mode)................................................542

14.6.4 Continuous mode (master mode, reception mode).....................................................................543

14.6.5 Continuous reception mode (error).............................................................................................544

14.6.6 Continuous mode (slave mode, transmission/reception mode)...................................................545

14.6.7 Continuous mode (slave mode, reception mode)........................................................................546

14.6.8 Clock timing................................................................................................................................547

14.7 Output Pins..............................................................................................................................549

14.8 Operation Flow ........................................................................................................................550

14.9 Prescaler 3 ...............................................................................................................................556

14.9.1 Control registers of prescaler 3...................................................................................................556

14.9.2 Generation of count clock...........................................................................................................557

14.10 Cautions ...................................................................................................................................558

CHAPTER 15 CAN CONTROLLER......................................................................................................559

15.1 Overview...................................................................................................................................559

15.1.1 Features......................................................................................................................................559

User’s Manual U17830EE1V0UM00

15.1.2 Overview of Functions.................................................................................................................560

15.1.3 Configuration...............................................................................................................................561

15.2 CAN Protocol .......................................................................................................................... 562

15.2.1 Frame format...............................................................................................................................562

15.2.2 Frame types................................................................................................................................563

15.2.3 Data frame and remote frame.....................................................................................................563

15.2.4 Error frame..................................................................................................................................571

15.2.5 Overload frame ...........................................................................................................................572

15.3 Functions................................................................................................................................. 573

15.3.1 Determining bus priority ..............................................................................................................573

15.3.2 Bit stuffing...................................................................................................................................573

15.3.3 Multi masters...............................................................................................................................572

15.3.4 Multi cast.....................................................................................................................................573

15.3.5 CAN sleep mode/CAN stop mode function .................................................................................574

15.3.6 Error control function...................................................................................................................574

15.3.7 Baud rate control function ...........................................................................................................581

15.4 Connection with Target System............................................................................................ 585

15.5 Internal Registers of CAN controller .................................................................................... 586

15.5.1 CAN controller configuration .......................................................................................................586

15.5.2 Register access type...................................................................................................................588

15.5.3 Register bit configuration.............................................................................................................656

15.6 Control Registers.................................................................................................................... 660

15.7 Bit Set/Clear Function............................................................................................................ 694

15.8 CAN Controller Initialization.................................................................................................. 696

15.8.1 Initialization of CAN module........................................................................................................696

15.8.2 Initialization of message buffer....................................................................................................696

15.8.3 Redefinition of message buffer....................................................................................................695

15.8.4 Transition from initialization mode to operation mode.................................................................697

15.8.5 Resetting error counter CnERC of CAN module.........................................................................698

15.9 Message Reception................................................................................................................ 699

15.9.1 Message reception......................................................................................................................699

15.9.2 Receive history list function.........................................................................................................700

15.9.3 Mask function..............................................................................................................................702

15.9.4 Multi buffer receive block function...............................................................................................704

15.9.5 Remote frame reception..............................................................................................................705

15.10 Message Transmission.......................................................................................................... 706

15.10.1 Message transmission ................................................................................................................706

15.10.2 Transmit history list function........................................................................................................708

15.10.3 Automatic block transmission (ABT) ...........................................................................................710

15.10.4 Transmission abort process........................................................................................................712

15.10.5 Remote frame transmission ........................................................................................................712

15.11 Power Saving Modes.............................................................................................................. 713

15.11.1 CAN sleep mode.........................................................................................................................713

15.11.2 CAN stop mode...........................................................................................................................714

15.11.3 Example of using power saving modes.......................................................................................715

15.12 Interrupt Function................................................................................................................... 716

15.13 Diagnosis Functions and Special Operational Modes........................................................ 717

15.13.1 Receive-only mode .....................................................................................................................717

User’s Manual U17830EE1V0UM00 15

15.13.2 Single-shot mode........................................................................................................................718

15.13.3 Self-test mode.............................................................................................................................719

15.14 Time Stamp Function..............................................................................................................720

15.14.1 Time stamp function....................................................................................................................720

15.15 Baud Rate Settings .................................................................................................................722

15.15.1 Bit rate setting conditions............................................................................................................722

15.15.2 Representative examples of baud rate settings..........................................................................726

15.16 Operation of CAN Controller..................................................................................................730

CHAPTER 16 DMA CONTROLLER (DMAC)......................................................................................755

16.1 Features....................................................................................................................................755

16.2 Configuration...........................................................................................................................756

16.3 Registers..................................................................................................................................757

16.4 DMA Bus States.......................................................................................................................766

16.4.1 Types of bus states.....................................................................................................................766

16.4.2 DMAC bus cycle state transition.................................................................................................767

16.5 Transfer Targets......................................................................................................................768

16.6 Transfer Modes........................................................................................................................768

16.7 Transfer Types.........................................................................................................................769

16.8 DMA Channel Priorities ..........................................................................................................770

16.9 Time Related to DMA Transfer...............................................................................................770

16.10 DMA Transfer Start Factors....................................................................................................771

16.11 DMA Abort Factors..................................................................................................................772

16.12 End of DMA Transfer...............................................................................................................772

16.13 Operation Timing.....................................................................................................................772

16.14 Cautions ...................................................................................................................................777

CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION ...............................................782

17.1 Features....................................................................................................................................782

17.2 Non-Maskable Interrupts........................................................................................................787

17.2.1 Non-maskable interrupt request signal .......................................................................................787

17.2.2 Operation....................................................................................................................................789

17.2.3 Restore.......................................................................................................................................790

17.2.4 NP flag........................................................................................................................................792

17.2.5 Eliminating noise on NMI pin.......................................................................................................792

17.2.6 Function to detect edge of NMI pin.............................................................................................792

17.3 Maskable Interrupts ................................................................................................................794

17.3.1 Operation....................................................................................................................................794

17.3.2 Restore.......................................................................................................................................796

17.3.3 Priorities of maskable interrupts..................................................................................................797

17.3.4 Interrupt control registers (xxICn)................................................................................................801

17.3.5 Interrupt mask registers 0 to 5 (IMR0 to IMR4, IMR5L) ..............................................................804

17.3.6 In-service priority register (ISPR)................................................................................................806

17.3.7 ID flag .........................................................................................................................................807

17.3.8 Watchdog timer mode register 2 (WDTM2) ................................................................................807

17.3.9 Eliminating noise on INTP0 to INTP7 pins..................................................................................808

17.4 Software Exceptions...............................................................................................................818

17.4.1 Operation....................................................................................................................................818

User’s Manual U17830EE1V0UM00

17.4.2 Restore .......................................................................................................................................819

17.4.3 EP flag ........................................................................................................................................820

17.5 Exception Trap........................................................................................................................ 821

17.5.1 Illegal opcode definition...............................................................................................................821

17.5.2 Debug trap ..................................................................................................................................823

17.6 Interrupt Acknowledgment Time of CPU ............................................................................. 825

17.7 Periods in Which Interrupts Are Not Acknowledged by CPU............................................ 826

CHAPTER 18 KEY INTERRUPT FUNCTION ..................................................................................... 827

18.1 Function................................................................................................................................... 827

18.2 Control Register...................................................................................................................... 828

CHAPTER 19 STANDBY FUNCTION.................................................................................................. 829

19.1 Overview.................................................................................................................................. 829

19.2 HALT Mode.............................................................................................................................. 834

19.2.1 Setting and operation status........................................................................................................834

19.2.2 Releasing HALT mode................................................................................................................834

19.3 IDLE1 Mode ............................................................................................................................. 836

19.3.1 Setting and operation status........................................................................................................836

19.3.2 Releasing IDLE1 mode ...............................................................................................................836

19.4 IDLE2 Mode ............................................................................................................................. 838

19.4.1 Setting and operation status........................................................................................................838

19.4.2 Releasing IDLE2 mode ...............................................................................................................838

19.4.3 Securing setup time after release of IDLE2 mode.......................................................................840

19.5 Software STOP Mode ............................................................................................................. 841

19.5.1 Setting and operation status........................................................................................................841

19.5.2 Releasing software STOP mode.................................................................................................842

19.5.3 Securing setup time after release of software STOP mode.........................................................844

19.6 Subclock Operation Mode ..................................................................................................... 845

19.6.1 Setting and operation status........................................................................................................845

19.6.2 Releasing subclock operation mode............................................................................................845

19.7 Sub-IDLE Mode ....................................................................................................................... 847

19.7.1 Setting and operation status........................................................................................................847

19.7.2 Releasing sub-IDLE mode ..........................................................................................................847

19.8 Control Registers.................................................................................................................... 849

CHAPTER 20 RESET FUNCTION ....................................................................................................... 852

20.1 Overview.................................................................................................................................. 852

20.2 Register to Check Reset Source........................................................................................... 853

20.3 Operation................................................................................................................................. 854

20.3.1 Reset operation by RESET pin ..................................................................................................854

20.3.2 Reset operation by WDT2RES signal .........................................................................................856

CHAPTER 21 CLOCK MONITOR ........................................................................................................ 859

21.1 Function of Clock Monitor..................................................................................................... 859

21.2 Configuration of Clock Monitor............................................................................................. 859

21.3 Register Controlling Clock Monitor...................................................................................... 860

21.4 Operation of Clock Monitor ................................................................................................... 861

User’s Manual U17830EE1V0UM00 17

CHAPTER 22 POWER-ON CLEAR CIRCUIT .....................................................................................864

22.1 Functions of Power-on Clear Circuit.....................................................................................864

22.2 Configuration of Power-on Clear Circuit ..............................................................................865

22.3 Operation of Power-on Clear Circuit.....................................................................................865

CHAPTER 23 LOW-VOLTAGE DETECTOR........................................................................................866

23.1 Functions of Low-Voltage Detector.......................................................................................866

23.2 Configuration of Low-Voltage Detector................................................................................866

23.3 Registers Controlling Low-Voltage Detector .......................................................................867

23.4 Operation of Low-Voltage Detector.......................................................................................870

23.4.1 To use for internal reset signal....................................................................................................870

23.4.2 To use for interrupt......................................................................................................................871

23.5 RAM Retention Voltage Detection Operation.......................................................................872

CHAPTER 24 REGULATOR..................................................................................................................873

24.1 Overview...................................................................................................................................873

24.2 Operation..................................................................................................................................873

CHAPTER 25 FLASH MEMORY...........................................................................................................875

25.1 Features....................................................................................................................................875

25.1.1 Erasure unit ................................................................................................................................876

25.1.2 Functional outline........................................................................................................................877

25.2 Writing with Flash programmer.............................................................................................879

25.3 Programming Environment....................................................................................................879

25.4 Communication Mode.............................................................................................................880

25.5 Pin Connection........................................................................................................................885

25.5.1 FLMD0 pin..................................................................................................................................885

25.5.2 FLMD1 pin..................................................................................................................................886

25.5.3 Serial interface pins ....................................................................................................................886

25.5.4 RESET pin..................................................................................................................................888

25.5.5 Port pins (including NMI).............................................................................................................888

25.5.6 Other signal pins.........................................................................................................................888

25.5.7 Power supply ..............................................................................................................................888

25.6 Programming Method .............................................................................................................889

25.6.1 Flash memory control .................................................................................................................889

25.6.2 Selecting communication mode..................................................................................................890

25.6.3 Communication commands.........................................................................................................891

25.7 Rewriting by Self-Programming.............................................................................................892

25.7.1 Overview.....................................................................................................................................892

25.7.2 Features......................................................................................................................................893

25.7.3 Standard self-programming flow.................................................................................................894

25.7.4 Flash functions............................................................................................................................895

25.7.5 Pin processing ............................................................................................................................895

25.7.6 Internal resources used ..............................................................................................................896

CHAPTER 26 OPTION FUNCTION ......................................................................................................897

26.1 Mask Options...........................................................................................................................897

User’s Manual U17830EE1V0UM00

CHAPTER 27 ON-CHIP DEBUG FUNCTION (ON-CHIP DEBUG UNIT)........................................ 899

27.1 Functional Outline.................................................................................................................. 899

27.1.1 Type of on-chip debug unit..........................................................................................................899

27.1.2 Debug functions..........................................................................................................................899

27.2 Connection Circuit Example.................................................................................................. 901

27.3 Interface Signals..................................................................................................................... 901

27.4 Register ................................................................................................................................... 903

27.5 Operation................................................................................................................................. 904

27.6 ROM Security Function.......................................................................................................... 906

27.6.1 Security ID ..................................................................................................................................906

27.6.2 Setting.........................................................................................................................................907

27.7 Connection to N-Wire Emulator ............................................................................................ 909

27.7.1 KEL connector.............................................................................................................................909

27.8 Cautions .................................................................................................................................. 913

APPENDIX A REGISTER INDEX......................................................................................................... 914

APPENDIX B INSTRUCTION SET LIST............................................................................................. 927

B.1 Conventions............................................................................................................................ 927

B.2 Instruction Set (in Alphabetical Order) ................................................................................ 930

B.3 Description of Operating Precautions.................................................................................. 937

APPENDIX C REVISION HISTORY ..................................................................................................... 942

User’s Manual U17830EE1V0UM00 19

CHAPTER 1 INTRODUCTION

The V850ES/FE2, V850ES/FF2, V850ES/FG2, V850ES/FJ2 are products of NEC Electronics’ V850 Series of

single-chip microcontrollers for real-time control.

1.1 General

The V850ES/FE2, V850ES/FF2, V850ES/FG2, V850ES/FJ2 are 32-bit single-chip microcontroller that include the

V850ES CPU core and inte grate peripheral functions such as timers/counters, serial int erfaces, an d an A/D converter.

These microcontrollers also incorporate a CAN (Controller Area Network) as an automotive LAN.

In addition to highly real-time responsive, 1-clock-pitch basic instructions, this microcontroller have instructions

ideal for digital servo applications, such as multiplication instructions using a hardware multiplier, sum-of-products

operation instructions, and bit manipulation instructions. This microcontroller can also realize a real-time control

system that is highly cost effective and can be used in automotive instrumentation fields.

V850ES/FE2, V850ES/FF2, V850ES/FG2, are models of the V850ES/FJ2 with reduced I/O, timer/counter, and

serial interface functions (See 1.2 Product Development of V850ES/FE2, V850ES/FF2, V850ES/FG2, and

V850ES/FJ2 and Table 1-1. Functional Outline of V850ES/FE2, V850ES/FF2, V850ES/FG2, and V850ES/FJ2).

CHAPTER 1 INTRODUCTION

User’s Manual U17830EE1V0UM00

1.2 Product Development of V850ES/FE2, V850ES/FF2, V850ES/FG2, and V850ES/FJ2

PD70F3239

PD70F3237

V850ES/FJ2

PD70F3233

PD703233

V850ES/FF2

PD70F3231

PD703231

V850ES/FE2

144-pin plastic LQFP (fine pitch) (20 X 20)

Flash memory: 512 KB, RAM: 20 KB

Flash memory: 256 KB, RAM: 12 KB

Mask ROM: 256 KB, RAM: 12 KB

Flash memory: 128 KB, RAM: 6 KB

Mask ROM: 128 KB, RAM: 6 KB

80-pin plastic TQFP (fine pitch) (12 X 12)

64-pin plastic LQFP (fine pitch) (10 X 10)

PD703232

Mask ROM: 128 KB, RAM: 6 KB

PD703230

Mask ROM: 64 KB, RAM: 4 KB

PD70F3236

PD70F3235

PD703235

V850ES/FG2

Flash memory: 256 KB, RAM: 12 KB

Mask ROM: 256 KB, RAM: 12 KB

Flash memory: 384 KB, RAM: 16 KB

100-pin plastic LQFP (fine pitch) (14 X 14)

PD703234

Mask ROM: 128 KB, RAM: 6 KB

PD70F3234

Flash memory: 128 KB, RAM: 6 KB

PD70F3232

Flash memory: 128 KB, RAM: 12 KB

PD70F3238

Flash memory: 376 KB, RAM: 20 KB

CHAPTER 1 INTRODUCTION

User’s Manual U17830EE1V0UM00 21

1.3 Features

Number of instructions: 83

Minimum instruction exec ution time: 50 ns (main clock (fXX) = 20 MHz)

General-purpose registers: 32 bits × 32

Power-on clear function

Low-voltage detection function

Ring-OSC: 200 kHz (TYP.)

Inter nal memory RAM: 4/6/8/12/16/20 KB (see Table 1-1)

Flash memory: 64/128/2 56/376/384/512KB (see Table 1-1)

Interrupts/exceptions

Non-maskable interrupts (see Table 1-1)

Maskable interrupts (see Table 1-1)

Software exceptions： 2 sources

Exception trap： 1 sources

I/O lines I/O ports: 128

Timer/counters

16-bit interval timer M (TMM): 1 ch

16-bit timer/event counter P (TMP): 4 ch

16-bit timer/event counter Q (TMQ): 1 to 3 ch (see Table 1-1)

Watch timer: 1 ch

Watchdog time r 2: 1 ch

Serial interface (SIO)

Asynchronous serial interface A (UART): 2 to 4 (see Table 1-1)

3-wire variable-length serial interface B (CSIB): 2 to 3ch (see Table 1-1)

CAN controller: 1 to 4 ch (see Table 1-1)

A/D converter 10-bit resolution: 10 to 24 ch (see Table 1-1)

Clock generator Main clock/subclock operation

CPU clock in seven steps (fXX, fXX/2, fXX/4, fXX/8, fXX/16, fXX/32, fXT)

Clock-through mode/PLL mode selectable

Inter nal oscillator: 200 kHz（TYP.）

Power save function HALT/IDLE1/IDLE2/software STOP/subclock/sub-IDLE modes

Package 64-pin plastic LQFP (fine pitch) (10 × 10)

80-pin plastic TQFP (fine pitch) (12 × 12)

100-pin plastic LQFP (fine pitch) (14 × 14)

144-pin plastic LQFP (fine pitch) (20 × 20)

CHAPTER 1 INTRODUCTION

User’s Manual U17830EE1V0UM00

Table 1-1. Functional Outline of V850ES/FE2, V850ES/FF2, V850ES/FG2, and V850ES/FJ2

Series name V850ES/FE2 V850ES/FF2 V850ES/FG2 V850ES/FJ2

Part number

PD70(F)3230

PD70(F)3231

PD703232

PD70F3232

PD70(F)3233

PD70(F)3234

PD70(F)3235

PD70(F)3236

PD70F)237

PD70(3238

PD70F3239

Flash (bytes) 64K 128

K 128

K 256

K 128K 256K 384K 256K 376K 512K

Mask ROM

(bytes) 64K 128K 128K 256K 128K 256K - - - -

Internal

memory

RAM (bytes) 4K 6K 6K 12K 12K 6K 12K 16K 12K 20K 20K

DMA None None Provided Provided

Main

(internal) 20 MHz

max. 20 MHz max. 20 MHz max. 20 MHz max.

Ring-OSC 200 kHz typ. 200 kHz typ. 200 kHz typ. 200 kHz typ.

Operating

clock

Subclock RC or crystal RC or crystal RC or crystal RC or crystal

I/O ports 51 67 84 128

A/D converter 10 bits × 10

ch 10 bits × 12 ch 10 bits × 16 ch 10 bits × 24 ch

Timers TMQ 1 ch 1 ch 2 ch 3 ch

TMP 4 ch 4 ch 4 ch 4 ch

TMM 1 ch 1 ch 1 ch 1 ch

WDT2 1 ch 1 ch 1 ch 1 ch

Watch 1 ch 1 ch 1 ch 1 ch

CSI 2 ch 2 ch 2 ch 3 ch

UART 2 ch 2 ch 3 ch 3 ch 4 ch

Serial

interfaces

CAN 1 ch 1 ch 2 ch 2 ch 4 ch

External 8 ch 8 ch 11 ch 15 ch

Internal 35 ch 35 ch 50 ch 57 ch 67 ch

Interrupts

NMI 1 ch 1 ch 1 ch 1 ch

Key return

input 8 ch 8 ch 8 ch 8 ch

Clock monitor

function Provided Provided Provided Provided

POC/LVI

function Provided Provided Provided Provided

Clock output

function Provided Provided Provided Provided

PCL output

function Provided Provided Provided Provided

Other

functions

On-chip

debug

function

Provided

(Note) Prov ided

(Note) Provided

(Note)

External memory interface None None None Provided

Operating voltage 3.5 V to 5.5

V 3.5 V to 5.5 V 3.5 V to 5.5 V 3.5 V to 5.5 V

Package 64-pin LQFP 80-pin TQFP 100-pin LQFP 144-pin LQFP

Note On Flash version only (µPD70F323x)

CHAPTER 1 INTRODUCTION

User’s Manual U17830EE1V0UM00 23

1.4 Ordering Information

• V850ES/FJ2

Part Number Note Package On-Chip Flash

Memory

CAN Buffer Quality Grade Remark

PD70F3237M1GJ(A)-UEN

PD70F3237M1GJ(A1)-UEN

PD70F3237M1GJ(A2)-UEN

Without power-on clear

function

PD70F3237M2GJ(A)-UEN

PD70F3237M2GJ(A1)-UEN

PD70F3237M2GJ(A2)-UEN

256 KB

With power-on clear

function

PD70F3238M1GJ(A)-UEN

PD70F3238M1GJ(A1)-UEN

PD70F3238M1GJ(A2)-UEN

Without power-on clear

function

PD70F3238M2GJ(A)-UEN

PD70F3238M2GJ(A1)-UEN

PD70F3238M2GJ(A2)-UEN

376 KB

With power-on clear

function

PD70F3239M1GJ(A)-UEN

PD70F3239M1GJ(A1)-UEN

PD70F3239M1GJ(A2)-UEN

Without power-on clear

function

PD70F3239M2GJ(A)-UEN

PD70F3239M2GJ(A1)-UEN

PD70F3239M2GJ(A2)-UEN

144-pin plastic

LQFP

(fine pitch)

(20 × 20)

512 KB

32 buf f er/ch Special

With power-on clear

function

Note: The operating ambient temperature of each quality grades is as follows.

(A)：－40 to +85℃，(A1)：－40 to +110℃，(A2)：－40 to +125℃

Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by

NEC Electronics Corporation to know the specification of the quality grade on the device and its

recommended applications.

CHAPTER 1 INTRODUCTION

User’s Manual U17830EE1V0UM00

• V850ES/FG2

Part Number Package Internal Memory

Number of CAN

Buffers

Quality

Grade

Remark

PD703234GC(A)-xxx-8EA

100-pin plastic LQFP

128 KB

32 buffers/ch

Special

Note

−

PD703234GC(A1)-xxx-8EA

(fine pitch) (14

14)

(Mask ROM)

PD703234GC(A2)-xxx-8EA

PD703235GC(A)-xxx-8EA 256 KB

PD703235GC(A1)-xxx-8EA (Mask ROM)

PD703235GC(A2)-xxx-8EA

PD70F3234M1GC(A)-8EA 128 KB

Without power-on clear function

PD70F3234M1GC(A1)-8EA

(Flash Memory)

PD70F3234M1GC(A2)-8EA

PD70F3234M2GC(A)-8EA

With power-on clear function

PD70F3234M2GC(A1)-8EA

PD70F3234M2GC(A2)-8EA

PD70F3235M1GC(A)-8EA 256 KB

Without power-on clear function

PD70F3235M1GC(A1)-8EA

(Flash Memory)

PD70F3235M1GC(A2)-8EA

PD70F3235M2GC(A)-8EA With power-on clear function

PD70F3235M2GC(A1)-8EA

PD70F3235M2GC(A2)-8EA

PD70F3236M1GC(A)-8EA 384 KB

Without power-on clear function

PD70F3236M1GC(A1)-8EA

(Flash Memory)

PD70F3236M1GC(A2)-8EA

PD70F3236M2GC(A)-8EA With power-on clear function

PD70F3236M2GC(A1)-8EA

PD70F3236M2GC(A2)-8EA

Note: The operating ambie nt temperature of each quality grades is as follows.

(A)：－40 to +85℃，(A1)：－40 to +110℃，(A2)：－40 to +125℃

Remark xxx is ROM code number.

Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by

NEC Electronics Corporation to know the specification of the quality grade on the device and its

recommended applications.

CHAPTER 1 INTRODUCTION

User’s Manual U17830EE1V0UM00 25

• V850ES/FF2

Part Number Package Internal Memory

Number of CAN

Buffers

Quality

Grade

Remark

PD703232GK(A)-xxx-9EU

80-pin plastic TQFP

128 KB

32 buffers/ch

Special

Note

−

PD703232GK(A1)-xxx-9EU

(fine pitch) (12

12)

(Mask ROM)

PD703232GK(A2)-xxx-9EU

PD703233GK(A)-xxx-9EU 256 KB

PD703233GK(A1)-xxx-9EU (Mask ROM)

PD703233GK(A2)-xxx-9EU

PD70F3232M1GK(A)-9EU 128 KB

Without power-on clear function

PD70F3232M1GK(A1)-9EU

(Flash Memory)

PD70F3232M1GK(A2)-9EU

PD70F3232M2GK(A)-9EU

With power-on clear function

PD70F3232M2GK(A1)-9EU

PD70F3232M2GK(A2)-9EU

PD70F3233M1GK(A)-9EU 256 KB

Without power-on clear function

PD70F3233M1GK(A1)-9EU

(Flash Memory)

PD70F3233M1GK(A2)-9EU

PD70F3233M2GK(A)-9EU With power-on clear function

PD70F3233M2GK(A1)-9EU

PD70F3233M2GK(A2)-9EU

Note: The operating ambient temperature of each quality grades is as follows.

(A)：－40 to +85℃，(A1)：－40 to +110℃，(A2)：－40 to +125℃

Remark xxx is ROM code number.

Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by

NEC Electronics Corporation to know the specification of the quality grade on the device and its

recommended applications.

CHAPTER 1 INTRODUCTION

User’s Manual U17830EE1V0UM00

• V850ES/FE2

Part Number Package Internal Memory

Number of CAN

Buffers

Quality

Grade

Remark

PD703230GB(A)-xxx-8EA

64-pin plastic LQFP

64 KB

32 buffers/ch

Special

Note

−

PD703230GB(A1)-xxx-8EA

(fine pitch) (10

10)

(Mask ROM)

PD703230GB(A2)-xxx-8EA

PD703231GB(A)-xxx-8EA 128KB

PD703231GB(A1)-xxx-8EA (Mask ROM)

PD703231GB(A2)-xxx-8EA

PD70F3231M1GB(A)-8EA 128 KB

Without power-on clear function

PD70F3231M1GB(A1)-8EA

(Flash Memory)

PD70F3231M1GB(A2)-8EA

PD70F3231M2GB(A)-8EA With power-on clear function

PD70F3231M2GB(A1)-8EA

PD70F3231M2GB(A2)-8EA

Note: The ope rating ambient temperature of each quality grades is as follows.

(A)：－40 to +85℃，(A1)：－40 to +110℃，(A2)：－40 to +125℃

Remark xxx is ROM code number.

Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by

NEC Electronics Corporation to know the specification of the quality grade on the device and its

recommended applications.

1.5 Applications

Automotive body electrical systems (CAN controller equipped general-purpose products)

CHAPTER 1 INTRODUCTION

User’s Manual U17830EE1V0UM00 27

1.6 Pin Configuration (Top View)

• V850ES/FJ2 (

PD70F3237)

144-pin plastic LQFP (fine pitch) (20 × 20)

REF0

P10/INTP9

P11/INTP10

P00/TIP31/TOP31

P01/TIP30/TOP30

FLMD0

REGC

RESET

XT1

XT2

P02/NMI

P03/INTP0/ADTRG

P04/INTP1

P05/INTP2/DRST

P06/INTP3

P40/SIB0

P41/SOB0

P42/SCKB0

P30/TXDA0

P31/RXDA0/INTP7

P32/ASCKA0/TIP00/TOP00/TOP01

P33/TIP01/TOP01/CTXD0

P34/TIP10/TOP10/CRXD0

P35/TIP11/TOP11

P36/CTXD1

P37/CRXD1

P38/TXDA2

P39/RXDA2/INTP8

PDL3/AD3

PDL2/AD2

PDL1/AD1

PDL0/AD0

PCT7

PCT6/ASTB

PCT5

PCT4/RD

PCT3

PCT2

PCT1/WR1

PCT0/WR0

PCS7

PCS6

PCS5

PCS4

PCM5

PCM4

PCM3/HLDRQ

PCM2/HLDAK

PCM1/CLKOUT

PCM0/WAIT

PCS3/CS3

PCS2/CS2

PCS1/CS1

PCS0/CS0

PCD3

PCD2

PCD1

PCD0

P915/INTP6

P914/INTP5

P913/INTP4/PCL

P912/SCKB2

P50/KR0/TIQ01/TOQ01

P51/KR1/TIQ02/TOQ02

P52/KR2/TIQ03/TOQ03/DDI

P53/KR3/TIQ00/TOQ00/DDO

P54/KR4/DCK

P55/KR5/DMS

P60/INTP11

P61/INTP12

P62/INTP13

P63

P64

P65

P66

P67

P68

P69

P610/TIQ20/TOQ20

P611/TIQ21/TOQ21

P612/TIQ22/TOQ22

P613/TIQ23/TOQ23

P614

P615

P80/INTP14

P81

P90/KR6/TXDA1

P91/KR7/RXDA1

P92/TIQ11/TOQ11

P93/TIQ12/TOQ12

P94/TIQ13/TOQ13

P95/TIQ10/TOQ10

P96/TIP21/TOP21

P97/SIB1/TIP20/TOP20

P98/SOB1

P99/SCKB1

P910/SIB2

P911/SOB2

P70/ANI0

P71/ANI1

P72/ANI2

P73/ANI3

P74/ANI4

P75/ANI5

P76/ANI6

P77/ANI7

P78/ANI8

P79/ANI9

P710/ANI10

P711/ANI11

P712/ANI12

P713/ANI13

P714/ANI14

P715/ANI15

P120/ANI16

P121/ANI17

P122/ANI18

P123/ANI19

P124/ANI20

P125/ANI21

P126/ANI22

P127/ANI23

PDL15/AD15

PDL14/AD14

PDL13/AD13

PDL12/AD12

PDL11/AD11

PDL10/AD10

PDL9/AD9

PDL8/AD8

PDL7/AD7

PDL6/AD6

PDL5/AD5/FLMD1

PDL4/AD4

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

102

101

100

Notes 1 IC: Connect to VSS directly（mask ROM products only ）

FLMD0: Connect to VSS in the normal operation mode.（Flash memory versions only）

FLMD1: Flash memory versions only

Notes 2 REGC can be connect to VSS via capacitor of 4.7uF

CHAPTER 1 INTRODUCTION

User’s Manual U17830EE1V0UM00

• V850ES/FJ2 (

PD70F3238,

PD70F3239)

144-pin plastic LQFP (fine pitch) (20 × 20)

REF0

P10/INTP9

P11/INTP10

P00/TIP31/TOP31

P01/TIP30/TOP30

FLMD0

REGC

RESET

XT1

XT2

P02/NMI

P03/INTP0/ADTRG

P04/INTP1

P05/INTP2/DRST

P06/INTP3

P40/SIB0

P41/SOB0

P42/SCKB0

P30/TXDA0

P31/RXDA0/INTP7

P32/ASCKA0/TIP00/TOP00/TOP01

P33/TIP01/TOP01/CTXD0

P34/TIP10/TOP10/CRXD0

P35/TIP11/TOP11

P36/CTXD1

P37/CRXD1

P38/TXDA2

P39/RXDA2/INTP8

PDL3/AD3

PDL2/AD2

PDL1/AD1

PDL0/AD0

PCT7

PCT6/ASTB

PCT5

PCT4/RD

PCT3

PCT2

PCT1/WR1

PCT0/WR0

PCS7

PCS6

PCS5

PCS4

PCM5

PCM4

PCM3/HLDRQ

PCM2/HLDAK

PCM1/CLKOUT

PCM0/WAIT

PCS3/CS3

PCS2/CS2

PCS1/CS1

PCS0/CS0

PCD3

PCD2

PCD1

PCD0

P915/INTP6

P914/INTP5

P913/INTP4/PCL

P912/SCKB2

P50/KR0/TIQ01/TOQ01

P51/KR1/TIQ02/TOQ02

P52/KR2/TIQ03/TOQ03/DDI

P53/KR3/TIQ00/TOQ00/DDO

P54/KR4/DCK

P55/KR5/DMS

P60/INTP11

P61/INTP12

P62/INTP13

P63

P64

P65/CTXD2

P66/CRXD2

P67/CTXD3

P68/CRXD3

P69

P610/TIQ20/TOQ20

P611/TIQ21/TOQ21

P612/TIQ22/TOQ22

P613/TIQ23/TOQ23

P614

P615

P80/RXDA3/INTP14

P81/TXDA3

P90/KR6/TXDA1

P91/KR7/RXDA1

P92/TIQ11/TOQ11

P93/TIQ12/TOQ12

P94/TIQ13/TOQ13

P95/TIQ10/TOQ10

P96/TIP21/TOP21

P97/SIB1/TIP20/TOP20

P98/SOB1

P99/SCKB1

P910/SIB2

P911/SOB2

P70/ANI0

P71/ANI1

P72/ANI2

P73/ANI3

P74/ANI4

P75/ANI5

P76/ANI6

P77/ANI7

P78/ANI8

P79/ANI9

P710/ANI10

P711/ANI11

P712/ANI12

P713/ANI13

P714/ANI14

P715/ANI15

P120/ANI16

P121/ANI17

P122/ANI18

P123/ANI19

P124/ANI20

P125/ANI21

P126/ANI22

P127/ANI23

PDL15/AD15

PDL14/AD14

PDL13/AD13

PDL12/AD12

PDL11/AD11

PDL10/AD10

PDL9/AD9

PDL8/AD8

PDL7/AD7

PDL6/AD6

PDL5/AD5/FLMD1

PDL4/AD4

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

102

101

100

Notes 1 IC: Connect to VSS directly

FLMD0: Connect to VSS in the normal operation mode.（Flash memory versions only）

FLMD1: Flash memory versions only

Notes 2 REGC can be connect to VSS via capacitor of 4.7uF

CHAPTER 1 INTRODUCTION

User’s Manual U17830EE1V0UM00 29

• V850ES/FG2 (

PD70F3234,

PD70F3235,

PD70F3236)

100-pin plastic LQFP (fine pitch) (14 × 14)

2526 27 28 29 30 31 32 33 34 35 36 37 38 39 40

10099 98 97 96 95 94 93 92 91 90 89 88 87 86 85 75

AVSS

/TIP

/TOP

/TIP

/TOP

/[F

]

VSS

ESET

ST]

/SIB

/SOB

/TX

041

/AS

/TOP

/TIP

/TOP

/TIP

/TOP

/TIP

/TOP

/TIP

/TOP

EVSS

/TX

/TIQ

/TOQ

/TIQ

/TOQ

/TIQ

/TOQ

/TIQ

/TOQ

/TX

/TIQ

/TOQ

/TIQ

/TOQ

/TIQ

/TOQ

/TIQ

/TOQ

/TIP

/TOP

/SIB

/TIP

/TOP

BVSS

915

914

913

912

911

910

/SOB

710

711

712

713

714

715

DL13

DL12

DL11

DL10

DL9

DL8

DL7

DL6

DL5

/[F

]

43 4442 45

84 8283 81

4946 4847 50

7780 7879 76

Notes 1 IC: Connect to VSS directly

FLMD0: Connect to VSS in the normal operation mode.（Flash memory versions only）

FLMD1: Flash memory versions only

Notes 2 REGC can be connect to VSS via capacitor of 4.7uF

Remark Pins in brackets are valid only in

PD70F3234, 70F3235, 70F3236

CHAPTER 1 INTRODUCTION

User’s Manual U17830EE1V0UM00

• V850ES/FF2 (

PD70F3232,

PD70F3233)

80-pin plastic TQFP (fine pitch) (12 × 12)

AVREF0

AVSS

P00/TIP31/TOP31

P01/TIP30/TOP30

P02/NMI

P03/INTP0/ADTRG

P04/INTP1

IC/[FLMD0]

VDD

REGC

VSS

RESET

XT1

XT2

P05/INTP2/[DRST]

P06/INTP3

P40/SIB0

P41/SOB0

PDL3

PDL2

PDL1

PDL0

PCT6

PCT4

PCT1

PCT0

PCM3

PCM2

PCM1/CLKOUT

PCM0

PCS1

PCS0

P915/INTP6

P914/INTP5

P913/INTP4/PCL

P99/SCKB1

P98/SOB1

P97/SIB1/TIP20/TOP20

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

P42/SCKB0

P30/TXDA0

P31/RXDA0/INTP7

P32/ASCKA0/TIP00/TOP00/TOP01

P33/TIP01/TOP01/CTXD0

P34/TIP10/TOP10/CRXD0

P35/TIP11/TOP11

P38

P39

EVSS

EVDD

P50/KR0/TIQ01/TOQ01

P51/KR1/TIQ02/TOQ02

P52/KR2/TIQ03/TOQ03/[DDI]

P53/KR3/TIQ00/TOQ00/[DDO]

P54/KR4/[DCK]

P55/KR5/[DMS]

P90/KR6/TXDA1

P91/KR7/RXDA1

P96/TIP21/TOP21

P70/ANI0

P71/ANI1

P72/ANI2

P73/ANI3

P74/ANI4

P75/ANI5

P76/ANI6

P77/ANI7

P78/ANI8

P79/ANI9

P710/ANI10

P711/ANI11

PDL11

PDL10

PDL9

PDL8

PDL7

PDL6

PDL5/[FLMD1]

PDL4

Note1

Note2

Notes 1 IC: Connect to VSS directly

FLMD0: Connect to VSS in the normal operation mode.（Flash memory versions only）

FLMD1: Flash memory versions only

Notes 2 REGC can be connect to VSS via capacitor of 4.7uF

Remark Pins in brackets are only valid for

PD70F3232,

70F3233

CHAPTER 1 INTRODUCTION

User’s Manual U17830EE1V0UM00 31

• V850ES/FE2 (

PD703230,

PD70F3231)

64-pin plastic LQFP (fine pitch) (10 × 10)

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48

AVREF0

IC/[FLMD0]

REGC

RESET

XT1

XT2

P00/TIP31/TOP31

P01/TIP30/TOP30

P02/NMI

P03/INTP0/ADTRG

P04/INTP1 32

P05/INTP2/[DRST]

P06/INTP3

P40/SIB0

P41/SOB0

P42/SCKB0

P30/TXDA0

P31/RXDA0/INTP7

P32/ASCKA0/TIP00/TOP00/TOP01

P33/TIP01/TOP01/CTXD0

P34/TIP10/TOP10/CRXD0

P35/TIP11/TOP11

P50/KR0/TIQ01/TOQ01

P51/KR1/TIQ02/TOQ02

P52/KR2/TIQ03/TOQ03/[DDI]

P53/KR3/TIQ00/TOQ00/[DDO]

PDL1

PDL0

PCM1/CLKOUT

PCM0

P915/INTP6

P914/INTP5

P913/INTP4/PCL

P99/SCKB1

P98/SOB1

P97/SIB1/TIP20/TOP20

P96/TIP21/TOP21

P91/KR7/RXDA1

P90/KR6/TXDA1

P55/KR5/[DMS]

P54/KR4/[DCK]

P70/ANI0

P71/ANI1

P72/ANI2

P73/ANI3

P74/ANI4

P75/ANI5

P76/ANI6

P77/ANI7

P78/ANI8

P79/ANI9

PDL7

PDL6

PDL5/[FLMD1]

PDL4

PDL3

PDL2

Note1

Note2

Note 1 IC: Connect to VSS directly

FLMD0: Connect to VSS in the normal operation mode.（Flash memory versions only）

FLMD1: Flash memory versions only

Note 2 REGC can be connect to VSS via capacitor of 4.7uF

Remark Pins in brackets are only valid for

PD70F3231

CHAPTER 1 INTRODUCTION

User’s Manual U17830EE1V0UM00

Pin identification

AD0 to AD15:

ADTRG:

ANI0 to ANI23:

ASCKA0:

ASTB:

AVREF0:

AVSS:

BVDD:

BVSS:

CLKOUT:

CRXD0 to CRXD3:

CS0 to CS3:

CTXD0 to CTXD3:

DCK:

DDI:

DDO:

DMS:

DRST:

EVDD:

EVSS:

FLMD0, FLMD1:

HLDAK:

HLDRQ:

INTP0 to INTP14:

KR0 to KR7:

NMI:

P00 to P06:

P10, P11:

P30 to P39:

P40 to P42:

P50 to P55:

P60 to P615:

P70 to P715:

P80, P81:

P90 to P915:

Address/data bus

A/D trigger input

Analog input

Asynchronous serial clock

Address strobe

Analog reference voltage

Analog VSS

Power supply for bus interface

Ground for bus interface

Clock output

CAN receive data

Chip select

CAN transmit data

Debug clock

Debug data input

Debug data output

Debug mode select

Debug reset

Power supply for port

Ground for port

Flash programming mode

Hold acknowledge

Hold request

Interrupt request from per ipherals

Key return

Non-maskable interrupt request

Port 0

Port 1

Port 3

Port 4

Port 5

Port 6

Port 7

Port 8

Port 9

P120 to P127:

PCD0 to PCD3:

PCL:

PCM0 to PCM5:

PCS0 to PCS7:

PCT0 to PCT7:

PDL0 to PDL15:

RD:

REGC:

RESET:

RXDA0 to RXDA3:

SCKB0 to SCKB2:

SIB0 to SIB2:

SOB0 to SOB2:

TIP00, TIP01,

TIP10, TIP1 1,

TIP20, TIP21,

TIP30, TIP31,

TIQ00 to TIQ03,

TIQ10 to TIQ13,

TIQ20 to TIQ23:

T OP00, TOP01,

T OP10, TOP11,

T OP20, TOP21,

T OP30, TOP31,

TOQ01 to TO Q03,

TOQ11 to TOQ13,

TOQ20 to TO Q23:

TXDA0 to TXDA3:

VDD:

VSS:

WAIT:

WR0:

WR1:

X1, X2:

XT1, XT2:

Port 12

Port CD

Programmable clock output

Port CM

Port CS

Port CT

Port DL

Read strobe

Regulator control

Reset

Receive data

Serial clock

Serial input

Serial output

Timer input

Timer output

Transmit data

Power supply

Ground

Wait

Write strobe low level data

Write strobe high level data

Crystal for main clock

Crystal for subclock

CHAPTER 1 INTRODUCTION

User’s Manual U17830EE1V0UM00 33

1.7 Function Block Configuration

1.7.1 Internal block diagram

• V850ES/FJ2 (

PD70F3237)

NMI

SOB0 to SOB2

SIB0 to SIB2

SCKB0 to SCKB2

INTP0 to INTP14 INTC

16-bit timer/

counter Q:

3 ch

TIP00 to TIP30

TIP01 to TIP31

TOP00 to TOP30

TOP01 to TOP31

16-bit timer/

counter P:

4 ch

DMAC

256 KB

RAM

Flash memory

12 KB

General-

purpose registers

32 bits ⋅ 32

Multiplier

16 ⋅ 16 32

ALU

System

registers

32-bit barrel

shifter

CPU

HLDRQ

HLDAK

ASTB

WAIT

WR0, WR1

CS0 to CS3

AD0 to AD1

Ports

PCS0 to PCS7

PCM0 to PCM5

PCT0 to PCT7

PDL0 to PDL15

PCD0 to PCD3

P120 to P127

P90 to P915

P80, P81

P70 to P715

P60 to P615

P50 to P55

P40 to P42

P30 to P39

P10, P11

P00 to P06

16-bit

interval

timer M:

1 ch

CSIB: 3 ch

Watch timer

TIQ00 to TIQ20

TIQ01 to TIQ21

TIQ02 to TIQ22

TIQ03 to TIQ23

TOQ00 to TOQ20

TOQ01 to TOQ21

TOQ02 to TOQ22

TOQ03 to TOQ23

TXDA0 to TXDA2

RXDA0 to RXDA2

ASCKA0 UARTA: 3 ch

CTXD0, CTXD1

CRXD0, CRXD1 CAN: 2 ch

Instruction

queue

BCU

MEMC

Watchdog

timer 2

Key return

function

KR0 to KR7

ANI0 to ANI23

REF0

ADTRG

A/D

converter

FLMD0

FLMD1

Regulator

CLM

POC

PLL

REGC

PCL

CLKOUT

XT1

XT2

RESET

On chip debug

DRST

DMS

DDO

DCK

DDI

RCU

RSU

ROMC

LVI

Note

Note: only POC version

CHAPTER 1 INTRODUCTION

User’s Manual U17830EE1V0UM00

• V850ES/FJ2 (

PD70F3238

PD70F3239)

NMI

SOB0 to SOB2

SIB0 to SIB2

SCKB0 to SCKB2

INTP0 to INTP14 INTC

16-bit timer/

counter Q:

3 ch

TIP00 to TIP30

TIP01 to TIP31

TOP00 to TOP30

TOP01 to TOP31

16-bit timer/

counter P:

4 ch

DMAC

Note 1

RAM

Flash memory

20 KB

General-

purpose registers

32 bits ⋅ 32

Multiplier

16 ⋅ 16 32

ALU

System

registers

32-bit barrel

shifter

CPU

HLDRQ

HLDAK

ASTB

WAIT

WR0, WR1

CS0 to CS3

AD0 to AD15

FLMD0

FLMD1

Ports

Regulator

CLM

PLL

FLMD0

PCS0 to PCS7

PCM0 to PCM5

PCT0 to PCT7

PDL0 to PDL15

PCD0 to PCD3

P120 to P127

P90 to P915

P80, P81

P70 to P715

P60 to P615

P50 to P55

P40 to P42

P30 to P39

P10, P11

P00 to P06

REGC

16-bit

interval

timer M:

1 ch

CSIB: 3 ch

Watch timer

TIQ00 to TIQ20

TIQ01 to TIQ21

TIQ02 to TIQ22

TIQ03 to TIQ23

TOQ00 to TOQ20

TOQ01 to TOQ21

TOQ02 to TOQ22

TOQ03 to TOQ23

TXDA0 to TXDA3

RXDA0 to RXDA3

ASCKA0 UARTA: 4 ch

CTXD0 to CTXD3

CRXD0 to CRXD3 CAN: 4 ch

Instruction

queue

BCU

MEMC

Watchdog

timer 2

Key return

function

KR0 to KR7

ANI0 to ANI23

REF0

ADTRG

A/D

converter

PCL

CLKOUT

XT1

XT2

RESET

On chip debug

DRST

DMS

DDO

DCK

DDI

RCU

RSU

ROMC

POC

LVI

Note 2

Notes: 1 376 KB/512 KB (Flash memory see Table1-1)

2. POC version

CHAPTER 1 INTRODUCTION

User’s Manual U17830EE1V0UM00 35

• V850ES/FG2 (

PD70F3234,

PD70F3235,

PD70F3236)

NMI

SOB0, SOB1

SIB0, SIB1

SCKB0, SCKB1

INTP0 to INTP10 INTC

16-bit timer/

counter Q:

2 ch

TIP00 to TIP30

TIP01 to TIP31

TOP00 to TOP30

TOP01 to TOP31

16-bit timer/

counter P:

4 ch

DMAC

General-

purpose register

32 bits ⋅ 32

ALU

System

registers

32-bit barrel

shifter

CPU

Ports

PCS0, PCS1

PCM0 to PCM3

PCT0, PCT1, PCT4, PCT6

PDL0 to PDL13

P90 to P915

P70 to P715

P50 to P55

P40 to P42

P30 to P39

P10, P11

P00 to P06

16-bit

interval

timer M:

1 ch

CSIB: 2ch

Watch timer

TIQ00 to TIQ10

TIQ01 to TIQ11

TIQ02 to TIQ12

TIQ03 to TIQ13

TOQ00 to TOQ10

TOQ01 to TOQ11

TOQ02 to TOQ12

TOQ03 to TOQ13

TXDA0 to TXDA2

RXDA0 to RXDA2

ASCKA0 UARTA: 3ch

CTXD0, CTXD1

CRXD0, CRXD1 CAN: 2ch

Instruction

queue

BCU

Watchdog

timer 2

Key return

function

KR0 to KR7

ANI0 to ANI15

AVSS

AVREF0

ADTRG

A/D

converter

FLMD0

FLMD1

Regulator

CLM

POC

PLL

FLMD0

VDD

VSS

REGC

BVDD

BVSS

EVDD

EVSS

PCL

CLKOUT

XT1

XT2

RESET

On chip debug

DRST

DMS

DDO

DCK

DDI

RCU

RSU

ROMC

LVI

Note 1

RAM

ROM

Note 2

Multiplier

16 16 32

Note 3

Notes: 1 128/256/384KB (Flash memory see Table1-1)

128/256KB (Mask ROM see Table1-1)

2 6/12/16KB (see Table1-1)

3 POC version only

CHAPTER 1 INTRODUCTION

User’s Manual U17830EE1V0UM00

• V850ES/FF2 (

PD70F3232,

PD70F3233)

NMI

SOB0, SOB1

SIB0, SIB1

SCKB0, SCKB1

INTP0 to INTP7 INTC

16-bit timer/

counter Q:

1 ch

TIP00 to TIP30

TIP01 to TIP31

TOP00 to TOP30

TOP01 to TOP31

16-bit timer/

counter P:

4 ch

General-

purpose registers

32 bits ⋅ 32

ALU

System

registers

32-bit barrel

shifter

CPU

Ports

PCS0,PCS1

PCM0 to PCM3

PCT0,PCT1,PCT4,PCT6

PDL0 to PDL11

P90,P91,P96 to P99,P913 to P915

P70 to P711

P50 to P55

P40 to P42

P30 to P35,P38, P39

P00 to P06

16-bit

interval

timer M:

1 ch

CSIB: 2ch

Watch timer

TIQ00

TIQ01

TIQ02

TIQ03

TOQ00

TOQ01

TOQ02

TOQ03

TXDA0, TXDA1

RXDA0, RXDA1

ASCKA0 UARTA: 2ch

CTXD0

CRXD0 CAN: 1ch

Instruction

queue

BCU

Watchdog

timer 2

Key return

function

KR0 to KR7

ANI0 to ANI11

REF0

ADTRG

A/D

converter

FLMD0

FLMD1

Regulator

CLM

PLL

FLMD0

REGC

PCL

CLKOUT

XT1

XT2

RESET

On chip debug

DRST

DMS

DDO

DCK

DDI

RCU

RSU

ROMC

Note 1

RAM

ROM

Note 2

POC

LVI

Multiplier

16 16 32

Note 3

Notes: 1 128/256 (Flash memory see Table1-1)

128/256KB (Mask ROM see Table1-1)

2 6/12KB (see Table1-1)

3 POC version only

CHAPTER 1 INTRODUCTION

User’s Manual U17830EE1V0UM00 37

• V850ES/FE2 (

PD703230,

PD70F3231)

NMI

SOB0, SOB1

SIB0, SIB1

SCKB0, SCKB1

INTP0 to INTP7 INTC

16-bit timer/

counter Q:

1 ch

TIP00 to TIP30

TIP01 to TIP31

TOP00 to TOP30

TOP01 to TOP31

16-bit timer/

counter P:

4 ch

General-

purpose register

32 bits ⋅ 32

ALU

System

registers

32-bit barrel

shifter

CPU

Ports

On chip debug

PCM0,PCM1

PDL0 to PDL7

P90,P91,P96 to P99,P913 to P915

P70 to P79

P50 to P55

P40 to P42

P30 to P35

P00 to P06

16-bit

interval

timer M:

1 ch

CSIB: 2ch

DRST

DMS

DDO

DCK

DDI

Watch timer

TIQ00

TIQ01

TIQ02

TIQ03

TOQ00

TOQ01

TOQ02

TOQ03

TXDA0, TXDA1

RXDA0, RXDA1

ASCKA0 UARTA: 2ch

CTXD0

CRXD0 CAN: 1ch

Instruction

queue

BCU

Watchdog

timer 2

Key return

function

KR0 to KR7

ANI0 to ANI9

REF0

ADTRG

A/D

converter RCU

RSU

ROMC

FLMD0

FLMD1

Regulator

CLM

PLL

FLMD0

REGC

PCL

CLKOUT

XT1

XT2

RESET

Note 1

RAM

ROM

Note 2

POC

LVI

Multiplier

16 16 32

Note 3

Notes: 1 128KB (Flash memory see Table1-1)

64/128KB (Mask ROM see Table1-1)

2 4/6KB (see Table1-1)

3 POC version only

CHAPTER 1 INTRODUCTION

User’s Manual U17830EE1V0UM00

1.7.2 Internal units

(1) CPU

The CPU can execute almost all instruction processing, such as address calculation, arithmetic and logic

operations, and data transfer, in one clock under control of a five-stage pipeline.

Dedicated hardware units such as a multiplier (16 bits × 16 bits Æ 32 bits) and a barrel shifter (32 bits) are

provided to speed up complicated instruction processing.

(2) External memory control unit (MEMC)

This unit starts necessary external bus cycles based on the physical addresses obtained by the CPU. If the

CPU does not request the start of a bus cycle when it fetches an instruction from an external memor y area,

this unit generates a prefetch address and prefetches an in struction code. The prefetched instruction code is

sent to an internal instructio n queue.

(3) ROM

This is a flash memory of 512/384/376/256/128/64 KB mapped to addresses 0000000H-

007FFFFH/0000000H-005FFFFH/0000000H-005DFFFH/0000000H-003FFFFH/0000000H-

001FFFFH/0000000H-000FFFFH. The CPU can access this memory in one clock when it fetches an

instruction.

(4) RAM

This is a RAM of 20/16/12/6/4 KB mapped to addresses 3FFA000H-3FFEFFFH/3FFB000H-

3FFEFFFH/3FFC000H-3FFEFFFH/3FFD8000H-3FFEFFFH/3FFE000H-3FFEFFFH. The CPU can access

this RAM in one clock when it accesses data.

(5) Interrupt controller (INTC)

The interrupt controller processes interrupt requests (NMI and INTP0 up to INTP14 refer to Table 1-1) from

the on-chip peripheral hardware and external sources. Eight levels of priorities can be specified for these

interrupt reque sts, and multiple servicing cont rol can be performed on interr upt sources.

(6) Clock generator (CG)

Two types of oscillators, a main clock (fXX) a nd a subclock (fXT), are provided. The clock generator generates

seven types of clocks (fXX, fXX/2, fXX/4, fXX/8, fXX/16, fXX/32, and fXT), of which one is supp lied as the operating

clock of the CPU (fCPU).

(7) Ring-OSC

A Ring-OSC oscillator is provided. The oscillation frequency is 200 kHz (TYP.). This Ring-OSC oscillator

supplies a clock to watchdog timer 2 and timer M.

(8) Timers/counters

16-bit timer/event counter P (TMP), 16-bit timer/event counter Q (TMQ), and 16-bit interval timer M (TMM) are

provided (refer to Table 1-1).

(9) Watch timer

This timer counts the reference time for watch counting from the subclock or fBRG from prescaler 3. At the

same time, it can also be used as an interval timer that operates on the main clock.

CHAPTER 1 INTRODUCTION

User’s Manual U17830EE1V0UM00 39

(10) Watchdog timer 2

This watchdog timer is used to detect a program loop and system errors.

As the source clock of this timer, Ring-OSC, or main clock can be selected.

When this watchdog timer overflows, it generates a non-maskable interrupt request signal (INTWDT2) or

system reset signal (WDT2RES).

(11) Serial interface (SIO)

The V850ES /FE2, V850ES/FF2, V850ES/FG2, V850ES/FJ2 have asynchronous serial interface A (UARTA)

and 3-wire variable-length serial interface B (CSIB) as serial interfaces, and up to seven chann els can be used

at the same time.

UARTA transfers data by using the TXDAn and RXDAn pins (n = 0 up to 3 refer to Table 1-1).

CSIB transfers data by using the SOBm, SIBm, and SCKBm pins (m = 0 up to 2 refer to Table 1-1).

UARTA has a dedicated baud rate generator.

(12) CAN controller

The CAN controller is a small-scale digital data transmission system that transfers data between units.

(13) A/D converter

This is a high-speed, high-resolutio n 10-bit A/D conver ter with up to 24 analo g input pins (refer to Table 1-1).

This converter is a successive approximati on type.

(14) DMA controller

The V850ES/FG2, V850ES/FJ2 has a four-channel DMA controller that transfers data between the internal

RAM, on-chip peripheral I/O, and external memory, in response to interrupt requests from the on-chip

peripheral I/O.

(15) Key interrupt function

A key interrupt request signal (INTKR) can be generated by inputting a falling edge to key input pins of eight

channels.

(16) On-chip debug function (Flash memory product only)

An on-chip debug function (Flash memory product only) that uses the communication specifications of JTAG

(Joint Test Action Group) and that is used via an N-Wire in-circuit emulator is provided. The normal port

function and on-chip debug function are selected by using the input level of a control pin and on-chip debug

mode setting register (OCDM).

(17) Ports

General-purpose port functions and control pin functions are available. For details, refer to CHAPTER 4

PORT FUNCTIONS.

User’s Manual U17830EE1V0UM00

CHAPTER 2 PIN FUNCT IONS

This section explains the names and functions of the pins of the V850ES/FE2, V850ES/FF2, V850ES/FG2,

V850ES/FJ2.

2.1 Pin Function List

2.1.1 V850ES/FE2

Two I/O buffer power supplies, AVREF0 and EVDD, are available.The relatio nship between the power suppl ies and the

pins is shown below.

Table 2-1. Pin I/O Buffer Power Supplies (V850ES/FE2)

Power Supply Corresponding Pin

AVREF0 Port 7

EVDD Port 0, Port 3, Port 4, Port 5, Port 6, Port 8, Port 9, Port CM, Port DL, RESET

CHAPTER 2 PIN FUNCTIONS

User’s Manual U17830EE1V0UM00 41

(1) Port pins Table 2-2. Pin List (Port Pins V850ES/FE2)

Pin Name I/O Function Alternate Function

P00 TIP31/TOP31

P01 TIP30/TOP30

P02 NMI

P03 INTP0/ADTRG

P04 INTP1

P05 INTP2/DRST

P06

I/O Port 0

7-bit I/O port

Input/output can be specified in 1-bit units.

INTP3

P30 TXDA0

P31 RXDA0/INTP7

P32 ASCKA0/TIP00/TOP00/TOP01

P33 TIP01/TOP01/CTXD0

P34 TIP10/TOP10/CRXD0

P35

I/O Port 3

6-bit I/O port

Input/output can be specified in 1-bit units.

TIP11/TOP11

P40 SIB0

P41 SOB0

P42

I/O Port 4

3-bit I/O port

Input/output can be specified in 1-bit units. SCKB0

P50 KR0/TIQ01/TOQ01

P51 KR1/TIQ02/TOQ02

P52 KR2/TIQ03/TOQ03/DDI

P53 KR3/TIQ00/TOQ00/DDO

P54 KR4/DCK

P55

I/O Port 5

6-bit I/O port

Input/output can be specified in 1-bit units.

KR5/DMS

P70 to P79 I/O Port 7

10-bit I/O port

Input/output can be specified in 1-bit units.

ANI0 to ANI9

P90 KR6/TXDA1

P91 KR7/RXDA1

P96 TIP21/TOP21

P97 SIB1/TIP20/TOP20

P98 SOB1

P99 SCKB1

P913 INTP4/PCL

P914 INTP5

P915

I/O Port 9

9-bit I/O port

Input/output can be specified in 1-bit units.

INTP6

PCM0 -

PCM1

I/O Port CM

2-bit I/O port

Input/output can be specified in 1-bit units. CLKOUT

PDL0 to PDL4 -

PDL5 FLMD1

PDL6, PDL7

I/O Port DL

8-bit I/O port

Input/output can be specified in 1-bit units. -

CHAPTER 2 PIN FUNCTIONS

User’s Manual U17830EE1V0UM00

(2) Non-port pins

Table 2-3. Pin List (Non-Port Pins V850ES/FE2) (1/3)

Pin Name I/O Function Alternate Function

NMI Input

External interrupt input

(non-maskable, with analog noise eliminated)

P02 Note

INTP0 P03/ADTRG

INTP1 P04

INTP2 P05/DRST

INTP3 P06

INTP4 P913/PCL

INTP5 P914

INTP6 P915

INTP7

Input External interrupt request input

(maskable, with analog noise eliminated)

P31/RXDA0

TIP00 External event/clock input (TMP00) P32/ASCKA0/TOP00/TOP01

TIP01 External event input (TMP01) P33/TOP01/CTXD0

TIP10 External event/clock input (TMP10) P34/TOP10/CRXD0

TIP11 External event input (TMP11) P35/TOP11

TIP20 External event/clock input (TMP20) P97/SIB1/TOP20

TIP21 External event input (TMP21) P96/TOP21

TIP30 External event/clock input (TMP30) P01/TOP30

TIP31

Input

External event input (TMP31) P00/TOP31

TOP00 Timer output (TMP00) P32/ASCKA0/TIP00/TOP01

P32/ASCKA0/TIP00/TOP00 TOP01 Timer output (TMP01)

P33/TIP01/CTXD0

TOP10 Timer output (TMP10) P34/TIP10/CRXD0

TOP11 Timer output (TMP11) P35/TIP11

TOP20 Timer output (TMP20) P97/SIB1/TIP20

TOP21 Timer output (TMP21) P96/TIP21

TOP30 Timer output (TMP30) P01/TIP30

TOP31

Output

Timer output (TMP31) P00/TIP31

Note: The NMI pin and P02 pin are an alternate-function pin. This pin functions as the P02 pin after if has been

reset. To enable the NMI pin, set the PMC0.PMC02 bit to 1.The initial setting of the NMI pin is "No edge

detected". Select the NMI pin valid edge using INTF0 and INTR0 registers .

CHAPTER 2 PIN FUNCTIONS

User’s Manual U17830EE1V0UM00 43

Table 2-3. Pin List (Non-Port Pins V850ES/FE2) (2/3)

Pin Name I/O Function Alternate Function

TIQ00 External event/clock input (TMQ00) P53/KR3/TOQ00/DDO

TIQ01 External event input (TMQ01) P50/KR0/TOQ01

TIQ02 External event input (TMQ02) P51/KR1/TOQ02

TIQ03

Input

External event input (TMQ03) P52/KR2/TO Q03/DDI

TOQ00 Timer output (TMQ00) P53/KR3/TIQ00/DDO

TOQ01 Timer output (TMQ01) P50/KR0/TIQ01

TOQ02 Timer output (TMQ02) P51/KR1/TIQ02

TOQ03

Output

Timer output (TMQ03) P52/KR2/TIQ03/DDI

SIB0 Serial receive data input (CSIB0) P40

SIB1

Input

Serial receive data input (CSIB1) P97/TIP20/TOP20

SOB0 Serial transmit data output (CSIB0) P41

SOB1

Output

Serial transmit data output (CSIB1) P98

SCKB0 Serial clock I/O (CSIB0) P42

SCKB1

I/O

Serial clock I/O (CSIB1) P99

RXDA0 Serial receive data input (UARTA0) P31/INTP7

RXDA1

Input

Serial receive data input (UARTA1) P91/KR7

TXDA0 Serial transmit data output (UARTA0) P30

TXDA1

Output

Serial transmit data output (UARTA1) P90/KR6

ASCKA0 Input Baud rate clock input to UARTA0 P32/TIP00/TOP00/TOP01

CRXD0 Input CAN receive data input (CAN0) P34/TIP10/TOP10

CTXD0 Output CAN transmit data output (CAN0) P33/TIP01/TOP01

ANI0 to ANI9 Input Analog voltage input to A/D converter P70 to P79

AVREF0 Input Reference voltage input to A/D converter, and positive power supply

pin for port 7

−

AVSS − Ground potential for A/D converter (same potential as VSS) −

ADTRG Input A/D converter external trigger input P03/INTP0

KR0 P50/TIQ01/TOQ01

KR1 P51/TIQ02/TOQ02

KR2 P52/TIQ03/TOQ03/DDI

KR3 P53/TIQ00/TOQ00/DDO

KR4 P54/DCK

KR5 P55/DMS

KR6 P90/TXDA1

KR7

Input Key interrupt input

P91/RXDA1

CHAPTER 2 PIN FUNCTIONS

User’s Manual U17830EE1V0UM00

Table 2-3. Pin List (Non-Port Pins V850ES/FE2) (2/3)

Pin Name I/O Function Alternate Function

DMS Input Debug mode select P55/KR5

DDI Input Debug data input P52/KR2/TIQ03/TOQ03

DDO Output Debug data output P53/KR3/TIQ00/TOQ00

DCK Input Debug clock input P54/KR4

DRST Input Debug reset input P05/INTP2

CS0 to CS3 Output Chip select signal output PCS0 to PCS3

FLMD0 −

FLMD1

Input Flash programming mode setting pins

PDL5

CLKOUT Output

Internal system clock output PCM1

PCL Output Clock output (timing output of X1 input clock and subclock) P913/INTP4

REGC − Regulator output stabilizing capacitor connection −

RESET Input System reset input −

X1 Input −

X2 −

Main clock resonator connection

−

XT1 Input −

XT2 −

Subclock resonator connection

−

VDD − Positive power supply pin for internal circuitry −

VSS − Ground potential for internal circuitry −

EVDD − Positive po w er supply pin for external circuitry (same potential as VDD) −

EVSS − Ground potential for external circuitry (same potential as VSS) −

CHAPTER 2 PIN FUNCTIONS

User’s Manual U17830EE1V0UM00 45

2.1.2 V850ES/FF2

Two I/O buffer power supplies, AVREF0 and EVDD, are available. The relationship between the power supplies and the

pins is shown below.

Table 2-4. Pin I/O Buffer Power Supplies (V850ES/FF2)

Power Supply Corresponding Pin

AVREF0 Port 7

EVDD Port 0, Port 3, Port 4, Port 5, Port 6, Port 8, Port 9, Port CM, Port CS, Port CT, Port DL,

RESET

(1) Port pins

Table 2-5. Pin List (Port Pins V850ES/FF2) (1/2)

Pin Name I/O Function Alternate Function

P00 TIP31/TOP31

P01 TIP30/TOP30

P02 NMI

P03 INTP0/ADTRG

P04 INTP1

P05 INTP2/DRST

P06

I/O Port 0

7-bit I/O port

Input/output can be specified in 1-bit units.

INTP3

P30 TXDA0

P31 RXDA0/INTP7

P32 ASCKA0/TIP00/TOP00/TOP01

P33 TIP01/TOP01/CTXD0

P34 TIP10/TOP10/CRXD0

P35 TIP11/TOP11

P38 -

P39

I/O Port 3

8-bit I/O port

Input/output can be specified in 1-bit units.

P40 SIB0

P41 SOB0

P42

I/O Port 4

3-bit I/O port

Input/output can be specified in 1-bit units. SCKB0

P50 KR0/TIQ01/TOQ01

P51 KR1/TIQ02/TOQ02

P52 KR2/TIQ03/TOQ03/DDI

P53 KR3/TIQ00/TOQ00/DDO

P54 KR4/DCK

P55

I/O Port 5

6-bit I/O port

Input/output can be specified in 1-bit units.

KR5/DMS

CHAPTER 2 PIN FUNCTIONS

User’s Manual U17830EE1V0UM00

Table 2-5. Pin List (Port Pins V850ES/FF2) (2/2)

Pin Name I/O Function Alternate Function

P70 to P711 I/O Port 7

12-bit I/O port

Input/output can be specified in 1-bit units.

ANI0 to ANI11

P90 KR6/TXDA1

P91 KR7/RXDA1

P96 TIP21/TOP21

P97 SIB1/TIP20/TOP20

P98 SOB1

P99 SCKB1

P913 INTP4/PCL

P914 INTP5

P915

I/O Port 9

9-bit I/O port

Input/output can be specified in 1-bit units.

INTP6

PCM0 -

PCM1 CLKOUT

PCM2, PCM3

I/O Port CM

4-bit I/O port

Input/output can be specified in 1-bit units. -

PCS0, PCS1 I/O Port CS

2-bit I/O port

Input/output can be specified in 1-bit units.

PCT0, PCT1,

PCT4, PCT6

I/O Port CT

4-bit I/O port

Input/output can be specified in 1-bit units.

PDL0 to PDL4 -

PDL5 FLMD1

PDL6 to PDL11

I/O Port DL

8-bit I/O port

Input/output can be specified in 1-bit units. -

CHAPTER 2 PIN FUNCTIONS

User’s Manual U17830EE1V0UM00 47

(2) Non-port pins

Table 2-6. Pin List (Non-Port Pins V850ES/FF2) (1/3)

Pin Name I/O Function Alternate Function

NMI Input

External interrupt input

(non-maskable, with analog noise eliminated)

P02 Note

INTP0 P03/ADTRG

INTP1 P04

INTP2 P05/DRST

INTP3 P06

INTP4 P913/PCL

INTP5 P914

INTP6 P915

INTP7

Input External interrupt request input

(maskable, with analog noise eliminated)

P31/RXDA0

TIP00 External event/clock input (TMP00) P32/ASCKA0/TOP00/TOP01

TIP01 External event input (TMP01) P33/TOP01/CTXD0

TIP10 External event/clock input (TMP10) P34/TOP10/CRXD0

TIP11 External event input (TMP11) P35/TOP11

TIP20 External event/clock input (TMP20) P97/SIB1/TOP20

TIP21 External event input (TMP21) P96/TOP21

TIP30 External event/clock input (TMP30) P01/TOP30

TIP31

Input

External event input (TMP31) P00/TOP31

TOP00 Timer output (TMP00) P32/ASCKA0/TIP00/TOP01

P32/ASCKA0/TIP00/TOP00 TOP01 Timer output (TMP01)

P33/TIP01/CTXD0

TOP10 Timer output (TMP10) P34/TIP10/CRXD0

TOP11 Timer output (TMP11) P35/TIP11

TOP20 Timer output (TMP20) P97/SIB1/TIP20

TOP21 Timer output (TMP21) P96/TIP21

TOP30 Timer output (TMP30) P01/TIP30

TOP31

Output

Timer output (TMP31) P00/TIP31

Note: The NMI pin and P02 pin are an alternate-function pin. This pin functions as the P02 pin after if has been

reset. To enable the NMI pin, set the PMC0.PMC02 bit to 1.The initial setting of the NMI pin is "No edge

detected". Select the NMI pin valid edge using INTF0 and INTR0 registers .

CHAPTER 2 PIN FUNCTIONS

User’s Manual U17830EE1V0UM00

Table 2-6. Pin List (Non-Port Pins V850ES/FF2) (2/3)

Pin Name I/O Function Alternate Function

TIQ00 External event/clock input (TMQ00) P53/KR3/TOQ00/DDO

TIQ01 External event input (TMQ01) P50/KR0/TOQ01

TIQ02 External event input (TMQ02) P51/KR1/TOQ02

TIQ03

Input

External event input (TMQ03) P52/KR2/TO Q03/DDI

TOQ00 Timer output (TMQ00) P53/KR3/TIQ00/DDO

TOQ01 Timer output (TMQ01) P50/KR0/TIQ01

TOQ02 Timer output (TMQ02) P51/KR1/TIQ02

TOQ03

Output

Timer output (TMQ03) P52/KR2/TIQ03/DDI

SIB0 Serial receive data input (CSIB0) P40

SIB1

Input

Serial receive data input (CSIB1) P97/TIP20/TOP20

SOB0 Serial transmit data output (CSIB0) P41

SOB1

Output

Serial transmit data output (CSIB1) P98

SCKB0 Serial clock I/O (CSIB0) P42

SCKB1

I/O

Serial clock I/O (CSIB1) P99

RXDA0 Serial receive data input (UARTA0) P31/INTP7

RXDA1

Input

Serial receive data input (UARTA1) P91/KR7

TXDA0 Serial transmit data output (UARTA0) P30

TXDA1

Output

Serial transmit data output (UARTA1) P90/KR6

ASCKA0 Input Baud rate clock input to UARTA0 P32/TIP00/TOP00/TOP01

CRXD0 Input CAN receive data input (CAN0) P34/TIP10/TOP10

CTXD0 Output CAN transmit data output (CAN0) P33/TIP01/TOP01

ANI0 to ANI11 Input Analog voltage input to A/D converter P70 to P711

AVREF0 Input Reference voltage input to A/D converter , and positive power supply

pin for port 7

−

AVSS − Ground potential for A/D converter (same potential as VSS) −

ADTRG Input A/D converter external trigger input P03/INTP0

KR0 P50/TIQ01/TOQ01

KR1 P51/TIQ02/TOQ02

KR2 P52/TIQ03/TOQ03/DDI

KR3 P53/TIQ00/TOQ00/DDO

KR4 P54/DCK

KR5 P55/DMS

KR6 P90/TXDA1

KR7

Input Key interrupt input

P91/RXDA1

CHAPTER 2 PIN FUNCTIONS

User’s Manual U17830EE1V0UM00 49

Table 2-6. Pin List (Non-Port Pins V850ES/FF2) (2/3)

Pin Name I/O Function Alternate Function

DMS Input Debug mode select P55/KR5

DDI Input Debug data input P52/KR2/TIQ03/TOQ03

DDO Output Debug data output P53/KR3/TIQ00/TOQ00

DCK Input Debug clock input P54/KR4

DRST Input Debug reset input P05/INTP2

FLMD0 −

FLMD1

Input Flash programming mode setting pins

PDL5

CLKOUT Output

Internal system clock output PCM1

PCL Output Clock output (timing output of X1 input clock and subclock) P913/INTP4

REGC − Regulator output stabilizing capacitor connection −

RESET Input System reset input −

X1 Input −

X2 −

Main clock resonator connection

−

XT1 Input −

XT2 −

Subclock resonator connection

−

VDD − Positive power supply pin for internal circuitry −

VSS − Ground potential for internal circuitry −

EVDD − Positive po w er supply pin for external circuitry (same potential as VDD) −

EVSS − Ground potential for external circuitry (same potential as VSS) −

CHAPTER 2 PIN FUNCTIONS

User’s Manual U17830EE1V0UM00

2.1.3 V850ES/FG2

Three I/O buffer power supplies, AVREF0, BVDD and EVDD, are available. The relationship between the power

supplies and the pins is shown below.

Table 2-7. Pin I/O Buffer Power Supplies (V850ES/FG2)

Power Supply Corresponding Pin

AVREF0 Port 7

EVDD Port 0, Port 1, Port 3, Port 4, Port 5, Port 9, RESET

BVDD Port CM, Port CS, Port CT, Port DL

(1) Port pins

Table 2-8. Pin List (Port Pins V850ES/FG2) (1/2)

Pin Name I/O Function Alternate Function

P00 TIP31/TOP31

P01 TIP30/TOP30

P02 NMI

P03 INTP0/ADTRG

P04 INTP1

P05 INTP2/DRST

P06

I/O Port 0

7-bit I/O port

Input/output can be specified in 1-bit units.

INTP3

P10 INTP9

P11

I/O Port 1

2-bit I/O port

Input/output can be specified in 1-bit units.

INTP10

P30 TXDA0

P31 RXDA0/INTP7

P32 ASCKA0/TIP00/TOP00/TOP01

P33 TIP01/TOP01/CTXD0

P34 TIP10/TOP10/CRXD0

P35 TIP11/TOP11

P36 CTXD1

P37 CRXD1

P38 TXDA2

P39

I/O Port 3

10-bit I/O port

Input/output can be specified in 1-bit units.

RXDA2/INTP8

P40 SIB0

P41 SOB0

P42

I/O Port 4

3-bit I/O port

Input/output can be specified in 1-bit units. SCKB0

CHAPTER 2 PIN FUNCTIONS

User’s Manual U17830EE1V0UM00 51

Table 2-8. Pin List (Port Pins V850ES/FG2) (2/2)

Pin Name I/O Function Alternate Function

P50 KR0/TIQ01/TOQ01

P51 KR1/TIQ02/TOQ02

P52 KR2/TIQ03/TOQ03/DDI

P53 KR3/TIQ00/TOQ00/DDO

P54 KR4/DCK

P55

I/O Port 5

6-bit I/O port

Input/output can be specified in 1-bit units.

KR5/DMS

P70 to P715 I/O Port 7

16-bit I/O port

Input/output can be specified in 1-bit units.

ANI0 to ANI15

P90 KR6/TXDA1

P91 KR7/RXDA1

P92 TIQ11/TOQ11

P93 TIQ12/TOQ12

P94 TIQ13/TOQ13

P95 TIQ10/TOQ10

P96 TIP21/TOP21

P97 SIB1/TIP20/TOP20

P98 SOB1

P99 SCKB1

P910 −

P911 −

P912 −

P913 INTP4/PCL

P914 INTP5

P915

I/O Port 9

16-bit I/O port

Input/output can be specified in 1-bit units.

INTP6

PCM0 −

PCM1 CLKOUT

PCM2, PCM3

I/O Port CM

4-bit I/O port

Input/output can be specified in 1-bit units. −

PCS0, PCS1 I/O Port CS

2-bit I/O port

Input/output can be specified in 1-bit units.

−

− PCT0, PCT1,

PCT4, PCT6

I/O Port CT

4-bit I/O port

Input/output can be specified in 1-bit units.

−

PDL0 to PDL4 −

PDL5 FLMD1

PDL6 to PDL13

I/O Port DL

14-bit I/O port

Input/output can be specified in 1-bit units. −

CHAPTER 2 PIN FUNCTIONS

User’s Manual U17830EE1V0UM00

(2) Non-port pins Table 2-9. Pin List (Non-Port Pins V850ES/FG2) (1/3)

Pin Name I/O Function Alternate Function

NMI Input

External interrupt input

(non-maskable, with analog noise eliminated)

P02 Note

INTP0 P03/ADTRG

INTP1 P04

INTP2 P05/DRST

INTP3 P06

INTP4 P913/PCL

INTP5 P914

INTP6 P915

INTP7 P31/RXDA0

INTP8 P39/RXDA2

INTP9 P10

INTP10

Input External interrupt request input

(maskable, with analog noise eliminated)

P11

TIP00 External event/clock input (TMP00) P32/ASCKA0/TOP00/TOP01

TIP01 External event/clock input (TMP01) P33/TOP01/CTXD0

TIP10 External event/clock input (TMP10) P34/TOP10/CRXD0

TIP11 External event/clock input (TMP11) P35/TOP11

TIP20 External event/clock input (TMP20) P97/SIB1/TOP20

TIP21 External event/clock input (TMP21) P96/TOP21

TIP30 External event/clock input (TMP30) P01/TOP30

TIP31

Input

External event/clock input (TMP31) P00/TOP31

TOP00 Timer output (TMP00) P32/ASCKA0/TIP00/TOP01

P32/ASCKA0/TIP00/TOP00 TOP01 Timer output (TMP01)

P33/TIP01/CTXD0

TOP10 Timer output (TMP10) P34/TIP10/CRXD0

TOP11 Timer output (TMP11) P35/TIP11

TOP20 Timer output (TMP20) P97/SIB1/TIP20

TOP21 Timer output (TMP21) P96/TIP21

TOP30 Timer output (TMP30) P01/TIP30

TOP31

Output

Timer output (TMP31) P00/TIP31

TIQ00 External event/clock input (TMQ00) P53/KR3/TOQ00/DDO

TIQ01 External event input (TMQ01) P50/KR0/TOQ01

TIQ02 External event input (TMQ02) P51/KR1/TOQ02

TIQ03

Input

External event input (TMQ03) P52/KR2/TOQ03/DDI

Note: The NMI pin and P02 pin are an alternate-function pin. This pin functions as the P02 pin after if has been

reset. To enable the NMI pin, set the PMC0.PMC02 bit to 1.The initial setting of the NMI pin is "No edge

detected". Select the NMI pin valid edge using INTF0 and INTR0 registers .

CHAPTER 2 PIN FUNCTIONS

User’s Manual U17830EE1V0UM00 53

Table 2-9. Pin List (Non-Port Pins V850ES/FG2) (2/3)

Pin Name I/O Function Alternate Function

TIQ10 External event input (TMQ10) P95/TOQ10

TIQ11 External event input (TMQ11) P92/TOQ11

TIQ12 External event input (TMQ12) P93/TOQ12

TIQ13

Input

External event input (TMQ13) P94/TOQ13

TOQ00 Timer output (TMQ00) P53/KR3/TIQ00/DDO

TOQ01 Timer output (TMQ01) P50/KR0/TIQ01

TOQ02 Timer output (TMQ02) P51/KR1/TIQ02

TOQ03 Timer output (TMQ03) P52/KR2/TIQ03/DDI

TOQ10 Timer output (TMQ10) P95/TIQ10

TOQ11 Timer output (TMQ11) P92/TIQ11

TOQ12 Timer output (TMQ12) P93/TIQ12

TOQ13

Output

Timer output (TMQ13) P94/TIQ13

SIB0 Serial receive data input (CSIB0) P40

SIB1

Input

Serial receive data input (CSIB1) P97/TIP20/TOP20

SOB0 Serial transmit data output (CSIB0) P41

SOB1

Output

Serial transmit data output (CSIB1) P98

SCKB0 Serial clock I/O (CSIB0) P42

SCKB1

I/O

Serial clock I/O (CSIB1) P99

RXDA0 Serial receive data input (UARTA0) P31/INTP7

RXDA1 Serial receive data input (UARTA1) P91/KR7

RXDA2

Input

Serial receive data input (UARTA2) P39/INTP8

TXDA0 Serial transmit data output (UARTA0) P30

TXDA1 Serial transmit data output (UARTA1) P90/KR6

TXDA2

Output

Serial transmit data output (UARTA2) P38

ASCKA0 Input Baud rate clock input to UARTA0 P32/TIP00/TOP00/TOP01

CRXD0 CAN receive data input (CAN0) P34/TIP10/TOP10

CRXD1

Input

CAN receive data input (CAN1) P37

CTXD0 CAN transmit data output (CAN0) P33/TIP01/TOP01

CTXD1

Output

CAN transmit data output (CAN1) P36

ANI0 to ANI15 Input Analog voltage input to A/D converter P70 to P715

AVREF0 Input Reference voltage input to A/D conver ter , and positive power supply

pin for port 7

–

AVSS – Ground potential for A/D converter (same potential as VSS) –

ADTRG Input A/D converter external trigger input P03/INTP0

KR0 P50/TIQ01/TOQ01

KR1 P51/TIQ02/TOQ02

KR2 P52/TIQ03/TOQ03/DDI

KR3 P53/TIQ00/TOQ00/DDO

KR4 P54/DCK

KR5 P55/DMS

KR6

Input Key interrupt input

P90/TXDA1

CHAPTER 2 PIN FUNCTIONS

User’s Manual U17830EE1V0UM00

KR7 P91/RXDA1

Table 2-9. Pin List (Non-Port Pins V850ES/FG2) (3/3)

Pin Name I/O Function Alternate Function

DMS Input Debug mode select P55/KR5

DDI Input Debug data input P52/KR2/TIQ03/TOQ03

DDO Output Debug data output P53/KR3/TIQ00/TOQ00

DCK Input Debug clock input P54/KR4

DRST Input Debug reset input P05/INTP2

FLMD0 −

FLMD1

Input Flash programming mode setting pins

PDL5

CLKOUT Output Inter nal system clock output PCM1

PCL Output Clock output (timing output of X1 input clock and subclock) P913/INTP4

REGC − Regulator output stabilizing capacitor connection −

RESET Input System reset input −

X1 Input −

X2 −

Main clock resonator connection

−

XT1 Input −

XT2 −

Subclock resonator connection

−

VDD − Positive power supply pin for internal circuitry −

VSS − Ground potential for internal circuitry −

EVDD − Positive power supply pin for external circuitry (same potential as

VDD)

−

EVSS − Ground potential for external circuitry (same potential as VSS) −

BVDD − Positive power supply pin for external circuitry (same potential as

VDD)

−

BVSS − Ground potential for external circuitry (same potential as VSS) −

CHAPTER 2 PIN FUNCTIONS

User’s Manual U17830EE1V0UM00 55

2.1.4 V850ES/FJ2

Three I/O buffer power supplies, AVREF0, BVDD, and EVDD, are available. The relationship between the power

supplies and the pins is shown below.

Table 2-10. Pin I/O Buffer Power Supplies (V850ES/FJ2)

Power Supply Corresponding Pin

AVREF0 Port 7, Port 12

BVDD Port CD, Port CM Port CS, Port CT, Port DL

EVDD Port 0, Port 1, Port 3, Port 4, Port 5, Port 6, Port 8, Port 9, RESET

CHAPTER 2 PIN FUNCTIONS

User’s Manual U17830EE1V0UM00

(1) Port pins

Table 2-11. Pin List (Port Pins) (1/3)

Pin Name I/O Function Alternate Function

P00 TIP31/TOP31

P01 TIP30/TOP30

P02 NMI

P03 INTP0/ADTRG

P04 INTP1

P05 INTP2/DRST

P06

I/O Port 0

7-bit I/O port

Input/output can be specified in 1-bit units.

INTP3

P10 I/O INTP9

P11

Port 1

2-bit I/O port

Input/output can be specified in 1-bit units. INTP10

P30 TXDA0

P31 RXDA0/INTP7

P32 ASCKA0/TIP00/TOP00/TOP01

P33 TIP01/TOP01/CTXD0

P34 TIP10/TOP10/CRXD0

P35 TIP11/TOP11

P36 CTXD1

P37 CRXD1

P38 TXDA2

P39

I/O Port 3

10-bit I/O port

Input/output can be specified in 1-bit units.

RXDA2/INTP8

P40 SIB0

P41 SOB0

P42

I/O Port 4

3-bit I/O port

Input/output can be specified in 1-bit units. SCKB0

P50 KR0/TIQ01/TOQ01

P51 KR1/TIQ02/TOQ02

P52 KR2/TIQ03/TOQ03/DDI

P53 KR3/TIQ00/TOQ00/DDO

P54 KR4/DCK

P55

I/O Port 5

6-bit I/O port

Input/output can be specified in 1-bit units.

KR5/DMS

CHAPTER 2 PIN FUNCTIONS

User’s Manual U17830EE1V0UM00 57

Table 2-11. Pin List (Port Pins) (2/3)

Pin Name I/O Function Alternate Function

P60 INTP11

P61 INTP12

P62 INTP13

P63 −

P64 −

P65 CTXD2Note 1

P66 CRXD2Note 1

P67 CTXD3Note 1

P68 CRXD3Note 1

P69 −

P610 TIQ20/TOQ20

P611 TIQ21/TOQ21

P612 TIQ22/TOQ22

P613 TIQ23/TOQ23

P614 −

P615

I/O Port 6

16-bit I/O port

Input/output can be specified in 1-bit units.

−

P70 to P715 I/O Port 7

16-bit I/O port

Input/output can be specified in 1-bit units.

ANI0 to ANI15

P80 RXDA3/INTP14Note 2

P81

I/O Port 8

2-bit I/O port

Input/output can be specified in 1-bit units. TXDA3Note 2

P90 KR6/TXDA1

P91 KR7/RXDA1

P92 TIQ11/TOQ11

P93 TIQ12/TOQ12

P94 TIQ13/TOQ13

P95 TIQ10/TOQ10

P96 TIP21/TOP21

P97 SIB1/TIP20/TOP20

P98 SOB1

P99 SCKB1

P910 SIB2

P911 SOB2

P912 SCKB2

P913 INTP4/PCL

P914 INTP5

P915

I/O Port 9

16-bit I/O port

Input/output can be specified in 1-bit units.

INTP6

Notes 1. In the

PD70F3237, alternate functions of the P65 to P68 p ins (CTXD2, CRXD2, CTXD3, and CRXD 3)

are not available.

2. In the

PD70F3237, the alternate functions of the P80 and P81 pins (RXDA3 and TXDA3) are not

available. The alternate function of the P80 pin in the

PD70F3237 is INTP14 only.

CHAPTER 2 PIN FUNCTIONS

User’s Manual U17830EE1V0UM00

Table 2-11. Pin List (Port Pins) (3/3)

Pin Name I/O Function Alternate Function

P120 to P127

I/O Port 12

8-bit I/O port

Input/output can be specified in 1-bit units.

ANI16 to ANI23

PCD0 to PCD3

I/O Port CD

4-bit I/O port

Input/output can be specified in 1-bit units.

−

PCM0 WAIT

PCM1 CLKOUT

PCM2 HLDAK

PCM3 HLDRQ

PCM4 −

PCM5

I/O Port CM

6-bit I/O port

Input/output can be specified in 1-bit units.

−

PCS0 to PCS3 CS0 to CS3

PCS4 to PCS7

I/O Port CS

8-bit I/O port

Input/output can be specified in 1-bit units.

−

PCT0 WR0

PCT1 WR1

PCT2 −

PCT3 −

PCT4 RD

PCT5 −

PCT6 ASTB

PCT7

I/O Port CT

8-bit I/O port

Input/output can be specified in 1-bit units.

−

PDL0 to PDL4 AD0 to AD4

PDL5 AD5/FLMD1

PDL6 to PDL15

I/O Port DL

16-bit I/O port

Input/output can be specified in 1-bit units. AD6 to AD15

CHAPTER 2 PIN FUNCTIONS

User’s Manual U17830EE1V0UM00 59

(2) Non-port pins

Table 2-12. Pin List (Non-Port Pins) (1/4)

Pin Name I/O Function Alternate Function

NMI Note 1 Input

External interrupt input

(non-maskable, with analog noise eliminated)

P02 Note 1

INTP0 P03/ADTRG

INTP1 P04

INTP2 P05/DRST

INTP3 P06

INTP4 P913/PCL

INTP5 P914

INTP6 P915

INTP7 P31/RXDA0

INTP8 P39/RXDA2

INTP9 P10

INTP10 P11

INTP11 P60

INTP12 P61

INTP13 P62

INTP14

Input External interrupt request input

(maskable, with analog noise eliminated)

P80/RXDA3No te 2

TIP00 External event/clock input (TMP00) P32/ASCKA0/TOP00/TOP01

TIP01 External event input (TMP01) P33/TOP01/CTXD0

TIP10 External event/clock input (TMP10) P34/TOP10/CRXD0

TIP11 External event input (TMP11) P35/TOP11

TIP20 External event/clock input (TMP20) P97/SIB1/TOP20

TIP21 External event input (TMP21) P96/TOP21

TIP30 External event/clock input (TMP30) P01/TOP30

TIP31

Input

External event input (TMP31) P00/TOP31

TOP00 Timer output (TMP00) P32/ASCKA0/TIP00/TOP01

P32/ASCKA0/TIP00/TOP00 TOP01 Timer output (TMP01)

P33/TIP01/CTXD0

TOP10 Timer output (TMP10) P34/TIP10/CRXD0

TOP11 Timer output (TMP11) P35/TIP11

TOP20 Timer output (TMP20) P97/SIB1/TIP20

TOP21 Timer output (TMP21) P96/TIP21

TOP30 Timer output (TMP30) P01/TIP30

TOP31

Output

Timer output (TMP31) P00/TIP31

Notes 1. The NMI pin and P02 pin are an alternate-function pin. This pin functions as the P02 pin after if has

been reset. To enable the NMI pin, set the PMC0.PMC02 bit to 1.The initial setting of the NMI pin is "No

edge detected". Select the NMI pin valid edge using INTF0 and INTR0 registers.

2. In the µPD70F3237, the alternate functions of the P80 and P81 pins (RXDA3 and TXDA3) are not

available. The alternate function of the P80 p in in the µPD70F3237 is only INTP14.

CHAPTER 2 PIN FUNCTIONS

User’s Manual U17830EE1V0UM00

Table 2-12. Pin List (Non-Port Pins) (2/4)

Pin Name I/O Function Alternate Function

TIQ00 External event/clock input (TMQ00) P53/KR3/TOQ00/DDO

TIQ01 External event input (TMQ01) P50/KR0/TOQ01

TIQ02 External event input (TMQ02) P51/KR1/TOQ02

TIQ03 External event input (TMQ03) P52/KR2/TOQ03/DDI

TIQ10 External event input (TMQ10) P95/TOQ10

TIQ11 External event input (TMQ11) P92/TOQ11

TIQ12 External event input (TMQ12) P93/TOQ12

TIQ13 External event input (TMQ13) P94/TOQ13

TIQ20 External event/clock input (TMQ20) P610/TOQ20

TIQ21 External event input (TMQ21) P611/TOQ21

TIQ22 External event input (TMQ22) P612/TOQ22

TIQ23

Input

External event input (TMQ23) P613/TOQ23

TOQ00 Timer output (TMQ00) P53/KR3/TIQ00/DDO

TOQ01 Timer output (TMQ01) P50/KR0/TIQ01

TOQ02 Timer output (TMQ02) P51/KR1/TIQ02

TOQ03 Timer output (TMQ03) P52/KR2/TIQ03/DDI

TOQ10 Timer output (TMQ10) P95/TIQ10

TOQ11 Timer output (TMQ11) P92/TIQ11

TOQ12 Timer output (TMQ12) P93/TIQ12

TOQ13 Timer output (TMQ13) P94/TIQ13

TOQ20 Timer output (TMQ20) P610/TIQ20

TOQ21 Timer output (TMQ21) P611/TIQ21

TOQ22 Timer output (TMQ22) P612/TIQ22

TOQ23

Output

Timer output (TMQ23) P613/TIQ23

SIB0 Serial receive data input (CSIB0) P40

SIB1 Serial receive data input (CSIB1) P97/TIP20/TOP20

SIB2

Input

Serial receive data input (CSIB2) P910

SOB0 Serial transmit data output (CSIB0) P41

SOB1 Serial transmit data output (CSIB1) P98

SOB2

Output

Serial transmit data output (CSIB2) P911

SCKB0 Serial clock I/O (CSIB0) P42

SCKB1 Serial clock I/O (CSIB1) P99

SCKB2

I/O

Serial clock I/O (CSIB2) P912

RXDA0 Serial receive data input (UARTA0) P31/INTP7

RXDA1 Serial receive data input (UARTA1) P91/KR7

RXDA2 Serial receive data input (UARTA2) P39/INTP8

RXDA3Note

Input

Serial receive data input (UARTA3) P80/INTP14

TXDA0 Serial transmit data output (UARTA0) P30

TXDA1 Serial transmit data output (UARTA1) P90/KR6

TXDA2 Serial transmit data output (UARTA2) P38

TXDA3Note

Output

Serial transmit data output (UARTA3) P81

Note In the

PD70F3237, the alternate functio ns of the P80 and P81 pins (RXDA3 and TXDA3) are not available.

CHAPTER 2 PIN FUNCTIONS

User’s Manual U17830EE1V0UM00 61

Table 2-12. Pin List (Non-Port Pins) (3/4)

Pin Name I/O Function Alternate Function

ASCKA0 Input Baud rate clock input to UARTA0 P32/TIP00/TOP00/TOP01

CRXD0 CAN receive data input (CAN0) P34/TIP10/TOP10

CRXD1 CAN receive data input (CAN1) P37

CRXD2Note CAN receive data input (CAN2) P66

CRXD3Note

Input

CAN receive data input (CAN3) P68

CTXD0 CAN transmit data output (CAN0) P33/TIP01/TOP01

CTXD1 CAN transmit data output (CAN1) P36

CTXD2Note CAN transmit data output (CAN2) P65

CTXD3Note

Output

CAN transmit data output (CAN3) P67

ANI0 to ANI15 P70 to P715

ANI16 to ANI23

Input Analog voltage input to A/D converter

P120 to P127

AVREF0 Input Reference voltage input to A/D converter, and positive power supply

pin for port 7

−

AVSS − Ground potential for A/D converter（same potential as VSS） −

ADTRG Input A/D converter external trigger input P03/INTP0

KR0 P50/TIQ01/TOQ01

KR1 P51/TIQ02/TOQ02

KR2 P52/TIQ03/TOQ03/DDI

KR3 P53/TIQ00/TOQ00/DDO

KR4 P54/DCK

KR5 P55/DMS

KR6 P90/TXDA1

KR7

Input Key interrupt input

P91/RXDA1

DMS Input Debug mode select P55/KR5

DDI Input Debug data input P52/KR2/TIQ03/TOQ03

DDO Output Debug data output P53/KR3/TIQ00/TOQ00

DCK Input Debug clock input P54/KR4

DRST Input Debug reset input P05/INTP2

CS0 to CS3 Output Chip select signal output PCS0 to PCS3

AD0 to AD4 PDL0 to PDL4

AD5 PDL5/FLMD1

AD6 to AD15

I/O Address/data bus for external memory

PDL6 to PDL15

ASTB Output Address strobe signal output to external memory PCT6

HLDRQ Input Bus hold request input PCM3

HLDAK Output Bus hold acknowledge output PCM2

RD Output Read strobe signal output to external memory PCT4

WAIT Input External wait input PCM0

WR0 Write strobe to external memory (lower 8 bits) PCT0

WR1

Output

Write strobe to external memory (higher 8 bits) PCT1

Note In the

PD70F3237, the alternate functions of the P65 to P68 pins (CTXD2, CRXD2, CTXD3, and CRX D3)

are not available.

CHAPTER 2 PIN FUNCTIONS

User’s Manual U17830EE1V0UM00

Table 2-12. Pin List (Non-Port Pins) (4/4)

Pin Name I/O Function Alternate Function

FLMD0 −

FLMD1

Input Flash programming mode setting pins

PDL5/AD5

CLKOUT Output

Internal system clock output PCM1

PCL Output Clock output (timing output of X1 input clock and subclock) P913/INTP4

REGC − Regulator output stabilizing capacitor connection −

RESET Input System reset input −

X1 Input −

X2 −

Main clock resonator connection

−

XT1 Input −

XT2 −

Subclock resonator connection

−

VDD − Positive power supply pin for internal circuitry −

VSS − Ground potential for internal circuitry −

BVDD − Positive power supply for bus interface and port −

BVSS − Ground potential for bus interface and port −

EVDD − Positive power supply pin for external circuitry (same potential as VDD) −

EVSS − Ground potential for external circuitry (same potential as VSS) −

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2.2 Pin Status (V850ES/FJ2)

The V850ES/FJ2 has an external bus interface function that enables connection of external memories, such as

ROM and RAM, and I/O.

Table 2-4 shows the operating status of each external bus interface pin in each operation mode.

Table 2-13. Pin Operating Status in Each Operation Mode

Bus Control Pin Reset HALT Mode and

DMA Transfer IDLE1, IDLE2, and

Software STOP

Modes

Idle StateNote 2 Bus Hold

AD0 to AD15 Hi-Z

CS0 to CS3 H

Held Hi-Z

WAIT − − −

CLKOUT L Operating Operating

WR0, WR1

ASTB

Hi-Z

HLDAK

H H

HLDRQ

Hi-ZNote Operating

− − Operating

Notes 1. The bus control pins function alternately as port pins and are initialized to the input mode (port mode).

2. Pin status in the idle state that is inserted after the T3 state.

Remark Hi-Z: High impedance

Held: The state during the immediately preceding external bus cycle is held.

L: Low-level output

H: High-level outp ut

−: Input without sampling (not acknowledged)

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2.3 Description of Pin Functions

2.3.1 V850ES/FE2

(1) P00 to P06 (port 0) … 3-state I/O

P00 to P06 function as a 7-bit I/O port that can be set to input or output in 1-bit units.

Besides functioning as an I/O port, these pins operate as NMI input, external interrupt request signal input,

timer/counter I/O, external trigger of the A/D converter, and debug reset input.

This port can be set in the port mode or control mode in 1-bit units. The valid edge of each pin is specified by

the INTR0 and INTF0 registers.

An on-chip pull-up resistor can be connected to P00 to P06 by using pull-up resistor option register 0 (PU0).

(a) Port mode

P00 to P06 can be set in the input or output mode in 1-bit units, by using port mode register 0 (PM0).

(b) Control mode

(i) NMI (Non-maskable interrupt request) … input

This pin inputs a non-maskable interrupt request signal.

(ii) INTP0 to INTP3 (Interrupt request from peripherals) … input

These pins input external interrupt request signals.

(iii) TIP30, TIP31 (Timer input) … input

These pins input to timers P3 (TMP3).

(iv) TOP30, TOP31 (Timer output) … output

These pins output from timers P3 (TMP3).

(v) ADTRG (A/D trigger input) … input

This pin inputs an external trigger to the A/ D converter. It is controlled by using A/D converter mode

(vi) DRST (Debug reset) … input

This pin inputs a debug reset signal, a ne gative-logic signal that asynchron ously initializes the on-chip

debug circuit. To deassert this signal, reset or invalidate the on-chip debug circuit. Deassert this

signal when the debug function is not used.

For details, refer to CHAPTER 27 ON-CHIP DEBUG FUNCTION (ON-CHIP DEBUG UNIT).

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User’s Manual U17830EE1V0UM00 65

(2) P30 to P35 (port 3) … 3-state output

P30 to P35 function as a 6-bit I/O port that can be set to input or output in 1-bit units.

Besides functioning as an I/O port, these pins operate as external interrupt request signal input, ser ial int erface

I/O, timer/counter I/O, and CAN data I/O. This port can be set in the port mode or control mode in 1-bit units.

The valid edge of each pin is specified by using INTR3 and INTF3 registers.

An on-chip pull-up resistor can be connected to P30 to P35 by using pull-up resistor option register 3 (PU3).

(a) Port mode

P30 to P35 can be set in the input or output mode in 1-bit units, by using port mode register 3 (PM3).

(b) Control mode

(i) RXDA0 (Receive data) … input

These pins input the serial receive data of UARTA0.

(ii) TXDA0 (Transmit data) … output

These pins output the serial transmit data of UARTA0.

(iii) ASCKA0 (Asynchronous serial clock) … input

This pin inputs UARTA0.

(iv) INTP7 (Interrupt request from peripherals) … input

These pins input an external interrupt request signal.

(v) TIP00, TIP01, TIP10, TIP11 (Timer input) … input

These pins input to timers P0 and P1 (TMP0, TMP1).

(vi) TOP00, TOP01, TOP10, TOP11 (Timer output) … output

These pins output from timers P0 and P1 (TMP0, TMP1).

(vii) CRXD0 (CAN receive data) … input

These pins input the receive data of CAN0.

(viii) CTXD0 (CAN transmit data) … output

These pins output the transmit data of CAN0.

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User’s Manual U17830EE1V0UM00

(3) P40 to P42 (port 4) … 3-state I/O

P40 to P42 function as a 3-bit I/O port that can be set to input or output in 1-bit units.

Besides functioning as an I/O port, these pins operate as serial interface I/O. This port can be set in the port

mode or control mode in 1-bit units.

An on-chip pull-up resistor can be connected to P40 to P42 by using pull-up resistor option register 4 (PU4).

(a) Port mode

P40 to P42 can be set in the input or output mode in 1-bit units, by using port mode register 4 (PM4).

(b) Control mode

(i) SIB0 (Serial input) … input

This pin inputs the serial receive data of CSIB0.

(ii) SOB0 (Serial output) … output

This pin outputs the serial transmit data of CSIB0.

(iii) SCKB0 (serial clock) … 3-state I/O

This pin inputs/outputs the serial clock of CSIB0.

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User’s Manual U17830EE1V0UM00 67

(4) P50 to P55 (Port 5) … 3-state I/O

P50 to P55 function as a 6-bit I/O port that can be set to input or output in 1-bit units.

Besides functioning as an I/O port, these pins operate as an I/O port, but also as timer/counter I/O, debug

function I/O, and key interrupt input. This port can be set in the port mode or control mode in 1-bit units.

An on-chip pull-up resistor can be connected to P50 to P55 by using pull-up resistor option register 5 (PU5).

(a) Port mode

P50 to P55 can be set in the input or output mode in 1-bit units, by using port mode register 5 (PM5).

(b) Control mode

(i) KR0 to KR5 (Key return) … input

These pins input a key interrupt. Their operation is specified by using the key return mode register

(KRM) in the input port mode.

(ii) TIQ00, TIQ01, TIQ02, TIQ03 (Timer input) … input

These pins input to timers Q0 (TMQ0).

(iii) TOQ00, TOQ01, TOQ02, TOQ03 (Timer output) … output

These pins output from timers Q0 (TMQ0).

(iv) DDI (Debug data input) … input

This pin inputs debug dat a to the on-chip debug circuit.

For details, refer to CHAPTER 27 ON-CHIP DEBUG FUNCTION (ON-CHIP DEBUG UNIT).

(v) DDO (Debug data output) … output

This pin outputs debug data from the on-chip debug circuit.

For details, refer to CHAPTER 27 ON-CHIP DEBUG FUNCTION (ON-CHIP DEBUG UNIT).

(iv) DCK (Debug clock input) … input

This pin inputs a debug clock t o the on-ch ip debug circuit.

For details, refer to CHAPTER 27 ON-CHIP DEBUG FUNCTION (ON-CHIP DEBUG UNIT).

(vii) DMS (Debug mode select) … input

This pin selects the debug mode of the on-chip debug circuit.

For details, refer to CHAPTER 27 ON-CHIP DEBUG FUNCTION (ON-CHIP DEBUG UNIT).

(5) P70 to P79 (Port 7) … 3-state I/O

P70 to P79 function as a 10-bit I/O port that can be set to input or output in 1-bit units.

Besides functioning as an I/O port, these pins operate as the analog input pins of the A/D converter in the

control mode. When using this port as analog input pins, however, set the port in the input mode. At this time,

do not read the port.

(a) Port mode

P70 to P79 can be set in the input or output mode in 1- bit units, by using port mode regist er 7L, H (PM7L,

PM7H)

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User’s Manual U17830EE1V0UM00

(b) Control mode

P70 to P79 function alternately as the ANI0 to ANI9 pins.

(i) ANI0 to ANI9 (Analog input 0 to 9) … input

These pins input an analog signal to the A/D converter.

(6) P90, P91, P96 to P99, P913 to P915 (Port 9) … 3-state I/O

P90, P91, P96 to P99, P913 to P915 function as a 9-bit I/O port that can be set to input or output in 1-bit units.

Besides functioning as an I/O port, these pins operate as serial interface I/O, timer/counter I/O, clock output,

external interrupt request sign al input, and key interrupt input. This port c an be set in the port mode or control

mode in 1-bit units. The valid edge of P913 t o P915 is speci fied by using INTF9H register.

An on-chip pull- up resistor can be connected to P90, P 91, P96 to P99, P913 to P915 b y using pull-up resistor

option register 9 (PU9).

(a) Port mode

P90, P91, P96 to P99, P913 to P915 can be set in the input or output mode in 1-bit units, by using port 9

mode register (PM9).

(b) Control mode

(i) SIB1 (Serial input) … input

These pins input the serial receive data of CSIB1.

(ii) SOB1 (Serial output) … output

These pins output the serial receive data of CSIB1.

(iii) SCKB1 (Serial clock) … 3-state I/O

These pins input/output the serial clock of CSIB1.

(iv) RXDA1 (Receive data) … input

This pin inputs the serial receive data of UARTA1.

(v) TXDA1 (Transmit data) … output

This pin outputs the serial transmit data of UARTA1.

(vi) TIP20, TIP21 (Timer input) … input

These pins input to timers P2 (TMP2).

(vii) TOP20, TOP21 (Timer output) … output

These pins output from timers P2 (TMP2).

(viii) PCL (Clock output) … output

This pin outputs a clock.

(ix) INTP4 to INTP6 (Interrupt request from peripherals) … input

These pins input an external interrupt request signal.

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User’s Manual U17830EE1V0UM00 69

(x) KR6, KR7 (Key return) … input

These pins input a key interrupt. Their opera t ion is specified by the key return mod e register (KRM) in

the input port mode.

(7) PCM0, PCM1 (port CM) … 3-state I/O

PCM0, PCM1 function as a 2-bit I/O port that can be set to input or output in 1-bit units.

Besides functioning as an I/O port, and bus clock output.

(a) Port mode

PCM0, PCM1 can be set in the input or output mode in 1-bit units, by using port mode register CM

(PMCM).

(b) Control mode

(i) CLKOUT (Clock output) … output

This pin outputs an internally generated bus clock.

(8) PDL0 to PDL7 (port DL) … 3-state I/O

PDL0 to PDL7 function as an 8-bit I/O port that can be set to input or output in 1-bit units.

PDL5 also functions as the FLMD1 pin when the flash memory is programmed (when a high level is input to

FLD0). At this time, be sure to input a low level to the FLMD1 pin.

(a) Port mode

PDL0 to PDL7 can be set in the input or output mode in 1-bit units, by using port mode register DL (PMDL).

(9) RESET (Reset) … input

RESET input is asynchronous input. When a signal with a fixed low level width is input to the RESET pin

regardless of the operating clock, the system is reset, taking precedence over all the other operations.

This pin is used to release the standby mod e (HALT, IDLE, or STOP), as well as for normal initialization/start.

(10) X1, X2 (Crystal for main clock)

These pins are used to connect the resonator that generates the system clock.

(11) XT1, XT2 (Crystal for subclock)

These pins are used to connect the resonator that generates the subclock.

(12) AVSS (Ground for analog)

This is a ground pin for the A/D converter, and alter nate-function ports.

(13) AVREF0 (Analog reference voltage) … input

This pin supplies positive ana log power to the A/D converter and alternate-function ports.

It also supplies a reference voltage to the A/ D converter.

(14) EVDD (Power supply for port)

This pin supplies positive power to the I/O ports and alternate-function pins.

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User’s Manual U17830EE1V0UM00

(15) EVSS (Ground for port)

This is a ground pin for the I/O ports and alternate-function pins.

(16) VDD (Power supply)

This pin supplies positive po wer. Connect all the VDD pins to a positive power supply.

(17) VSS (Ground)

This is a ground pin. Connect all the VSS pins to ground.

(18) FLMD0 (Flash programming mode) Input

This is a signal input pin for flash memory programming mo de. Connect this pin to VSS in the normal op eration

mode.

(19) REGC (Regulator control) … input

This pin connects a capacitor for the regulato r.

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User’s Manual U17830EE1V0UM00 71

2.3.2 V850ES/FF2

(1) P00 to P06 (port 0) … 3-state I/O

P00 to P06 function as a 7-bit I/O port that can be set to input or output in 1-bit units.

Besides functioning as an I/O port, these pins operate as NMI input, external interrupt request signal input,

timer/counter I/O, external trigger of the A/D converter, and debug reset input.

This port can be set in the port mode or control mode in 1-bit units. The valid edge of each pin is specified by

the INTR0 and INTF0 registers.

An on-chip pull-up resistor can be connected to P00 to P06 by using pull-up resistor option register 0 (PU0).

(a) Port mode

P00 to P06 can be set in the input or output mode in 1-bit units, by using port mode register 0 (PM0).

(b) Control mode

(i) NMI (Non-maskable interrupt request) … input

This pin inputs a non-maskable interrupt request signal.

(ii) INTP0 to INTP3 (Interrupt request from peripherals) … input

These pins input external interrupt request signals.

(iii) TIP30, TIP31 (Timer input) … input

These pins input to timers P3 (TMP3).

(iv) TOP30, TOP31 (Timer output) … output

These pins output from timers P3 (TMP3).

(v) ADTRG (A/D trigger input) … input

This pin inputs an external trigger to the A/ D converter. It is controlled by using A/D converter mode

(vi) DRST (Debug reset) … input

This pin inputs a debug reset signal, a ne gative-logic signal that asynchron ously initializes the on-chip

debug circuit. To deassert this signal, reset or invalidate the on-chip debug circuit. Deassert this

signal when the debug function is not used.

For details, refer to CHAPTER 27 ON-CHIP DEBUG FUNCTION (ON-CHIP DEBUG UNIT).

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User’s Manual U17830EE1V0UM00

(2) P30 to P35, P38, P39 (port 3) … 3-state output

P30 to P35, P38, P39 function as an 8-bit I/O port that can be set to input or output in 1-bit units.

Besides functioning as an I/O port, these pins operate as external interrupt request signal input, ser ial int erface

I/O, timer/counter I/O, and CAN data I/O. This port can be set in the port mode or control mode in 1-bit units.

The valid edge of each pin is specified by using INTR3 and INTF3 registers.

An on-chip pull-up resistor can be connecte d to P30 to P35, P38, P39 by using pull-up resistor option register

3 (PU3).

(a) Port mode

P30 to P35, P38, P39 can be set in the input or output mode in 1-bit units, by using port mode register 3

(PM3).

(b) Control mode

(i) RXDA0 (Receive data) … input

These pins input the serial receive data of UARTA0.

(ii) TXDA0 (Transmit data) … output

These pins output the serial transmit data of UARTA0.

(iii) ASCKA0 (Asynchronous serial clock) … input

This pin inputs of UARTA0.

(iv) INTP7 (Interrupt request from peripherals) … input

These pins input an external interrupt request signal.

(v) TIP00, TIP01, TIP10, TIP11 (Timer input) … input

These pins input to timers P0, P1 (TMP0, TMP1).

(vi) TOP00, TOP01, TOP10, TOP11 (Timer output) … output

These pins output from timers P0, P1 (TMP0, TMP1).

(vii) CRXD0 (CAN receive data) … input

These pins input the receive data of CAN0.

(viii) CTXD0 (CAN transmit data) … output

These pins output the transmit data of CAN0.

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User’s Manual U17830EE1V0UM00 73

(3) P40 to P42 (port 4) … 3-state I/O

P40 to P42 function as a 3-bit I/O port that can be set to input or output in 1-bit units.

Besides functioning as an I/O port, these pins operate as serial interface I/O. This port can be set in the port

mode or control mode in 1-bit units.

An on-chip pull-up resistor can be connected to P40 to P42 by using pull-up resistor option register 4 (PU4).

(a) Port mode

P40 to P42 can be set in the input or output mode in 1-bit units, by using port mode register 4 (PM4).

(b) Control mode

(i) SIB0 (Serial input) … input

This pin inputs the serial receive data of CSIB0.

(ii) SOB0 (Serial output) … output

This pin outputs the serial transmit data of CSIB0.

(iii) SCKB0 (serial clock) … 3-state I/O

This pin inputs/outputs the serial clock of CSIB0.

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(4) P50 to P55 (Port 5) … 3-state I/O

P50 to P55 function as a 6-bit I/O port that can be set to input or output in 1-bit units.

Besides functioning as an I/O port, these pins operate as an I/O port, but also as timer/counter I/O, debug

function I/O, and key interrupt input. This port can be set in the port mode or control mode in 1-bit units.

An on-chip pull-up resistor can be connected to P50 to P55 by using pull-up resistor option register 5 (PU5).

(a) Port mode

P50 to P55 can be set in the input or output mode in 1-bit units, by using port mode register 5 (PM5).

(b) Control mode

(i) KR0 to KR5 (Key return) … input

These pins input a key interrupt. Their operation is specified by using the key return mode register

(KRM) in the input port mode.

(ii) TIQ00, TIQ01, TIQ02, TIQ03 (Timer input) … input

These pins input to timers Q0 (TMQ0).

(iii) TOQ00, TOQ01, TOQ02, TOQ03 (Timer output) … output

These pins output from timers Q0 (TMQ0).

(iv) DDI (Debug data input) … input

This pin inputs debug dat a to the on-chip debug circuit.

For details, refer to CHAPTER 27 ON-CHIP DEBUG FUNCTION (ON-CHIP DEBUG UNIT).

(v) DDO (Debug data output) … output

This pin outputs debug data from the on-chip debug circuit.

For details, refer to CHAPTER 27 ON-CHIP DEBUG FUNCTION (ON-CHIP DEBUG UNIT).

(iv) DCK (Debug clock input) … input

This pin inputs a debug clock t o the on-ch ip debug circuit.

For details, refer to CHAPTER 27 ON-CHIP DEBUG FUNCTION (ON-CHIP DEBUG UNIT).

(vii) DMS (Debug mode select) … input

This pin selects the debug mode of the on-chip debug circuit.

For details, refer to CHAPTER 27 ON-CHIP DEBUG FUNCTION (ON-CHIP DEBUG UNIT).

(5) P70 to P711 (Port 7) … 3-state I/O

P70 to P711 function as a 12-bit I/O port that can be set to input or output in 1-bit units.

Besides functioning as an I/O port, these pins operate as the analog input pins of the A/D converter in the

control mode. When using this port as analog input pins, however, set the port in the input mode. At this time,

do not read the port.

(a) Port mode

P70 to P711 can be set in the input or output mode in 1-bit units, by using port mode register 7L, H (PM7L,

PM7H).

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User’s Manual U17830EE1V0UM00 75

(b) Control mode

P70 to P711 function alternately as the ANI0 to ANI11 pins.

(i) ANI0 to ANI11 (Analog input 0 to 11) … input

These pins input an analog signal to the A/D converter.

(6) P90, P91, P96 to P99, P913 to P915 (Port 9) … 3-state I/O

P90, P91, P96 to P99, P913 to P915 function as a 9-bit I/O port that can be set to input or output in 1-bit units.

Besides functioning as an I/O port, these pins operate as serial interface I/O, timer/counter I/O, clock output,

external interrupt request sign al input, and key interrupt input. This port c an be set in the port mode or control

mode in 1-bit units. The valid edge of P913 t o P915 is speci fied by using INTF9H register.

An on-chip pull- up resistor can be connected to P90, P 91, P96 to P99, P913 to P915 b y using pull-up resistor

option register 9 (PU9).

(a) Port mode

P90, P91, P96 to P99, P913 to P915 can be set in the input or output mode in 1-bit units, by using port 9

mode register (PM9).

(b) Control mode

(i) SIB1 (Serial input) … input

These pins input the serial receive data of CSIB1.

(ii) SOB1 (Serial output) … output

These pins output the serial receive data of CSIB1.

(iii) SCKB1 (Serial clock) … 3-state I/O

These pins input/output the serial clock of CSIB1.

(iv) RXDA1 (Receive data) … input

This pin inputs the serial receive data of UARTA1.

(v) TXDA1 (Transmit data) … output

This pin outputs the serial transmit data of UARTA1.

(vi) TIP20, TIP21 (Timer input) … input

These pins input to timers P2 (TMP2).

(vii) TOP20, TOP21 (Timer output) … output

These pins output from timers P2 (TMP2).

(viii) PCL (Clock output) … output

This pin outputs a clock.

(ix) INTP4 to INTP6 (Interrupt request from peripherals) … input

These pins input an external interrupt request signal.

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(x) KR6, KR7 (Key return) … input

These pins input a key interrupt. Their opera t ion is specified by the key return mod e register (KRM) in

the input port mode.

(7) PCM0 to PCM3 (port CM) … 3-state I/O

PCM0 to PCM3 function as a 4-bit I/O port that can be set to input or output in 1-bit units.

Besides functioning as an I/O port, and bus clock output.

(a) Port mode

PCM0 to PCM3 can be set in the input or output mode in 1-bit units, by using port mode register CM

(PMCM).

(b) Control mode

(i) CLKOUT (Clock output) … output

This pin outputs an internally generated bus clock.

(13) PCS0, PCS1 (port CS) … 3-state I/O

PCS0, PCS1 function as a 2-bit I/O port that can be set to input or output in 1-bit units.

Besides functioning as an I/O port.

(a) Port mode

PCS0, PCS1 can be set in the input or output mode in 1-bit units, by using port mode register CS (PMCS).

(14) PCT0, PCT1, PCT4, PCT6 (port CT) … 3-state I/O

PCT0, PCT1, PCT4, PCT6 function as an 4-bit I/O port that can be set to input or output in 1-bit units.

Besides functioning as an I/O port.

(a) Port mode

PCT0, PCT1, PCT4, PCT6 can be set in the input or output mode in 1-bit units, by using port mode

(8) PDL0 to PDL11 (port DL) … 3-state I/O

PDL0 to PDL11 function as a 12-bit I/O port that can be set to input or output in 1-bit units.

PDL5 also functions as the FLMD1 pin when the flash memory is programmed (when a high level is input to

FLD0). At this time, be sure to input a low level to the FLMD1 pin.

(a) Port mode

PDL0 to PDL11 can be set in the input or output mode in 1-bit units, by using port mode register DL

(PMDL).

(9) RESET (Reset) … input

RESET input is asynchronous input. When a signal with a fixed low level width is input to the RESET pin

regardless of the operating clock, the system is reset, taking precedence over all the other operations.

This pin is used to release the standby mod e (HALT, IDLE, or STOP), as well as for normal initialization/start.

(10) X1, X2 (Crystal for main clock)

These pins are used to connect the resonator that generates the system clock.

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User’s Manual U17830EE1V0UM00 77

(11) XT1, XT2 (Crystal for subclock)

These pins are used to connect the resonator that generates the subclock.

(12) AVSS (Ground for analog)

This is a ground pin for the A/D converter, and alter nate-function ports.

(13) AVREF0 (Analog reference voltage) … input

This pin supplies positive ana log power to the A/D converter and alternate-function ports.

It also supplies a reference voltage to the A/ D converter.

(14) EVDD (Power supply for port)

This pin supplies positive power to the I/O ports and alternate-function pins.

(15) EVSS (Ground for port)

This is a ground pin for the I/O ports and alternate-function pins.

(16) VDD (Power supply)

This pin supplies positive po wer. Connect all the VDD pins to a positive power supply.

(17) VSS (Ground)

This is a ground pin. Connect all the VSS pins to ground.

(18) FLMD0 (Flash programming mode) Input

This is a signal input pin for flash memory programming mo de. Connect this pin to VSS in the normal op eration

mode.

(19) REGC (Regulator control) … input

This pin connects a capacitor for the regulato r.

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2.3.3 V850ES/FG2

(1) P00 to P06 (port 0) … 3-state I/O

P00 to P06 function as a 7-bit I/O port that can be set to input or output in 1-bit units.

Besides functioning as an I/O port, these pins operate as NMI input, external interrupt request signal input,

timer/counter I/O, external trigger of the A/D converter, and debug reset input.

This port can be set in the port mode or control mode in 1-bit units. The valid edge of each pin is specified by

the INTR0 and INTF0 registers.

An on-chip pull-up resistor can be connected to P00 to P06 by using pull-up resistor option register 0 (PU0).

(a) Port mode

P00 to P06 can be set in the input or output mode in 1-bit units, by using port mode register 0 (PM0).

(b) Control mode

(i) NMI (Non-maskable interrupt request) … input

This pin inputs a non-maskable interrupt request signal.

(ii) INTP0 to INTP3 (Interrupt request from peripherals) … input

These pins input external interrupt request signals.

(iii) TIP30, TIP31 (Timer input) … input

These pins input an external count clock to timer P3 (TMP3).

(iv) TOP30, TOP31 (Timer output) … output

These pins output a pulse signal from timer P3 (TMP3).

(v) ADTRG (A/D trigger input) … input

This pin inputs an external trigger to the A/ D converter. It is controlled by using A/D converter mode

(vi) DRST (Debug reset) … input

This pin inputs a debug reset signal, a ne gative-logic signal that asynchron ously initializes the on-chip

debug circuit. To deassert this signal, reset or invalidate the on-chip debug circuit. Deassert this

signal when the debug function is not used.

For details, refer to CHAPTER 26 ON-CHIP DEBUG FUNCTION (ON-CHIP DEBUG UNIT).

(2) P10, P11 (port 1) … 3-state I/O

P10 and P11 function as a 2-bit I/O port that can be set to input or output i n 1-bit units.

Besides functioning as an I/O port, these pins operate as external interrupt request signal input in the control

mode. This port can be set in the port mode or control mode in 1-bit units. The valid edge of each pin is

specified by INTR1 and INTF1 registers.

An on-chip pull-up resistor can be connected to P10 and P11 by using pull-up resistor option register 1 (PU1).

(a) Port mode

P10 and P11 can be set in the input or output mode in 1-bit units, by using port mode register 1 (PM1).

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User’s Manual U17830EE1V0UM00 79

(b) Control mode

(i) INTP9, INTP10 (Interrupt request from peripherals) … input

These pins input an external interrupt request signal.

(3) P30 to P39 (port 3) … 3-state I/O

P30 to P39 function as a 10-bit I/O port that can be set to input or output in 1-bit units.

Besides functioning as an I/O port, these pins operate as external i nterrupt request signal input, serial i nt erface

I/O, timer/counter I/O, and CAN data I/O. This port can be set in the port mode or control mode in 1-bit units.

The valid edge of each pin is specified by using INTR3 and INTF3 registers.

An on-chip pull-up resistor can be connected to P30 to P39 by using pull-up resistor option register 3 (PU3).

(a) Port mode

P30 to P39 can be set in the input or output mode in 1-bit units, by using port mode register 3 (PM3).

(b) Control mode

(i) RXDA0, RXDA2 (Receive data) … input

This pin inputs the serial receive data of UARTA0.

(ii) TXDA0, TXDA2 (Transmit data) … output

This pin outputs the serial transmit data of UARTA0.

(iii) ASCKA0 (Asynchronous serial clock) … input

This pin inputs of UARTA0.

(iv) INTP7, INTP8 (Interrupt request from peripherals) … input

This pin inputs an external int errupt req uest signal.

(v) TIP00, TIP01, TIP10, TIP11 (Timer input) … input

These pins input an external count clock to timers P0, P1 (TMP0, TMP1).

(vi) TOP00, TOP01, TOP10, TOP11 (Timer output) … output

These pins output a pulse signal from timers P0, P1 (TMP0, TMP1).

(vii) CRXD0, CRXD1 (CAN receive data) … input

These pins input the receive data of CAN0 and CAN1.

(viii) CTXD0, CTXD1 (CAN transmit data) … output

These pins output the transmit data of CAN0 and CAN1.

(4) P40 to P42 (port 4) … 3-state I/O

P40 to P42 function as a 3-bit I/O port that can be set to input or output in 1-bit units.

Besides functioning as an I/O port, these pins operate as serial interface I/O. This port can be set in the port

mode or control mode in 1-bit units.

An on-chip pull-up resistor can be connected to P40 to P42 by using pull-up resistor option register 4 (PU4).

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User’s Manual U17830EE1V0UM00

(a) Port mode

P40 to P42 can be set in the input or output mode in 1-bit units, by using port mode register 4 (PM4).

(b) Control mode

(i) SIB0 (Serial input) … input

This pin inputs the serial receive data of CSIB0.

(ii) SOB0 (Serial output) … output

This pin outputs the serial transmit data of CSIB0.

(iii) SCKB0 (serial clock) … 3-state I/O

This pin inputs/outputs the serial clock of CSIB0.

(5) P50 to P55 (Port 5) … 3-state I/O

P50 to P55 function as a 6-bit I/O port that can be set to input or output in 1-bit units.

Besides functioning as an I/O port, these pins operate as an I/O port, but also as timer/counter I/O, debug

function I/O, and key interrupt input. This port can be set in the port mode or control mode in 1-bit units.

An on-chip pull-up resistor can be connected to P50 to P55 by using pull-up resistor option register 5 (PU5).

(a) Port mode

P50 to P55 can be set in the input or output mode in 1-bit units, by using port mode register 5 (PM5).

(b) Control mode

(i) KR0 to KR5 (Key return) … input

These pins input a key interrupt. Their operation is specified by using the key return mode register

(KRM) in the input port mode.

(ii) TIQ00, TIQ01, TIQ02, TIQ03 (Timer input) … input

These pins input an external count clock to timer Q0 (TMQ0).

(iii) TOQ00, TOQ01, TOQ02, TOQ03 (Timer output) … output

These pins output a pulse signal from timer Q0 (TMQ0).

(iv) DDI (Debug data input) … input

This pin inputs debug dat a to the on-chip debug circuit.

For details, refer to CHAPTER 26 ON-CHIP DEBUG FUNCTION (ON-CHIP DEBUG UNIT).

(v) DDO (Debug data output) … output

This pin outputs debug data from the on-chip debug circuit.

For details, refer to CHAPTER 26 ON-CHIP DEBUG FUNCTION (ON-CHIP DEBUG UNIT).

(iv) DCK (Debug clock input) … input

This pin inputs a debug clock t o the on-ch ip debug circuit.

For details, refer to CHAPTER 26 ON-CHIP DEBUG FUNCTION (ON-CHIP DEBUG UNIT).

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User’s Manual U17830EE1V0UM00 81

(vii) DMS (Debug mode select) … input

This pin selects the debug mode of the on-chip debug circuit.

For details, refer to CHAPTER 26 ON-CHIP DEBUG FUNCTION (ON-CHIP DEBUG UNIT).

(6) P70 to P715 (Port 7) … 3-state I/O

P70 to P715 function as a 16-bit I/O port that can be set to input or output in 1-bit units.

Besides functioning as an I/O port, these pins operate as the analog input pins of the A/D converter in the

control mode. When using this port as analog input pins, however, set the port in the input mode. At this time,

do not read the port.

(a) Port mode

P70 to P715 can be set in the input or output mode in 1-bit units, by using port mode register 7L, H (PM7L,

PM7H).

(b) Control mode

P70 to P715 function alternately as the ANI0 to ANI15 pins.

(i) ANI0 to ANI15 (Analog input 0 to 15) … input

These pins input an analog signal to the A/D converter.

(7) P90 to P915 (Port 9) … 3-state I/O

P90 to P915 function as a 16-bit I/O port that can be set to input or output in 1-bit units.

Besides functioning as an I/O port, these pins operate as serial interface I/O, timer/counter I/O, clock output,

external interrupt request sign al input, and key interrupt input. This port c an be set in the port mode or control

mode in 1-bit units. The valid edge of P913 t o P915 is specified by using INTR9H and INTF9H registers.

An on-chip pull-up resistor can be connected to P90 to P915 by using pull-up resistor option register 9 (PU9).

(a) Port mode

P90 to P915 can be set in the input or output mode in 1-bit units, by using port mode register 9 (PM9).

(b) Control mode

(i) SIB1 (Serial input) … input

This pin inputs the serial receive data of CSIB1.

(ii) SOB1 (Serial output) … output

This pin outputs the serial receive data of CSIB1.

(iii) SCKB1 (Serial clock) … 3-state I/O

This pin inputs/outputs the serial clock of CSIB1.

(iv) RXDA1 (Receive data) … input

This pin inputs the serial receive data of UARTA1.

(v) TXDA1 (Transmit data) … output

This pin outputs the serial transmit data of UARTA1.

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(vi) TIP20, TIP21 (Timer input) … input

These pins input timers P2 (TMP2).

(vii) TOP20, TOP21 (Timer output) … output

These pins output a pulse signal from timers P2 (TMP2).

(viii) TIQ10, TIQ11, TIQ12, TIQ13 (Timer input) … input

These pins input to timers Q1 (TMQ1), respectively.

(ix) TOQ10, TOQ11, TOQ12, TOQ13 (Timer output) … output

These pins output a pulse signal from timers Q1 (TMQ1), respectively.

(x) PCL (Clock output) … output

This pin outputs a clock.

(xi) INTP4 to INTP6 (Interrupt request from peripherals) … input

These pins input an external interrupt request signal.

(xii) KR6, KR7 (Key return) … input

These pins input a key interrupt. Their opera t ion is specified by key return mode register (KRM) in the

input port mode.

(8) PCM0 to PCM3 (port CM) … 3-state I/O

PCM0 to PCM3 function as a 4-bit I/O port that can be set to input or output in 1-bit units.

Besides functioning as an I/O port, these pins operate as bus clock output.

(a) Port mode

PCM0 to PCM3 can be set in the input or output mode in 1-bit units, by using port mode register CM

(PMCM).

(b) Control mode

(i) CLKOUT (Clock output) … output

This pin outputs an internally generated bus clock.

(9) PCS0, PCS1 (Port CS) … 3-state I/O

PCS0 and PCS1 function as a 2-bit I/O port that can be set to input or output in 1-bit units.

(a) Port mode

PCS0 and PCS1 can be set in the input or output mode in 1-bit units, by using port mode register CS

(PMCS).

(10) PCT0, PCT1, PCT4, PCT6 (Port CT) … 3-state I/O

PCT0, PCT1, PCT4, and PCT6 function as a 4-bit I/O port that can be set to input or output in 1-bit units.

(a) Port mode

PCT0, PCT1, PCT4, and PCT6 can be set in the input or output mode in 1-bit units, by using port mode

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User’s Manual U17830EE1V0UM00 83

(11) PDL0 to PDL13 (port DL) … 3-state I/O

PDL0 to PDL13 function as a 14-bit I/O port that can be set to input or output in 1-bit units.

PDL5 also functions as the FLMD1 pin when the flash memory is programmed (when a high level is input to

FLMD0). At this time, be sure to input a low level to the FLMD1 pin.

(a) Port mode

PDL0 to PDL13 can be set in the input or output mode in 1-bit units, by using port mode register DL

(PMDL).

(12) RESET (Reset) … input

RESET input is asynchronous input. When a signal with a fixed low level width is input to the RESET pin

regardless of the operating clock, the system is reset, taking precedence over all the other operations.

This pin is used to release the standby mod e (HALT, IDLE, or STOP), as well as for normal initialization/start.

(13) X1, X2 (Crystal for main clock)

These pins are used to connect the resonator that generates the system clock.

(14) XT1, XT2 (Crystal for subclock)

These pins are used to connect the resonator that generates the subclock.

(15) AVSS (Ground for analog)

This is a ground pin for the A/D converter, and alter nate-function ports.

(16) AVREF0 (Analog reference voltage) … input

This pin supplies positive ana log power to the A/D converter and alternate-function ports.

It also supplies a reference voltage to the A/ D converter.

(17) EVDD (Power supply for port)

This pin supplies positive power to the I/O ports and alternate-function pins.

(18) EVSS (Ground for port)

This is a ground pin for the I/O ports and alternate-function pins.

(19) VDD (Power supply)

This pin supplies positive po wer. Connect all the VDD pins to a positive power supply.

(20) VSS (Ground)

This is a ground pin. Connect all the VSS pins to ground.

(21) FLMD0 (Flash programming mode) Input

This is a signal input pin for flash memory programming mo de. Connect this pin to VSS in the normal op eration

mode.

(22) BVDD (Power supply for port)

This pin supplies positive power to the I/O ports and alternate-function pins.

(23) BVSS (Ground for port)

This is a ground pin for the I/O ports and alternate-function pins.

(24) REGC (Regulator control) … input

This pin connects a capacitor for the regulato r.

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User’s Manual U17830EE1V0UM00

2.3.4 V850ES/FJ2

(1) P00 to P06 (port 0) … 3-state I/O

P00 to P06 function as a 7-bit I/O port that can be set to input or output in 1-bit units.

Besides functioning as an I/O port, these pins operate as NMI input, external interrupt request signal input,

timer/counter I/O, external trigger of the A/D converter, and debug reset input.

This port can be set in the port mode or control mode in 1-bit units. The valid edge of each pin is specified by

the INTR0 and INTF0 registers.

An on-chip pull-up resistor can be connected to P00 to P06 by using pull-up resistor option register 0 (PU0).

(a) Port mode

P00 to P06 can be set in the input or output mode in 1-bit units, by using port mode register 0 (PM0).

(b) Control mode

(i) NMI (Non-maskable interrupt request) … input

This pin inputs a non-maskable interrupt request signal.

(ii) INTP0 to INTP3 (Interrupt request from peripherals) … input

These pins input external interrupt request signals.

(iii) TIP30, TIP31 (Timer input) … input

These pins input to timers P3 (TMP3).

(iv) TOP30, TOP31 (Timer output) … output

These pins output from timers P3 (TMP3).

(v) ADTRG (A/D trigger input) … input

This pin inputs an external trigger to the A/ D converter. It is controlled by using A/D converter mode

(vi) DRST (Debug reset) … input

This pin inputs a debug reset signal, a ne gative-logic signal that asynchron ously initializes the on-chip

debug circuit. To deassert this signal, reset or invalidate the on-chip debug circuit. Deassert this

signal when the debug function is not used.

For details, refer to CHAPTER 27 ON-CHIP DEBUG FUNCTION (ON-CHIP DEBUG UNIT).

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User’s Manual U17830EE1V0UM00 85

(2) P10, P11 (port 1) … 3-state I/O

P10 and P11 function as a 2-bit I/O port that can be set to input or output i n 1-bit units.

Besides functioning as an I/O port, these pins operate as external interrupt request input in the control mode.

This port can be set in the port mode or control mode in 1-bit units. The valid edge of each pin is specified by

INTR1 and INTF1 registers.

An on-chip pull-up resistor can be connected to P10 and P11 by using pull-up resistor option register 1 (PU1).

(a) Port mode

P10 and P11 can be set in the input or output mode in 1-bit units, by using port mode register 1 (PM1).

(b) Control mode

(i) INTP9, INTP10 (Interrupt request from peripherals) … input

These pins input an external interrupt request signal.

(3) P30 to P39 (port 3) … 3-state output

P30 to P39 function as a 10-bit I/O port that can be set to input or output in 1-bit units.

Besides functioning as an I/O port, these pins operate as external i nterrupt request signal input, serial i nt erface

I/O, timer/counter I/O, and CAN data I/O. This port can be set in the port mode or control mode in 1-bit units.

The valid edge of each pin is specified by using INTR3 and INTF3 registers.

An on-chip pull-up resistor can be connected to P30 to P39 by using pull-up resistor option register 3 (PU3).

(a) Port mode

P30 to P39 can be set in the input or output mode in 1-bit units, by using port mode register 3 (PM3).

(b) Control mode

(i) RXDA0, RXDA2 (Receive data) … input

These pins input the serial receive data of UARTA0 and UARTA2.

(ii) TXDA0, TXDA2 (Transmit data) … output

These pins output the serial transmit data of UARTA0 and UARTA2.

(iii) ASCKA0 (Asynchronous serial clock) … input

This pin inputs of UARTA0.

(iv) INTP7, INTP8 (Interrupt request from peripherals) … input

These pins input an external interrupt request signal.

(v) TIP00, TIP01, TIP10, TIP11 (Timer input) … input

These pins input to timers P0 and P1 (TMP0, TMP1).

(vi) TOP00, TOP01, TOP10, TOP11 (Timer output) … output

These pins output from timers P0 and P1 (TMP0, TMP1).

(vii) CRXD0, CRXD1 (CAN receive data) … input

These pins input the receive data of CAN0 and CAN1.

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(viii) CTXD0, CTXD1 (CAN transmit data) … output

These pins output the transmit data of CAN0 and CAN1.

(4) P40 to P42 (port 4) … 3-state I/O

P40 to P42 function as a 3-bit I/O port that can be set to input or output in 1-bit units.

Besides functioning as an I/O port, these pins operate as serial interface I/O. This port can be set in the port

mode or control mode in 1-bit units.

An on-chip pull-up resistor can be connected to P40 to P42 by using pull-up resistor option register 4 (PU4).

(a) Port mode

P40 to P42 can be set in the input or output mode in 1-bit units, by using port mode register 4 (PM4).

(b) Control mode

(i) SIB0 (Serial input) … input

This pin inputs the serial receive data of CSIB0.

(ii) SOB0 (Serial output) … output

This pin outputs the serial transmit data of CSIB0.

(iii) SCKB0 (serial clock) … 3-state I/O

This pin inputs/outputs the serial clock of CSIB0.

(5) P50 to P55 (Port 5) … 3-state I/O

P50 to P55 function as a 6-bit I/O port that can be set to input or output in 1-bit units.

Besides functioning as an I/O port, these pins operate as an I/O port, but also as timer/counter I/O, debug

function I/O, and key interrupt input. This port can be set in the port mode or control mode in 1-bit units.

An on-chip pull-up resistor can be connected to P50 to P55 by using pull-up resistor option register 5 (PU5).

(a) Port mode

P50 to P55 can be set in the input or output mode in 1-bit units, by using port mode register 5 (PM5).

(b) Control mode

(i) KR0 to KR5 (Key return) … input

These pins input a key interrupt. Their operation is specified by using the key return mode register

(KRM) in the input port mode.

(ii) TIQ00, TIQ01, TIQ02, TIQ03 (Timer input) … input

These pins input to timers Q0 (TMQ0).

(iii) TOQ00, TOQ01, TOQ02, TOQ03 (Timer output) … output

These pins output from timers Q0 (TMQ0).

(iv) DDI (Debug data input) … input

This pin inputs debug dat a to the on-chip debug circuit.

For details, refer to CHAPTER 27 ON-CHIP DEBUG FUNCTION (ON-CHIP DEBUG UNIT).

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(v) DDO (Debug data output) … output

This pin outputs debug data from the on-chip debug circuit.

For details, refer to CHAPTER 27 ON-CHIP DEBUG FUNCTION (ON-CHIP DEBUG UNIT).

(iv) DCK (Debug clock input) … input

This pin inputs a debug clock t o the on-ch ip debug circuit.

For details, refer to CHAPTER 27 ON-CHIP DEBUG FUNCTION (ON-CHIP DEBUG UNIT).

(vii) DMS (Debug mode select) … input

This pin selects the debug mode of the on-chip debug circuit.

For details, refer to CHAPTER 27 ON-CHIP DEBUG FUNCTION (ON-CHIP DEBUG UNIT).

(6) P60 to P615 … 3-state I/O

P60 to P615 function as a 16-bit I/O port that can be set to input or output in 1-bit units.

Besides functioning as an I/O port, these pins operate as external interrupt request signal input, timer/counter

I/O, and CAN data I/O. P60 to P62 can be set in the port mode or control mode in 1-bit units. The valid edge

of each pin is specified by INTR6L and INTF6L registers.

(a) Port mode

P60 to P65 can be set in the input or output mode in 1-bit units, by using port mode register 6 (PM6).

(b) Control mode

(i) INTP11 to INTP13 (Interrupt request from peripherals) … input

These pins input an external interrupt request signal.

(ii) TIQ20, TIQ21, TIQ22, TIQ23 (Timer input) … input

These pins input to timers Q2 (TMQ2).

(iii) TOQ20, TOQ21, TOQ22, TOQ23 (Timer output) … input

These pins output from timers Q2 (TMQ2).

(iv) CRXD2, CRXD3 (CAN receive data)Note … input

These pins input the receive data of CAN2 and CAN3.

(v) CTXD2, CTXD3 (CAN transmit data)Note … output

These pins output the transmit data of CAN2 and CAN3.

Note In the

PD70F3237, the alternate functions of the P65 to P68 pins (CTXD2, CRXD2, CTXD3, and

CRXD3) are not available.

(7) P70 to P715 (Port 7) … 3-state I/O

P70 to P715 function as a 16-bit I/O port that can be set to input or output in 1-bit units.

Besides functioning as an I/O port, these pins operate as the analog input pins of the A/D converter in the

control mode. When using this port as analog input pins, however, set the port in the input mode. At this time,

do not read the port.

(a) Port mode

P70 to P715 can be set in the input or output mode in 1-bit units, by using port mode register 7L, H (PM7L,

PM7H).

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(b) Control mode

P70 to P715 function alternately as the ANI0 to ANI15 pins.

(i) ANI0 to ANI15 (Analog input 0 to 15) … input

These pins input an analog signal to the A/D converter.

(8) P80 and P81 (port 8) … 3-state I/O

P80 and P81 function as a 2-bit I/O port that can be set to input or output i n 1-bit units.

Besides functioning as an I/O port, these pins operate as external interrupt request signal input, and serial

interface I/O. P80 and P81 can be set in the port mode or control mode in 1-bit units. The valid edge of each

pin is specified by INTR8 and INTF8 registers.

An on-chip pull-up resistor can be connected to P80 and P81 by using pull-up resistor option register 8 (PU8).

(a) Port mode

P80 and P81 can be set in the input or output mode in 1-bit units, by using port mode register 8 (PM8).

(b) Control mode

(i) INTP14 (Interrupt request from peripherals) … input

This pin inputs an external int errupt req uest signal.

(ii) RXDA3 (Receive data)Note … input

This pin inputs the serial receive data of UARTA3.

(iii) TXDA3 (Transmit data)Note … output

This pin outputs the serial transmit data of UARTA3.

Note In the

PD70F3237, the alternate functio ns of the P80 and P81 pins (RXDA3 and TXDA3) are

not available. The alternate function of the P80 pin in the

PD70F3237 is INTP14 only.

(9) P90 to P915 (Port 9) … 3-state I/O

P90 to P915 function as a 16-bit I/O port that can be set to input or output in 1-bit units.

Besides functioning as an I/O port, these pins operate as serial interface I/O, timer/counter I/O, clock output,

external interrupt request sign al input, and key interrupt input. This port c an be set in the port mode or control

mode in 1-bit units. The valid edge of P913 t o P915 is speci fied by using INTF9H register.

An on-chip pull-up resistor can be connected to P90 to P915 by using pull-up resistor option register 9 (PU9).

(a) Port mode

P90 to P915 can be set in the input or output mode in 1-bi t units, by using port 9 mode register (PM9).

(b) Control mode

(i) SIB1, SIB2 (Serial input) … input

These pins input the serial receive data of CSIB1 and CSIB2.

(ii) SOB1, SOB2 (Serial output) … output

These pins output the serial receive data of CSIB1 and CSIB2.

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(iii) SCKB1, SCKB2 (Serial clock) … 3-state I/O

These pins input/output the serial clock of CSIB1 and CSIB2.

(iv) RXDA1 (Receive data) … input

This pin inputs the serial receive data of UARTA1.

(v) TXDA1 (Transmit data) … output

This pin outputs the serial transmit data of UARTA1.

(vi) TIP20, TIP21 (Timer input) … input

These pins input timers P2 (TMP2).

(vii) TOP20, TOP21 (Timer output) … output

These pins output from timers P2 (TMP2).

(viii) TIQ10, TIQ11, TIQ12, TIQ13 (Timer input) … input

These pins input an external count clock to timers Q1.

(ix) TOQ10, TOQ11, TOQ12, TOQ13 (Timer output) … output

These pins output a pulse signal from timers Q1.

(x) PCL (Clock output) … output

This pin outputs a clock.

(xi) INTP4 to INTP6 (Interrupt request from peripherals) … input

These pins input an external interrupt request signal.

(xii) KR6, KR7 (Key return) … input

These pins input a key interrupt. Their opera t ion is specified by the key return mod e register (KRM) in

the input port mode.

(10) P120 to P127 (Port 12) … 3-state I/O

P120 to P127 function as an 8-bit I/O port that can be set to input or output in 1-bit units.

Besides functioning as an I/O port, these pins operate as the analog input pins of the A/D converter in the

control mode. When using this port as analog input pins, however, set the port in the input mode. At this time,

do not read the port.

(a) Port mode

P120 to P127 can be set in the input or output mode in 1-bit units, by using port mode register 12 (PM12).

(b) Control mode

P120 to P127 function alternately as the ANI16 to ANI23 pins.

(i) ANI16 to ANI23 (Analog input 16 to 23) … input

These pins input an analog signal to the A/D converter.

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(11) PCD0 to PCD3 (port CD) … 3-state I/O

PCD0 to PCD3 function as a 4-bit I/O port that can be set to input or output in 1-bit units.

(a) Port mode

PCD0 to PCD3 can be set in the input or output mode in 1-bit units, by using port mode register CD

(PMCD).

(12) PCM0 to PCM5 (port CM) … 3-state I/O

PCM0 to PCM5 function as a 6-bit I/O port that can be set to input or output in 1-bit units.

Besides functioning as an I/O port, these pins operate as bus hold control signal I/O, bus clock output, and a

control signal that inserts a wait cycle in the bus cycle (WAIT), in the control mode.

(a) Port mode

PCM0 to PCM5 can be set in the input or output mode in 1-bit units, by using port mode register CM

(PMCM).

(b) Control mode

(i) HLDAK (Hold acknowledge) … output

This pin outputs an acknowledge signal that indicates that the V850ES/FJ2 has placed the address

bus, data bus, and control bus in a high-impedance state in response to a bus hold request.

While this signal is active, the address bus, data bus, and control bus go i nto a hig h-impedance state.

(ii) HLDRQ (Hold request) … input

An external device uses this input pin to request the V850ES/FJ2 to release the address bus, data

bus, and control bus. A signal can be input to this pin asynchronously to CLKOUT. When this pin is

asserted, the V850ES/FJ2 places the address bus, data bus, and control bus in a high-impedance

state after completion of a bus cycle under execution, if any, or immediately if no such bus cycle is

under execution. The V850ES/FJ2 then asserts the HLDAK signal and releases the buses.

(iii) CLKOUT (Clock output) … output

This pin outputs an internally generated bus clock.

(iv) WAIT (Wait) … input

This is a control signal input pin that inserts a data wait state in the bus cycle. A signal can be input to

this pin asynchronously to the CLKOUT signal. The signal input to this pin is sampled at the falling

edge of the CLKOUT signal in the T2 and TW states of the bus cycle in the multiplexed mode. No wait

state may be inserted if the setup/hold time of the sampling timing is not satisfied.

The wait function is set to on or off by port mode control register CM (PMCCM).

(13) PCS0 to PCS7 (port CS) … 3-state I/O

PCS0 to PCS7 function as an 8-bit I/O port that can be set to input or output in 1-bit units.

Besides functioning as an I/O port, these pins operate as chip select signal output in the control mode.

CHAPTER 2 PIN FUNCTIONS

User’s Manual U17830EE1V0UM00 91

(a) Port mode

PCS0 to PCS7 can be set in the input or output mode in 1-bit units, by using port mode register CS

(PMCS).

(b) Control mode

(i) CS0 to CS3 (Chip select input) … output

These pins output a chip select signal to external memory and external peripheral I/O.

The CSn signal is assigned to memory block n (n = 0 to 3).

This signal is asserted while a bus cycle for accessing the corresponding memory block is being

executed.

This signal is deasserted in the idle state (TI).

(14) PCT0 to PCT7 (port CT) … 3-state I/O

PCT0 to PCT7 function as an 8-bit I/O port that can be set to input or output in 1-bit units.

Besides functioning as an I/O port, these pins operate as control signal output in the control mode when

memory is externally expanded.

(a) Port mode

PCT0 to PCT7 can be set in the input or output mode in 1-bit units, by using port mode register CT

(PMCT).

(b) Control mode

(i) WR0 (Lower byte write strobe) … output

This pin outputs the write strobe signal of the lower data of the external 16-bit data bus.

(ii) WR1 (Upper byte write strobe) … output

This pin outputs the write strobe signal of the higher data of the external 16-bit data bus.

(iii) RD (Read strobe) … output

This pin outputs the read strobe signal of the external 16-bit data bus.

(iv) ASTB (Address strobe) … output

This pin outputs the latch strobe signal of the external address bus. The signal output from this pin

goes low at the falling edge of the T1 state of the bus cycle, and goes high at the falling edge of the

T3 state. It goes high while the bus cycle is not active.

(15) PDL0 to PDL15 (port DL) … 3-state I/O

PDL0 to PDL15 function as a 16-bit I/O port that can be set to input or output in 1-bit units.

Besides functioning as an I/O port, these pins operate as a time-division address/data bus (AD0 to AD15)

when the memory is externally expanded.

PDL5/AD5 also functions as the FLMD1 pin when the flash memory is programmed (when a high level i s input

to FLD0). At this time, be sure to input a low level to the FLMD1 pin.

(a) Port mode

PDL0 to PDL15 can be set in the input or output mode in 1-bit units, by using port mode register DL

(PMDL).

CHAPTER 2 PIN FUNCTIONS

User’s Manual U17830EE1V0UM00

(b) Control mode

(i) AD0 to AD15 (Address/Dat a Bus 0 to 15) … 3-state I/O

This is a multiplexed address/data bus for ex ternal access.

(16) RESET (Reset) … input

RESET input is asynchronous input. When a signal with a fixed low level width is input to the RESET pin

regardless of the operating clock, the system is reset, taking precedence over all the other operations.

This pin is used to release the standby mod e (HALT, IDLE, or STOP), as well as for normal initialization/start.

(17) X1, X2 (Crystal for main clock)

These pins are used to connect the resonator that generates the system clock.

(18) XT1, XT2 (Crystal for subclock)

These pins are used to connect the resonator that generates the subclock.

(19) AVSS (Ground for analog)

This is a ground pin for the A/D converter, and alter nate-function ports.

(20) AVREF0 (Analog reference voltage) … input

This pin supplies positive ana log power to the A/D converter and alternate-function ports.

It also supplies a reference voltage to the A/ D converter.

(21) EVDD (Power supply for port)

This pin supplies positive power to the I/O ports and alternate-function pins.

(22) EVSS (Ground for port)

This is a ground pin for the I/O ports and alternate-function pins.

(23) VDD (Power supply)

This pin supplies positive po wer. Connect all the VDD pins to a positive power supply.

(24) VSS (Ground)

This is a ground pin. Connect all the VSS pins to ground.

(25) FLMD0 (Flash programming mode) Input

This is a signal input pin for flash memory programming mo de. Connect this pin to VSS in the normal op eration

mode.

(26) BVDD (Power supply for port)

This pin supplies positive power to the I/O ports and alternate-function pins.

CHAPTER 2 PIN FUNCTIONS

User’s Manual U17830EE1V0UM00 93

(27) BVSS (Ground for port)

This is a ground pin for the I/O ports and alternate-function pins.

(28) REGC (Regulator control) … input

This pin connects a capacitor for the regulato r.

CHAPTER 2 PIN FUNCTIONS

User’s Manual U17830EE1V0UM00

2.4 Pin I/O Circuit Types and Recommended Connection of Unused Pins

2.4.1 V850ES/FE2 (1/2)

Pin I/O Circuit

Type Recommended Connection

P00/TIP31/TOP31

P01/TIP30/TOP30

P02/NMI

P03/INTP0/ADTRG

P04/INTP1

5-W Input: Independently connect to EVDD or EVSS via a resistor

Output: Leave open

P05/INTP2/DRST

5-AF Input: Independentl y connect to EVSS

Output: Leave open

P06/INTP3

5-W Input: Independently connect to EVDD or EVSS via a resistor

Output: Leave open

P30/TXDA0 5-A

P31/RXDA0/INTP7

P32/ASCKA0/TIP00/T OP00/ TOP01

P33/TIP01/TOP01/CTXD0

P34/TIP10/TOP10/CRXD0

P35/TIP11/TOP11

5-W

Input: Independentl y connect to EVDD or EVSS via a resistor

Output: Leave open

P40/SIB0 5-W

P41/SOB0 5-A

P42/SCKB0 5-W

Input: Independentl y connect to EVDD or EVSS via a resistor

Output: Leave open

P50/KR0/TIQ01/TOQ01

P51/KR1/TIQ02/TOQ02

P52/KR2/TIQ03/TOQ03/DDI

P53/KR3/TIQ00/TOQ00/DDO

P54/KR4/DCK

P55/KR5/DMS

5-W Input: Independently connect to EVDD or EVSS via a resistor

Output: Leave open

CHAPTER 2 PIN FUNCTIONS

User’s Manual U17830EE1V0UM00 95

(2/2)

Pin I/O Circuit

Type

Recommended Connection

P70/ANI0 to P79/ANI9 11-G Input: Independently connect to AVREF0 or AVSS via a resistor

Output: Leave open

P90/KR6/TXDA1

P91/KR7/RXDA1

P96/TIP21/TOP21

P97/SIB1/TIP20/TOP20

5-W

P98/SOB1 5-A

P99/SCKB1 5-W

Input: Independentl y connect to EVDD or EVSS via a resistor

Output: Leave open

P913/INTP4/PCL

P914/INTP5

P915/INTP6

5-W Input: Independently connect to EVDD or EVSS via a resistor

Output: Leave open

PCM0

PCM1/CLKOUT

5 Input: Independentl y connect to EVDD or EVSS via a resistor

Output: Leave open

PDL0 to PDL4

PDL5/FLMD1

PDL6, PDL7

5 Input: Independentl y connect to EVDD or EVSS via a resistor

Output: Leave open

AVREF0 − Directly connect to VDD

AVSS − −

FLMD0Note − Directly connect to VSS

REGC − −

RESET 2 −

X1 − −

X2 − −

XT1 16 Connect to VSS via a resistor

XT2 16 Leave open

VDD − −

VSS − −

EVDD − −

EVSS − −

Note If noise that exceeds the noise elimination width is input to the RESET pin during self programming, the

flash on-board mode may be entered depending on the capacita nce charge end timing when a capacit or is

connected to the FLMD0 pin. Therefore, do not connect a capacitor to the FLMD0 pin.

CHAPTER 2 PIN FUNCTIONS

User’s Manual U17830EE1V0UM00

2.4.2 V850ES/FF2 (1/2)

Pin I/O Circuit

Type Recommended Connection

P00/TIP31/TOP31

P01/TIP30/TOP30

P02/NMI

P03/INTP0/ADTRG

P04/INTP1

5-W Input: Independently connect to EVDD or EVSS via a resistor

Output: Leave open

P05/INTP2/DRST

5-AF Input: Independentl y connect to EVSS

Output: Leave open

P06/INTP3

5-W Input: Independently connect to EVDD or EVSS via a resistor

Output: Leave open

P30/TXDA0 5-A

P31/RXDA0/INTP7

P32/ASCKA0/TIP00/T OP00/ TOP01

P33/TIP01/TOP01/CTXD0

P34/TIP10/TOP10/CRXD0

P35/TIP11/TOP11

5-W

P38 5-A

P39 5-W

Input: Independentl y connect to EVDD or EVSS via a resistor

Output: Leave open

P40/SIB0 5-W

P41/SOB0 5-A

P42/SCKB0 5-W

Input: Independentl y connect to EVDD or EVSS via a resistor

Output: Leave open

P50/KR0/TIQ01/TOQ01

P51/KR1/TIQ02/TOQ02

P52/KR2/TIQ03/TOQ03/DDI

P53/KR3/TIQ00/TOQ00/DDO

P54/KR4/DCK

P55/KR5/DMS

5-W Input: Independently connect to EVDD or EVSS via a resistor

Output: Leave open

CHAPTER 2 PIN FUNCTIONS

User’s Manual U17830EE1V0UM00 97

(2/2)

Pin I/O Circuit

Type

Recommended Connection

P70/ANI0 to P711/ANI11 11-G Input: Independently connect to AVREF0 or AVSS via a resistor

Output: Leave open

P90/KR6/TXDA1

P91/KR7/RXDA1

P96/TIP21/TOP21

P97/SIB1/TIP20/TOP20

5-W

P98/SOB1 5-A

P99/SCKB1 5-W

Input: Independentl y connect to EVDD or EVSS via a resistor

Output: Leave open

P913/INTP4/PCL

P914/INTP5

P915/INTP6

5-W Input: Independently connect to EVDD or EVSS via a resistor

Output: Leave open

PCM0

PCM1/CLKOUT

PCM2, PCM3

5 Input: Independentl y connect to EVDD or EVSS via a resistor

Output: Leave open

PCS0, PCS1 5 Input: Independently connect to EVDD or EVSS via a resistor

Output: Leave open

PCT0. PCT1, PCT4, PCT6 5 Input: Independently connect to EVDD or EVSS via a resistor

Output: Leave open

PDL0 to PDL4

PDL5/FLMD1

PDL6 to PDL11

5 Input: Independentl y connect to EVDD or EVSS via a resistor

Output: Leave open

AVREF0 − Directly connect to VDD

AVSS − −

FLMD0Note − Directly connect to VSS

REGC − −

RESET 2 −

X1 − −

X2 − −

XT1 16 Connect to VSS via a resistor

XT2 16 Leave open

VDD − −

VSS − −

EVDD − −

EVSS − −

Note If noise that exceeds the noise elimination width is input to the RESET pin during self programming, the

flash on-board mode may be entered depending on the capacita nce charge end timing when a capacit or is

connected to the FLMD0 pin. Therefore, do not connect a capacitor to the FLMD0 pin.

CHAPTER 2 PIN FUNCTIONS

User’s Manual U17830EE1V0UM00

2.4.3 V850ES/FG2 (1/2)

Pin I/O Circuit

Type Recommended Connection

P00/TIP31/TOP31

P01/TIP30/TOP30

P02/NMI

P03/INTP0/ADTRG

P04/INTP1

5-W Input: Independently connect to EVDD or EVSS via a resistor

Output: Leave open

P05/INTP2/DRST 5-AF

Input: Independentl y connect to EVSS via a resistor

Output: Leave open

P06/INTP3 5-W

Input: Independentl y connect to EVDD or EVSS via a resistor

Output: Leave open

P10/INTP9

P11/INTP10

5-W Input: Independently connect to EVDD or EVSS via a resistor

Output: Leave open

P30/TXDA0 5-A

P31/RXDA0/INTP7

P32/ASCKA0/TIP00/TOP00/TOP01

P33/TIP01/TOP01/CTXD0

P34/TIP10/TOP10/CRXD0

P35/TIP11/TOP11

5-W

P36/CTXD1 5-A

P37/CRXD1 5-W

P38/TXDA2 5-A

P39/RXDA2/INTP8 5-W

Input: Independentl y connect to EVDD or EVSS via a resistor

Output: Leave open

P40/SIB0 5-W

P41/SOB0 5-A

P42/SCKB0

Input: Independentl y connect to EVDD or EVSS via a resistor

Output: Leave open

P50/KR0/TIQ01/TOQ01

P51/KR1/TIQ02/TOQ02

P52/KR2/TIQ03/TOQ03/DDI

P53/KR3/TIQ00/TOQ00/DDO

P54/KR4/DCK

P55/KR5/DMS

5-W

Input: Independentl y connect to EVDD or EVSS via a resistor

Output: Leave open

P70/ANI0 to P711/ANI11

P712/ANI12 to P715/ANI15 11-G Input: Independently connect to AVREF0 or AVSS via a resistor

Output: Leave open

P90/KR6/TXDA1

P91/KR7/RXDA1

P92/TIQ11/TOQ11

P93/TIQ12/TOQ12

P94/TIQ13/TOQ13

P95/TIQ10/TOQ10

5-W Input: Independently connect to EVDD or EVSS via a resistor

Output: Leave open

CHAPTER 2 PIN FUNCTIONS

User’s Manual U17830EE1V0UM00 99

(2/2)

Pin I/O Circuit

Type

Recommended Connection

P96/TIP21/TOP21

P97/SIB1/TIP20/TOP20

5-W

P98/SOB1 5-A

P99/SCKB1 5-W

P910

P911

P912

5-A

P913/INTP4/PCL

P914/INTP5

P915/INTP6

5-W

Input: Independentl y connect to EVDD or EVSS via a resistor

Output: Leave open

PCM0

PCM1/CLKOUT

PCM2, PCM3

5 Input: Independently connect to BVDD or BVSS via a resistor

Output: Leave open

PCS0, PCS1 5 Input: Independently connect to BVDD or BVSS via a resistor

Output: Leave open

PCT0, PCT1, PCT4,

PCT6

5 Input: Independently connect to BVDD or BVSS via a resistor

Output: Leave open

PDL0 to PDL4

PDL5/ FLMD1

PDL6 to AD13

5 Input: Independently connect to BVDD or BVSS via a resistor

Output: Leave open

AVREF0 − Directly connect to VDD

AVSS − −

FLMD0Note − Directly connect to VSS

REGC − −

RESET 2 −

X1 − −

X2 − −

XT1 16 Connect to VSS via a resistor

XT2 16 Leave open

VDD − −

VSS − −

BVDD − −

BVSS − −

EVDD − −

EVSS − −

Note If noise that exceeds the noise elimination width is input to the RESET pin during self programming, the

flash on-board mode may be entered depending on the capacita nce charge end timing when a capacit or is

connected to the FLMD0 pin. Therefore, do not connect a capacitor to the FLMD0 pin.

CHAPTER 2 PIN FUNCTIONS

User’s Manual U17830EE1V0UM00

100

2.4.4 V850ES/FJ2 (1/4)

Pin I/O Circuit

Type Recommended Connection

P00/TIP31/TOP31

P01/TIP30/TOP30

P02/NMI

P03/INTP0/ADTRG

P04/INTP1

5-W Input: Independently connect to EVDD or EVSS via a resistor

Output: Leave open

P05/INTP2/DRST

5-AF Input: Independentl y connect to EVSS

Output: Leave open

P06/INTP3

5-W Input: Independently connect to EVDD or EVSS via a resistor

Output: Leave open

P10/INTP9

P11/INTP10

5-W Input: Independently connect to EVDD or EVSS via a resistor

Output: Leave open

P30/TXDA0 5-A

P31/RXDA0/INTP7

P32/ASCKA0/TIP00/T OP00/ TOP01

P33/TIP01/TOP01/CTXD0

P34/TIP10/TOP10/CRXD0

P35/TIP11/TOP11

5-W

P36/CTXD1 5-A

P37/CRXD1 5-W

P38/TXDA2Note 5-A

P39/RXDA2/INTP8Note 5-W

Input: Independentl y connect to EVDD or EVSS via a resistor

Output: Leave open

P40/SIB0 5-W

P41/SOB0 5-A

P42/SCKB0 5-W

Input: Independentl y connect to EVDD or EVSS via a resistor

Output: Leave open

P50/KR0/TIQ01/TOQ01

P51/KR1/TIQ02/TOQ02

P52/KR2/TIQ03/TOQ03/DDI

P53/KR3/TIQ00/TOQ00/DDO

P54/KR4/DCK

P55/KR5/DMS

5-W Input: Independently connect to EVDD or EVSS via a resistor

Output: Leave open

CHAPTER 2 PIN FUNCTIONS

User’s Manual U17830EE1V0UM00 101

(2/4)

Pin I/O Circuit

Type

Recommended Connection

P60/INTP11

P61/INTP12

P62/INTP13

5-W

P63

P64

P65/CTXD2Note1

5-A

P66/CRXD2Note1 5-W

P67/CTXD3Note1 5-A

P68/CRXD3Note1 5-W

P69 5-A

P610/TIQ20/TOQ20

P611/TIQ21/TOQ21

P612/TIQ22/TOQ22

P613/TIQ23/TOQ23

5-W

P614

P615

5-A

Input: Independentl y connect to EVDD or EVSS via a resistor

Output: Leave open

P70/ANI0 to P79/ANI9

P710/ANI10, P11/ANI11

P712/ANI12 to P715/ANI15

11-G Input: Independently connect to AVREF0 or AVSS via a resistor

Output: Leave open

P80/RXDA3/INTP14Note2 5-W

P81/TXDA3Note2 5-A

Input: Independentl y connect to EVDD or EVSS via a resistor

Output: Leave open

P90/KR6/TXDA1

P91/KR7/RXDA1

P92/TIQ11/TOQ11

P93/TIQ12/TOQ12

P94/TIQ13/TOQ13

P95/TIQ10/TOQ10

P96/TIP21/TOP21

P97/SIB1/TIP20/TOP20

5-W

P98/SOB1 5-A

P99/SCKB1

P910/SIB2

5-W

P911/SOB2 5-A

P912/SCKB2 5-W

Input: Independentl y connect to EVDD or EVSS via a resistor

Output: Leave open

Notes 1. In the

PD70F3237, the alternate functions of the P65 to P68 pins (CTXD2, CRXD2, CTXD3, and

CRXD3) are not available.

2. In the

PD70F3237, the alternate functions of the P80 and P81 pins (RXDA3 and TXDA3) are not

available.

The alternate function of the P80 pin in the

PD70F3237 is only INTP14.

CHAPTER 2 PIN FUNCTIONS

User’s Manual U17830EE1V0UM00

102

(3/4)

Pin I/O Circuit

Type

Recommended Connection

P913/INTP4/PCL

P914/INTP5

P915/INTP6

5-W Input: Independently connect to EVDD or EVSS via a resistor

Output: Leave open

P120/ANI16 to P127/ANI23 11-G Input: Independently connect to AVREF0 or AVSS via a resistor

Output: Leave open

PCD0 to PCD3 5 Input: Independently connect to BVDD or BVSS via a resistor

Output: Leave open

PCM0/WAIT

PCM1/CLKOUT

PCM2/HLDAK

PCM3/HLDRQ

PCM4

PCM5

5 Input: Independently connect to BVDD or BVSS via a resistor

Output: Leave open

PCS0/CS0, PCS3/CS1

PCS0/CS2, PCS3/CS3,

PCS4 to PCS7

5 Input: Independently connect to BVDD or BVSS via a resistor

Output: Leave open

PCT0/WR0

PCT1/WR1

PCT2

PCT3

PCT4/RD

PCT5

PCT6/ASTB

PCT7

5 Input: Independently connect to BVDD or BVSS via a resistor

Output: Leave open

PDL0/AD0 to PDL4/AD4

PDL5/AD5/FLMD1

PDL6/AD6, PDL7/AD7

PDL8/AD8 to PDL11/AD11

PDL12/AD12, PDL13/AD13

PDL14/AD14, PDL15/AD15

5 Input: Independently connect to BVDD or BVSS via a resistor

Output: Leave open

CHAPTER 2 PIN FUNCTIONS

User’s Manual U17830EE1V0UM00 103

(4/4)

Pin I/O Circuit

Type

Recommended Connection

AVREF0 − Directly connect to VDD

AVSS − −

FLMD0Note − Directly connect to VSS

REGC − −

RESET 2 −

X1 − −

X2 − −

XT1 16 Connect to VSS via a resistor

XT2 16 Leave open

VDD − −

VSS − −

BVDD − −

BVSS − −

EVDD − −

EVSS − −

Note If noise that exceeds the noise elimination width is input to the RESET pin during self programming, the

flash on-board mode may be entered depending on the capacita nce charge end timing when a capacit or is

connected to the FLMD0 pin. Therefore, do not connect a capacitor to the FLMD0 pin.

CHAPTER 2 PIN FUNCTIONS

User’s Manual U17830EE1V0UM00

104

2.5 Pin I/O Circuits

Figure 2-1. Pin I/O Circuit Types (1/2)

Data

Output

disable

P-ch

IN/OUT

N-ch

Input

enable

Data

Output

disable

REF0

P-ch

IN/OUT

N-ch

P-ch

N-ch

REF

(Threshold voltage)

Comparator

Schmitt-triggered input with hysteresis characteristics

Input enable

Pullup

enable

Pulldown

enable

Data

Output

disable

Input enable

P-ch

IN/OUT

-ch

Type 2 Type 5-AF

Type 5 Type 11-G

CHAPTER 2 PIN FUNCTIONS

User’s Manual U17830EE1V0UM00 105

Figure 2-1. Pin I/O Circuit Types (2/2)

Data

Output

disable

P-ch

IN/OUT

VDD

N-ch

Input

enable

P-ch

VDD

Pullup

enable

Pullup

enable

Data

Output

disable

Input

enable

VDD

P-ch

VDD

P-ch

IN/OUT

-ch

P-ch

Feedback cut-off

XT1 XT2

Type 5-A

Type 5-W

Type 16

User’s Manual U17830EE1V0UM00

106

CHAPTER 3 CPU FUNCTIONS

Based on the RISC architecture, the CPU of the V850ES/FE2, V850ES/FF2, V850ES/FG2, V850ES/FJ2 executes

most of the instructions in one clock under control of a five-stage pipel ine.

3.1 Features

{ Minimum instruction execution time: 50 ns (at 20 MHz operation)

{ Memory space Program space: 64 MB, linear

Data space: 4 GB, linear

{ General-purpose registers: 32 bits × 32

{ Internal 32-bit architecture

{ Five-stage pipeline control

{ Multiplication/division instructions

{ Saturation operation instructions

{ 32-bit shift instructions: 1 clock

{ Load/store instructions with long/short format

{ Four types of bit manipulation instructions

• SET1

• CLR1

• NOT1

• TST1

CHAPTER 3 CPU FUNCTIONS

User’s Manual U17830EE1V0UM00 107

3.2 CPU Register Set

The registers of the V850ES/FE2, V850ES/FF2, V850ES/FG2, V850ES/FJ2 can be classified into two types:

general-purpose program registers and dedicated system registers. All the registers are 3 2 bits wide.

For details, refer to V850ES Architecture User’s Manual.

r10

r11

r12

r13

r14

r15

r16

r17

r18

r19

r20

r21

r22

r23

r24

r25

r26

r27

r28

r29

r30

r31

PSW

ECR

FEPC

FEPSW

EIPC

EIPSW

31 0

31 0 31 0

CTBP

DBPC

DBPSW

CTPC

CTPSW

(Status saving register on interrupt)

(Status saving register on NMI)

(Interrupt source register)

(Program status word)

(Status saving register on CALLT execution)

(Status saving register on exception/debug trap)

(CALLT base pointer)

(Zero register)

(Assembler-reserved register)

(Stack pointer (SP))

(Global pointer (GP))

(Text pointer (TP))

(Element pointer (EP))

(Link pointer (LP))

(Program counter)

(1) Program register set (2) System register set

CHAPTER 3 CPU FUNCTIONS

User’s Manual U17830EE1V0UM00

108

3.2.1 Program register set

The program registers include general-purpose registers and a program counter.

(1) General-purpose registers (r0 to r31)

Thirty-two general-purpose registers, r0 to r31, are available. Any of these registers can be used for a data

variable or address variable.

However, r0 and r30 are implicitly used by in structions, and care must be exercised w hen using thes e registers.

used as a base pointer when the SLD or SST instruction is used to access the memory. Registers r1, r3 to r5,

and r31 are implicitly used by the assembler and C compiler. When using these registers, therefore, their

contents must be saved so that they are not lost, and later restored to the registers. Register r2 may be used

by a real-time OS. If the real-time OS used does not use r2, r2 can be used as a register for variables.

Table 3-1. Program Register List

Name Usage Operation

r0 Zero register Always holds 0.

r1 Assembler-reserved register Used as a working register for creating 32-bit immediate

r2 Register for address/data variable (if the real-time OS used does not use r2)

r3 Stack pointer Used to generate a stack frame when a function is called

r4 Global pointer Used to access a global variable in the data area

r5 Text pointer Used as a register that p oints to the beginning of a text area

(area where program codes are located)

r6 to r29 Registers for address/data variable

r30 Element pointer Used as a base pointer when memory is accessed

r31 Link pointer Used when the compiler calls a function

PC Program counter Holds an instruction address during program execution

Remark For further details on the r1, r3 to r5, and r31that are used in the assembler and C compiler, refer to the

CA850 (C Compiler Package) Assembly L anguage of the user’s Manual.

(2) Program counter (PC)

The program counter hol ds an instruction ad dress during pr ogram execution. The lower 26 bits of this counter

are valid. Bits 31 to 26 are fixed to 0. A carry from bit 25 to bit 26 is ignored.

Bit 0 is always fixed to 0, and execution cannot branch to an odd address.

31 2625 1 0

PC 0Default value

00000000H

Instruction address during program execution

Fixed to 0

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3.2.2 System register set

The system registers are used to control the status of the CPU or to hold interrupt information.

Data can be read from or written to system registers by setting one of the system register numbers listed below

using a system register load or store (LDSR or STSR) instruction.

Table 3-2. System Register Numbers

Operand Specification Register No. Syste m Register Name

LDSR

Instruction STSR

Instruction

0 Interrupt status saving register (EIPC)Note 1 √ √

1 Interrupt status saving register (EIPSW)Note 1 √ √

2 NMI status saving register (FEPC) √ √

3 NMI status saving register (FEPSW) √ √

4 Interrupt source register (ECR) × √

5 Program status word (PSW) √ √

6 to 15 Reserved for future function expansion. (Operation is not guaranteed if these

registers are accessed.) × ×

16 CALLT execution status saving register (CTPC) √ √

17 CALLT execution status saving register (CTPSW) √ √

18 Exception/debug trap status saving register (DBPC) √Note 2 √

19 Exception/debug trap status saving register (DBPSW) √Note 2 √

20 CALLT base pointer (CTBP) √ √

21 to 31 Reserved for future function expansion. (Operation is not guaranteed if these

registers are accessed.)

× ×

Notes 1. Because only one pair of these registers is provided, the c ontents of these registers must be saved by

program when multiple interrupt servicing is enable d.

2. These registers can be accessed only between DBTRAP or the illegal instruction execution and DBRET

instruction execution.

Caution Even if bit 0 of EIPC, FEPC, or CTPC is set to 1 by the LDSR instruction, bit 0 is ignored when

execution returns from interrupt servicing to the main routine by the RETI instruction (this is

because bit 0 of the PC is fixed to 0). When setting a value to EIPC, FEPC, or CTPC, set an even

value (bit = 0).

Remark √: Accessible

×: Access prohibited

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(1) Interrupt status saving registers (EIPC and EIPSW)

EIPC and EIPSW are interrupt status saving registers.

If a software exception or a maskable interrupt occurs, the contents of the progr am counter (PC) are saved to

EIPC, and the contents of the program status word (PSW) are saved to EIPSW. (The contents of the PC and

PSW are saved to FEPC and FEPSW (NMI status saving registers) if a non-maskable interrupt (NMI) occurs.)

The address of the instruction next to the one under execution, except some instructions (see 17.7 Periods in

Which Interrupts Are Not Acknowledged by CPU), is saved to EIPC when a software exception or a maskable

interrupt occurs.

The current contents of the PSW are saved to EIPSW.

Because only one pair of interrupt status saving regist ers is available, the contents of these registers must be

saved by program if multiple interrupt servicing is enabl ed.

Bits 31 to 26 of EIPC and bits 31 to 8 of EIPSW are reserved for future function expansion (these bits are fixed

to 0). The values of EIPC restore the PC, and the values of EIPSW do to the PSW by the RETI instruction.

31 0

EIPC 00 Default value

0xxxxxxxH

(x: undefined)

2625

0000

31 0

EIPSW 00 Default value

000000xxH

(x: undefined)

000000 000000 000000 0000(Contents of PSW)

(Contents of PC)

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(2) NMI status saving registers (FEPC and FEPSW)

FEPC and FEPSW are NMI status saving registers.

If a non-maskable interrupt (NMI) occurs, the contents of the program counter (PC) are saved to FEPC, and

the contents of the program status word (PS W ) are saved to FEPSW.

The address of the instruction next to the one under execution, except some instructions, is saved to FEPC.

The current contents of the PSW are saved to FEPSW.

Bits 31 to 26 of FEPC and bits 31 to 8 of FEPSW are reserved for future function expansion (these bits are

fixed to 0).

31 0

FEPC 00 Default value

0xxxxxxxH

(x: undefined)

2625

0 0 0 0

31 0

FEPSW 00 Default value

000000xxH

(x: undefined)

0 0 0 0 00 0 0 0 0 00 0 0 0 0 00 0 0 0 0 (Contents of PSW)

(Contents of PC)

(3) Interrupt source register (ECR)

The interrupt source register ECR holds the source of an exception or an interrupt that has occurred. The

value ECR is to hold is a n exception code for each interrupt source. This register is a read- only register. No

data can be written to this register by using the LDSR instruction.

31 0

ECR FECC EICC Default value

00000000H

1615

Bit Position Bit Name Meaning

31 to 16 FECC Exception code of non-maskable interrupt (NMI)

15 to 0 EICC Exception code of exception or maskable interrupt

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(4) Program status word (PSW)

The program status word (PSW) is a collection of flags that indicate the status of the program (result of

instruction execution) or the CPU.

If the contents of any bit of this register are changed by usi ng the LDSR instruction, the new contents b ecome

valid immediately after execution of the LDSR instruction. When the ID flag is set to 1, however,

acknowledgment of an interrupt request is disable d from when the LDSR in struction is still under execution.

Bits 31 to 8 are reserved for future function expansion (these bits are fixed to 0).

31 0

PSW RFU Default value

00000020H

SAT

Bit Position Flag Name Meaning

31 to 8 RFU Reserved field. Always fixed to 0

7 NP

Indicates that a non-maskable interrupt (NMI) is b eing serviced. This flag is set to 1, disabling

multiple interrupt servicing, when an NMI request is acknowledged.

0: NMI is not being serviced.

1: NMI is being serviced.

6 EP

Indicates that exception processing is in progress. This flag is set to 1 when an exception is

generated. Interrupt requests are acknowledged even if this bit is set.

0: Exception is not being processed.

1: Exception is being processed.

5 ID

Indicates whether a maskable interrupt request can be acknowledged.

0: Interrupts enabled

1: Interrupts disabled

4 SATNote Indicates that the result of an operation of a satu ration operation inst ruction overflows and that

the operation result is saturated. Because this is a cumulative flag, it is set to 1 if the operation

result of a saturation operation instruction is saturated, and is not cleared to 0 even if the

operation result of the subsequent instructions is not satura ted. This flag is cleared to 0 by the

LDSR instruction. When an arithmetic operation instruction is executed, this flag is neither set

to 1 nor cleared to 0.

0: Not saturated

1: Saturated

3 CY

Indicates whether a carry or a borrow occurred as a result of an operation.

0: Carry or borrow did not occur.

1: Carry or borrow occurred.

2 OVNote Indicates whether an overflow occurred during an operation.

0: Overflow did not occur.

1: Overflow occurred.

1 SNote Indicates whether the result of an operation is negative or not.

0: Operation result is positive or 0.

1: Operation result is negative.

0 Z

Indicates whether the result of an operation is 0 or not.

0: Result of operation is not 0.

1: Result of operation is 0.

Remark Refer to the next page for the explanation of Note.

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User’s Manual U17830EE1V0UM00 113

(2/2)

Note The result of an operation of saturation processing is determined by the contents of the OV and S flags when a

saturation operation is performed. The SAT flag is set to 1 only when the OV flag is set to 1 as a result of a

saturation operation.

Flag Status

Status of Operation

Result SAT OV S

Result of Operation of Saturation

Processing

Maximum positive

value is exceeded. 1 1 0 7FFFFFFFH

Maximum negative

value is exceeded. 1 1 1 80000000H

Positive (maximum

value not exceeded) 0

Negative (maximum

value not exceeded)

Holds value

before

operation.

Operation result itself

(5) CALLT execution status saving registers (CTPC and CTPSW)

CTPC and CTPSW are CALLT execution status saving registers.

When the CALLT instruction is executed, the contents of the program counter (PC) are saved to CTPC, and

the contents of the program status word (PS W ) are saved to CTPSW.

The contents saved to CTPC are the address of the instruction next to the CALLT instruction.

The current contents of the PSW are saved to CTPSW.

Bits 31 to 26 of CTPC and bits 31 to 8 of CTPSW are reserved for future function expansion (these bits are

fixed to 0).

31 0

CTPC (Contents of PC)

00 Default value

0xxxxxxxH

(x: undefined)

2625

0 0 0 0

31 0

CTPSW 00 Default value

000000xxH

(x: undefined)

0 0 0 0 00 0 0 0 0 00 0 0 0 0 00 0 0 0 0 (Contents of PSW)

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(6) Exception/debug trap status saving registers (DBPC and DBPSW)

DBPC and DBPSW are exception/debug trap status saving registers.

If an exception trap or a debug trap occurs, the contents of the program counter (PC) are saved to DBPC, and

the contents of the program status word (PSW ) are saved to DBPSW.

The contents saved to DBPC are the address of the instruction next to the one under execution when an

exception trap or a debug trap has occurre d.

The current contents of the PSW are saved to DBPSW.

These registers can be accessed only between DBTRAP or the illegal instruction execution and DBRET

instruction execution.

Bits 31 to 26 of DBPC and bits 31 to 8 of DBPSW are reserved for future function expansion (these bits are

fixed to 0).

The values of DBPC restore PC, and the values of DBPSW do to PSW by DBRET instruction.

31 0

DBPC 00 Default value

0xxxxxxxH

(x: undefined)

2625

0 0 0 0

31 0

DBPSW 00 Default value

000000xxH

(x: undefined)

0 0 0 0 00 0 0 0 0 00 0 0 0 0 00 0 0 0 0

(Contents of PC)

(Contents of PSW)

(7) CALLT base pointer (CTBP)

The CALLT base pointer (CTBP) is used to specify a table address or to generate a target address (bit 0 is

fixed to 0).

Bits 31 to 26 of this register are reserved for future function expansion (these bits are fixed to 0).

31 0

CTBP 00 Default value

0xxxxxxxH

(x: undefined)

2625

00000

(Base address)

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User’s Manual U17830EE1V0UM00 115

3.3 Operation Modes

The V850ES/Fx2 have the following operation modes.

FLMD0 FLMD1 Operation Mode

0 X Normal operation mode

1 0 Flash memory programming mode

1 1 Setting prohibited

Remark x: don't care

(1) Normal operation mode

After system reset is released, each pin related to the bus interface is set in the port mode, execution branch es

to the reset entry address of the internal ROM, and instruction processing is started. When the PMCDL,

PMCCM, PMCCS, and PMCCT registers are set in the control mode by software, an external device can be

connected to the external memory area.

(2) Flash memory programming mode

When this mode is specified, the internal flas h memory can be programmed by using a flash programmer .

(3) On-chip debug mode

The V850ES/FJ2 is provided with an on-chip debug function that employ the JTAG (Joint Test Action Group)

communication specifications and that is executed via an N-Wire emulator. For details, see CHAPTER 27 ON-

CHIP DEBUG FUNCTION."

3.3.1 Specifying operation mode

Specify the operation mode by using the FLMD0 and FLMD1 pins. In the normal mode, make sure that the

FLMD0/IC pin goes low when reset is releas ed.

In the flash memory programming mode, a high level is in put to the FLMD0 pin from th e flash programmer if a flash

programmer is connected, but it must be input from an external circuit in the self-programming mode.

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3.4 Address Space

3.4.1 CPU address space

The CPU of the V850ES/Fx2 has 32-bit architecture, and supp orts a linear address space (data space) of up to 4

GB for operand addressing (data acc ess). It also su pports a lin ear addr es s space ( progr am spac e) of up to 64 MB for

addressing instruction addresses. However, both the program and data spaces have areas prohibited from being

used. For details, refer to Figure 3-2.

Figure 3-1 illustrates the CPU address space.

Figure 3-1. CPU Address Space

Data area

(4 GB, linear)

Program area

(64 MB, linear)

CPU address space

FFFFFFFFH

04000000H

03FFFFFFH

00000000H

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User’s Manual U17830EE1V0UM00 117

3.4.2 Image

Up to 16 MB of external memory area, internal ROM area, and internal RAM area of up to 16 MB of linear address

space (program space) are supported for addressing of instruction addresses. Up to 4 GB of linear address space

(data space) are supported for operand addressing (data access). Note, however, that there seems to be sixty-four

64 MB physical address spaces on the 4 GB address space. This means that the same 64 MB physical address

space is accessed regardless of the value of bits 31 to 26.

Figure 3-2. Image on Address Space

Peripheral I/O area

Data space

Internal ROM area

(external memory area)

External memory area

Use-prohibited area

Internal RAM area

Internal ROM area

(external memory area)

External memory area

Use-prohibited area

Internal RAM area

Use-prohibited area

Program space

4 GB

64 MB

16 MB

Image 63

Image 1

Image 0

64 MB

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118

3.4.3 Wraparound of CPU address space

(1) Program space

Of the 32 bits of the PC (program counter), the higher 6 b its are fixed to 0 and on ly the lower 26 bits are valid.

The higher 6 bits ignore a carry or borrow from bit 25 to 26 during branch address calculation.

Therefore, the highest address of the program space, 03FFFFFFH, and the lowest address, 00000000H, are

contiguous addresses. That the h ighest address and the lowest address of the program space are contiguous

in this way is called wraparound.

Caution Because the 4 KB area of addresses 03FFF000H to 03FFFFFFH is an on-chip peripheral I/O

area, instructions cannot be fetched from this area. Therefore, do not execute an operation

in which the result of a branch address calculation affects this area.

Program space

(+) direction (−) direction

00000001H

00000000H

03FFFFFFH

03FFFFFEH

(2) Data space

The result of an operand address calculation operation that exceeds 32 bits is ignored.

Therefore, the highest address of the data space, FFFFFFFFH, and the lowest address, 00000000H, are

contiguous, and wraparound occurs at the boundary of these addresses.

Data space

(+) direction (−) direction

00000001H

00000000H

FFFFFFFFH

FFFFFFFEH

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User’s Manual U17830EE1V0UM00 119

3.4.4 Memory map

The V850ES/Fx2 reserves the areas shown in Figure 3-3.

Figure 3-3. Data Memory Map (Physical Addresses)

3FFFFFFH

3FEC000H

1000000H

0FFFFFFH

0800000H

07FFFFFH

0400000H

03FFFFFH

0200000H

01FFFFFH

0000000H

3FEBFFFH

3FFFFFFH

3FFF000H

3FFEFFFH

3FF0000H

3FEFFFFH

3FEF000H

3FEEFFFH

3FEC000H

01FFFFFH

0100000H

00FFFFFH

0000000H

(80 KB)

Programmable peripheral

I/O area

Use prohibited

Note 2

Internal RAM area

(60 KB)

Note 1

Internal ROM area

Note 3

(1 MB)

On-chip peripheral I/O area

(4 KB)

External memory area

(8 MB)

External memory area

(4 MB)

External memory area

(2 MB) External memory area

(1 MB)

(2 MB)

Use prohibited

Notes 1. V850ES/FE2: µPD703230: 4K, µPD70F3231: 6K are provided.

V850ES/FF2: µPD703232: 6K , µPD70F3232: 12K , µPD703232: 12K are provided

V850ES/FG2: µPD70F3234: 6K , µPD70F3235: 12K , µPD70F3236: 16K are provided

V850ES/FJ2: µPD70F3237: 12KB, µPD70F3238: 20KB, µPD703239: 20KB are provi ded.

2. Use of addresses 3FEF000H to 3FEFFFFH is prohibited because these addresses are in the same

area as the on-chip peripheral I/O area.

3. A fetch access and a read access to addresses 0000000H to 00FFFFFH is made to the internal

ROM area, but these addresses are use d as an external memory area when a data write access is

made.

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Figure 3-4. Program Memory Map

Internal RAM area (60 KB)

Use prohibited

(program fetch prohibited area)

Use prohibited

(program fetch prohibited area)

External memory area

(14 MB)

External memory area

(1 MB)

Internal ROM area

(1 MB)

03FFFFFFH

03FFF000H

03FFEFFFH

01000000H

00FFFFFFH

03FF0000H

03FEFFFFH

00200000H

001FFFFFH

00100000H

000FFFFFH

00000000H

Remark Instructions can be executed in the external memory area without a branch from the internal ROM

area to the external memory area. For details, refer to 3.4.5 (2) Internal RAM area

CHAPTER 3 CPU FUNCTIONS

User’s Manual U17830EE1V0UM00 121

3.4.5 Areas

(1) Internal flash memory area

Up to 1 MB is reserved as an internal flash memory area.

(a) Internal Mask ROM memory area (64 KB)

64 KB, addresses 0000000H to 000FFFFH, are provided in the following products as an internal flash

memory area.

Accessing addresses 0001000H to 00FFFFFH is prohibited.

• V850ES/FE2:

PD703230

Figure 3-5. Internal Flash Memory Area (64 KB)

Access-prohibited

area

Internal flash memory

00FFFFFH

0010000H

0000FFFFH

0000000H

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(b) Internal flash memory area (128 KB)

128 KB, addresses 0000000H to 001FFFFH, are provided in the following products as an internal flash

memory area.

Accessing addresses 0020000H to 00FFFFFH is prohibited.

• V850ES/FE2:

PD70F3231

• V850ES/FF2:

PD70F3232

• V850ES/FG2:

PD70F3234

Figure 3-6. Internal Flash Memory Area (128 KB)

Access-prohibited

area

Internal flash memory

00FFFFFH

0020000H

001FFFFH

0000000H

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User’s Manual U17830EE1V0UM00 123

256 KB, addresses 0000000H to 003FFFFH, are provided in the following products as an internal flash

memory area.

Accessing addresses 0040000H to 00FFFFFH is prohibited.

• V850ES/FF2:

PD70F3233

• V850ES/FG2:

PD70F3235

• V850ES/FJ2:

PD70F3237

Figure 3-7. Internal Flash Memory Area (256 KB)

Access-prohibited

area

Internal flash memory

00FFFFFH

0040000H

003FFFFH

0000000H

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(d) Internal flash memory area (376 KB)

The following products have a 376 KB area of 00000000H to 0005DFFFH.

Use of addresses 005E000H to 00FFFFFH is prohibited.

• V850ES/FJ2:

PD70F3238

Figure 3-8. Internal Flash Memory Area (376 KB)

Access-prohibited

area

Internal flash memory

00FFFFFH

005E000H

005DFFFH

0000000H

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User’s Manual U17830EE1V0UM00 125

(e) Internal flash memory area (384 KB)

The following products have a 384 KB area of 00000000H to 0005FFFFH.

Use of addresses 0060000H to 00FFFFFH is prohibited.

• V850ES/FG2:

PD70F3236

Figure 3-9. Internal Flash Memory Area (384 KB)

Access-prohibited

area

Internal flash memory

00FFFFFH

0060000H

0005FFFFH

0000000H

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(f) Internal flash memory area (512 KB)

512 KB, addresses 0000000H to 007FFFFH, are provided in the following product as an internal flash

memory area.

Accessing addresses 0080000H to 00FFFFFH is prohibited.

• V850ES/FJ2:

PD70F3239

Figure 3-10. Internal Flash Memory Area (512 KB)

Access-prohibited

area

Internal flash memory

00FFFFFH

0080000H

007FFFFH

0000000H

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User’s Manual U17830EE1V0UM00 127

(2) Internal RAM area

Up to 60 KB are reserved as an internal RAM area.

(a) Internal RAM (4 KB)

The following product has a 4 KB area from addresses 3FFE000H to 3FFEFFFH. Use of addresses

3FF0000H to 3FFDFFFH is prohibited.

• V850ES/FE2:

PD703230

Figure 3-11. Internal RAM Area (4 KB)

FFEFFF

FFE

000

FFF

0000

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128

(b) Internal RAM (6 KB)

The following products have a 6 KB area from addresses 3FFD800H to 3FFEFFFH. Use of addresses

3FF0000H to 3FFD7FFH is prohibited.

• V850ES/FE2:

PD70F3231

• V850ES/FF2:

PD703232

• V850ES/FG2:

PD70F3234

Figure 3-12. Internal RAM Area (6 KB)

Access-prohibited

area

Internal RAM

3FFEFFFH

3FFD800H

3FFD7FFH

3FF0000H

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User’s Manual U17830EE1V0UM00 129

The following products have a 12 KB area from addresses 3FFC000H to 3FFEFFFH. Use of addresses

3FF0000H to 3FFBFFFH is prohibited.

• V850ES/FF2:

PD70F3232, µPD70F3233

• V850ES/FG2:

PD70F3235

• V850ES/FJ2:

PD70F3237

Figure 3-13. Internal RAM Area (12 KB)

Access-prohibited

area

Internal RAM

3FFEFFFH

3FFC000H

3FFBFFFH

3FF0000H

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(d) Internal RAM (16 KB)

The following product has a 16 KB area from addresses 3FFb000H to 3FFEFFFH. Use of addresses

3FF0000H to 3FFAFFFH is prohibited.

• V850ES/FG2:

PD70F3236

Figure 3-14. Internal RAM Area (16 KB)

Access-prohibited

area

Internal RAM

3FFEFFFH

3FFB000H

3FFAFFFH

3FF0000H

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User’s Manual U17830EE1V0UM00 131

(e) Internal RAM (20 KB)

The following products have a 20 KB area from addresses 3FFA000H to 3FFEFFFH. Use of addresses

3FF0000H to 3FF9FFFH is prohibited.

• V850ES/FJ2:

PD70F3238,

PD70F3239

Figure 3-15. Internal RAM Area (20 KB)

Access-prohibited

area

Internal RAM

3FFEFFFH

3FFA000H

3FF9FFFH

3FF0000H

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(3) On-chip peripheral I/O area

4 KB, addresses 3FFF000H to 3FFFFFFH, are reserved as an on-chip peripheral I/O area.

Figure 3-16. On-Chip Peripheral I/O Area

On-chip peripheral I/O area

(4 KB)

3FFFFFFH

3FFF000H

Peripheral I/O registers that are used to specify the operation mode of and to monitor the status of the on-chip

peripheral I/O are mapped to the on-chip peripheral I/O area. Program cannot be fetched from this area.

Cautions 1. If a register is accessed in word units, a word area with the lower 2 bits of an address

ignored is accessed in halfword units in the order of the lower halfword and the higher

halfword.

2. If a register that can be accessed in bytes is accessed in halfwords, the higher 8 bits are

undefined when the register is read. Data is written to the lower 8 bits when a write

access is made to the register.

3. Addresses not defined as those of registers are reserved for future expansion. If these

addresses are accessed, the operation is undefined and not guaranteed.

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User’s Manual U17830EE1V0UM00 133

(4) Programmable peripheral I/O area

12 KB of addresses 03FEC000H to 03FEEFFFH are reserved as the programmable per ipheral I/O area.

Figure 3-17. Programmable Peripheral I/O Area

Programmable peripheral

I/O area

(12 KB)

03FEEFFFH

03FEC000H

Caution The programmable peripheral I/O area is seen as images of 256 MB each in the 4 GB

address space.

(5) External memory area

An external memory area of 15 MB (0100000H to 0FFFFFFH) is available. For details, refer to CHAPTER 5

BUS CONTROL FUNCTION.

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134

3.4.6 Recommended use of address space

With the architecture of the V850ES/Fx2, a register that serves as a pointer must be secured for address

generation when operand data in the data space is to be accessed. The ±32 KB of this pointer register can be directly

accessed from an instruction for operand data. However, the number of general-purpose registers that can be used

as a pointer is limited. The nu mber of gener al-purpose r egist ers that can be all ocated for variab les can b e maximized

and the program size can be reduced by suppressing a drop in performance due to address calculation when a

pointer value is to be chan ged.

(1) Program space

Of the 32 bits of the PC (program counter), only the lower 26 b its are valid and the high er 6 bits are fixed to 0.

Therefore, a contiguous 64 MB space, starting from addres s 00000000H, is mapped as a program space.

When using the internal RAM area as a program space, access the following addresses.

Caution The prefetch operation (invalid fetch) across internal peripheral I/O area is not generated if

there is a branch instruction in the upper-limit addresses of the internal RAM area.

RAM Size Addresses to Be Accessed

20 KB 3FFA000H to 3FFEFFFH

16 KB 3FFB000H to 3FFEFFFH

12 KB 3FFC000H to3FFEFFFH

6 KB 3FFD800H to3FFEFFFH

4 KB 3FFE000H to3FFEFFFH

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User’s Manual U17830EE1V0UM00 135

(2) Data space

On the 4 GB CPU address space of the V850ES/Fx2, there seems to be sixty-four 64 MB physical address

spaces. Therefore, 26-bit addresses with the most significant bit (bit 25) sign-extended u p to 32 bits in length

are allocated.

(a) Application example of wraparound

If R = r0 (zero register) is specified for the LD/ST disp16 [R] instruction, the range of address 0000000 0H

±32 KB can be addressed by sign-extended disp16. All the resources of the internal hardware can be

addressed by using one pointer.

The zero register (r0) is fixed to 0 by hardware and a register used for a pointer is basically unnecessary.

Example:

PD70F3239

Use prohibited

Internal ROM area

Internal RAM area

On-chip peripheral

I/O area

32 KB

(R = ) 4 KB

20 KB

8 KB

00080000H

00007FFFH

00000000H

FFFFF000H

FFFFEFFFH

FFFFA000H

FFFF9FFFH

FFFF8000H

CHAPTER 3 CPU FUNCTIONS

User’s Manual U17830EE1V0UM00

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Figure 3-18. Recommended Memory Map

Program space,

64 MB

FFFFFFFFH

FFFFF000H

FFFFEFFFH

FFFFC000H

FFFFBFFFH

04000000H

03FFFFFFH

03FFF000H

03FFEFFFH

03FF0000H

03FEFFFFH

03FEC000H

03FEBFFFH

01000000H

00FFFFFFH

00020000H

0001FFFFH

00000000H

xFFFFFFFH

xFFFF000H

xFFFEFFFH

xFFF7000H

xFFF6FFFH

xFFEC000H

xFFEBFFFH

x0100000H

x00FFFFFH

x0000000H

External memory

External

memory

Use prohibited

Internal RAM

On-chip

peripheral I/O

Internal RAM

Internal ROM

On-chip

peripheral I/O

On-chip

peripheral I/ONote

Data spaceProgram space

Note Accessing this area is prohibited. To access on-chip peripheral I/O in this area, specify addresses

FFFF000H to FFFFFFFH.

Remarks 1. The upper and lower arrows indicate the area recommended to be used.

2. This figure is the recommended memory map of the uPD70F3238 and uPD79F0239.

CHAPTER 3 CPU FUNCTIONS

User’s Manual U17830EE1V0UM00 137

3.4.7 Peripheral I/O registers

3.4.7.1 V850ES/FE2

(1/9)

Manipulatable Bits

Address Function Register Name Symbol R/W

1 8 16

Default Value

FFFFF004H Port DL PDL √ Undefined

FFFFF004H Port DLL PDLL √ √

Undefined

FFFFF005H Port DLH PDLH √ √

Undefined

FFFFF00CH Port CM PCM √ √

Undefined

FFFFF024H Port mode register DL PMDL √ FFFFH

FFFFF024H Port mode register DLL PMDLL √ √

FFH

FFFFF025H Port mode register DLH PMDLH √ √

FFH

FFFFF02CH Port mode register CM PMCM √ √

FFH

FFFFF04CH Port mode control register CM PMCCM √ √

00H

FFFFF064H Peripheral I/O area select control registe r BPC √ 0000H

FFFFF06EH System wait control register VSWC √

77H

FFFFF100H Interrupt mask register 0 IMR0

√ FFFFH

FFFFF100H Interrupt mask register 0L IMR0L √ √ FFH

FFFFF101H Interrupt mask register 0H IMR0H √ √ FFH

FFFFF102H Interrupt mask register 1 IMR1

√ FFFFH

FFFFF102H Interrupt mask register 1L IMR1L √ √ FFH

FFFFF103H Interrupt mask register 1H IMR1H √ √ FFH

FFFFF104H Interrupt mask register 2 IMR2

√ FFFFH

FFFFF104H Interrupt mask register 2L IMR2L √ √ FFH

FFFFF105H Interrupt mask register 2H IMR2H √ √ FFH

FFFFF106H Interrupt mask register 3 IMR3

√ FFFFH

FFFFF106H Interrupt mask register 3L IMR3L √ √ FFH

FFFFF107H Interrupt mask register 3H IMR3H √ √ FFH

FFFFF108H Interrupt mask register 4 IMR4

√ FFFFH

FFFFF108H Interrupt mask register 4L IMR4L √ √ FFH

FFFFF109H Interrupt mask register 4H IMR4H

R/W

√ √ FFH

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Manipulatable Bits

Address Function Register Name Symbol R/W

1 8 16

Default Value

FFFFF10AH Interrupt mask register 5L IMR5L √ √ FFH

FFFFF110H Interrupt control register LVIIC √ √ 47H

FFFFF112H Interrupt control register PIC0 √ √ 47H

FFFFF114H Interrupt control register PIC1 √ √ 47H

FFFFF116H Interrupt control register PIC2 √ √ 47H

FFFFF118H Interrupt control register PIC3 √ √ 47H

FFFFF11AH Interrupt control register PIC4 √ √ 47H

FFFFF11CH Interrupt control register PIC5 √ √ 47H

FFFFF11EH Interrupt control register PIC6 √ √ 47H

FFFFF120H Interrupt control register PIC7 √ √ 47H

FFFFF122H Interrupt control register TQ0OVIC √ √ 47H

FFFFF124H Interrupt control register TQ0CCIC0 √ √ 47H

FFFFF126H Interrupt control register TQ0CCIC1 √ √ 47H

FFFFF128H Interrupt control register TQ0CCIC2 √ √ 47H

FFFFF12AH Interrupt control register TQ0CCIC3 √ √ 47H

FFFFF12CH Interrupt control register TP0OVIC √ √ 47H

FFFFF12EH Interrupt control register TP0CCIC0 √ √ 47H

FFFFF130H Interrupt control register TP0CCIC1 √ √ 47H

FFFFF132H Interrupt control register TP1OVIC √ √ 47H

FFFFF134H Interrupt control register TP1CCIC0 √ √ 47H

FFFFF136H Interrupt control register TP1CCIC1 √ √ 47H

FFFFF138H Interrupt control register TP2OVIC √ √ 47H

FFFFF13AH Interrupt control register TP2CCIC0 √ √ 47H

FFFFF13CH Interrupt control register TP2CCIC1

R/W

√ √ 47H

CHAPTER 3 CPU FUNCTIONS

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Manipulatable Bits

Address Function Register Name Symbol R/W

1 8 16

Default Value

FFFFF13EH Interrupt control register TP3OVIC √ √ 47H

FFFFF140H Interrupt control register TP3CCIC0 √ √ 47H

FFFFF142H Interrupt control register TP3CCIC1 √ √ 47H

FFFFF144H Interrupt control register TM0EQIC0 √ √ 47H

FFFFF146H Interrupt control register CB0RIC √ √ 47H

FFFFF148H Interrupt control register CB0TIC √ √ 47H

FFFFF14AH Interrupt control register CB1RIC √ √ 47H

FFFFF14CH Interrupt control register CB1TIC √ √ 47H

FFFFF14EH Interrupt control register UA0RIC √ √ 47H

FFFFF150H Interrupt control register UA0TIC √ √ 47H

FFFFF152H Interrupt control register UA1RIC √ √ 47H

FFFFF154H Interrupt control register UA1TIC √ √ 47H

FFFFF156H Interrupt control register ADIC √ √ 47H

FFFFF158H Interrupt control register C0ERRIC √ √ 47H

FFFFF15AH Interrupt control register C0WUPIC √ √ 47H

FFFFF15CH Interrupt control register C0RECIC √ √ 47H

FFFFF15EH Interrupt control register C0TRXIC √ √ 47H

FFFFF160H Interrupt control register KRIC √ √ 47H

FFFFF162H Interrupt control register

WTIIC

√ √ 47H

FFFFF164H Interrupt control register WTIC

R/W

√ √ 47H

FFFFF1FAH In-service priority register ISPR R √ √ 00H

FFFFF1FCH Command register PRCMD W √ Undefined

FFFFF1FEH Power save control register PSC √ √ 00H

FFFFF200H A/D converter mode register 0 ADA0M0 √ √ 00H

FFFFF201H A/D converter mode register 1 ADA0M1 √ √ 00H

FFFFF202H A/D converter channel specification register 0 ADA0S √ √ 00H

FFFFF203H A/D converter mode register 2 ADA0M2 √ √ 00H

FFFFF204H Power-fail comparison mode register ADA0PFM √ √ 00H

FFFFF205H Power-fail comparison threshold value register ADA0PFT

R/W

√ √ 00H

CHAPTER 3 CPU FUNCTIONS

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Manipulatable Bits

Address Function Register Name Symbol R/W

1 8 16

Default Value

FFFFF210H A/D conversion result register 0 ADA0CR0 √ Undefined

FFFFF211H A/D conversion result register 0H ADA0CR0H √

Undefined

FFFFF212H A/D conversion result register 1 ADA0CR1 √ Undefined

FFFFF213H A/D conversion result register 1H ADA0CR1H √

Undefined

FFFFF214H A/D conversion result register 2 ADA0CR2 √ Undefined

FFFFF215H A/D conversion result register 2H ADA0CR2H √

Undefined

FFFFF216H A/D conversion result register 3 ADA0CR3 √ Undefined

FFFFF217H A/D conversion result register 3H ADA0CR3H √

Undefined

FFFFF218H A/D conversion result register 4 ADA0CR4 √ Undefined

FFFFF219H A/D conversion result register 4H ADA0CR4H √

Undefined

FFFFF21AH A/D conversion result register 5 ADA0CR5 √ Undefined

FFFFF21BH A/D conversion result register 5H ADA0CR5H √

Undefined

FFFFF21CH A/D conversion result register 6 ADA0CR6 √ Undefined

FFFFF21DH A/D conversion result register 6H ADA0CR6H √

Undefined

FFFFF21EH A/D conversion result register 7 ADA0CR7 √ Undefined

FFFFF21FH A/D conversion result register 7H ADA0CR7H √

Undefined

FFFFF220H A/D conversion result register 8 ADA0CR8 √ Undefined

FFFFF221H A/D conversion result register 8H ADA0CR8H √

Undefined

FFFFF222H A/D conversion result register 9 ADA0CR9 √ Undefined

FFFFF223H A/D conversion result register 9H ADA0CR9H

√

Undefined

FFFFF300H Key return mode register KRM √ √ 00H

FFFFF308H Selector operation control register 0 SELCNT0 √ √ 00H

FFFFF318H Noise elimination control register NFC √ √ 00H

FFFFF400H Port 0 P0 √ √ Undefined

FFFFF406H Port 3 P3 √ Undefined

FFFFF406H Port 3L P3L √ √ Undefined

FFFFF408H Port 4 P4 √ √ Undefined

FFFFF40AH Port 5 P5 √ √ Undefined

FFFFF40EH Port 7L P7L √ √ Undefined

FFFFF40FH Port 7H P7H √ √ Undefined

FFFFF412H Port 9 P9 √ Undefined

FFFFF412H Port 9L P9L √ √ Undefined

FFFFF413H Port 9H P9H

R/W

√ √ Undefined

CHAPTER 3 CPU FUNCTIONS

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Manipulatable Bits

Address Function Register Name Symbol R/W

1 8 16

Default Value

FFFFF420H Port mode register 0 PM0 √ √ FFH

FFFFF426H Port mode register 3 PM3 √ FFFFH

FFFFF426H Port mode register 3L PM3L √ √ FFH

FFFFF428H Port mode register 4 PM4 √ √ FFH

FFFFF42AH Port mode register 5 PM5 √ √ FFH

FFFFF42EH Port mode register 7 PM7 √ FFFFH

FFFFF42EH Port mode register 7L PM7L √ √ FFH

FFFFF42FH Port mode register 7H PM7H √ √ FFH

FFFFF432H Port mode register 9 PM9 √ FFFFH

FFFFF432H Port mode register 9L PM9L √ √ FFH

FFFFF433H Port mode regist er 9H PM9H √ √ FFH

FFFFF440H Port mode control register 0 PMC0 √ √ 00H

FFFFF446H Port mode control register 3 PMC3 √ 0000H

FFFFF446H Port mode control register 3L PMC3L √ √ 00H

FFFFF447H Port mode control register 3H PMC3H √ √ 00H

FFFFF448H Port mode control register 4 PMC4 √ √ 00H

FFFFF44AH Port mode control register 5 PMC5 √ √ 00H

FFFFF452H Port mode control register 9 PMC9 √ 0000H

FFFFF452H Port mode control register 9L PMC9L √ √ 00H

FFFFF453H Port mode control register 9H PMC9H √ √ 00H

FFFFF460H Port function control register 0 PFC0 √ √ 00H

FFFFF466H Port function control register 3L PFC3L √ √ 00H

FFFFF46AH Port function control register 5 PFC5 √ √ 00H

FFFFF472H Port function control register 9 PFC9 √ 0000H

FFFFF472H Port function control register 9L PFC9L √ √ 00H

FFFFF473H Port function control register 9H PFC9H √ √ 00H

FFFFF540H TMQ0 control register 0 TQ0CTL0 √ √ 00H

FFFFF541H TMQ0 control register 1 TQ0CTL1 √ √ 00H

FFFFF542H TMQ0 I/O control register 0 TQ0IOC0 √ √ 00H

FFFFF543H TMQ0 I/O control register 1 TQ0IOC1

R/W

√ √ 00H

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Manipulatable Bits

Address Function Register Name Symbol R/W

1 8 16

Default Value

FFFFF544H TMQ0 I/O control register 2 TQ0IOC2 √ √ 00H

FFFFF545H TMQ0 option register 0 TQ0OPT0 √ √ 00H

FFFFF546H TMQ0 capture/ compare registe r 0 TQ0CCR0 √ 0000H

FFFFF548H TMQ0 capture/ compare registe r 1 TQ0CCR1 √ 0000H

FFFFF54AH TMQ0 capture/compare register 2 TQ0CCR2 √ 0000H

FFFFF54CH TMQ0 capture/compare register 3 TQ0CCR3

R/W

√ 0000H

FFFFF54EH TMQ0 counter read buffer register TQ0CNT R √ 0000H

FFFFF590H TMP0 control register 0 TP0CTL0 √ √ 00H

FFFFF591H TMP0 control register 1 TP0CTL1 √ √ 00H

FFFFF592H TMP0 I/O control register 0 TP0IOC0 √ √ 00H

FFFFF593H TMP0 I/O control register 1 TP0IOC1 √ √ 00H

FFFFF594H TMP0 I/O control register 2 TP0IOC2 √ √ 00H

FFFFF595H TMP0 option register 0 TP0OPT0 √ √ 00H

FFFFF596H TMP0 capture/compare register 0 TP0CCR0 √ 0000H

FFFFF598H TMP0 capture/compare register 1 TP0CCR1

R/W

√ 0000H

FFFFF59AH TMP0 counter read buffer register TP0CNT R √ 0000H

FFFFF5A0H TMP1 control register 0 TP1CTL0 √ √ 00H

FFFFF5A1H TMP1 control register 1 TP1CTL1 √ √ 00H

FFFFF5A2H TMP1 I/O control register 0 TP1IOC0 √ √ 00H

FFFFF5A3H TMP1 I/O control register 1 TP1IOC1 √ √ 00H

FFFFF5A4H TMP1 I/O control register 2 TP1IOC2 √ √ 00H

FFFFF5A5H TMP1 option register 0 TP1OPT0 √ √ 00H

FFFFF5A6H TMP1 capture/compare register 0 TP1CCR0 √ 0000H

FFFFF5A8H TMP1 capture/compare register 1 TP1CCR1

R/W

√ 0000H

FFFFF5AAH TMP1 counter read buffer register TP1CNT R √ 0000H

FFFFF5B0H TMP2 control register 0 TP2CTL0 √ √ 00H

FFFFF5B1H TMP2 control register 1 TP2CTL1 √ √ 00H

FFFFF5B2H TMP2 I/O control register 0 TP2IOC0 √ √ 00H

FFFFF5B3H TMP2 I/O control register 1 TP2IOC1 √ √ 00H

FFFFF5B4H TMP2 I/O control register 2 TP2IOC2 √ √ 00H

FFFFF5B5H TMP2 option register 0 TP2OPT0 √ √ 00H

FFFFF5B6H TMP2 capture/compare register 0 TP2CCR0 √ 0000H

FFFFF5B8H TMP2 capture/compare register 1 TP2CCR1

R/W

√ 0000H

FFFFF5BAH TMP2 counter read buffer register TP2CNT R √ 0000H

FFFFF5C0H TMP3 control register 0 TP3CTL0 √ √ 00H

FFFFF5C1H TMP3 control register 1 TP3CTL1 √ √ 00H

FFFFF5C2H TMP3 I/O control register 0 TP3IOC0 √ √ 00H

FFFFF5C3H TMP3 I/O control register 1 TP3IOC1 √ √ 00H

FFFFF5C4H TMP3 I/O control register 2 TP3IOC2 √ √ 00H

FFFFF5C5H TMP3 option register 0 TP3OPT0 √ √ 00H

FFFFF5C6H TMP3 capture/compare register 0 TP3CCR0 √ 0000H

FFFFF5C8H TMP3 capture/compare register 1 TP3CCR1

R/W

√ 0000H

CHAPTER 3 CPU FUNCTIONS

User’s Manual U17830EE1V0UM00 143

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Manipulatable Bits

Address Function Register Name Symbol R/W

1 8 16

Default Value

FFFFF5CAH TMP3 counter read buffer register TP3CNT R √ 0000H

FFFFF610H TMQ1 timer control register 0 TQ1CTL0 R/W √ √ 00H

FFFFF680H Watch timer operation mode register WTM √ √ 00H

FFFFF690H TMM0 control register 0 TM0CTL0 √ √ 00H

FFFFF694H TMM0 compare register 0 TM0CMP0 √ 0000H

FFFFF6C0H Oscillation stabilization time select register OSTS √ 06H

FFFFF6C1H PLL lockup time specification register PLLS √ 03H

FFFFF6D0H Watchdog timer mode register 2 WDTM2 √ 67H

FFFFF6D1H Watchdog timer enable register WDTE √ 9AH

FFFFF706H Port function control expansion register 3L PFCE3L √ √ 00H

FFFFF70AH Port function control expansion register 5 PFCE5 √ √ 00H

FFFFF712H Port function control expansion register 9 PFCE9 √ 0000H

FFFFF712H Port function control expansion register 9L PFCE9L √ √ 00H

FFFFF713H Port function control expansion register 9H PFCE9H √ √ 00H

FFFFF802H System status register SYS √ √ 00H

FFFFF80CH Ring OSC mode register RCM √ √ 00H

FFFFF820H Power save mode register PSMR

R/W

√ √ 00H

FFFFF824H Lock register LOCKR R √ √ 00H

FFFFF828H Processor clock control register PCC √ √ 03H

FFFFF82CH PLL control register PLLCTL

R/W

√ √ 01H

FFFFF82EH CPU operating clock statu s regist er CCLS R √ √ 00H

FFFFF82FH Programmable clock mode register PCLM √ √ 00H

FFFFF870H Clock monitor mode register CLM √ √ 00H

FFFFF888H Reset source flag register RESF √ √ 00H

FFFFF890H Low-voltage detection register LVIM √ √ 00H

FFFFF891H Low-voltage detection level select register LVIS √ 00H

FFFFF892H Internal RAM data status register RAMS √ √ 01H

FFFFF8B0H Prescaler mode register 0 PRSM0 √ 00H

FFFFF8B1H Prescaler compare register 0 PRSCM0 √ 00H

FFFFF9FCH On-chip debug mode register OCDM √ √ 01H

FFFFF9FEH Peripheral emulation register 1 PEMU1 √ √ 00H

FFFFFA00H UARTA0 control register 0 UA0CTL0 √ √ 10H

FFFFFA01H UARTA0 control register 1 UA0CTL1 √ 00H

FFFFFA02H UARTA0 control register 2 UA0CTL2 √ FFH

FFFFFA03H UARTA0 option control register 0 UA0OPT0 √ √ 14H

FFFFFA04H UARTA0 status register UA0STR

R/W

√ √ 00H

FFFFFA06H UARTA0 receive data register UA0RX R √ FFH

FFFFFA07H UARTA0 transmit data register UA0TX √ FFH

FFFFFA10H UARTA1 control register 0 UA1CTL0 √ √ 10H

FFFFFA11H UARTA1 control register 1 UA1CTL1 √ 00H

FFFFFA12H UARTA1 control register 2 UA1CTL2

R/W

√ FFH

Caution For OCDM details, refer to CHAPTER 25 ON-CHIP DEBUG FUNCTION (ON-CHIP DEBUG UNIT).

CHAPTER 3 CPU FUNCTIONS

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Manipulatable Bits

Address Function Register Name Symbol R/W

1 8 16

Default Value

FFFFFA13H UARTA1 option control register 0 UA1OPT0 √ √ 14H

FFFFFA14H UARTA1 status register UA1STR √ √ 00H

FFFFFA16H UARTA1 receive data register UA1RX R √ FFH

FFFFFA17H UARTA1 receive data register UA1TX R/W √ FFH

FFFFFB00H TIP00 noise eliminator control register P00NFC √ √ 00H

FFFFFB04H TIP01 noise eliminator control register P01NFC √ √ 00H

FFFFFB08H TIP10 noise eliminator control register P10NFC √ √ 00H

FFFFFB0CH TIP11 noise eliminator control register P11NFC √ √ 00H

FFFFFB10H TIP20 noise eliminator control register P20NFC √ √ 00H

FFFFFB14H TIP21 noise eliminator control register P21NFC √ √ 00H

FFFFFB18H TIP30 noise eliminator control register P30NFC √ √ 00H

FFFFFB1CH TIP31 noise eliminator control register P31NFC √ √ 00H

FFFFFB50H TIQ00 noise eliminator control register Q00NFC √ √ 00H

FFFFFB54H TIQ01 noise eliminator control register Q01NFC √ √ 00H

FFFFFB58H TIQ02 noise eliminator control register Q02NFC √ √ 00H

FFFFFB5CH TIQ03 noise eliminator control register Q03NFC √ √ 00H

FFFFFC00H External interrupt falling edge specification register 0 INTF0 √ √ 00H

FFFFFC06H External interrupt falling edge specification register 3 INTF3

R/W

√ 0000H

FFFFFC06H External interrupt falling edge specification register 3L INTF3L √ √ 00H

FFFFFC07H External interrupt falling edge specification register 3H INTF3H √ √ 00H

FFFFFC13H External interrupt falling edge specification register 9H INTF9H √ √ 00H

FFFFFC20H External interrupt rising edge spe cification register 0 INTR0 √ √ 00H

FFFFFC26H External interrupt rising edge spe cification register 3 INTR3 √ 0000H

FFFFFC26H External interrupt rising edge specification register 3L INTR3L √ √ 00H

FFFFFC27H External interrupt rising edge specification register 3H INTR3H √ √ 00H

FFFFFC33H External interrupt rising edge spe cification register 9H INTR9H √ √ 00H

FFFFFC40H Pull-up resistor option register 0 PU0 √ √ 00H

FFFFFC46H Pull-up resistor option register 3 PU3 √ 0000H

CHAPTER 3 CPU FUNCTIONS

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Manipulatable Bits

Address Function Register Name Symbol R/W

1 8 16

Default Value

FFFFFC46H Pull-up resistor option register 3L PU3L √ √ 00H

FFFFFC47H Pull-up resistor option register 3H PU3H √ √ 00H

FFFFFC48H Pull-up resistor option register 4 PU4 √ √ 00H

FFFFFC4AH Pull-up resistor option register 5 PU5 √ √ 00H

FFFFFC52H Pull-up resistor option register 9 PU9 √ 0000H

FFFFFC52H Pull-up resistor option register 9L PU9L √ √ 00H

FFFFFC53H Pull-up resistor option register 9H PU9H √ √ 00H

FFFFFD00H CSIB0 control register 0 CB0CTL0 √ √ 01H

FFFFFD01H CSIB0 control register 1 CB0CTL1 √ √ 00H

FFFFFD02H CSIB0 control register 2 CB0CTL2 √ 00H

FFFFFD03H CSIB0 status register CB0STR

R/W

√ √ 00H

FFFFFD04H CSIB0 receive data register CB0RX √ 0000H

FFFFFD04H CSIB0 receive data register L CB0RXL

√ 00H

FFFFFD06H CSIB0 transmit data register CB0TX √ 0000H

FFFFFD06H CSIB0 transmit data register L CB0TXL √ 00H

FFFFFD10H CSIB1 control register 0 CB1CTL0 √ √ 01H

FFFFFD11H CSIB1 control register 1 CB1CTL1 √ √ 00H

FFFFFD12H CSIB1control register 2 CB1CTL2 √ 00H

FFFFFD13H CSIB1 status register CB1STR

R/W

√ √ 00H

FFFFFD14H CSIB1 receive data register CB1RX √ 0000H

FFFFFD14H CSIB1 receive data register L CB1RXL

√ 00H

FFFFFD16H CSIB1 transmit data register CB1TX √ 0000H

FFFFFD16H CSIB1 transmit data register L CB1TXL

R/W

√ 00H

CHAPTER 3 CPU FUNCTIONS

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3.4.1.2 V850ES/FF2

(1/9)

Manipulatable Bits

Address Function Register Name Symbol R/W

1 8 16

Default Value

FFFFF004H Port DL PDL √ Undefined

FFFFF004H Port DLL PDLL √ √

Undefined

FFFFF005H Port DLH PDLH √ √

Undefined

FFFFF008H Port CS PCS √ √

Undefined

FFFFF00AH Port CT PCT √ √

Undefined

FFFFF00CH Port CM PCM √ √

Undefined

FFFFF024H Port mode register DL PMDL √ FFFFH

FFFFF024H Port mode register DLL PMDLL √ √

FFH

FFFFF025H Port mode register DLH PMDLH √ √

FFH

FFFFF02CH Port mode register CM PMCM √ √

FFH

FFFFF04CH Port mode control register CM PMCCM √ √

00H

FFFFF064H Peripheral I/O area select control register BPC √ 0000H

FFFFF06EH System wait control register VSWC √

77H

FFFFF100H Interrupt mask register 0 IMR0

√ FFFFH

FFFFF100H Interrupt mask register 0L IMR0L √ √ FFH

FFFFF101H Interrupt mask register 0H IMR0H √ √ FFH

FFFFF102H Interrupt mask register 1 IMR1

√ FFFFH

FFFFF102H Interrupt mask register 1L IMR1L √ √ FFH

FFFFF103H Interrupt mask register 1H IMR1H √ √ FFH

FFFFF104H Interrupt mask register 2 IMR2

√ FFFFH

FFFFF104H Interrupt mask register 2L IMR2L √ √ FFH

FFFFF105H Interrupt mask register 2H IMR2H √ √ FFH

FFFFF106H Interrupt mask register 3 IMR3

√ FFFFH

FFFFF106H Interrupt mask register 3L IMR3L √ √ FFH

FFFFF107H Interrupt mask register 3H IMR3H √ √ FFH

FFFFF108H Interrupt mask register 4 IMR4

√ FFFFH

FFFFF108H Interrupt mask register 4L IMR4L √ √ FFH

FFFFF109H Interrupt mask register 4H IMR4H

R/W

√ √ FFH

CHAPTER 3 CPU FUNCTIONS

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Manipulatable Bits

Address Function Register Name Symbol R/W

1 8 16

Default Value

FFFFF10AH Interrupt mask register 5L IMR5L √ √ FFH

FFFFF110H Interrupt control register LVIIC √ √ 47H

FFFFF112H Interrupt control register PIC0 √ √ 47H

FFFFF114H Interrupt control register PIC1 √ √ 47H

FFFFF116H Interrupt control register PIC2 √ √ 47H

FFFFF118H Interrupt control register PIC3 √ √ 47H

FFFFF11AH Interrupt control register PIC4 √ √ 47H

FFFFF11CH Interrupt control register PIC5 √ √ 47H

FFFFF11EH Interrupt control register PIC6 √ √ 47H

FFFFF120H Interrupt control register PIC7 √ √ 47H

FFFFF122H Interrupt control register TQ0OVIC √ √ 47H

FFFFF124H Interrupt control register TQ0CCIC0 √ √ 47H

FFFFF126H Interrupt control register TQ0CCIC1 √ √ 47H

FFFFF128H Interrupt control register TQ0CCIC2 √ √ 47H

FFFFF12AH Interrupt control register TQ0CCIC3 √ √ 47H

FFFFF12CH Interrupt control register TP0OVIC √ √ 47H

FFFFF12EH Interrupt control register TP0CCIC0 √ √ 47H

FFFFF130H Interrupt control register TP0CCIC1 √ √ 47H

FFFFF132H Interrupt control register TP1OVIC √ √ 47H

FFFFF134H Interrupt control register TP1CCIC0 √ √ 47H

FFFFF136H Interrupt control register TP1CCIC1 √ √ 47H

FFFFF138H Interrupt control register TP2OVIC √ √ 47H

FFFFF13AH Interrupt control register TP2CCIC0 √ √ 47H

FFFFF13CH Interrupt control register TP2CCIC1

R/W

√ √ 47H

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Manipulatable Bits

Address Function Register Name Symbol R/W

1 8 16

Default Value

FFFFF13EH Interrupt control register TP3OVIC √ √ 47H

FFFFF140H Interrupt control register TP3CCIC0 √ √ 47H

FFFFF142H Interrupt control register TP3CCIC1 √ √ 47H

FFFFF144H Interrupt control register TM0EQIC0 √ √ 47H

FFFFF146H Interrupt control register CB0RIC √ √ 47H

FFFFF148H Interrupt control register CB0TIC √ √ 47H

FFFFF14AH Interrupt control register CB1RIC √ √ 47H

FFFFF14CH Interrupt control register CB1TIC √ √ 47H

FFFFF14EH Interrupt control register UA0RIC √ √ 47H

FFFFF150H Interrupt control register UA0TIC √ √ 47H

FFFFF152H Interrupt control register UA1RIC √ √ 47H

FFFFF154H Interrupt control register UA1TIC √ √ 47H

FFFFF156H Interrupt control register ADIC √ √ 47H

FFFFF158H Interrupt control register C0ERRIC √ √ 47H

FFFFF15AH Interrupt control register C0WUPIC √ √ 47H

FFFFF15CH Interrupt control register C0RECIC √ √ 47H

FFFFF15EH Interrupt control register C0TRXIC √ √ 47H

FFFFF160H Interrupt control register KRIC √ √ 47H

FFFFF162H Interrupt control register

WTIIC

√ √ 47H

FFFFF164H Interrupt control register WTIC

R/W

√ √ 47H

FFFFF1FAH In-service priority register ISPR R √ √ 00H

FFFFF1FCH Command register PRCMD W √ Undefined

FFFFF1FEH Power save control register PSC √ √ 00H

FFFFF200H A/D converter mode register 0 ADA0M0 √ √ 00H

FFFFF201H A/D converter mode register 1 ADA0M1 √ √ 00H

FFFFF202H A/D converter channel specification register 0 ADA0S √ √ 00H

FFFFF203H A/D converter mode register 2 ADA0M2 √ √ 00H

FFFFF204H Power-fail comparison mode register ADA0PFM √ √ 00H

FFFFF205H Power-fail comparison threshold value register ADA0PFT

R/W

√ √ 00H

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Manipulatable Bits

Address Function Register Name Symbol R/W

1 8 16

Default Value

FFFFF210H A/D conversion result register 0 ADA0CR0 √ 00H

FFFFF211H A/D conversion result register 0H ADA0CR0H √

00H

FFFFF212H A/D conversion result register 1 ADA0CR1 √ 00H

FFFFF213H A/D conversion result register 1H ADA0CR1H √

00H

FFFFF214H A/D conversion result register 2 ADA0CR2 √ 00H

FFFFF215H A/D conversion result register 2H ADA0CR2H √

00H

FFFFF216H A/D conversion result register 3 ADA0CR3 √ 00H

FFFFF217H A/D conversion result register 3H ADA0CR3H √

00H

FFFFF218H A/D conversion result register 4 ADA0CR4 √ 00H

FFFFF219H A/D conversion result register 4H ADA0CR4H √

00H

FFFFF21AH A/D conversion result register 5 ADA0CR5 √ 00H

FFFFF21BH A/D conversion result register 5H ADA0CR5H √

00H

FFFFF21CH A/D conversion result register 6 ADA0CR6 √ 00H

FFFFF21DH A/D conversion result register 6H ADA0CR6H √

00H

FFFFF21EH A/D conversion result register 7 ADA0CR7 √ 00H

FFFFF21FH A/D conversion result register 7H ADA0CR7H √

00H

FFFFF220H A/D conversion result register 8 ADA0CR8 √ 00H

FFFFF221H A/D conversion result register 8H ADA0CR8H √

00H

FFFFF222H A/D conversion result register 9 ADA0CR9 √ 00H

FFFFF223H A/D conversion result register 9H ADA0CR9H √

00H

FFFFF224H A/D conversion result register 10 ADA0CR10 √ 00H

FFFFF225H A/D conversion result register 10H ADA0CR10H √

00H

FFFFF226H A/D conversion result register 11 ADA0CR11 √ 00H

FFFFF227H A/D conversion result register 11H ADA0CR11H

√

00H

FFFFF300H Key return mode register KRM √ √ 00H

FFFFF308H Selector operation control register 0 SELCNT0 √ √ 00H

FFFFF318H Noise elimination control register NFC √ √ 00H

FFFFF400H Port 0 P0 √ √ Undefined

FFFFF406H Port 3 P3 √ Undefined

FFFFF406H Port 3L P3L √ √ Undefined

FFFFF407H Port 3H P3H √ √ Undefined

FFFFF408H Port 4 P4 √ √ Undefined

FFFFF40AH Port 5 P5 √ √ Undefined

FFFFF40EH Port 7L P7L √ √ Undefined

FFFFF40FH Port 7H P7H √ √ Undefined

FFFFF412H Port 9 P9 √ Undefined

FFFFF412H Port 9L P9L √ √ Undefined

FFFFF413H Port 9H P9H

R/W

√ √ Undefined

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Manipulatable Bits

Address Function Register Name Symbol R/W

1 8 16

Default Value

FFFFF420H Port mode register 0 PM0 √ √ FFH

FFFFF426H Port mode register 3 PM3 √ FFFFH

FFFFF426H Port mode register 3L PM3L √ √ FFH

FFFFF427H Port mode regist er 3H PM3H √ √ FFH

FFFFF428H Port mode register 4 PM4 √ √ FFH

FFFFF42AH Port mode register 5 PM5 √ √ FFH

FFFFF42EH Port mode register 7 PM7 √ FFFFH

FFFFF42EH Port mode register 7L PM7L √ √ FFH

FFFFF42FH Port mode register 7H PM7H √ √ FFH

FFFFF432H Port mode register 9 PM9 √ FFFFH

FFFFF432H Port mode register 9L PM9L √ √ FFH

FFFFF433H Port mode regist er 9H PM9H √ √ FFH

FFFFF440H Port mode control register 0 PMC0 √ √ 00H

FFFFF446H Port mode control register 3 PMC3 √ 0000H

FFFFF446H Port mode control register 3L PMC3L √ √ 00H

FFFFF447H Port mode control register 3H PMC3H √ √ 00H

FFFFF448H Port mode control register 4 PMC4 √ √ 00H

FFFFF44AH Port mode control register 5 PMC5 √ √ 00H

FFFFF452H Port mode control register 9 PMC9 √ 0000H

FFFFF452H Port mode control register 9L PMC9L √ √ 00H

FFFFF453H Port mode control register 9H PMC9H √ √ 00H

FFFFF460H Port function control register 0 PFC0 √ √ 00H

FFFFF466H Port function control register 3L PFC3L √ √ 00H

FFFFF46AH Port function control register 5 PFC5 √ √ 00H

FFFFF472H Port function control register 9 PFC9 √ 0000H

FFFFF472H Port function control register 9L PFC9L √ √ 00H

FFFFF473H Port function control register 9H PFC9H √ √ 00H

FFFFF540H TMQ0 control register 0 TQ0CTL0 √ √ 00H

FFFFF541H TMQ0 control register 1 TQ0CTL1 √ √ 00H

FFFFF542H TMQ0 I/O control register 0 TQ0IOC0 √ √ 00H

FFFFF543H TMQ0 I/O control register 1 TQ0IOC1

R/W

√ √ 00H

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Manipulatable Bits

Address Function Register Name Symbol R/W

1 8 16

Default Value

FFFFF544H TMQ0 I/O control register 2 TQ0IOC2 √ √ 00H

FFFFF545H TMQ0 option register 0 TQ0OPT0 √ √ 00H

FFFFF546H TMQ0 capture/ compare registe r 0 TQ0CCR0 √ 0000H

FFFFF548H TMQ0 capture/ compare registe r 1 TQ0CCR1 √ 0000H

FFFFF54AH TMQ0 capture/compare register 2 TQ0CCR2 √ 0000H

FFFFF54CH TMQ0 capture/compare register 3 TQ0CCR3

R/W

√ 0000H

FFFFF54EH TMQ0 counter read buffer register TQ0 CNT R √ 0000H

FFFFF590H TMP0 control register 0 TP0CTL0 √ √ 00H

FFFFF591H TMP0 control register 1 TP0CTL1 √ √ 00H

FFFFF592H TMP0 I/O control register 0 TP0IOC0 √ √ 00H

FFFFF593H TMP0 I/O control register 1 TP0IOC1 √ √ 00H

FFFFF594H TMP0 I/O control register 2 TP0IOC2 √ √ 00H

FFFFF595H TMP0 option register 0 TP0OPT0 √ √ 00H

FFFFF596H TMP0 capture/compare register 0 TP0CCR0 √ 0000H

FFFFF598H TMP0 capture/compare register 1 TP0CCR1

R/W

√ 0000H

FFFFF59AH TMP0 counter read buffer register TP0CNT R √ 0000H

FFFFF5A0H TMP1 control register 0 TP1CTL0 √ √ 00H

FFFFF5A1H TMP1 control register 1 TP1CTL1 √ √ 00H

FFFFF5A2H TMP1 I/O control register 0 TP1IOC0 √ √ 00H

FFFFF5A3H TMP1 I/O control register 1 TP1IOC1 √ √ 00H

FFFFF5A4H TMP1 I/O control register 2 TP1IOC2 √ √ 00H

FFFFF5A5H TMP1 option register 0 TP1OPT0 √ √ 00H

FFFFF5A6H TMP1 capture/compare register 0 TP1CCR0 √ 0000H

FFFFF5A8H TMP1 capture/compare register 1 TP1CCR1

R/W

√ 0000H

FFFFF5AAH TMP1 counter read buffer register TP1CNT R √ 0000H

FFFFF5B0H TMP2 control register 0 TP2CTL0 √ √ 00H

FFFFF5B1H TMP2 control register 1 TP2CTL1 √ √ 00H

FFFFF5B2H TMP2 I/O control register 0 TP2IOC0 √ √ 00H

FFFFF5B3H TMP2 I/O control register 1 TP2IOC1 √ √ 00H

FFFFF5B4H TMP2 I/O control register 2 TP2IOC2 √ √ 00H

FFFFF5B5H TMP2 option register 0 TP2OPT0 √ √ 00H

FFFFF5B6H TMP2 capture/compare register 0 TP2CCR0 √ 0000H

FFFFF5B8H TMP2 capture/compare register 1 TP2CCR1

R/W

√ 0000H

FFFFF5BAH TMP2 counter read buffer register TP2CNT R √ 0000H

FFFFF5C0H TMP3 control register 0 TP3CTL0 √ √ 00H

FFFFF5C1H TMP3 control register 1 TP3CTL1 √ √ 00H

FFFFF5C2H TMP3 I/O control register 0 TP3IOC0 √ √ 00H

FFFFF5C3H TMP3 I/O control register 1 TP3IOC1 √ √ 00H

FFFFF5C4H TMP3 I/O control register 2 TP3IOC2 √ √ 00H

FFFFF5C5H TMP3 option register 0 TP3OPT0 √ √ 00H

FFFFF5C6H TMP3 capture/compare register 0 TP3CCR0 √ 0000H

FFFFF5C8H TMP3 capture/compare register 1 TP3CCR1

R/W

√ 0000H

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Manipulatable Bits

Address Function Register Name Symbol R/W

1 8 16

Default Value

FFFFF5CAH TMP3 counter read buffer register TP3CNT R √ 0000H

FFFFF680H Watch timer operation mode register WTM √ √ 00H

FFFFF690H TMM0 control register 0 TM0CTL0 √ √ 00H

FFFFF694H TMM0 compare register 0 TM0CMP0 √ 0000H

FFFFF6C0H Oscillation stabilization time select register OSTS √ 06H

FFFFF6C1H PLL lockup time specification register PLLS √ 03H

FFFFF6D0H Watchdog timer mode register 2 WDTM2 √ 67H

FFFFF6D1H Watchdog timer enable register WDTE √ 9AH

FFFFF706H Port function control expansion register 3L PFCE3L √ √ 00H

FFFFF70AH Port function control expansion register 5 PFCE5 √ √ 00H

FFFFF712H Port function control expansion register 9 PFCE9 √ 0000H

FFFFF712H Port function control expansion register 9L PFCE9L √ √ 00H

FFFFF713H Port function control expansion register 9H PFCE9H √ √ 00H

FFFFF802H System status register SYS √ √ 00H

FFFFF80CH Ring OSC mode register RCM √ √ 00H

FFFFF820H Power save mode register PSMR

R/W

√ √ 00H

FFFFF824H Lock register LOCKR R √ √ 00H

FFFFF828H Processor clock control register PCC √ √ 03H

FFFFF82CH PLL control register PLLCTL

R/W

√ √ 01H

FFFFF82EH CPU operating clock statu s regist er CCLS R √ √ 00H

FFFFF82FH Programmable clock mode register PCLM √ √ 00H

FFFFF870H Clock monitor mode register CLM √ √ 00H

FFFFF888H Reset source flag register RESF √ √ 00H

FFFFF890H Low-voltage detection register LVIM √ √ 00H

FFFFF891H Low-voltage detection level select register LVIS √ 00H

FFFFF892H Internal RAM data status register RAMS √ √ 01H

FFFFF8B0H Prescaler mode register 0 PRSM0 √ 00H

FFFFF8B1H Prescaler compare register 0 PRSCM0 √ 00H

FFFFF9FCH On-chip debug mode register OCDM √ √ 01H

FFFFF9FEH Peripheral emulation register 1 PEMU1 √ √ 00H

FFFFFA00H UARTA0 control register 0 UA0CTL0 √ √ 10H

FFFFFA01H UARTA0 control register 1 UA0CTL1 √ 00H

FFFFFA02H UARTA0 control register 2 UA0CTL2 √ FFH

FFFFFA03H UARTA0 option control register 0 UA0OPT0 √ √ 14H

FFFFFA04H UARTA0 status register UA0STR

R/W

√ √ 00H

FFFFFA06H UARTA0 receive data register UA0RX R √ FFH

FFFFFA07H UARTA0 transmit data register UA0TX √ FFH

FFFFFA10H UARTA1 control register 0 UA1CTL0 √ √ 10H

FFFFFA11H UARTA1 control register 1 UA1CTL1 √ 00H

FFFFFA12H UARTA1 control register 2 UA1CTL2

R/W

√ FFH

Caution For OCDM details, refer to CHAPTER 25 ON-CHIP DEBUG FUNCTION (ON-CHIP DEBUG UNIT).

CHAPTER 3 CPU FUNCTIONS

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