AS5SS256K36ADQ-8.5/883C - Micross Components, Inc.

SSRAMSSRAM

SSRAM

AS5SS256K36 &

AS5SS256K36A

AS5SS256K36 &

AS5SS256K36A

Rev. 3.6 06/05

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

1

Austin Semiconductor, Inc.

For more products and information

please visit our web site at

www.austinsemiconductor.com

256K x 36 SSRAM

Flow-Through, Synchronous

Burst SRAM

FEATURES

z Organized 256K x 36

z Fast Clock and OE\ access times

z Single +3.3V +0.3V/-0.165V power supply (VDD)

z SNOOZE MODE for reduced-power standby

z Common data inputs and data outputs

z Individual BYTE WRITE control and GLOBAL WRITE

z Three chip enables for simple depth expansion and address

pipelining

z Clock-controlled and registered addresses, data I/Os and

control signals

z Internally self-timed WRITE cycle

z Burst control (interleaved or linear burst)

z Automatic power-down for portable applications

z 100-lead TQFP package for high density, high speed

z Low capacitive bus loading

OPTIONS MARKING

z Timing

8.5ns/10ns/100MHz -8.5*

10ns/15ns/66MHz -10

z Packages

100-pin TQFP (2-chip enable) DQ No. 1001

z Pinout

2-chip Enables A (PRELIMINARY)

3-chip Enables no indicator

z Operating Temperature Ranges

Military (-55oC to +125oC) XT*

Industrial (-40oC to +85oC) IT

*NOTE: -8.5/XT combination not available.

PIN ASSIGNMENT

(Top View)

100-pin TQFP (DQ)

(2-chip enable version, “A” indicator)

100-pin TQFP (DQ)

(3-chip enable version, no indicator)

GENERAL DESCRIPTION

The AS5SS256K36 employs high-speed, low-power CMOS

designs that are fabricated using an advanced CMOS process.

This 8Mb Synchronous Burst SRAM integrates a 256K x 36

SRAM core with advanced synchronous peripheral circuitry and a 2-bit

burst counter. All synchronous inputs pass through registers controlled

by a positive-edge-triggered single-clock input (CLK). The synchro-

nous inputs include all addresses, all data inputs, active LOW chip en-

able (CE\), two additional chip enables for easy depth expansion (CE2\,

CE2), burst control inputs (ADSC\, ADSP\, ADV\), byte write enables

(BWx\) and global write (GW\). Note that CE2\ is not available on the

A version.

DQPc

DQc

VDDQ

Vss

DQc

Vss

VDDQ

DQc

Vss

VDD

NC

Vss

DQd

VDDQ

Vss

DQd

Vss

VDDQ

DQd

DQPd

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

DQPb

DQb

VDDQ

Vss

DQb

Vss

VDDQ

DQb

Vss

NC

VDD

ZZ

DQa

VDDQ

Vss

DQa

Vss

VDDQ

DQa

DQPa

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

SA

NF

VDD

Vss

DNU

SA0

SA1

SA

MODE

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

SA

ADV\

ADSP\

ADSC\

OE\

BWE\

GW\

CLK

Vss

VDD

CE2\

BWa\

BWb\

BWc\

BWd\

CE2

CE\

SA

DQPc

DQc

VDDQ

Vss

DQc

Vss

VDDQ

DQc

Vss

VDD

NC

Vss

DQd

VDDQ

Vss

DQd

Vss

VDDQ

DQd

DQPd

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

DQPb

DQb

VDDQ

Vss

DQb

Vss

VDDQ

DQb

Vss

NC

VDD

ZZ

DQa

VDDQ

Vss

DQa

Vss

VDDQ

DQa

DQPa

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

SA

NF

VDD

Vss

DNU

SA0

SA1

SA

MODE

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

SA

ADV\

ADSP\

ADSC\

OE\

BWE\

GW\

CLK

Vss

VDD

SA

BWa\

BWb\

BWc\

BWd\

CE2

CE\

SA

SSRAMSSRAM

SSRAM

AS5SS256K36 &

AS5SS256K36A

AS5SS256K36 &

AS5SS256K36A

Rev. 3.6 06/05

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

2

Austin Semiconductor, Inc.

GENERAL DESCRIPTION (continued)

Asynchronous inputs include the output enable (OE\),

clock (CLK) and snooze enable (ZZ). There is also a burst

mode input (MODE) that selects between interleaved and lin-

ear burst modes. The data-out (Q), enabled by OE\, is also

asynchronous. WRITE cycles can be from one to four bytes

wide as controlled by the write control inputs.

Burst operation can be initiated with either address

status processor (ADSP\) or address status controller (ADSC\)

inputs. Subsequent burst addresses can be internally gener-

ated as controlled by the burst advance input (ADV\).

Address and write control are registered on-chip to

simplify WRITE cycles. This allows self-timed WRITE cycles.

Individual byte enables allow individual bytes to be written.

During WRITE cycles on the x18 device, BWa\ controls DQa’s

and DQPa; BWb\ controls DQb’s and DQPb; BWc\ controls

DQc’s and DQPc; BWd\ controls DQd’s and DQPd. GW\ LOW

causes all bytes to be written. Parity bits are also featured on

this device.

This 8Mb Synchronous Burst SRAM operates from a

+3.3V VDD power supply, and all inputs and outputs are TTL-

compatible. The device is ideally suited for 486, Pentium©, 680x0

and PowerPCTM systems and those systems that benefit from a

wide synchronous data bus.

18 18 16 18

SA0, SA1, SAs SA0-SA1

MODE

ADV\

CLK

SA1'

SA0'

BWd\

BWc\ DQs

DQPa

DQPb

DQPc

BWb\ DQPd

BWa\

BWE\

GW\

OE\

ADDRESS

REGISTER

BINARY

COUNTER

AND LOGIC

Q

1

Q0CL

ADSC\

A

DSP\

BYTE "d"

WRITE REGISTER

BYTE "c"

WRITE REGISTER

BYTE "b"

WRITE REGISTER

BYTE "a"

WRITE REGISTER

ENABLE

REGISTER

CE\

CE2

\

BYTE "d"

WRITE DRIVER

BYTE "c"

WRITE DRIVER

BYTE "b"

WRITE DRIVER

BYTE "a"

WRITE DRIVER

256K x 9 x 4

(x36)

MEMORY

ARRAY

SENSE

AMPS

OUTPUT

BUFFERS

INPUT

REGISTERS

4

FUNCTIONAL BLOCK DIAGRAM

NOTE: Functional Block Diagrams illustrate simplified device operation. See Truth Table, Pin Descriptions and time diagrams for detailed

information.

SSRAMSSRAM

SSRAM

AS5SS256K36 &

AS5SS256K36A

AS5SS256K36 &

AS5SS256K36A

Rev. 3.6 06/05

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

3

Austin Semiconductor, Inc.

PIN DESCRIPTION

Pin Number SYMBOL TYPE

DESCRIPTION

37

36

32-35, 44-50,

81, 82, 99,

100

92 (A version)

43 (3 CE version)

SA0

SA1

SA Input Synchronous Address Inputs: These inputs are registered and must

meet the setup and hold times around the rising edge of CLK. Two

different pinouts are available for the TQFP packages.

93

94

95

96

BWa\

BWb\

BWc\

BWd\

Input

Synchronous Byte Write Enables: These active LOW inputs allow

individual bytes to be written and must meet the setup and hold times

around the rising edge of CLK. A byte write enable is LOW for a WRITE

cycle and HIGH for a READ cycle. Bwa\ controls DQa pins and DQPa;

Bwb\ controls DQb pins and DQPb; Bwc\ controls DQc pins and DQPc;

Bwd\ controls DQd pins and DQPd. Parity bits are featured on this

device.

87 BWE\ Input Byte Write Enable: This active LOW input permits BYTE WRITE

operations and must meet the setup and hold items around the rising

edge of CLK.

88 GW\ Input Global Write: This active LOW input allows a full 36-bit WRITE to occur

independent of the BWE\ and BWx\ lines and must meet the setup and

hold times around the rising edge of CLK.

89 CLK Input Clock: CLK registers address, data, chip enable, byte write enables and

burst control inputs on its rising edge. All synchronous inputs must meet

setup and hold times around the clock's rising edge.

98 CE\ Input Synchronous Chip Enable: This active LOW input is used to enable the

device and conditions the internal use of ADSP\. CE\ is sampled only

when a new external address is loaded.

92

(3 CE version) CE2\ Input Synchronous Chip Enable: This active LOW input is used to enable the

device and is sampled only when a new external address is loaded.

CE2\ is only available on the 3 CE version.

97 CE2 Input Synchronous Chip Enable: This active HIGH input is used to enable the

device and is sampled only when a new external address is loaded.

86 OE\ Input Output Enable: This active LOW, asynchronous input enables the data

I/O output drivers.

83 ADV\ Input

Synchronous Address Advance: This active LOW input is used to

advance the internal burst counter, controlling burst access after the

external address is loaded. A HIGH on this pin effectively causes wait

states to be generated (no address advance). To ensure use of correct

address during a WRITE cycle, ADV\ must be HIGH at the rising edge of

the first clock after an ADSP\ cycle is initiated.

85 ADSC\ Input

Synchronous Address Status Controller: This active LOW input

interrupts any ongoing burst, causing a new external address to be

registered. A READ or WRITE is performed using the new address if

CE\ is LOW. ADSC\ is also used to place the chip into power-down state

when CE\ is HIGH.

SSRAMSSRAM

SSRAM

AS5SS256K36 &

AS5SS256K36A

AS5SS256K36 &

AS5SS256K36A

Rev. 3.6 06/05

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

4

Austin Semiconductor, Inc.

PIN DESCRIPTION (continued)

Pin Number SYMBOL TYPE DESCRIPTION

84 ASDP\ Input

Synchronous Address Status Processor: This active LOW inputs

interrupts any ongoing burst, causing a new external address to be

registered. A READ is performed using the new address, independent of

the byte write enables and ADSC\, but dependent upon CE\, CE2 and

CE2\. ADSP\ is ignored if CE\ is HIGH. Power-down state is entered if

CE2 is LOW or CE2\ is HIGH.

31 MODE Input

MODE: This inputs selects the burst sequence. A LOW on this pin

select "linear burst." NC or HIGH on this pin selects "interleaved burst."

Do not alter input state while device is operating.

64 ZZ Input

Snooze Enable: This active HIGH, asynchronous input causes the

device to enter a low-power standby mode in which all data in the

memory array is retained. When ZZ is active, all other inputs are

ignored.

(a) 52, 53, 56-59,

62, 63

(b) 68, 69, 72-75,

78, 79

(c) 2, 3, 6-9, 12,

13

(d) 18, 19, 22-25,

28, 29

DQa

DQb

DQc

DQd

Input/

Output

SRAM Data I/O's: Byte "a" is DQa pins; Byte "b" is DQb pins; Byte "c" is

DQc pins; Byte "d" is DQd pins. Input data must meet setup and hold

times around the rising edge of CLK.

51

80

1

30

NC/DQPa

NC/DQPb

NC/DQPc

NC/DQPd

NC/ I/O Parity Data I/Os: Byte "a" parity is DQPa; Byte "b" parity is DQPb; Byte

"c" parity is DQPc; Byte "d" parity is DQPd.

15, 41, 65, 91 VDD Supply Power Supply: See DC Electrical Characteristics and Operating

Conditions for range.

4, 11, 20, 27, 54,

61, 70, 77 V

DD

QSupply Isolated Output Buffer Supply: See DC Electrical Characteristics and

Operating Conditions for range.

5, 10, 14, 17, 21,

26, 40, 55, 60, 67,

71, 76, 90

Vss Supply Ground: GND

38, 39 DNU --- Do Not Use: These signals may either be unconnected or wired to GND

to improve package heat dissipation.

16, 66 NC --- No Connect: These signals are not internally connected and may be

connected to GND to improve package heat dissipation.

42

43 (A version) NF ---

No Function: These pins are internally connected to the die and have

the capacitance of an input pin. It is allowable to leave these pins

unconnected or driven by signals. On the 3 CE version, pin 42 is

reserved as an address upgrade pin for the 16Mb Synchronous Burst.

SSRAMSSRAM

SSRAM

AS5SS256K36 &

AS5SS256K36A

AS5SS256K36 &

AS5SS256K36A

Rev. 3.6 06/05

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

5

Austin Semiconductor, Inc.

INTERLEAVED BURST ADDRESS TABLE (MODE = NC OR HIGH)

FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) THIRD ADDRESS (INTERNAL) FOURTH ADDRESS (INTERNAL)

X…X00 X…X01 X…X10 X…X11

X…X01 X…X00 X…X11 X…X10

X…X10 X…X11 X…X00 X…X01

X…X11 X…X10 X…X01 X…X00

LINEAR BURST ADDRESS TABLE (MODE = LOW)

FIRST ADDRESS (EXTERNAL)

SECOND ADDRESS (INTERNAL)

THIRD ADDRESS (INTERNAL) FOURTH ADDRESS (INTERNAL)

X…X00 X…X01 X…X10 X…X11

X…X01 X…X10 X…X11 X…X00

X…X10 X…X11 X…X00 X…X01

X…X11 X…X00 X…X01 X…X10

PARTIAL TRUTH TABLE FOR WRITE COMMANDS

FUNCTION GW\ BWE\ BWa\ BWb\

BWc\

BWd\

READ H H XXXX

READ H L HHHH

WRITE Byte "a" H L L H H H

WRITE All Bytes H L L L L L

WRITE All Bytes L XXXXX

SSRAMSSRAM

SSRAM

AS5SS256K36 &

AS5SS256K36A

AS5SS256K36 &

AS5SS256K36A

Rev. 3.6 06/05

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

6

Austin Semiconductor, Inc.

TRUTH TABLE

OPERATION ADDRESS

USED CE\ CE2\ CE2 ZZ ADSP\ ADSC\ ADV\ WRITE\ OE\ CLK DQ

Deselected Cycle, Power-Down None H X X L X L X X X L-H High-Z

Deselected Cycle, Power-Down None L X L L L X X X X L-H High-Z

Deselected Cycle, Power-Down None L H X L L X X X X L-H High-Z

Deselected Cycle, Power-Down None L X L L H L X X X L-H Hig h- Z

Deselected Cycle, Power-Down None L H X L H L X X X L-H High-Z

SNOOZE MODE, Power-Down None X X X H X X X X X X H igh-Z

READ Cycle, Begin Burst External L L H L L X X X L L-H Q

READ Cycle, Begin Burst External L L H L L X X X H L-H High-Z

WRITE Cycle, Begin Burst External L L H L H L X L X L-H D

READ Cycle, Begin Burst External L L H L H L X H L L-H Q

READ Cycle, Begin Burst External L L H L H L X H H L-H High-Z

READ Cycle, Continue Burst Next X X X L H H L H L L-H Q

READ Cycle, Continue Burst Next X X X L H H L H H L-H High-Z

READ Cycle, Continue Burst Next H X X L X H L H L L-H Q

READ Cycle, Continue Burst Next H X X L X H L H H L-H High-Z

WRITE Cycle, Continue Burst Next X X X L H H L L X L-H D

WRITE Cycle, Continue Burst Next H X X L X H L L X L-H D

READ Cycle, Suspend Burst Current X X X L H H H H L L-H Q

READ Cycle, Suspend Burst Current X X X L H H H H H L-H High-Z

READ Cycle, Suspend Burst Current H X X L X H H H L L-H Q

READ Cycle, Suspend Burst Current H X X L X H H H H L-H High-Z

WRITE Cycle, Suspend Burst Current X X X L H H H L X L-H D

WRITE Cycle, Suspend Burst Current H X X L X H H L X L-H D

NOTE:

1. X means “Don’t Care.” \ means active LOW. H Means logic HIGH. L means logic LOW.

2. For WRITE\, L means any one or more byte write enable signals (BWa\, BWb\, BWc\, or BWd\) and BWE\ are LOW or

GW\ is LOW. WRITE\ = H for all BWx\, BWE\, GW\ HIGH.

3. BWa\ enables WRITEs to DQa pins, DQPa. BWb\ enables WRITEs to DQb pins, DQPb. BWc\ enables WRITEs to DQc

pins, DQPc. BWd\ enables WRITEs to DQd pins, DQPd.

4. All inputs except OE\ and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.

5. Wait states are inserted by suspending burst.

6. For a WRITE operation following a READ operation, OE\ must be HIGH before the input data setup time and held HIGH

throughout the input data hold time.

7. This device contains circuitry that will ensure the outputs will be High-Z during power-up.

8. ADSP\ LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more

byte write enable signals and BWE\ LOW or GW\ LOW for the subsequent L-H edge of CLK. Refer to WRITE timing

diagram for clarification.

SSRAMSSRAM

SSRAM

AS5SS256K36 &

AS5SS256K36A

AS5SS256K36 &

AS5SS256K36A

Rev. 3.6 06/05

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

7

Austin Semiconductor, Inc.

ABSOLUTE MAXIMUM RATINGS*

Storage Temperature (Plastics) ...........................-55°C to +150°C

Storage Temperature (Ceramics) .........................-55°C to +125°C

Short Circuit Output Current (per I/O)…............................100mA

Voltage on any Pin Relative to Vss........................-0.5V to +4.6 V

Max Junction Temperature**..............................................+150°C

VIN (DQx) .........................................................-0.5V to VDDQ +0.5V

VIN (inputs) ................................................... ....-0.5V to VDD +0.5V

*Stresses greater than those listed under "Absolute Maximum

Ratings" may cause permanent damage to the device. This is

a stress rating only and functional operation of the device at

these or any other conditions above those indicated in the

operation section of this specification is not implied. Exposure

to absolute maximum rating conditions for extended periods

may affect reliability.

** Junction temperature depends upon package type, cycle

time, loading, ambient temperature and airflow, and humidity.

3.3V I/O DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS

(-55oC to +125oC or -40oC to +85oC; VDD, VDDQ = +3.3V +0.3V/-0.165V unless otherwise noted)

PARAMETER CONDITION SYMBOL MIN MAX UNITS NOTES

Input High (Logic 1) Voltage VIH 2.2 VCC +0.3 V 1, 2

Input Low (Logic 0) Voltage VIL -0.3 0.8 V 1, 2

Input Leakage Current OV < VIN < Vcc ILI-2 2 μΑ 3

Output Leakage Current Output(s) disabled, OV < VOUT < Vcc ILO-2 2 μΑ

Output High Voltage IOH = -4.0 mA VOH 2.4 -- V 1, 4

Output Low Voltage IOL = 8.0 mA VOL --- 0.4 V 1, 4

Supply Voltage VDD 3.135 3.6 V 1

Isolated Output Buffer Supply VDDQ3.135 3.6 V 1, 5

NOTES:

1. All voltages referenced to Vss (GND).

2. Overshoot: VIH < +4.6V for t<tKC/2 for I < 20mA

Undershoot: VIL > -0.7V for t<tKC/2 for I < 20mA

Power-up: VIH < +3.6V and VDD < 3.135V for t < 200ms

3. MODE and ZZ pins have internal pull-up resistors, and input leakage = +10μA

4. The load used for VOH, VOL testing is shown in Figure 2 for 3.3V I/O. AC load current is higher than the stated DC values.

AC I/O curves are available upon request.

5. VDDQ should never exceed VDD. VDD and VDDQ can be connected together.

6. This parameter is sampled.

THERMAL RESISTANCE

DESCRIPTION SYM TYP UNITS NOTES

Thermal Resistance

(Junction to Ambient) 1-layer θJA 40

o

C/W 6

Thermal Resistance

(Junction to Top of Case, Top) θJC 9

o

C/W 6

Thermal Resistance

(Junction to Pins, Bottom) θJB 17

o

C/W 6

CONDITIONS

Test conditions follow standard test

methods and procedures for measuring

thermal impedance, per EIA/JESD51.

SSRAMSSRAM

SSRAM

AS5SS256K36 &

AS5SS256K36A

AS5SS256K36 &

AS5SS256K36A

Rev. 3.6 06/05

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

8

Austin Semiconductor, Inc.

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IDD OPERATING CONDITIONS AND MAXIMUM LIMITS

(-55oC to +125oC or -40oC to +85oC)

CAPACITANCE

DESCRIPTION CONDITIONS SYM MAX UNITS NOTES

Control Input Capacitance

C

I

4pF4

Input/Output Capacitance (DQ) C

O

5pF4

Address Capacitance C

A

3.5 pF 4

Clock Capacitance C

CK

3.5 pF 4

T

A

= 25

o

C; f = 1MHz;

V

DD

= 3.3V

NOTES:

1. IDD is specified with no output current and increases with faster cycle times. IDDQ increases with faster cycle times and

greater output loading.

2. “Device deselected” means device is in power-down mode as defined in the truth table. “Device selected” means device

is active (not in power-down mode).

3. A typical value is measured at 3.3V, 25oC and 15ns cycle time.

4. This parameter is sampled.

SSRAMSSRAM

SSRAM

AS5SS256K36 &

AS5SS256K36A

AS5SS256K36 &

AS5SS256K36A

Rev. 3.6 06/05

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

9

Austin Semiconductor, Inc.

ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS

(Note 1) (-55oC to +125oC or -40oC to +85oC)

MIN MAX MIN MAX

CLOCK

Clock cycle time t

KC

10.0 15.0 ns

Clock frequency t

KF

100 66 MHz

Clock HIGH time t

KH

3.0 4.0 ns 2

Clock LOW time t

KL

3.0 4.0 ns 2

OUTPUT TIMES

Clock to output valid t

KQ

8.5 10.0 ns

Clock to output invalid t

KQX

3.0 3.0 ns 3

Clock to output in Low-Z t

KQLZ

3.0 3.0 ns 3, 4, 5, 6,

Clock to output in High-Z t

KQHZ

5.0 5.0 ns 3, 4, 5, 6,

OE\ to output valid t

OEQ

5.0 5.0 ns 7

OE\ to output in Low-Z t

OELZ

0 0 ns 3, 4, 5, 6,

OE\ to output in High-Z t

OEHZ

5.0 5.0 ns 3, 4, 5, 6,

SETUP TIMES

Address t

AS

1.8 2.0 ns 8, 9

Address status (ADSC\, ADSP\) t

ADSS

1.8 2.0 ns 8, 9

Address advance (ADV\) t

AAS

1.8 2.0 ns 8, 9

Byte write enables (BWa\ - BWd\, GW\, BWE\) t

WS

1.8 2.0 ns 8, 9

Data-in t

DS

1.8 2.0 ns 8, 9

Chip enable (CE\) t

CES

1.8 2.0 ns 8, 9

HOLD TIMES

Address t

AH

0.5 0.5 ns 8, 9

Address status (ADSC\, ADSP\) t

ADSH

0.5 0.5 ns 8, 9

Address advance (ADV\) t

AAH

0.5 0.5 ns 8, 9

Byte write enables (BWa\ - BWd\, GW\, BWE\) t

WH

0.5 0.5 ns 8, 9

Data-in t

DH

0.5 0.5 ns 8, 9

Chip enable (CE\) t

CEH

0.5 0.5 ns 8, 9

UNITS NOTESSYMBOLDESCRIPTION -10-8.5

NOTE:

1. Test conditions as specified with the output loading shown in Figure 1 unless otherwise noted.

2. Measured as HIGH above VIH and LOW below VIL.

3. This parameter is measured with the output loading shown in Figure 2 for 3.3V I/O.

4. This parameter is sampled.

5. Transition is measured +500mV from steady state voltage.

6. Refer to Technical Note TN-58-09, “Synchronous SRAM Bus Contention Design Considerations,” for a more thorough discussion on these

parameters.

7. OE\ is a “Don’t Care” when a byte write enable is sampled LOW.

8. A READ cycle is defined by byte write enables all HIGH or ADSP\ LOW for the required setup and hold times. A WRITE cycle is defined by

a t least one byte write enable LOW and ADSP\ HIGH for the required setup and hold times.

9. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK when either ADSP\ or

ADSC\ is LOW and chip enabled. All other synchronous inputs must meet the setup and hold times with stable logic levels for all rising edges

of clock (CLK) when the chip is enabled. Chip enable must be valid at each rising edge of CLK when either ADSP\ or ADSC\ is LOW to

remain enabled.

SSRAMSSRAM

SSRAM

AS5SS256K36 &

AS5SS256K36A

AS5SS256K36 &

AS5SS256K36A

Rev. 3.6 06/05

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

10

Austin Semiconductor, Inc.

OUTPUT LOADS +3.3v

DQ

Fig. 2 3.3V I/O OUTPUT LOAD EQUIVALENT

351Ω5 pF

317Ω

Fig. 1 3.3V I/O OUTPUT LOAD EQUIVALENT

DQ

50Ω

Z0=50Ω

Vt = 1.5V

AC TEST CONDITIONS

Input Pulse Levels..................VIH = (VDD/2.2) +1.5V

..................VIL = (VDD/2.2) -1.5V

Input rise and fall times..........................................1ns

Input timing reference levels............................VDD/2.2

Output reference levels................................VDDQ/2.2

Output load.................................See Figures 1 and 2

NOTE: SRAM timing is dependent upon the capacitive loading on the outputs.

SSRAMSSRAM

SSRAM

AS5SS256K36 &

AS5SS256K36A

AS5SS256K36 &

AS5SS256K36A

Rev. 3.6 06/05

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

11

Austin Semiconductor, Inc.

      

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



SNOOZE MODE

SNOOZE MODE is a low-current, “power-down” mode in

which the device is deselected and current is reduced to ISB2Z.

The duration of SNOOZE MODE is dictated by the length of

time ZZ is in a HIGH state. After the device enters SNOOZE

MODE, all inputs except ZZ become gated inputs and are ig-

nored.

ZZ is an asynchronous, active HIGH input that causes the

device to enter SNOOZE MODE. When ZZ becomes a logic

HIGH, ISB2Z is guaranteed after the setup time tZZ is met. Any

READ or WRITE operation pending when the device enters

SNOOZE MODE is not guaranteed to complete successfully.

Therefore, SNOOZE MODE must not be initiated until valid

pending operations are completed.

SNOOZE MODE ELECTRICAL CHARACTERISTICS

NOTE: 1. This parameter is sampled.

SNOOZE MODE WAVEFORM

CLK

ZZ

ISUPPLY

ALL INPUTS*

*Except ZZ

12345

123456789

1

2345678

9

1

2345678

9

123456789

1

1234

1

23

4

1

23

4

1

23

4

1234

Don’t Care

tZZ

tZZI

tRZZ

tRZZI

tSB2

SSRAMSSRAM

SSRAM

AS5SS256K36 &

AS5SS256K36A

AS5SS256K36 &

AS5SS256K36A

Rev. 3.6 06/05

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

12

Austin Semiconductor, Inc.

READ TIMING3

NOTE: 1. Q(A2) refers to output from address A2. Q(A2+1) refers to output from the next internal burst address following A2.

2. CE2\ and CE2 have timing identical to CE\. On this diagram, when CE\ is LOW, CE2\ is LOW and CE2 is HIGH. When CE\ is

HIGH, CE2\ is HIGH and CE2 is LOW.

3. Timing is shown assuming that the device was not enabled before entering into this sequence.

4. Outputs are disabled tKQHZ after deselect.

MIN MAX MIN MAX

t

KC

10.0 15 ns

t

KF

100 66 MHz

t

KH

3.0 4.0 ns

t

KL

3.0 4.0 ns

t

KQ

8.5 10.0 ns

t

KQX

3.0 3.0 ns

t

KQLZ

3.0 3.0 ns

t

KQHZ

5.0 5.0 ns

t

OEQ

5.0 5.0 ns

t

OELZ

00ns

t

OEHZ

5.0 5.0 ns

SYMBOL -8.5 -10 UNITS

READ/WRITE TIMING PARAMETERS

MIN MAX MIN

MAX

t

AS

1.8 2.0 ns

t

ADSS

1.8 2.0 ns

t

AAS

1.8 2.0 ns

t

WS

1.8 2.0 ns

t

CES

1.8 2.0 ns

t

AH

0.5 0.5 ns

t

ADSH

0.5 0.5 ns

t

AAH

0.5 0.5 ns

t

WH

0.5 0.5 ns

t

CEH

0.5 0.5 ns

SYMBOL -8.5

-10

UNITS

123456789012

12345

123456789

1

2345678

9

1

2345678

9

1

2345678

9

1

2345678

9

123456789

12345

1234

123456

12345678901234

1234

1234567890

1

23456789

0

1

23456789

0

1

23456789

0

1

23456789

0

1234567890

1234

12345

123456

1

2345

6

1

2345

6

1

2345

6

1

2345

6

123456

12

CLK

ADSP\

ADSC\

○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○

○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○

○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○

○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○

○○○○○ ○○○○ ○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○

○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○

ADDRESS

BWE\, GW\,

BWa\ - BWd\

○○○○○ ○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○

CE\

(Note 2)

ADV\

OE\

t

ADSH

t

AS

tAH

tKQLZ

tOEHZ

SINGLE READ BURST READ

○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○

Q

t

1234

12345678

123

1

2

3

1

2

3

1

2

3

1

2

3

123

12345678

123456789012345678901234567890121234567890123456789012345678901212345678901234567890

1

2345678901234567890123456789012123456789012345678901234567890121234567890123456789

0

1

2345678901234567890123456789012123456789012345678901234567890121234567890123456789

0

1

2345678901234567890123456789012123456789012345678901234567890121234567890123456789

0

1

2345678901234567890123456789012123456789012345678901234567890121234567890123456789

0

123456789012345678901234567890121234567890123456789012345678901212345678901234567890

1

AAS

tAAH

t

Q(A2) Q(A2+2)

12

Q(A2+3)

12

Q(A2)

123

12

Q(A2+1)

12

1

Q(A2+2)

123456

1234

123456

12345

123456

1234567

1

23456

7

1

23456

7

1

23456

7

1

23456

7

1234567

12

123456

1234567

123456

Q(A1) Q(A2+1)

123456

tKC

tKL

123456

1234567890123456789012

1

23456789012345678901

2

1

23456789012345678901

2

1

23456789012345678901

2

1

23456789012345678901

2

1

23456789012345678901

2

1234567890123456789012

1

12345

123456

1234567890123456789012345678901212345678901234567890123456789012123456789012345678

123456

1234567890123456789012

1

23456789012345678901

2

1

23456789012345678901

2

1

23456789012345678901

2

1

23456789012345678901

2

1234567890123456789012

1

1234567890123

12345678

1

234567

8

1

234567

8

1

234567

8

1

234567

8

12345678

1

123

1234

tKH

tOEQ tOELZ

tKQ

123456

Deselect Cycle

(note 4)

123456

ADSS

tADSH

t

ADSS

A2A1

tWS

tWH

tCEH

tCES

ADV\ suspends burst.

High-Z tKQ

tKQX

tKQHZ

Burst wraps around to

its initial state

(Note 1)

1234

1

23

4

1

23

4

1234

1

23

4

1

23

4

1234

Don’t Care Undefined

SSRAMSSRAM

SSRAM

AS5SS256K36 &

AS5SS256K36A

AS5SS256K36 &

AS5SS256K36A

Rev. 3.6 06/05

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

13

Austin Semiconductor, Inc.

NOTE: 1. D(A2) refers to output from address A2. D(A2+1) refers to output from the next internal burst address following A2.

2. CE2\ and CE2 have timing identical to CE\. On this diagram, when CE\ is LOW, CE2\ is LOW and CE2 is HIGH. When CE\ is HIGH, CE2\ is HIGH and CE2 is LOW.

3. OE\ must be HIGH before the input data setup and held HIGH throughout the data hold time. This prevents input/output data contention for the time period prior to the byte write enable

inputs being sampled.

4. ADV\ must be HIGH to permit a WRITE to the loaded address.

5. Full-width WRITE can be initiated by GW\ LOW; or GW\ HIGH and BEW\, BWa\ - BWd\ LOW.

WRITE TIMING PARAMETERS

MIN MAX MIN MAX

tKC 10.0 15 ns

tKF 100 66 MHz

tKH 3.0 4.0 ns

tKL 3.0 4.0 ns

tOEHZ 5.0 5.0 ns

tAS 1.8 2.0 ns

tADSS 1.8 2.0 ns

tAAS 1.8 2.0 ns

tWS 1.8 2.0 ns

SYMBOL

-8.5

-10 UNITS

MIN

MAX

MIN

MAX

t

DS

1.8 2.0 ns

t

CES

1.8 2.0 ns

t

AH

0.5 0.5 ns

t

ADSH

0.5 0.5 ns

t

AAH

0.5 0.5 ns

t

WH

0.5 0.5 ns

t

DH

0.5 0.5 ns

t

CEH

0.5 0.5 ns

SYMBOL

-8.5

-10 UNITS

WRITE TIMING

12345

123456789

1

2345678

9

1

2345678

9

1

2345678

9

1

2345678

9

123456789

12345

123456

12345

1234

123456789

1

2345678

9

1

2345678

9

1

2345678

9

1

2345678

9

123456789

12345

1234

12345

1234

123456789

1

2345678

9

1

2345678

9

1

2345678

9

1

2345678

9

123456789

1234

12345

123456789012

1234567

1

23456

7

1

23456

7

1

23456

7

1

23456

7

1234567

12

1234

123456789

1

2345678

9

1

2345678

9

1

2345678

9

1

2345678

9

123456789

1234

12345

1234

123456789

1

2345678

9

1

2345678

9

1

2345678

9

1

2345678

9

123456789

12345

1234

12345

123456789

1

2345678

9

1

2345678

9

1

2345678

9

1

2345678

9

1

2345678

9

123456789

12345

1234

1234567890

1

23456789

0

1

23456789

0

1

23456789

0

1

23456789

0

1

23456789

0

1234567890

12345

1234

123456789

1

2345678

9

1

2345678

9

1

2345678

9

1

2345678

9

123456789

12345

1234

12345

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1

2345678

9

1

2345678

9

1

2345678

9

1

2345678

9

123456789

1234

12345

CLK

ADSP\

ADSS

ADSC\

○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○

○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○

○○○○○ ○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○

○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○

○○○○○ ○○○○ ○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○

○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○

○○○○○ ○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○

○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○

ADDRESS

BWE\

BWa\ - BWd\

○○○○○ ○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○

CE\

(See Note)

ADV\

OE\

t

ADSH

tAS

tAH

tDS

Single WRITE BURST WRITE

GW\

○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○

D

Extended BURST WRITE

t

12345

12345678

123

1

2

3

1

2

3

1

2

3

1

2

3

123

12345678

123456789012345678901234567890121234567890123

1

2345678901234567890123456789012123456789012

3

1

2345678901234567890123456789012123456789012

3

1

2345678901234567890123456789012123456789012

3

1

2345678901234567890123456789012123456789012

3

123456789012345678901234567890121234567890123

12

1

A3

123456789

123456789012345678901

1

2345678901234567890

1

2345678901234567890

1

2345678901234567890

1

2345678901234567890

1

123456789012345678901

12

123456789012345678

1234567890123

1234567890123456789012345678901212345678901234567890123456789012123456789012345678901

1

23456789012345678901234567890121234567890123456789012345678901212345678901234567890

1

23456789012345678901234567890121234567890123456789012345678901212345678901234567890

1

23456789012345678901234567890121234567890123456789012345678901212345678901234567890

1

23456789012345678901234567890121234567890123456789012345678901212345678901234567890

1

23456789012345678901234567890121234567890123456789012345678901212345678901234567890

1

1234567890123456789012345678901212345678901234567890123456789012123456789012345678901

12

1234

123456789

1

2345678

9

1

2345678

9

123456789

12

D(A2) D(A2+1) D(A2+2)

12

D(A2+3)

12

D(A3)

12

D(A3+1)

12

D(A3+2)

123456

1234567

123456

12345

123456

12345

12345678

1

234567

8

1

234567

8

1

234567

8

1

234567

8

12345678

12

12345

12345678901234567

123456

12345

123456

12345

1234567890123456789012345678901212345678901234567890

1

23456789012345678901234567890121234567890123456789

0

1

23456789012345678901234567890121234567890123456789

0

1

23456789012345678901234567890121234567890123456789

0

1

23456789012345678901234567890121234567890123456789

0

1234567890123456789012345678901212345678901234567890

1234

12345

1234

123456

1234567890123456789012345

1

23456789012345678901234

5

1

23456789012345678901234

5

1

23456789012345678901234

5

1

23456789012345678901234

5

1234567890123456789012345

12

12345

123456

12345

D(A1) D(A2+1)

tKC

tKL

tKH

1234567890

Q

High-Z

12

ADSS

t

ADSH

t

A1 A2

BYTE WRITE signals are

ignored when ADSP\ is LOW.

ADSS

t

ADSH

t

BURST READ

ADSC\ extends burst.

123456

WS

tWH

t

WS

tWH

t

(Note 5)

CES

tCEH

t

(Note 4)

AAS

tAAH

t

ADV\ suspends burst.

(Note 3)

tDH

tOEHZ (Note 1)

12345

1

234

5

1

234

5

12345

1234

1

23

4

1

23

4

1234

Don’t Care Undefined

SSRAMSSRAM

SSRAM

AS5SS256K36 &

AS5SS256K36A

AS5SS256K36 &

AS5SS256K36A

Rev. 3.6 06/05

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

14

Austin Semiconductor, Inc.

READ/WRITE TIMING3

NOTE: 1. Q(A4) refers to output from address A. Q(A4+1) refers to output from the next internal burst address following A4.

2. CE2\ and CE2 have timing identical to CE\. On this diagram, when CE\ is LOW, CE2\ is LOW and CE2 is HIGH. When CE\ is HIGH, CE2\ is HIGH and CE2 is LOW.

3. The data bus (Q) remains in High-A following a WRITE cycle unless an ADSP\, ADSC\ or ADV\ cycle is performed.

4. GW\ is HIGH.

5. Back-to-back READs may be controlled by either ADSP\ or ADSC\.

WRITE TIMING PARAMETERS

123456

12345678

1234

1234567890123456

CLK

ADSP\

ADSS

ADSC\

○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○

○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○

○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○

○○○○○ ○○○○○○○○○○○○○○○○○○○○○○○○○○○○○

ADDRESS

WEH\, WEL\,

BWE\, GW\

○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○

CE\

(See

Note)

ADV\

OE\

tADSH

tAS

tAH

Back-to-Back

READs

(Note 5)

BURST READ

○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○

D

Back-to-Back

WRITEs

t

12345

12345678

123

1

2

3

1

2

3

1

2

3

1

2

3

123

12345678

12345678901234567890123456789012123

1

234567890123456789012345678901212

3

1

234567890123456789012345678901212

3

1

234567890123456789012345678901212

3

1

234567890123456789012345678901212

3

12345678901234567890123456789012123

12

1

A5

Q(A4) Q(A4+1)

12

Q(A4+2)

12

Q(A4+3)

D(A5) D(A6)

123456

12345678

12345678901234567

123456789012345678901234567890121234567890

1

2345678901234567890123456789012123456789

0

1

2345678901234567890123456789012123456789

0

1

2345678901234567890123456789012123456789

0

1

2345678901234567890123456789012123456789

0

123456789012345678901234567890121234567890

1234

Q(A1)

D(A3)

12345

A1

12345678

123

1

2

3

1

2

3

1

2

3

1

2

3

123

A4

123456

12345678901

12

123456789012345

123456

12345678

123456

1234567890123456789012345678901212345678901

1

23456789012345678901234567890121234567890

1

23456789012345678901234567890121234567890

1

23456789012345678901234567890121234567890

1

23456789012345678901234567890121234567890

1

1234567890123456789012345678901212345678901

1

123

Q(A2)

12

1

SINGLE WRITE

1234567

123456

12345

123456

12345

123456

123

A6

1

123456

12345

123456789

1

2345678

9

1

2345678

9

1

2345678

9

1

2345678

9

123456789

12345

1234

123456789

1

2345678

9

1

2345678

9

1

2345678

9

1

2345678

9

123456789

12345

1234

123456

12345678901234567

Q

tKC

tKL

tKH

A3

A2

tWS tWH

tCES

tCEH

tDS tDH

tOEHZ

High-Z

tKQ

tOELZ

(Note 1)

12345

1

234

5

1

234

5

12345

1234

1

23

4

1

23

4

1234

Don’t Care Undefined

MIN MAX MIN MAX

t

KC

10.0 15 ns

t

KF

100 66 MHz

t

KH

3.0 4.0 ns

t

KL

3.0 4.0 ns

t

KQ

8.5 10.0 ns

t

OELZ

00ns

t

OEHZ

5.0 5.0 ns

t

AS

1.8 2.0 ns

t

ADSS

1.8 2.0 ns

SYMBOL -8.5 -10 UNITS

MIN

MAX

MIN

MAX

t

WS

1.8 2.0 ns

t

DS

1.8 2.0 ns

t

CES

1.8 2.0 ns

t

AH

0.5 0.5 ns

t

ADSH

0.5 0.5 ns

t

WH

0.5 0.5 ns

t

DH

0.5 0.5 ns

t

CEH

0.5 0.5 ns

SYMBOL -8.5

-10

UNITS

SSRAMSSRAM

SSRAM

AS5SS256K36 &

AS5SS256K36A

AS5SS256K36 &

AS5SS256K36A

Rev. 3.6 06/05

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

15

Austin Semiconductor, Inc.

MECHANICAL DEFINITIONS

SSRAMSSRAM

SSRAM

AS5SS256K36 &

AS5SS256K36A

AS5SS256K36 &

AS5SS256K36A

Rev. 3.6 06/05

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

16

Austin Semiconductor, Inc.

ORDERING INFORMATION

EXAMPLE: AS5SS256K36ADQ-8.5/IT

Device Number Options** Package

Type Speed ns Process

AS5SS256K36 A DQ -8.5 /*

AS5SS256K36 A DQ -10 /*

*AVAILABLE PROCESSES

IT = Industrial Temperature Range -40oC to +85oC1

XT = Extended Temperature Range -55oC to +125oC

883C = Full Military Processing -55oC to +125oC

**DEFINITION OF OPTIONS

2-Chip Enable Pinout A

3-Chip Enable Pinout no indicator

NOTES:

1. -8.5/XT combination not available.