LM148JAN www.ti.com SNOSAI2A - FEBRUARY 2005 - REVISED MARCH 2013 LM148JAN Quad 741 Op Amps Check for Samples: LM148JAN FEATURES DESCRIPTION * * The LM148 is a true quad LM741. It consists of four independent, high gain, internally compensated, low power operational amplifiers which have been designed to provide functional characteristics identical to those of the familiar LM741 operational amplifier. In addition the total supply current for all four amplifiers is comparable to the supply current of a single LM741 type op amp. Other features include input offset currents and input bias current which are much less than those of a standard LM741. Also, excellent isolation between amplifiers has been achieved by independently biasing each amplifier and using layout techniques which minimize thermal coupling. 1 2 * * * * * * * * 741 Op Amp Operating Characteristics Class AB Output Stage--No Crossover Distortion Pin Compatible with the LM124 Overload Protection for Inputs and Outputs Low Supply Current Drain: 0.6 mA/Amplifier Low Input Offset Voltage: 1 mV Low Input Offset Current: 4 nA Low Input Bias Current 30 nA High Degree of Isolation between Amplifiers: 120 dB Gain Bandwidth Product (Unity Gain): 1.0 MHz The LM148 can be used anywhere multiple LM741 or LM1558 type amplifiers are being used and in applications where amplifier matching or high packing density is required. Connection Diagram Figure 1. Top View See Package Number J0014A, NAD0014B, NAC0014A 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2005-2013, Texas Instruments Incorporated LM148JAN SNOSAI2A - FEBRUARY 2005 - REVISED MARCH 2013 www.ti.com Schematic Diagram * 1 pF in the LM149 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 2 Submit Documentation Feedback Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LM148JAN LM148JAN www.ti.com SNOSAI2A - FEBRUARY 2005 - REVISED MARCH 2013 Absolute Maximum Ratings (1) Supply Voltage 22V Input Voltage Range 20V Input Current Range -0.1mA to 10mA Differential Input Voltage (2) 30V Output Short Circuit Duration (3) Continuous Power Dissipation (Pd at 25C) (4) CDIP JA Thermal Resistance JC Package Weight (typical) 400mW CLGA (NAD0014B) 350mW CDIP (Still Air) 103C/W CDIP (500LF/ Min Air flow) 52C/W CLGA (NAD0014B) (Still Air) 140C/W CLGA (NAD0014B) (500LF/ Min Air flow) 100C/W CLGA (NAC0014A) (Still Air) 176C/W CLGA (NAC0014A) (500LF/ Min Air flow) 116C/W CDIP 19C/W CLGA (NAD0014B) 25C/W CLGA (NAC0014A) 25C/W CDIP TBD CLGA (NAD0014B) 465mg CLGA (NAC0014A) 415mg Maximum Junction Temperature (TJMAX) 175C Operating Temperature Range -55C TA +125C Storage Temperature Range -65C TA +150C Lead Temperature (Soldering, 10 sec.) Ceramic 300C ESD tolerance (5) 500V (1) (2) (3) (4) (5) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. The differential input voltage range shall not exceed the supply voltage range. Any of the amplifier outputs can be shorted to ground indefinitely; however, more than one should not be simultaneously shorted as the maximum junction temperature will be exceeded. The maximum power dissipation for these devices must be derated at elevated temperatures and is dicated by TJMAX, JA, and the ambient temperature, TA. The maximum available power dissipation at any temperature is Pd = (TJMAX - TA)/JA or the number given in the Absolute Maximum Ratings, whichever is less. Human body model, 1.5 k in series with 100 pF. Quality Conformance Inspection MIL-STD-883, Method 5005 -- Group A Subgroup Description 1 Static tests at Temp ( C) +25 2 Static tests at +125 3 Static tests at -55 4 Dynamic tests at +25 5 Dynamic tests at +125 6 Dynamic tests at -55 7 Functional tests at +25 8A Functional tests at +125 8B Functional tests at -55 9 Switching tests at +25 Submit Documentation Feedback Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LM148JAN 3 LM148JAN SNOSAI2A - FEBRUARY 2005 - REVISED MARCH 2013 www.ti.com Quality Conformance Inspection (continued) MIL-STD-883, Method 5005 -- Group A Subgroup Description Temp ( C) 10 Switching tests at +125 11 Switching tests at -55 Electrical Characteristics DC PARAMETERS (The following conditions apply to all parameters, unless otherwise specified.) VCC = 20V, VCM = 0V, measure each amplifier. Symbol VIO Parameter Input Offset Voltage Conditions Notes Subgroups Min Max Units +VCC = 35V, -VCC = -5V, VCM = -15V -5.0 +5.0 mV 1 -6.0 +6.0 mV 2, 3 +VCC = 5V, -VCC = -35V, VCM = +15V -5.0 +5.0 mV 1 -6.0 +6.0 mV 2, 3 -5.0 +5.0 mV 1 -6.0 +6.0 mV 2, 3 -5.0 +5.0 mV 1 -6.0 +6.0 mV 2, 3 See (1) -25 25 V/C 2 See (1) -25 25 V/C 3 +VCC = 35V, -VCC = -5V, VCM = -15V -25 +25 nA 1, 2 -75 +75 nA 3 +VCC = 5V, -VCC = -35V, VCM = +15V -25 +25 nA 1, 2 -75 +75 nA 3 -25 +25 nA 1, 2 -75 +75 nA 3 -25 +25 nA 1, 2 -75 +75 nA 3 +VCC = 5V, -VCC = -5V, Delta VIO / Delta T Input Offset Voltage Temperature 25C TA 125C Stability -55C TA 25C IIO Input Offset Current +VCC = 5V, -VCC = -5V, Delta IIO / Delta T Input Offset Current Temperature Stability 25C TA 125C See (1) -200 200 pA/C 2 -55C TA 25C See (1) -400 400 pA/C 3 IIB Input Bias Current +VCC = 35V, -VCC = -5V, VCM = -15V -0.1 100 nA 1, 2 -0.1 325 nA 3 +VCC = 5V, -VCC = -35V, VCM = +15V -0.1 100 nA 1, 2 -0.1 325 nA 3 -0.1 100 nA 1, 2 -0.1 325 nA 3 -0.1 100 nA 1, 2 -0.1 325 nA 3 +VCC = 5V, -VCC = -5V, (1) (2) 4 PSRR+ Power Supply Rejection Ratio -VCC = -20V, +VCC = 20V to 10V See (2) -100 100 V/V 1, 2, 3 PSRR- Power Supply Rejection Ratio +VCC = 20V, -VCC = -20V to -10V See (2) -100 100 V/V 1, 2, 3 CMRR Common Mode Rejection Ratio VCM = 15 V, 5V VCC 35V dB 1, 2, 3 76 Calculated parameter. Datalogs as V Submit Documentation Feedback Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LM148JAN LM148JAN www.ti.com SNOSAI2A - FEBRUARY 2005 - REVISED MARCH 2013 Electrical Characteristics AC / DC PARAMETERS (The following conditions apply to all parameters, unless otherwise specified.) VCC = 20V, VCM = 0V, measure each amplifier. Symbol + IOS - IOS ICC -AVS Parameter Short Circuit Current Short Circuit Current Power Supply Current Open Loop Voltage Gain Conditions Notes +VCC = 15V, -VCC = -15V, VCM = -10V Open Loop Voltage Gain Open Loop Voltage Gain +VOP Output Voltage Swing -VOP Output Voltage Swing -55 mA 1, 2 -75 mA 3 55 mA 1, 2 75 mA 3 +VCC = 15V, -VCC = -15V 3.6 mA 1 4.5 mA 2, 3 50 V/mV 4 25 V/mV 5, 6 50 V/mV 4 25 V/mV 5, 6 50 V/mV 4 25 V/mV 5, 6 50 V/mV 4 25 V/mV 5, 6 VCC = 5V, VOUT = 2V, RL = 10K 10 V/mV 4, 5, 6 VCC = 5V, VOUT = 2V, RL = 2K 10 V/mV 4, 5, 6 RL = 10K +16 V 4, 5, 6 RL = 2K +15 VOUT = -15V, RL = 10K VOUT = +15V, RL = 10K VOUT = +15V, RL = 2K AVS Subgroups Max +VCC = 15V, -VCC = -15V, VCM = +10V VOUT = -15V, RL = 2K +AVS Units Min V 4, 5, 6 RL = 10K -16 V 4, 5, 6 RL = 2K -15 V 4, 5, 6 TRTR Transient Response Time VIN = 50mV, AV = 1 1 S 7, 8A, 8B TROS Transient Response Time VIN = 50mV, AV = 1 25 % 7, 8A, 8B SR Slew Rate VIN = -5V to +5V, AV = 1 0.2 V/S 7, 8A, 8B VIN = +5V to -5V, AV = 1 0.2 V/S 7, 8A, 8B Max Units Subgroups 15 VRMS 7 40 Electrical Characteristics AC PARAMETERS (The following conditions apply to all parameters, unless otherwise specified.) VCC = 20V, VCM = 0V, measure each amplifier. Symbol Parameter NIBB Noise (Broadband) NIPC Noise (Popcorn) CS Channel Separation Conditions Notes Min BW = 10Hz to 5KHz VPK 7 VIN = 10V, A to B, RL = 2K 80 dB 7 VIN = 10V, A to C, RL = 2K 80 dB 7 VIN = 10V, A to D, RL = 2K 80 dB 7 VIN = 10V, B to A, RL = 2K 80 dB 7 VIN = 10V, B to C, RL = 2K 80 dB 7 VIN = 10V, B to D, RL = 2K 80 dB 7 VIN = 10V, C to A, RL = 2K 80 dB 7 VIN = 10V, C to B, RL = 2K 80 dB 7 VIN = 10V, C to D, RL = 2K 80 dB 7 VIN = 10V, D to A, RL = 2K 80 dB 7 VIN = 10V, D to B, RL = 2K 80 dB 7 VIN = 10V, D to C, RL = 2K 80 dB 7 RS = 20K Submit Documentation Feedback Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LM148JAN 5 LM148JAN SNOSAI2A - FEBRUARY 2005 - REVISED MARCH 2013 www.ti.com Electrical Characteristics DC DRIFT PARAMETERS (The following conditions apply to all parameters, unless otherwise specified.) VCC = 20V, VCM = 0V, measure each amplifier. Delta calculations performed on JAN S and QMLV devices at group B, subgroup 5 only. Symbol Parameter Conditions Notes Min Max Units Subgroups VIO Input Offset Voltage -1 1 mV 1 IIB Input Bias Current -15 15 nA 1 Cross Talk Test Circuit VS = 15V 6 Submit Documentation Feedback Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LM148JAN LM148JAN www.ti.com SNOSAI2A - FEBRUARY 2005 - REVISED MARCH 2013 Typical Performance Characteristics Supply Current Input Bias Current Figure 2. Figure 3. Voltage Swing Positive Current Limit Figure 4. Figure 5. Negative Current Limit Output Impedance Figure 6. Figure 7. Submit Documentation Feedback Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LM148JAN 7 LM148JAN SNOSAI2A - FEBRUARY 2005 - REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) 8 Common-Mode Rejection Ratio Open Loop Frequency Response Figure 8. Figure 9. Bode Plot LM148 Large Signal Pulse Response (LM148) Figure 10. Figure 11. Small Signal Pulse Response (LM148) Undistorted Output Voltage Swing Figure 12. Figure 13. Submit Documentation Feedback Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LM148JAN LM148JAN www.ti.com SNOSAI2A - FEBRUARY 2005 - REVISED MARCH 2013 Typical Performance Characteristics (continued) Gain Bandwidth Slew Rate Figure 14. Figure 15. Inverting Large Signal Pulse Response (LM148) Input Noise Voltage and Noise Current Figure 16. Figure 17. Positive Common-Mode Input Voltage Limit Negative Common-Mode Input Voltage Limit Figure 18. Figure 19. Submit Documentation Feedback Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LM148JAN 9 LM148JAN SNOSAI2A - FEBRUARY 2005 - REVISED MARCH 2013 www.ti.com APPLICATION HINTS The LM148 series are quad low power LM741 op amps. In the proliferation of quad op amps, these are the first to offer the convenience of familiar, easy to use operating characteristics of the LM741 op amp. In those applications where LM741 op amps have been employed, the LM148 series op amps can be employed directly with no change in circuit performance. The package pin-outs are such that the inverting input of each amplifier is adjacent to its output. In addition, the amplifier outputs are located in the corners of the package which simplifies PC board layout and minimizes package related capacitive coupling between amplifiers. The input characteristics of these amplifiers allow differential input voltages which can exceed the supply voltages. In addition, if either of the input voltages is within the operating common-mode range, the phase of the output remains correct. If the negative limit of the operating common-mode range is exceeded at both inputs, the output voltage will be positive. For input voltages which greatly exceed the maximum supply voltages, either differentially or common-mode, resistors should be placed in series with the inputs to limit the current. Like the LM741, these amplifiers can easily drive a 100 pF capacitive load throughout the entire dynamic output voltage and current range. However, if very large capacitive loads must be driven by a non-inverting unity gain amplifier, a resistor should be placed between the output (and feedback connection) and the capacitance to reduce the phase shift resulting from the capacitive loading. The output current of each amplifier in the package is limited. Short circuits from an output to either ground or the power supplies will not destroy the unit. However, if multiple output shorts occur simultaneously, the time duration should be short to prevent the unit from being destroyed as a result of excessive power dissipation in the IC chip. As with most amplifiers, care should be taken lead dress, component placement and supply decoupling in order to ensure stability. For example, resistors from the output to an input should be placed with the body close to the input to minimize "pickup" and maximize the frequency of the feedback pole which capacitance from the input to ground creates. A feedback pole is created when the feedback around any amplifier is resistive. The parallel resistance and capacitance from the input of the device (usually the inverting input) to AC ground set the frequency of the pole. In many instances the frequency of this pole is much greater than the expected 3 dB frequency of the closed loop gain and consequently there is negligible effect on stability margin. However, if the feedback pole is less than approximately six times the expected 3 dB frequency a lead capacitor should be placed from the output to the input of the op amp. The value of the added capacitor should be such that the RC time constant of this capacitor and the resistance it parallels is greater than or equal to the original feedback pole time constant. 10 Submit Documentation Feedback Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LM148JAN LM148JAN www.ti.com SNOSAI2A - FEBRUARY 2005 - REVISED MARCH 2013 Typical Applications--LM148 fMAX = 5 kHz, THD 0.03% R1 = 100k pot. C1 = 0.0047 F, C2 = 0.01 F, C3 = 0.1 F, R2 = R6 = R7 = 1M, R3 = 5.1k, R4 = 12, R5 = 240, Q = NS5102, D1 = 1N914, D2 = 3.6V avalanche diode (ex. LM103), VS = 15V A simpler version with some distortion degradation at high frequencies can be made by using A1 as a simple inverting amplifier, and by putting back to back zeners in the feedback loop of A3. Figure 20. One Decade Low Distortion Sinewave Generator VS = 15V R = R2, trim R2 to boost CMRR Figure 21. Low Cost Instrumentation Amplifier Submit Documentation Feedback Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LM148JAN 11 LM148JAN SNOSAI2A - FEBRUARY 2005 - REVISED MARCH 2013 www.ti.com Adjust R for minimum drift D3 low leakage diode D1 added to improve speed VS = 15V Figure 22. Low Drift Peak Detector with Bias Current Compensation 12 Submit Documentation Feedback Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LM148JAN LM148JAN www.ti.com SNOSAI2A - FEBRUARY 2005 - REVISED MARCH 2013 Tune Q through R0, For predictable results: fO Q 4 x 104 Use Band Pass output to tune for Q Figure 23. Universal State-Variable Filter Submit Documentation Feedback Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LM148JAN 13 LM148JAN SNOSAI2A - FEBRUARY 2005 - REVISED MARCH 2013 www.ti.com Use general equations, and tune each section separately Q1stSECTION = 0.541, Q2ndSECTION = 1.306 The response should have 0 dB peaking Figure 24. A 1 kHz 4 Pole Butterworth Ex: fNOTCH = 3 kHz, Q = 5, R1 = 270k, R2 = R3 = 20k, R4 = 27k, R5 = 20k, R6 = R8 = 10k, R7 = 100k, C1 = C2 = 0.001 F Better noise performance than the state-space approach. Figure 25. A 3 Amplifier Bi-Quad Notch Filter 14 Submit Documentation Feedback Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LM148JAN LM148JAN www.ti.com SNOSAI2A - FEBRUARY 2005 - REVISED MARCH 2013 R1C1 = R2C2 = t R1C1 = R2C2 = t fC = 1 kHz, fS = 2 kHz, fp = 0.543, fZ = 2.14, Q = 0.841, f P = 0.987, f Z = 4.92, Q = 4.403, normalized to ripple BW Use the BP outputs to tune Q, Q, tune the 2 sections separately R1 = R2 = 92.6k, R3 = R4 = R5 = 100k, R6 = 10k, R0 = 107.8k, RL = 100k, RH = 155.1k, R1 = R2 = 50.9k, R4 = R5 = 100k, R6 = 10k, R0 = 5.78k, RL = 100k, RH = 248.12k, Rf = 100k. All capacitors are 0.001 F. Figure 26. A 4th Order 1 kHz Elliptic Filter (4 Poles, 4 Zeros) Figure 27. Lowpass Response Submit Documentation Feedback Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LM148JAN 15 LM148JAN SNOSAI2A - FEBRUARY 2005 - REVISED MARCH 2013 www.ti.com Typical Simulation For more details, see IEEE Journal of Solid-State Circuits, Vol. SC-9, No. 6, December 1974 o1 = 112IS = 8 x 10-16 o2 = 144*C2 = 6 pF for LM149 Figure 28. LM148, LM741 Macromodel for Computer Simulation 16 Submit Documentation Feedback Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LM148JAN LM148JAN www.ti.com SNOSAI2A - FEBRUARY 2005 - REVISED MARCH 2013 REVISION HISTORY SECTION Date Released Revision Section Originator Changes L. Lytle 1 MDS data sheet converted into one Corp. data sheet format. MJLM148-X, Rev. 0C1. MDS data sheet will be archived. 02/15/05 A New Release, Corporate format 03/20/13 A All Changed layout of National Data Sheet to TI format Submit Documentation Feedback Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LM148JAN 17 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (C) (3) Top-Side Markings (4) JL148BCA ACTIVE CDIP J 14 25 TBD Call TI Call TI -55 to 125 JL148BCA JM38510/11001BCA Q JL148SCA ACTIVE CDIP J 14 25 TBD Call TI Call TI -55 to 125 JL148SCA JM38510/11001SCA Q JM38510/11001BCA ACTIVE CDIP J 14 25 TBD Call TI Call TI -55 to 125 JL148BCA JM38510/11001BCA Q JM38510/11001SCA ACTIVE CDIP J 14 25 TBD Call TI Call TI -55 to 125 JL148SCA JM38510/11001SCA Q M38510/11001BCA ACTIVE CDIP J 14 25 TBD Call TI Call TI -55 to 125 JL148BCA JM38510/11001BCA Q (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF LM148JAN, LM148JAN-SP : * Military: LM148JAN * Space: LM148JAN-SP NOTE: Qualified Version Definitions: * Military - QML certified for Military and Defense Applications * Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application Addendum-Page 2 PACKAGE OUTLINE J0014A CDIP - 5.08 mm max height SCALE 0.900 CERAMIC DUAL IN LINE PACKAGE PIN 1 ID (OPTIONAL) A 4X .005 MIN [0.13] .015-.060 TYP [0.38-1.52] 1 14 12X .100 [2.54] 14X .014-.026 [0.36-0.66] 14X .045-.065 [1.15-1.65] .010 [0.25] C A B .754-.785 [19.15-19.94] 8 7 B .245-.283 [6.22-7.19] .2 MAX TYP [5.08] C .13 MIN TYP [3.3] SEATING PLANE .308-.314 [7.83-7.97] AT GAGE PLANE .015 GAGE PLANE [0.38] 0 -15 TYP 14X .008-.014 [0.2-0.36] 4214771/A 05/2017 NOTES: 1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This package is hermitically sealed with a ceramic lid using glass frit. 4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only. 5. Falls within MIL-STD-1835 and GDIP1-T14. www.ti.com EXAMPLE BOARD LAYOUT J0014A CDIP - 5.08 mm max height CERAMIC DUAL IN LINE PACKAGE (.300 ) TYP [7.62] SEE DETAIL A SEE DETAIL B 1 14 12X (.100 ) [2.54] SYMM 14X ( .039) [1] 8 7 SYMM LAND PATTERN EXAMPLE NON-SOLDER MASK DEFINED SCALE: 5X .002 MAX [0.05] ALL AROUND (.063) [1.6] METAL ( .063) [1.6] SOLDER MASK OPENING METAL (R.002 ) TYP [0.05] .002 MAX [0.05] ALL AROUND SOLDER MASK OPENING DETAIL A DETAIL B SCALE: 15X 13X, SCALE: 15X 4214771/A 05/2017 www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer's noncompliance with the terms and provisions of this Notice. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright (c) 2017, Texas Instruments Incorporated Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Texas Instruments: JL148BCA JM38510/11001BCA M38510/11001BCA