LM148JAN
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LM148JAN Quad 741 Op Amps
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1FEATURES DESCRIPTION
The LM148 is a true quad LM741. It consists of four
2• 741 Op Amp Operating Characteristics independent, high gain, internally compensated, low
• Class AB Output Stage—No Crossover power operational amplifiers which have been
Distortion designed to provide functional characteristics
• Pin Compatible with the LM124 identical to those of the familiar LM741 operational
amplifier. In addition the total supply current for all
• Overload Protection for Inputs and Outputs four amplifiers is comparable to the supply current of
• Low Supply Current Drain: 0.6 mA/Amplifier a single LM741 type op amp. Other features include
• Low Input Offset Voltage: 1 mV input offset currents and input bias current which are
much less than those of a standard LM741. Also,
• Low Input Offset Current: 4 nA excellent isolation between amplifiers has been
• Low Input Bias Current 30 nA achieved by independently biasing each amplifier and
• High Degree of Isolation between Amplifiers: using layout techniques which minimize thermal
120 dB coupling.
• Gain Bandwidth Product (Unity Gain): 1.0 MHz The LM148 can be used anywhere multiple LM741 or
LM1558 type amplifiers are being used and in
applications where amplifier matching or high packing
density is required.
Connection Diagram
Figure 1. Top View
See Package Number J0014A, NAD0014B, NAC0014A
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2005–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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Schematic Diagram
* 1 pF in the LM149
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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Absolute Maximum Ratings(1)
Supply Voltage ±22V
Input Voltage Range ±20V
Input Current Range −0.1mA to
10mA
Differential Input Voltage(2) ±30V
Output Short Circuit Duration(3) Continuous
Power Dissipation (Pdat 25°C)(4) CDIP 400mW
CLGA (NAD0014B) 350mW
Thermal Resistance θJA CDIP (Still Air) 103°C/W
CDIP (500LF/ Min Air flow) 52°C/W
CLGA (NAD0014B) (Still Air) 140°C/W
CLGA (NAD0014B) (500LF/ Min Air flow) 100°C/W
CLGA (NAC0014A) (Still Air) 176°C/W
CLGA (NAC0014A) (500LF/ Min Air flow) 116°C/W
θJC CDIP 19°C/W
CLGA (NAD0014B) 25°C/W
CLGA (NAC0014A) 25°C/W
Package Weight (typical) CDIP TBD
CLGA (NAD0014B) 465mg
CLGA (NAC0014A) 415mg
Maximum Junction Temperature (TJMAX) 175°C
Operating Temperature Range −55°C ≤TA≤
+125°C
Storage Temperature Range −65°C ≤TA≤
+150°C
Lead Temperature (Soldering, 10 sec.) Ceramic 300°C
ESD tolerance(5) 500V
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the
Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions.
(2) The differential input voltage range shall not exceed the supply voltage range.
(3) Any of the amplifier outputs can be shorted to ground indefinitely; however, more than one should not be simultaneously shorted as the
maximum junction temperature will be exceeded.
(4) The maximum power dissipation for these devices must be derated at elevated temperatures and is dicated by TJMAX,θJA, and the
ambient temperature, TA. The maximum available power dissipation at any temperature is Pd= (TJMAX −TA)/θJA or the number given in
the Absolute Maximum Ratings, whichever is less.
(5) Human body model, 1.5 kΩin series with 100 pF.
Quality Conformance Inspection
MIL-STD-883, Method 5005 — Group A
Subgroup Description Temp ( °C)
1 Static tests at +25
2 Static tests at +125
3 Static tests at -55
4 Dynamic tests at +25
5 Dynamic tests at +125
6 Dynamic tests at -55
7 Functional tests at +25
8A Functional tests at +125
8B Functional tests at -55
9 Switching tests at +25
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Quality Conformance Inspection (continued)
MIL-STD-883, Method 5005 — Group A
Subgroup Description Temp ( °C)
10 Switching tests at +125
11 Switching tests at -55
Electrical Characteristics
DC PARAMETERS (The following conditions apply to all parameters, unless otherwise specified.)
±VCC = ±20V, VCM = 0V, measure each amplifier. Sub-
Symbol Parameter Conditions Notes Min Max Units groups
VIO Input Offset Voltage +VCC = 35V, −VCC =−5V, −5.0 +5.0 mV 1
VCM =−15V −6.0 +6.0 mV 2, 3
+VCC = 5V, −VCC =−35V, −5.0 +5.0 mV 1
VCM = +15V −6.0 +6.0 mV 2, 3
−5.0 +5.0 mV 1
−6.0 +6.0 mV 2, 3
+VCC = 5V, −VCC =−5V, −5.0 +5.0 mV 1
−6.0 +6.0 mV 2, 3
Delta VIO / Input Offset Voltage Temperature 25°C ≤TA≤125°C See(1) −25 25 µV/°C 2
Delta TStability −55°C ≤TA≤25°C See(1) −25 25 µV/°C 3
IIO Input Offset Current +VCC = 35V, −VCC =−5V, −25 +25 nA 1, 2
VCM =−15V −75 +75 nA 3
+VCC = 5V, −VCC =−35V, −25 +25 nA 1, 2
VCM = +15V −75 +75 nA 3
−25 +25 nA 1, 2
−75 +75 nA 3
+VCC = 5V, −VCC =−5V, −25 +25 nA 1, 2
−75 +75 nA 3
Delta IIO / Input Offset Current Temperature 25°C ≤TA≤125°C See(1) -200 200 pA/°C 2
Delta TStability −55°C ≤TA≤25°C See(1) –400 400 pA/°C 3
±IIB Input Bias Current +VCC = 35V, −VCC =−5V, −0.1 100 nA 1, 2
VCM =−15V −0.1 325 nA 3
+VCC = 5V, −VCC =−35V, −0.1 100 nA 1, 2
VCM = +15V −0.1 325 nA 3
−0.1 100 nA 1, 2
−0.1 325 nA 3
+VCC = 5V, −VCC =−5V, −0.1 100 nA 1, 2
−0.1 325 nA 3
PSRR+ Power Supply Rejection Ratio −VCC =−20V, +VCC = 20V to 10V See(2) −100 100 µV/V 1, 2, 3
PSRR−Power Supply Rejection Ratio +VCC = 20V, −VCC =−20V to −10V See(2) −100 100 µV/V 1, 2, 3
CMRR Common Mode Rejection Ratio VCM = ±15 V, ±5V ≤VCC ≤± 35V 76 dB 1, 2, 3
(1) Calculated parameter.
(2) Datalogs as µV
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Electrical Characteristics
AC / DC PARAMETERS (The following conditions apply to all parameters, unless otherwise specified.)
±VCC = ±20V, VCM = 0V, measure each amplifier. Sub-
Symbol Parameter Conditions Notes Min Max Units groups
+ IOS Short Circuit Current +VCC = 15V, −VCC =−15V, −55 mA 1, 2
VCM =−10V −75 mA 3
−IOS Short Circuit Current +VCC = 15V, −VCC =−15V, 55 mA 1, 2
VCM = +10V 75 mA 3
ICC Power Supply Current +VCC = 15V, −VCC =−15V 3.6 mA 1
4.5 mA 2, 3
−AVS Open Loop Voltage Gain VOUT =−15V, RL= 10KΩ50 V/mV 4
25 V/mV 5, 6
VOUT =−15V, RL= 2KΩ50 V/mV 4
25 V/mV 5, 6
+AVS Open Loop Voltage Gain VOUT = +15V, RL= 10KΩ50 V/mV 4
25 V/mV 5, 6
VOUT = +15V, RL= 2KΩ50 V/mV 4
25 V/mV 5, 6
AVS Open Loop Voltage Gain VCC = ±5V, VOUT = ±2V, RL= 10KΩ10 V/mV 4, 5, 6
VCC = ±5V, VOUT = ±2V, RL= 2KΩ10 V/mV 4, 5, 6
+VOP Output Voltage Swing RL= 10KΩ+16 V 4, 5, 6
RL= 2KΩ+15 V 4, 5, 6
-VOP Output Voltage Swing RL= 10KΩ-16 V 4, 5, 6
RL= 2KΩ-15 V 4, 5, 6
TRTR Transient Response Time VIN = 50mV, AV= 1 1 µS 7, 8A, 8B
TROS Transient Response Time VIN = 50mV, AV= 1 25 % 7, 8A, 8B
±SR Slew Rate VIN =−5V to +5V, AV= 1 0.2 V/µS 7, 8A, 8B
VIN = +5V to −5V, AV= 1 0.2 V/µS 7, 8A, 8B
Electrical Characteristics
AC PARAMETERS (The following conditions apply to all parameters, unless otherwise specified.)
±VCC = ±20V, VCM = 0V, measure each amplifier. Sub-
Symbol Parameter Conditions Notes Min Max Units groups
NIBB Noise (Broadband) BW = 10Hz to 5KHz 15 μVRMS 7
NIPC Noise (Popcorn) RS= 20KΩ40 μVPK 7
CSChannel Separation VIN = ±10V, A to B, RL= 2KΩ80 dB 7
VIN = ±10V, A to C, RL= 2KΩ80 dB 7
VIN = ±10V, A to D, RL= 2KΩ80 dB 7
VIN = ±10V, B to A, RL= 2KΩ80 dB 7
VIN = ±10V, B to C, RL= 2KΩ80 dB 7
VIN = ±10V, B to D, RL= 2KΩ80 dB 7
VIN = ±10V, C to A, RL= 2KΩ80 dB 7
VIN = ±10V, C to B, RL= 2KΩ80 dB 7
VIN = ±10V, C to D, RL= 2KΩ80 dB 7
VIN = ±10V, D to A, RL= 2KΩ80 dB 7
VIN = ±10V, D to B, RL= 2KΩ80 dB 7
VIN = ±10V, D to C, RL= 2KΩ80 dB 7
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Electrical Characteristics
DC DRIFT PARAMETERS (The following conditions apply to all parameters, unless otherwise specified.)
±VCC = ±20V, VCM = 0V, measure each amplifier. Delta calculations performed on JAN S and QMLV devices at group B,
subgroup 5 only. Sub-
Symbol Parameter Conditions Notes Min Max Units groups
VIO Input Offset Voltage −1 1 mV 1
±IIB Input Bias Current −15 15 nA 1
Cross Talk Test Circuit
VS= ±15V
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Typical Performance Characteristics
Supply Current Input Bias Current
Figure 2. Figure 3.
Voltage Swing Positive Current Limit
Figure 4. Figure 5.
Negative Current Limit Output Impedance
Figure 6. Figure 7.
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Typical Performance Characteristics (continued)
Common-Mode Rejection Ratio Open Loop Frequency Response
Figure 8. Figure 9.
Bode Plot LM148 Large Signal Pulse Response (LM148)
Figure 10. Figure 11.
Small Signal Pulse Response (LM148) Undistorted Output Voltage Swing
Figure 12. Figure 13.
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Typical Performance Characteristics (continued)
Gain Bandwidth Slew Rate
Figure 14. Figure 15.
Inverting Large Signal Pulse Response (LM148) Input Noise Voltage and Noise Current
Figure 16. Figure 17.
Positive Common-Mode Input Voltage Limit Negative Common-Mode Input Voltage Limit
Figure 18. Figure 19.
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APPLICATION HINTS
The LM148 series are quad low power LM741 op amps. In the proliferation of quad op amps, these are the first
to offer the convenience of familiar, easy to use operating characteristics of the LM741 op amp. In those
applications where LM741 op amps have been employed, the LM148 series op amps can be employed directly
with no change in circuit performance.
The package pin-outs are such that the inverting input of each amplifier is adjacent to its output. In addition, the
amplifier outputs are located in the corners of the package which simplifies PC board layout and minimizes
package related capacitive coupling between amplifiers.
The input characteristics of these amplifiers allow differential input voltages which can exceed the supply
voltages. In addition, if either of the input voltages is within the operating common-mode range, the phase of the
output remains correct. If the negative limit of the operating common-mode range is exceeded at both inputs, the
output voltage will be positive. For input voltages which greatly exceed the maximum supply voltages, either
differentially or common-mode, resistors should be placed in series with the inputs to limit the current.
Like the LM741, these amplifiers can easily drive a 100 pF capacitive load throughout the entire dynamic output
voltage and current range. However, if very large capacitive loads must be driven by a non-inverting unity gain
amplifier, a resistor should be placed between the output (and feedback connection) and the capacitance to
reduce the phase shift resulting from the capacitive loading.
The output current of each amplifier in the package is limited. Short circuits from an output to either ground or the
power supplies will not destroy the unit. However, if multiple output shorts occur simultaneously, the time
duration should be short to prevent the unit from being destroyed as a result of excessive power dissipation in
the IC chip.
As with most amplifiers, care should be taken lead dress, component placement and supply decoupling in order
to ensure stability. For example, resistors from the output to an input should be placed with the body close to the
input to minimize “pickup” and maximize the frequency of the feedback pole which capacitance from the input to
ground creates.
A feedback pole is created when the feedback around any amplifier is resistive. The parallel resistance and
capacitance from the input of the device (usually the inverting input) to AC ground set the frequency of the pole.
In many instances the frequency of this pole is much greater than the expected 3 dB frequency of the closed
loop gain and consequently there is negligible effect on stability margin. However, if the feedback pole is less
than approximately six times the expected 3 dB frequency a lead capacitor should be placed from the output to
the input of the op amp. The value of the added capacitor should be such that the RC time constant of this
capacitor and the resistance it parallels is greater than or equal to the original feedback pole time constant.
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Typical Applications—LM148
fMAX = 5 kHz, THD ≤0.03%
R1 = 100k pot. C1 = 0.0047 μF, C2 = 0.01 μF, C3 = 0.1 μF, R2 = R6 = R7 = 1M,
R3 = 5.1k, R4 = 12Ω, R5 = 240Ω, Q = NS5102, D1 = 1N914, D2 = 3.6V avalanche
diode (ex. LM103), VS= ±15V
A simpler version with some distortion degradation at high frequencies can be made by using A1 as a simple inverting
amplifier, and by putting back to back zeners in the feedback loop of A3.
Figure 20. One Decade Low Distortion Sinewave Generator
VS= ±15V
R = R2, trim R2 to boost CMRR
Figure 21. Low Cost Instrumentation Amplifier
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Adjust R for minimum drift
D3 low leakage diode
D1 added to improve speed
VS= ±15V
Figure 22. Low Drift Peak Detector with Bias Current Compensation
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Tune Q through R0,
For predictable results: fOQ≤4 × 104
Use Band Pass output to tune for Q
Figure 23. Universal State-Variable Filter
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Use general equations, and tune each section separately
Q1stSECTION = 0.541, Q2ndSECTION = 1.306
The response should have 0 dB peaking
Figure 24. A 1 kHz 4 Pole Butterworth
Ex: fNOTCH = 3 kHz, Q = 5, R1 = 270k, R2 = R3 = 20k, R4 = 27k, R5 = 20k, R6 = R8 = 10k, R7 = 100k, C1 = C2 =
0.001 μF
Better noise performance than the state-space approach.
Figure 25. A 3 Amplifier Bi-Quad Notch Filter
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R1C1 = R2C2 = t
R′1C′1 = R′2C′2 = t′
fC= 1 kHz, fS= 2 kHz, fp= 0.543, fZ= 2.14, Q = 0.841, f′P= 0.987, f′Z= 4.92, Q′= 4.403, normalized to ripple BW
Use the BP outputs to tune Q, Q′, tune the 2 sections separately
R1 = R2 = 92.6k, R3 = R4 = R5 = 100k, R6 = 10k, R0 = 107.8k, RL= 100k, RH= 155.1k,
R′1 = R′2 = 50.9k, R′4 = R′5 = 100k, R′6 = 10k, R′0 = 5.78k, R′L= 100k, R′H= 248.12k, R′f = 100k. All capacitors
are 0.001 μF.
Figure 26. A 4th Order 1 kHz Elliptic Filter (4 Poles, 4 Zeros)
Figure 27. Lowpass Response
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Typical Simulation
For more details, see IEEE Journal of Solid-State Circuits, Vol. SC-9, No. 6, December 1974
o1 = 112IS= 8 × 10−16
o2 = 144*C2 = 6 pF for LM149
Figure 28. LM148, LM741 Macromodel for Computer Simulation
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REVISION HISTORY SECTION
Date Revision Section Originator Changes
Released
02/15/05 A New Release, Corporate format L. Lytle 1 MDS data sheet converted into one Corp.
data sheet format. MJLM148-X, Rev. 0C1.
MDS data sheet will be archived.
03/20/13 A All Changed layout of National Data Sheet to TI
format
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PACKAGE OPTION ADDENDUM
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Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Top-Side Markings
(4)
Samples
JL148BCA ACTIVE CDIP J 14 25 TBD Call TI Call TI -55 to 125 JL148BCA
JM38510/11001BCA Q
JL148SCA ACTIVE CDIP J 14 25 TBD Call TI Call TI -55 to 125 JL148SCA
JM38510/11001SCA Q
JM38510/11001BCA ACTIVE CDIP J 14 25 TBD Call TI Call TI -55 to 125 JL148BCA
JM38510/11001BCA Q
JM38510/11001SCA ACTIVE CDIP J 14 25 TBD Call TI Call TI -55 to 125 JL148SCA
JM38510/11001SCA Q
M38510/11001BCA ACTIVE CDIP J 14 25 TBD Call TI Call TI -55 to 125 JL148BCA
JM38510/11001BCA Q
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
PACKAGE OPTION ADDENDUM
www.ti.com 11-Apr-2013
Addendum-Page 2
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF LM148JAN, LM148JAN-SP :
•Military: LM148JAN
•Space: LM148JAN-SP
NOTE: Qualified Version Definitions:
•Military - QML certified for Military and Defense Applications
•Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application
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PACKAGE OUTLINE
C
14X .008-.014
[0.2-0.36]
TYP
-15
0
AT GAGE PLANE
-.314.308 -7.977.83[ ]
14X -.026.014 -0.660.36[ ]
14X -.065.045 -1.651.15[ ]
.2 MAX TYP
[5.08] .13 MIN TYP
[3.3]
TYP-.060.015 -1.520.38[ ]
4X .005 MIN
[0.13]
12X .100
[2.54]
.015 GAGE PLANE
[0.38]
A
-.785.754 -19.9419.15[ ]
B -.283.245 -7.196.22[ ]
CDIP - 5.08 mm max heightJ0014A
CERAMIC DUAL IN LINE PACKAGE
4214771/A 05/2017
NOTES:
1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for
reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package is hermitically sealed with a ceramic lid using glass frit.
4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only.
5. Falls within MIL-STD-1835 and GDIP1-T14.
78
14
1
PIN 1 ID
(OPTIONAL)
SCALE 0.900
SEATING PLANE
.010 [0.25] C A B
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EXAMPLE BOARD LAYOUT
ALL AROUND
[0.05] MAX.002
.002 MAX
[0.05]
ALL AROUND
SOLDER MASK
OPENING
METAL
(.063)
[1.6]
(R.002 ) TYP
[0.05]
14X ( .039)
[1]
( .063)
[1.6]
12X (.100 )
[2.54]
(.300 ) TYP
[7.62]
CDIP - 5.08 mm max heightJ0014A
CERAMIC DUAL IN LINE PACKAGE
4214771/A 05/2017
LAND PATTERN EXAMPLE
NON-SOLDER MASK DEFINED
SCALE: 5X
SEE DETAIL A SEE DETAIL B
SYMM
SYMM
1
78
14
DETAIL A
SCALE: 15X
SOLDER MASK
OPENING
METAL
DETAIL B
13X, SCALE: 15X
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Buyers and others who are developing systems that incorporate TI products (collectively, “Designers”) understand and agree that Designers
remain responsible for using their independent analysis, evaluation and judgment in designing their applications and that Designers have
full and exclusive responsibility to assure the safety of Designers' applications and compliance of their applications (and of all TI products
used in or for Designers’ applications) with all applicable regulations, laws and other applicable requirements. Designer represents that, with
respect to their applications, Designer has all the necessary expertise to create and implement safeguards that (1) anticipate dangerous
consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm and
take appropriate actions. Designer agrees that prior to using or distributing any applications that include TI products, Designer will
thoroughly test such applications and the functionality of such TI products as used in such applications.
TI’s provision of technical, application or other design advice, quality characterization, reliability data or other services or information,
including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to
assist designers who are developing applications that incorporate TI products; by downloading, accessing or using TI Resources in any
way, Designer (individually or, if Designer is acting on behalf of a company, Designer’s company) agrees to use any particular TI Resource
solely for this purpose and subject to the terms of this Notice.
TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TI
products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections,
enhancements, improvements and other changes to its TI Resources. TI has not conducted any testing other than that specifically
described in the published documentation for a particular TI Resource.
Designer is authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that
include the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE
TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY
RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or
endorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
TI RESOURCES ARE PROVIDED “AS IS” AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR
REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO
ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL
PROPERTY RIGHTS. TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY DESIGNER AGAINST ANY CLAIM,
INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF
PRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL,
DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN
CONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN
ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949
and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements.
Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such
products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards
and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must
ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in
life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use.
Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life
support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all
medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S.
TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product).
Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications
and that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatory
requirements in connection with such selection.
Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s non-
compliance with the terms and provisions of this Notice.
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