MC33178, MC33179 Low Power, Low Noise Operational Amplifiers The MC33178/9 series is a family of high quality monolithic amplifiers employing Bipolar technology with innovative high performance concepts for quality audio and data signal processing applications. This device family incorporates the use of high frequency PNP input transistors to produce amplifiers exhibiting low input offset voltage, noise and distortion. In addition, the amplifier provides high output current drive capability while consuming only 420 mA of drain current per amplifier. The NPN output stage used, exhibits no deadband crossover distortion, large output voltage swing, excellent phase and gain margins, low open-loop high frequency output impedance, symmetrical source and sink AC frequency performance. The MC33178/9 family offers both dual and quad amplifier versions in several package options. http://onsemi.com DUAL PDIP-8 P SUFFIX CASE 626 8 1 1 Features * * * * * * * * * * SOIC-8 D SUFFIX CASE 751 8 600 W Output Drive Capability Large Output Voltage Swing Low Offset Voltage: 0.15 mV (Mean) Low T.C. of Input Offset Voltage: 2.0 mV/C Low Total Harmonic Distortion: 0.0024% (@ 1.0 kHz w/600 W Load) High Gain Bandwidth: 5.0 MHz High Slew Rate: 2.0 V/ms Dual Supply Operation: 2.0 V to 18 V ESD Clamps on the Inputs Increase Ruggedness without Affecting Device Performance Pb-Free Packages are Available Micro8 DM SUFFIX CASE 846A 8 1 QUAD PDIP-14 P SUFFIX CASE 646 14 1 14 1 VCC 14 Iref Iref 1 Vin + Vin - SOIC-14 D SUFFIX CASE 751A TSSOP-14 DTB SUFFIX CASE 948G CC ORDERING INFORMATION VO CM See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. DEVICE MARKING INFORMATION See general marking information in the device marking section on page 4 of this data sheet. VEE Figure 1. Representative Schematic Diagram (Each Amplifier) (c) Semiconductor Components Industries, LLC, 2005 October, 2005 - Rev. 6 1 Publication Order Number: MC33178/D MC33178, MC33179 MAXIMUM RATINGS Rating Symbol Value Unit VS +36 V Input Differential Voltage Range VIDR Note 1 V Input Voltage Range VIR Note 1 V Output Short Circuit Duration (Note 2) tSC Indefinite sec Maximum Junction Temperature TJ +150 C Storage Temperature Range Tstg -60 to +150 C Maximum Power Dissipation PD Note 2 mW Operating Temperature Range TA -40 to +85 C Supply Voltage (VCC to VEE) Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. Either or both input voltages should not exceed VCC or VEE. 2. Power dissipation must be considered to ensure maximum junction temperature (TJ) is not exceeded. (See power dissipation performance characteristic, Figure 2.) ORDERING INFORMATION Package Shipping SOIC-8 98 Units / Rail MC33178DG SOIC-8 (Pb-Free) 98 Units / Rail MC33178DR2 SOIC-8 2500 / Tape & Reel SOIC-8 (Pb-Free) 2500 / Tape & Reel PDIP-8 1000 Units / Rail PDIP-8 (Pb-Free) 1000 Units / Rail Micro8 4000 / Tape & Reel MC33178DMR2G Micro8 (Pb-Free) 4000 / Tape & Reel MC33179D SOIC-14 55 Units / Rail MC33179DG SOIC-14 (Pb-Free) 55 Units / Rail MC33179DR2 SOIC-14 2500 / Tape & Reel MC33179DR2G SOIC-14 (Pb-Free) 2500 / Tape & Reel MC33179P PDIP-14 500 Units / Rail MC33179PG PDIP-14 (Pb-Free) 500 Units / Rail MC33179DTBR2G TSSOP-14 (Pb-Free) 2500 / Tape & Reel Device MC33178D MC33178DR2G MC33178P MC33178PG MC33178DMR2 For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 2 MC33178, MC33179 MARKING DIAGRAMS DUAL QUAD PDIP-8 CASE 626 PDIP-14 CASE 646 SOIC-8 CASE 751 8 14 8 MC33178P AWL YYWWG 1 1 SOIC-14 CASE 751A 33178 ALYW G 14 MC33179DG AWLYWW MC33179P AWLYYWWG 1 1 Micro8 CASE 846A TSSOP-14 CASE 948G 8 14 MC33 179 ALYW 3178 AYWG G 1 1 A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G, G = Pb-Free Package (Note: Microdot may be in either location) PIN CONNECTIONS DUAL CASE 626/751/846A Output 1 Inputs 1 VEE 1 8 2 7 3 4 - + QUAD CASE 646/751A/948G VCC Output 2 Output 1 14 2 13 Inputs 1 6 - + 5 1 Inputs 2 3 VCC (Top View) 1 4 + 11 10 + - 2 7 3 + - VEE Inputs 3 9 8 (Top View) 3 Inputs 4 12 5 6 http://onsemi.com - + 4 Inputs 2 Output 2 - Output 4 Output 3 MC33178, MC33179 DC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = -15 V, TA = 25C, unless otherwise noted.) Characteristics Figure Symbol Input Offset Voltage (RS = 50 W, VCM = 0 V, VO = 0 V) (VCC = +2.5 V, VEE = -2.5 V to VCC = +15 V, VEE = -15 V) TA = +25C TA = -40 to +85C 3 |VIO| Average Temperature Coefficient of Input Offset Voltage (RS = 50 W, VCM = 0 V, VO = 0 V) TA = -40 to +85C 3 Min 4, 5 Input Offset Current (VCM = 0 V, VO = 0 V) TA = +25C TA = -40 to +85C Max 0.15 - 3.0 4.0 DVIO/DT mV/C - 2.0 - - - 100 - 500 600 - - 5.0 - 50 60 -13 - -14 +14 - +13 50 25 200 - - - IIB nA |IIO| Common Mode Input Voltage Range (DVIO = 5.0 mV, VO = 0 V) Large Signal Voltage Gain (VO = -10 V to +10 V, RL = 600 W) TA = +25C TA = -40 to +85C Output Voltage Swing (VID = 1.0 V) (VCC = +15 V, VEE = -15 V) RL = 300 W RL = 300 W RL = 600 W RL = 600 W RL = 2.0 kW RL = 2.0 kW (VCC = +2.5 V, VEE = -2.5 V) RL = 600 W RL = 600 W 6 VICR 7, 8 AVOL nA V VO+ VO- VO+ VO- VO+ VO- - - +12 - +13 - +12 -12 +13.6 -13 +14 -13.8 - - - -12 - -13 VO+ VO- 1.1 - 1.6 -1.6 - -1.1 80 110 - 80 110 - +50 -50 +80 -100 - - Common Mode Rejection (Vin = 13 V) 12 CMR Power Supply Rejection VCC/VEE = +15 V/ -15 V, +5.0 V/ -15 V, +15 V/ -5.0 V 13 PSR 14, 15 Power Supply Current (VO = 0 V) (VCC = 2.5 V, VEE = -2.5 V to VCC = +15 V, VEE = -15 V) MC33178 (Dual) TA = +25C TA = -40 to +85C MC33179 (Quad) TA = +25C TA = -40 to +85C 16 http://onsemi.com 4 V kV/V 9, 10, 11 Output Short Circuit Current (VID = 1.0 V, Output to Ground) Source (VCC = 2.5 V to 15 V) Sink (VEE = -2.5 V to -15 V) Unit mV - - Input Bias Current (VCM = 0 V, VO = 0 V) TA = +25C TA = -40 to +85C Typ dB dB ISC mA ID mA - - - - 1.4 1.6 - - 1.7 - 2.4 2.6 MC33178, MC33179 AC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = -15 V, TA = 25C, unless otherwise noted.) Characteristics Slew Rate (Vin = -10 V to +10 V, RL = 2.0 kW, CL = 100 pF, AV = +1.0 V) Gain Bandwidth Product (f = 100 kHz) AC Voltage Gain (RL = 600 W, VO = 0 V, f = 20 kHz) Figure Symbol 17, 32 SR Min Typ Max Unit V/ms 1.2 2.0 - 18 GBW 2.5 5.0 - MHz 19, 20 AVO - 50 - dB Unity Gain Bandwidth (Open-Loop) (RL = 600 W, CL = 0 pF) BW - 3.0 - MHz Gain Margin (RL = 600 W, CL = 0 pF) 21, 23, 24 Am - 15 - dB Phase Margin (RL = 600 W, CL = 0 pF) 22, 23, 24 fm - 60 - Deg 25 CS - -120 - dB BWp - 32 - kHz - - - 0.0024 0.014 0.024 - - - - 150 - Channel Separation (f = 100 Hz to 20 kHz) Power Bandwidth (VO = 20 Vpp, RL = 600 W, THD 1.0%) Total Harmonic Distortion (RL = 600 W,, VO = 2.0 Vpp, AV = +1.0 V) (f = 1.0 kHz) (f = 10 kHz) (f = 20 kHz) 26 Open Loop Output Impedance (VO = 0 V, f = 3.0 MHz, AV = 10 V) 27 THD % W |ZO| Differential Input Resistance (VCM = 0 V) Rin - 200 - kW Differential Input Capacitance (VCM = 0 V) Cin - 10 - pF - - 8.0 7.5 - - - - 0.33 0.15 - - 28 Equivalent Input Noise Current f = 10 Hz f = 1.0 kHz 29 2400 2000 MC33178P/9P 1600 MC33179D 1200 800 nV/ Hz en pA/ Hz in 4.0 V, IO INPUT OFFSET VOLTAGE (mV) P(MAX), MAXIMUM POWER DISSIPATION (mW) D Equivalent Input Noise Voltage (RS = 100 W,) f = 10 Hz f = 1.0 kHz MC33178D 400 0 -60 -40 -20 0 20 40 60 2.0 Unit 1 1.0 Unit 2 0 Unit 3 -1.0 -2.0 -3.0 -4.0 -55 80 100 120 140 160 180 VCC = +15 V VEE = -15 V RS = 10 W VCM = 0 V 3.0 -25 0 25 50 75 100 TA, AMBIENT TEMPERATURE (C) TA, AMBIENT TEMPERATURE (C) Figure 2. Maximum Power Dissipation versus Temperature Figure 3. Input Offset Voltage versus Temperature for 3 Typical Units http://onsemi.com 5 125 MC33178, MC33179 120 140 I, IB INPUT BIAS CURRENT (nA) I, IB INPUT BIAS CURRENT (nA) 160 120 100 80 60 40 VCC = +15 V VEE = -15 V TA = 25C 20 0 -15 -10 -5.0 0 5.0 VCM, COMMON MODE VOLTAGE (V) 10 VCC = +15 V VEE = -15 V VCM = 0 V 110 100 90 80 70 60 -55 15 -25 AVOL, OPEN LOOP VOLTAGE GAIN (kV/V) VCC VCC -0.5 V VCC = +5.0 V to +18 V VEE = -5.0 V to -18 V DVIO = 5.0 mV VCC -1.0 V VCC -1.5 V VCC -2.0 V VEE +1.0 V VEE +0.5 V VEE -55 -25 0 25 50 75 100 150 VCC = +15 V VEE = -15 V f = 10 Hz DVO = 10 V to +10 V RL = 600 W 100 50 0 -55 -25 0 25 50 75 Figure 7. Open Loop Voltage Gain versus Temperature 40 80 100 VCC = +15 V VEE = -15 V VO = 0 V TA = 25C 120 140 160 0 180 -20 125 200 Figure 6. Input Common Mode Voltage Range versus Temperature 10 -10 100 250 TA, AMBIENT TEMPERATURE (C) 1A 200 1B 1A) Phase (RL = 600 W) 2B -30 2A) Phase (RL = 600 W, CL = 300 pF) 2A -40 1B) Gain (RL = 600 W) 2B) Gain (RL = 600 W, CL = 300 pF) -50 2 3 4 5 6 7 8 9 10 f, FREQUENCY (Hz) 220 240 260 20 35 VO , OUTPUT VOLTAGE (Vpp ) 20 125 , EXCESS PHASE (DEGREES) 30 125 TA, AMBIENT TEMPERATURE (C) 50 40 100 Figure 5. Input Bias Current versus Temperature A VOL, OPEN LOOP VOLTAGE GAIN (dB) V ICR, INPUT COMMON MODE VOLTAGE RANGE (V) Figure 4. Input Bias Current versus Common Mode Voltage 0 25 50 75 TA, AMBIENT TEMPERATURE (C) RL = 10 kW 25 RL = 600 W 20 15 10 5.0 0 280 TA = 25C 30 0 Figure 8. Voltage Gain and Phase versus Frequency 5.0 10 15 VCC, |VEE|, SUPPLY VOLTAGE (V) Figure 9. Output Voltage Swing versus Supply Voltage http://onsemi.com 6 20 VCC VO , OUTPUT VOLTAGE (Vpp ) VCC -1.0 V 28 Source TA = +125C TA = -55C VCC -2.0 V VEE +2.0 V Sink TA = -55C VEE +1.0 V VCC = +5.0 V to +18 V VEE = -5.0 V to -18 V TA = +125C VEE 0 5.0 10 15 16 VCC = +15 V VEE = -15 V RL = 600 W AV = +1.0 V THD = 1.0% TA = 25C 12 8.0 4.0 1.0 M Figure 11. Output Voltage versus Frequency VCC = +15 V VEE = -15 V VCM = 0 V DVCM = 1.5 V TA = -55 to +125C 60 - ADM + DVCM 20 CMR = 20 Log 100 DVO DVCM DVO x ADM 1.0 k 10 k f, FREQUENCY (Hz) 100 k 120 80 -PSR - ADM + 60 40 I, SC OUTPUT SHORT CIRCUIT CURRENT (mA) Source 80 Sink 60 VCC = +15 V VEE = -15 V VID = 1.0 V 20 -9.0 -3.0 0 3.0 VO, OUTPUT VOLTAGE (V) DVO 20 PSR = 20 Log DVO/ADM DVCC 100 1.0 k 10 k f, FREQUENCY (Hz) 100 k 1.0 M Figure 13. Power Supply Rejection versus Frequency Over Temperature 100 40 VCC VEE 0 10 1.0 M TA = -55 to +125C VCC = +15 V VEE = -15 V DVCC = 1.5 V +PSR 100 Figure 12. Common Mode Rejection versus Frequency Over Temperature I, SC OUTPUT SHORT CIRCUIT CURRENT (mA) 100 k Figure 10. Output Saturation Voltage versus Load Current 80 0 -15 10 k f, FREQUENCY (Hz) 100 0 10 20 IL, LOAD CURRENT (mA) 120 40 24 0 1.0 k 20 PSR, POWER SUPPLY REJECTION (dB) CMR, COMMON MODE REJECTION (dB) V sat , OUTPUT SATURATION VOLTAGE (V) MC33178, MC33179 9.0 15 100 90 VCC = +15 V VEE = -15 V VID = 1.0 V RL < 10 W Sink 80 Source 70 60 50 -55 -25 0 25 50 75 100 TA, AMBIENT TEMPERATURE (C) Figure 14. Output Short Circuit Current versus Output Voltage Figure 15. Output Short Circuit Current versus Temperature http://onsemi.com 7 125 1.15 625 SR, SLEW RATE (NORMALIZED) TA = +125C 500 375 TA = +25C 250 TA = -55C 125 0 0 2.0 4.0 6.0 8.0 10 12 14 VCC, |VEE| , SUPPLY VOLTAGE (V) 16 1.10 1.05 1.00 0.95 0.90 - DVin 0.75 -55 -25 0 25 50 75 TA, AMBIENT TEMPERATURE (C) 8.0 6.0 0 -55 VCC = +15 V VEE = -15 V f = 100 kHz RL = 600 W CL = 0 pF -25 100 30 140 10 180 0 VCC = +15 V VEE = -15 V RL = 600 W TA = 25C CL = 0 pF -20 -30 30 20 0 -10 1A 1B 2A -20 1A) Phase V =18 V, V = -18 V CC EE -30 2A) Phase VCC 1.5 V, VEE = -1.5 V 1B) Gain V = 18 V, V = -18 V -40 2B) Gain VCC = 1.5 V, VEE = -1.5 V CC EE -50 100 k 1.0 M 100 120 140 160 180 2B 200 220 240 260 10 M 220 240 260 280 100 M 1.0 M 10 M f, FREQUENCY (Hz) 15 Am, OPEN LOOP GAIN MARGIN (dB) 40 200 Figure 19. Voltage Gain and Phase versus Frequency , PHASE (DEGREES) TA = 25C RL = CL = 0 pF 160 Gain -10 80 50 120 20 -50 100 k 125 100 Phase -40 0 25 50 75 TA, AMBIENT TEMPERATURE (C) 125 80 Figure 18. Gain Bandwidth Product versus Temperature 10 100 50 40 2.0 600 W 100 pF Figure 17. Normalized Slew Rate versus Temperature 10 4.0 + 0.80 18 AV , VOLTAGE GAIN (dB) GBW, GAIN BANDWIDTH PRODUCT (MHz) VO 0.85 Figure 16. Supply Current versus Supply Voltage with No Load A, V VOLTAGE GAIN (dB) VCC = +15 V VEE = -15 V DVin = 20 Vpp , EXCESS PHASE (DEGREES) A) I CC , SUPPLY CURRENT/AMPLIFIER ( MC33178, MC33179 280 100 M CL = 10 pF 12 CL = 100 pF 9.0 CL = 300 pF 6.0 3.0 0 -55 VCC = +15 V VEE = -15 V RL = 600 W -25 0 25 50 75 100 TA, AMBIENT TEMPERATURE (C) f, FREQUENCY (Hz) Figure 20. Voltage Gain and Phase versus Frequency Figure 21. Open Loop Gain Margin versus Temperature http://onsemi.com 8 125 MC33178, MC33179 12 10 CL = 100 pF 40 30 CL = 300 pF 20 VCC = +15 V VEE = -15 V RL = 600 W 10 0 -55 -25 60 50 VCC = +15 V VEE = -15 V RT = R1+R2 VO = 0 V TA = 25C 8.0 6.0 4.0 25 50 75 100 1.0 k 30 9.0 - 20 VO + 600 W CL 10 0 1.0 k 0 100 Drive Channel VCC = +15 V CEE = -15 V RL = 600 W TA = 25C 140 130 120 110 100 100 1.0 k 10 k 100 k CL, OUTPUT LOAD CAPACITANCE (pF) f, FREQUENCY (Hz) Figure 24. Open Loop Gain Margin and Phase Margin versus Output Load Capacitance Figure 25. Channel Separation versus Frequency 10 AV = 1000 1.0 AV = 100 0.1 0.01 10 1.0 M 500 VCC = +15 V VO = 2.0 Vpp VEE = -15 V TA = 25C RL = 600 W |Z|, O OUTPUT IMPEDANCE () THD, TOTAL HARMONIC DISTORTION (%) 10 CS, CHANNEL SEPARATION (dB) 40 Gain Margin m, PHASE MARGIN (DEGREES) 50 A, m OPEN LOOP GAIN MARGIN (dB) VCC = +15 V VEE = -15 V VO = 0 V 12 3.0 0 100 k 10 k 150 60 Vin 10 Figure 23. Phase Margin and Gain Margin versus Differential Source Resistance 18 6.0 VO + RT, DIFFERENTIAL SOURCE RESISTANCE (W) Figure 22. Phase Margin versus Temperature 15 Phase Margin - R2 TA, AMBIENT TEMPERATURE (C) Phase Margin 30 Vin 0 100 125 40 20 R1 2.0 0 Gain Margin m, PHASE MARGIN (DEGREES) CL = 10 pF 50 A, m GAIN MARGIN (dB) m , PHASE MARGIN (DEGREES) 60 AV = 10 AV = 1.0 400 300 VCC = +15 V VEE = -15 V VO = 0 V TA = 25C 1. AV = 1.0 2. AV = 10 3. AV = 100 4. AV = 1000 200 100 3 2 1 4 100 1.0 k 10 k 0 1.0 k 100 k f, FREQUENCY (Hz) Figure 26. Total Harmonic Distortion versus Frequency 10 k 100 k f, FREQUENCY (Hz) 1.0 M Figure 27. Output Impedance versus Frequency http://onsemi.com 9 10 M 20 Hz i, () n INPUT REFERRED NOISE CURRENT pA/ e, nV/ Hz n INPUT REFERRED NOISE VOLTAGE () MC33178, MC33179 Input Noise Voltage Test Circuit + VO - 18 16 14 12 10 8.0 6.0 4.0 2.0 0 10 VCC = +15 V VEE = -15 V TA = 25C 100 1.0 k f, FREQUENCY (Hz) 10 k 10 k 0.5 Input Noise Current Test Circuit 0.4 + RS - VO 0.3 (RS = 10 kW) 0.2 0.1 0 10 Figure 28. Input Referred Noise Voltage versus Frequency VCC = +15 V VEE = -15 V TA = 25C 100 1.0 k f, FREQUENCY (Hz) 10 k 100 k Figure 29. Input Referred Noise Current versus Frequency 100 70 V O, OUTPUT VOLTAGE (5.0 V/DIV) 80 VCC = +15 V VEE = -15 V TA = 25C 60 50 RL = 600 W RL = 2.0 kW 40 30 20 10 0 10 100 1.0 k CL, LOAD CAPACITANCE (pF) 10 k VCC = +15 V VEE = -15 V AV = +1.0 RL = 600 W CL = 100 pF TA = 25C t, TIME (2.0 ms/DIV) Figure 30. Percent Overshoot versus Load Capacitance Figure 31. Non-inverting Amplifier Slew Rate VCC = +15 V VEE = -15 V AV = +1.0 RL = 600 W CL = 100 pF TA = 25C V O, OUTPUT VOLTAGE (5.0 V/DIV) VCC = +15 V VEE = -15 V AV = +1.0 RL = 600 W CL = 100 pF TA = 25C V O, OUTPUT VOLTAGE (50 mV/DIV) PERCENT OVERSHOOT (%) 90 t, TIME (5.0 ms/DIV) t, TIME (2.0 ns/DIV) Figure 32. Small Signal Transient Response Figure 33. Large Signal Transient Response http://onsemi.com 10 MC33178, MC33179 10 k A1 To Receiver - 10 k + 10 k 1.0 mF 200 k 120 k From Microphone 2.0 k - + 0.05 mF 300 A2 820 Tip VR 1N4678 Phone Line 10 k Ring 10 k - + A3 VR Figure 34. Telephone Line Interface Circuit APPLICATION INFORMATION MC33179 (quad op amp). Shorting more than one amplifier could easily exceed the junction temperature to the extent of causing permanent damage. This unique device uses a boosted output stage to combine a high output current with a drain current lower than similar bipolar input op amps. Its 60 phase margin and 15 dB gain margin ensure stability with up to 1000 pF of load capacitance (see Figure 24). The ability to drive a minimum 600 W load makes it particularly suitable for telecom applications. Note that in the sample circuit in Figure 34 both A2 and A3 are driving equivalent loads of approximately 600 W . The low input offset voltage and moderately high slew rate and gain bandwidth product make it attractive for a variety of other applications. For example, although it is not single supply (the common mode input range does not include ground), it is specified at +5.0 V with a typical common mode rejection of 110 dB. This makes it an excellent choice for use with digital circuits. The high common mode rejection, which is stable over temperature, coupled with a low noise figure and low distortion, is an ideal op amp for audio circuits. The output stage of the op amp is current limited and therefore has a certain amount of protection in the event of a short circuit. However, because of its high current output, it is especially important not to allow the device to exceed the maximum junction temperature, particularly with the Stability As usual with most high frequency amplifiers, proper lead dress, component placement, and PC board layout should be exercised for optimum frequency performance. For example, long unshielded input or output leads may result in unwanted input/output coupling. In order to preserve the relatively low input capacitance associated with these amplifiers, resistors connected to the inputs should be immediately adjacent to the input pin to minimize additional stray input capacitance. This not only minimizes the input pole frequency for optimum frequency response, but also minimizes extraneous "pick up" at this node. Supplying decoupling with adequate capacitance immediately adjacent to the supply pin is also important, particularly over temperature, since many types of decoupling capacitors exhibit great impedance changes over temperature. Additional stability problems can be caused by high load capacitances and/or a high source resistance. Simple compensation schemes can be used to alleviate these effects. http://onsemi.com 11 MC33178, MC33179 For moderately high capacitive loads (500 pF < CL < 1500 pF) the addition of a compensation resistor on the order of 20 W between the output and the feedback loop will help to decrease miller loop oscillation (see Figure 36). For high capacitive loads (CL > 1500 pF), a combined compensation scheme should be used (see Figure 37). Both the compensation resistor and the compensation capacitor affect the transient response and can be calculated for optimum performance. The value of CC can be calculated using Equation 1. The Equation to calculate RC is as follows: If a high source of resistance is used (R1 > 1.0 kW), a compensation capacitor equal to or greater than the input capacitance of the op amp (10 pF) placed across the feedback resistor (see Figure 35) can be used to neutralize that pole and prevent outer loop oscillation. Since the closed loop transient response will be a function of that capacitance, it is important to choose the optimum value for that capacitor. This can be determined by the following Equation: CC + (1 ) [R1R2])2 CL (ZOR2) (1) RC + ZO where: ZO is the output impedance of the op amp. (2) R1R2 R2 R2 CC - - + R1 + R1 ZL CL Figure 35. Compensation for High Source Impedance Figure 36. Compensation Circuit for Moderate Capacitive Loads R2 CC - R1 RC RC + CL Figure 37. Compensation Circuit for High Capacitive Loads http://onsemi.com 12 MC33178, MC33179 PACKAGE DIMENSIONS PDIP-8 P SUFFIX CASE 626-05 ISSUE L 8 NOTES: 1. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 2. PACKAGE CONTOUR OPTIONAL (ROUND OR SQUARE CORNERS). 3. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5 -B- 1 4 DIM A B C D F G H J K L M N F -A- NOTE 2 L C J -T- MILLIMETERS MIN MAX 9.40 10.16 6.10 6.60 3.94 4.45 0.38 0.51 1.02 1.78 2.54 BSC 0.76 1.27 0.20 0.30 2.92 3.43 7.62 BSC --- 10_ 0.76 1.01 INCHES MIN MAX 0.370 0.400 0.240 0.260 0.155 0.175 0.015 0.020 0.040 0.070 0.100 BSC 0.030 0.050 0.008 0.012 0.115 0.135 0.300 BSC --- 10_ 0.030 0.040 N SEATING PLANE D M K G H 0.13 (0.005) M T A M B M Micro8 DM SUFFIX CASE 846A-02 ISSUE F NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. 846A-01 OBSOLETE, NEW STANDARD 846A-02. -A- -B- K PIN 1 ID G D 8 PL 0.08 (0.003) M T B S A S SEATING -T- PLANE 0.038 (0.0015) C H L J http://onsemi.com 13 DIM A B C D G H J K L MILLIMETERS MIN MAX 2.90 3.10 2.90 3.10 --- 1.10 0.25 0.40 0.65 BSC 0.05 0.15 0.13 0.23 4.75 5.05 0.40 0.70 INCHES MIN MAX 0.114 0.122 0.114 0.122 --- 0.043 0.010 0.016 0.026 BSC 0.002 0.006 0.005 0.009 0.187 0.199 0.016 0.028 MC33178, MC33179 SOIC-8 D SUFFIX CASE 751-07 ISSUE AE NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751-01 THRU 751-06 ARE OBSOLETE. NEW STANDARD IS 751-07. -X- A 8 5 S B 1 0.25 (0.010) M Y M 4 K -Y- G C N DIM A B C D G H J K M N S X 45 _ SEATING PLANE -Z- 0.10 (0.004) H D 0.25 (0.010) M Z Y S X M J S SOLDERING FOOTPRINT* 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm inches *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 14 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 MC33178, MC33179 PACKAGE DIMENSIONS PDIP-14 P SUFFIX CASE 646-06 ISSUE N 14 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. 8 B 1 7 A F DIM A B C D F G H J K L M N L N C -T- SEATING PLANE J K H D 14 PL G M 0.13 (0.005) INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.290 0.310 --- 10_ 0.015 0.039 MILLIMETERS MIN MAX 18.16 18.80 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.37 7.87 --- 10_ 0.38 1.01 M SOIC-14 D SUFFIX CASE 751A-03 ISSUE G NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. -A- 14 8 -B- 1 P 7 PL 0.25 (0.010) 7 G B M M F R X 45 _ C -T- SEATING PLANE D 14 PL 0.25 (0.010) M K M T B S A S http://onsemi.com 15 J DIM A B C D F G J K M P R MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019 MC33178, MC33179 PACKAGE DIMENSIONS TSSOP-14 DTB SUFFIX CASE 948G-01 ISSUE A 14X K REF 0.10 (0.004) 0.15 (0.006) T U M T U V S NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. S S N 2X 14 L/2 0.25 (0.010) 8 M B -U- L PIN 1 IDENT. F 7 1 0.15 (0.006) T U N S DETAIL E K A -V- EEE CCC CCC EEE CCC K1 J J1 SECTION N-N -W- C 0.10 (0.004) -T- SEATING PLANE D G H DETAIL E DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.50 0.60 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.020 0.024 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). 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