PH20100S
N-channel TrenchMOS standard level FET
Rev. 03 — 2 February 2009 Product data sheet
1. Product profile
1.1 General description
Standard level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product is designed and qualified for use in
computing, communications, consumer and industria l applications only.
1.2 Features and benefits
Higher operating power due to low
thermal resistance
Low conduction losses due to low
on-state resistance
Simple gate drive required due to low
gate charge current
1.3 Applications
DC-to-DC convertors Switched-mode power supplies
1.4 Quick reference data
Table 1. Quick reference
Symbol Parameter Conditions Min Typ Max Unit
VDS drain-source voltage Tj≥25 °C; Tj≤150 °C - - 100 V
IDdrain current Tmb =25°C; V
GS =10V;
see Figure 2; see Fi gure 1 - - 34.3 A
Ptot total power
dissipation Tmb = 25 °C - - 62.5 W
Dynamic characteristics
QGD gate-drain charge VGS =10V; I
D=20A;
VDS =50V; T
j=25°C;
see Figure 11
-8.9-nC
Sta tic chara cteristics
RDSon drain-source
on-state resistance VGS =10V; I
D=10A;
Tj= 25 °C; see Figure 8;
see Figure 9
- 1923mΩ
PH20100S_3 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 03 — 2 February 2009 2 of 12
NXP Semiconductors PH20100S
N-channel TrenchMOS st andard level FET
2. Pinning information
3. Ordering information
4. Limiting values
Table 2. Pinning information
Pin Symbol Description Simplified outline Graphic symbol
1S source
SOT669
(LFPAK)
2S source
3S source
4G gate
mb D mounting base; connected to
drain
mb
1234
S
D
G
mbb076
Table 3. Ordering information
Type number Package
Name Description Version
PH20100S LFPAK plastic single-ended surface-mounted package (LFPAK); 4 leads SOT669
Table 4. Limiting values
In accordance with the Absolute Maxi mum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VDS drain-source voltage Tj≥25 °C; Tj≤150 °C - 100 V
VGS gate-source voltage -20 20 V
IDdrain current VGS =10V; T
mb = 100 °C; see Figure 2 -21.6A
VGS =10V; T
mb =25°C; see Figure 2;
see Figure 1 -34.3A
IDM peak drain current tp≤10 µs; pulsed; Tmb =25°C; see Figure 1 -137A
Ptot total power dissipation Tmb =25°C - 62.5 W
Tstg storage temperature -55 150 °C
Tjjunction temperature -55 150 °C
Source-drain diode
ISsource current Tmb =25°C - 52 A
ISM peak source current tp≤10 µs; pulsed; Tmb =25°C - 137 A
Avalanche ruggedness
EDS(AL)S non-repetitive
drain-source avalanche
energy
VGS =10V; T
j(init) =25°C; I
D=12A; V
sup ≤100 V;
unclamped; tp=0.3ms -250mJ
PH20100S_3 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 03 — 2 February 2009 3 of 12
NXP Semiconductors PH20100S
N-channel TrenchMOS st andard level FET
Fig 1. Safe operating area; continuous an d peak drain currents as a fun ction of drain-source voltage
Fig 2. Normalized continuous drain current as a function of mounting base temper ature
003aaa406
10-1
1
10
102
103
1 10 102
10
3
V
DS (V)
ID
(A)
DC
100 ms
10 ms
Limit RDSon = VDS / ID
1 ms
tp = 10 μs
100 μs
Tmb (°C)
0 20015050 100
03aa23
40
80
120
Ider
(%)
0
PH20100S_3 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 03 — 2 February 2009 4 of 12
NXP Semiconductors PH20100S
N-channel TrenchMOS st andard level FET
5. Thermal characteristics
Table 5. Thermal characteristics
Symbol Parameter Conditions Min Typ Max Unit
Rth(j-mb) thermal resistance from
junction to mounting
base
see Figure 3 --2K/W
Fig 3. Transient thermal impedance from junction to mounting base as a function of pulse duration
003aaa407
10
-2
10
-1
1
10
10
-5
10
-4
10
-3
10
-2
10
-1
1
t
p
(s)
Z
th(j-mb)
(K/W)
single pulse
0.2
0.1
0.05
δ = 0.5
0.02
tp
T
P
t
tp
T
δ =
PH20100S_3 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 03 — 2 February 2009 5 of 12
NXP Semiconductors PH20100S
N-channel TrenchMOS st andard level FET
6. Characteristics
Table 6. Characteristics
Symbol Parameter Conditions Min Typ Max Unit
Static characteristics
V(BR)DSS drain-source
breakdown voltage ID=1mA; V
GS =0V; T
j=25°C 100 - - V
VGS(th) gate-source threshold
voltage ID=1mA; V
DS = VGS; Tj=25°C;
see Figure 7 234V
ID=1mA; V
DS = VGS; Tj= 150 °C;
see Figure 7 1.2 - - V
IDSS drain leakage current VDS =100V; V
GS =0V; T
j= 25 °C - 0.06 1 µA
VDS =100V; V
GS =0V; T
j= 150 °C - - 500 µA
IGSS gate leakage current VGS =20V; V
DS =0V; T
j= 25 °C - 2 100 nA
VGS =-20V; V
DS =0V; T
j= 25 °C - 2 100 nA
RDSon drain-source on-state
resistance VGS =10V; I
D=10A; T
j= 150 °C;
see Figure 8; see Figure 9 -4353mΩ
VGS =10V; I
D=10A; T
j=25°C;
see Figure 8; see Figure 9 -1923mΩ
Dynamic characteristics
QG(tot) total gate charge ID=20A; V
DS =50V; V
GS =10V;
Tj=25°C; see Figure 11 -39-nC
QGS gate-source charge - 6.9 - nC
QGD gate-drain charge - 8.9 - nC
Ciss input capacitance VDS =25V; V
GS = 0 V; f = 1 MHz;
Tj=25°C; see Figure 12 - 2264 - pF
Coss output capacitance - 290 - p F
Crss reverse transfer
capacitance - 111 - pF
td(on) turn-on delay time VDS =50V; R
L=5Ω; VGS =10V;
RG(ext) =4.7Ω; ID=10A; T
j=25°C -23-ns
trrise time - 15 - ns
td(off) turn-off delay time - 47 - ns
tffall time - 9.3 - ns
Source-drain diode
VSD source-drain voltage IS=10A; V
GS =0V; T
j=25°C;
see Figure 10 -0.81.2V
trr reverse recovery time IS=20A; dI
S/dt = -100 A/µs; VGS =0V;
VDS =25V; T
j=25°C -110-ns
PH20100S_3 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 03 — 2 February 2009 6 of 12
NXP Semiconductors PH20100S
N-channel TrenchMOS st andard level FET
Fig 4. Output characteristics: drain current as a
function of drain-source voltage; typical values Fig 5. Transfer characteristics: drain curren t as a
function of gate-source vo ltage; typical values
Fig 6. Sub-threshold drain current as a function of
gate-source voltage Fig 7. Gate-source threshold voltag e as a function of
junction temperature
003aaa408
0
10
20
30
40
01234
V
DS
(V)
I
D
(A)
V
GS
= 5.5 V
4.5 V
5 V
4.8 V
5.2 V
6 V
10 V
003aaa409
0
10
20
30
40
23456
V
GS
(V)
I
D
(A)
T
j
= 150 °C25 °C
03aa35
VGS (V)
0642
10−4
10−5
10−2
10−3
10−1
ID
(A)
10−6
min typ max
Tj (°C)
−60 180120060
03aa32
2
3
1
4
5
VGS(th)
(V)
0
max
typ
min
PH20100S_3 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 03 — 2 February 2009 7 of 12
NXP Semiconductors PH20100S
N-channel TrenchMOS st andard level FET
Fig 8. Drain-source on-state resistance as a function
of drain current; typical values F ig 9. Normalized drain-source on-state resistance
factor as a functio n o f jun ction temperature
Fig 10. Source current as a fun ction of source-d ra in
voltage; typical values Fig 11. G ate-source voltage as a function of gate
charge; typical values
003aaa410
10
20
30
40
50
60
0 10203040
I
D
(A)
R
DSon
(mΩ)
5.2 V
7 V
V
GS
= 5 V 5.5 V
10 V
6 V
03aa31
0
1
2
3
-60 0 60 120 180
Tj (°C)
a
003aaa412
0
10
20
30
40
0.2 0.4 0.6 0.8 1
V
SD
(V)
I
S
(A)
T
j
= 25 °C
150 °C
003aaa413
0
2
4
6
8
10
0 10203040
Q
G
(nC)
V
GS
(V)
PH20100S_3 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 03 — 2 February 2009 8 of 12
NXP Semiconductors PH20100S
N-channel TrenchMOS st andard level FET
Fig 12. Inp ut, ou tp ut an d reverse transfer capac itances as a function of drain-sou rce voltage; typical values
003aaa411
10
2
10
3
10
4
10
-1
1 10 10
2
V
DS
(V)
C
(pF)
C
iss
C
oss
C
rss
PH20100S_3 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 03 — 2 February 2009 9 of 12
NXP Semiconductors PH20100S
N-channel TrenchMOS st andard level FET
7. Package outline
Fig 13. Package outline SOT669 (LFPAK)
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT669 MO-235 04-10-13
06-03-16
0 2.5 5 mm
scale
e
E1
b
c2
A2
A2bcA e
UNIT
DIMENSIONS (mm are the original dimensions)
mm 1.10
0.95
A3
A1
0.15
0.00
1.20
1.01
0.50
0.35
b2
4.41
3.62
b3
2.2
2.0
b4
0.9
0.7
0.25
0.19
c2
0.30
0.24
4.10
3.80
6.2
5.8
H
1.3
0.8
L2
0.85
0.40
L
1.3
0.8
L1
8°
0°
wy
D(1)
5.0
4.8
E(1)
3.3
3.1
E1(1)
D1(1)
max
0.25 4.20 1.27 0.25 0.1
1234
mounting
base
D1
c
Plastic single-ended surface-mounted package (LFPAK); 4 leads SOT669
E
b2
b3
b4
HD
L2
L1
A
A
wM
C
C
X
1/2 e
yC
θ
θ
(A )
3
L
A
A1
detail X
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
PH20100S_3 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 03 — 2 February 2009 10 of 12
NXP Semiconductors PH20100S
N-channel TrenchMOS st andard level FET
8. Revision history
Table 7. Revision history
Document ID Release date Data sheet status Change notice Supersedes
PH20100S_3 20090202 Product data sheet - PH20100S_2
Modifications: •The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
•Legal texts have been adapted to the new company name where appropriate .
PH20100S_2
(9397 750 13698) 20040817 Product data sheet - PH20100S_1
PH20100S_1
(9397 750 12815) 20040305 Preliminary data sheet - -
PH20100S_3 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 03 — 2 February 2009 11 of 12
NXP Semiconductors PH20100S
N-channel TrenchMOS st andard level FET
9. Legal information
9.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product
status information is available on the Internet at URL http://www.nxp.com.
9.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warrant ies as to t he accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full da ta sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not b e relied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall pre va il.
9.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors d oes not give any represent ations or
warranties, expressed or impli ed, as to the accuracy or completeness of such
information and shall have no liability for th e co nsequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where f ailure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for il lustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Rati ngs System of I EC 60134) may cause perman ent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other co nditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may af fect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between inf ormation in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an of fer t o sell product s that is open for accept ance or the gr ant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
9.4 Trademarks
Notice: All refe renced brands, produc t names, service names and trademarks
are the property of their respective ow ners.
TrenchMOS — is a trademark of NXP B.V.
10. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to : salesaddresses@nxp.com
Document status [1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objecti ve specificat ion for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] dat a sheet Production This document contains the product specification.
NXP Semiconductors PH20100S
N-channel TrenchMOS st andard level FET
© NXP B.V. 2009. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 2 February 2009
Document identifier: PH20100S_3
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
11. Contents
1 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1
1.1 General description . . . . . . . . . . . . . . . . . . . . . .1
1.2 Features and benefits. . . . . . . . . . . . . . . . . . . . .1
1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
1.4 Quick reference data . . . . . . . . . . . . . . . . . . . . .1
2 Pinning information. . . . . . . . . . . . . . . . . . . . . . .2
3 Ordering information. . . . . . . . . . . . . . . . . . . . . .2
4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .2
5 Thermal characteristics . . . . . . . . . . . . . . . . . . .4
6 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . .5
7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . .9
8 Revision history. . . . . . . . . . . . . . . . . . . . . . . . .10
9 Legal information. . . . . . . . . . . . . . . . . . . . . . . .11
9.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . .11
9.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
9.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . .11
9.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .11
10 Contact information. . . . . . . . . . . . . . . . . . . . . .11
