FEATURES
Data Retention in the absence of power
· Automatic data protection during power
failure
· Data Retention over 10 years
· Unlimited write cycles
· Conventional SRAM write cycles
· Low power CMOS – only 225mW active
· Equal read/write cycle times
· +5V only read/write
· Operating voltage range +10%
· Direct replacement for 8K X 8 SRAM
or EPROM
· Standard 28 pin DIP JEDEC Pinout
Functional Description
The IM 1225Y–150 is a 65,536 bit, fully static NP
RAM organized as 8K X 8 using CMOS and an
internal lithium energy source.
This ‘NO POWER’ RAM has all the normal
characteristics of a CMOS static RAM with an impor-
tant benefit of data being retained in the absence of
power. Data retention current is so small that a
miniature lithium cell contained within the package
provides an energy source to preserve data.
Protection against data loss has also been
incorporated to maintain data integrity during power
on/off conditions.
The IM 1225Y–150 RAM can be directly used
in place of existing static RAMs. There is no limit to
the number of write cycles that can be executed and
no additional support circuitry is required for interface
to a microprocessor.
1 28
2 27
3 26
4 25
5 24
6 23
7 22
8 21
9 20
10 19
11 18
12 17
13 16
14 15
NC VCC
A12 WE
A7 NC
A6 A8
A5 A9
A4 A11
A3 OE
A2 A10
A1 CE
A0 I/O7
I/O0 I/O6
I/O1 I/O5
I/O2 I/O4
Gnd I/O3
PIN NAMES
NC No Connection
OE Output Enable
Gnd Ground
I/O0 – I/O7 Data in/ Data Out
Vcc Power Supply +5V
WE Write Enable
A0 – A12 Address Inputs
CE Chip Enable
Pin configuration
INNOVATIVE MICROTECHNOLOGY INC.Phone/Fax-440-322-8083.Website:www.innovativemicrotechnology.com
INNOVATIVE IM1225Y-150
8K X 8 Nonvolatile SRAM
Maximum Ratings
Operating Temperature….0oC to 70oC
Storage Temperature…….0oC to 70oC
Soldering Temperature
And Time………………….260oC for 10 sec
Supply Voltage……………....0V to 7.0V
Input Voltage………………-0.3V to 7.0V
Input/ Output Voltage…….-0.3V to Vcc
+ 0.3V
Power Dissipation…………1.0W
Parameter Symbol Min. Typ Max. Unit
Supply Voltage Vcc 4.5 5.0 5.5 V
Gnd 0 - 0 V
Input Voltage VIH 2.2 - Vcc
+0.3 V
VIL 0 - 0.8 V
Recommended D.C. Operating Conditions
WRITE MODE
The IM 1225Y-150 is in the write mode when-
ever CE and WE inputs are held low. The latter occur-
ring falling edge of either CE or WE determines the
start of a write cycle. A write is terminated by the ear-
lier rising edge of CE or WE. The address must be held
valid throughout the write cycle. WE must return to the
high state for a minimum recovery time (tWR) before an-
other Read or Write cycle can be initiated. CE or WE is
high during power on to protect memory after Vcc
reaches Vcc (min) but before the processor stabilizes.
DATA RETENTION
The IM 1225Y-150 provides full functional ca-
pability for Vcc greater than 4.5V and write protects at
4.25V. Data is retained in the absence of Vcc without
any additional support circuitry. The SRAM constantly
monitors Vcc. The moment Vcc decays, the RAM au-
tomatically write protects itself. All inputs to the RAM
become “don’t care” and all outputs are in high imped-
ance-state. As Vcc falls below approximately 3.0V the
power switching circuit connects the lithium energy
source to RAM to retain data. During power-on, when
Vcc rises above approximately 3.0V the power switch-
ing circuit connects external Vcc to the RAM and dis-
connects the lithium energy source. Normal RAM op-
eration can resume after Vcc becomes greater than
4.5V.
READ MODE
The IM 1225Y-150 performs a read cycle when-
ever WE high and CE low. The unique address speci-
fied by the 13 address inputs A0-A12 defines which of
the 8,192 bytes of data is to be accessed. Valid data
will be available to the eight data output drivers within
access time tACC after the last address input is stable,
provided that CE and OE access times are satisfied. If
OE or CE access times are not satisfied, data access
will be measured from the limiting parameter (tCO or tOE),
rather than address.The state of the eight data I/O lines
is controlled by the OE and CE control signals. The
data lines may be in an indeterminate state between
tOH and tAA but the data lines will always have valid data
at tAA.
INNOVATIVE IM1225Y-150
8K X 8 Nonvolatile SRAM
Notes
1. Typical values are measured at Ta = 25o
I
C and Vcc = 5V
Capacitance
Parameter Description Test conditons Min. Typ Max Unit
CADD Address capacitance VADD = 0V - 3 5 pF
CIInput capacitance Vi =0V - 5 6 pF
CI/O I/O capacitance VIO = 0V - 6 7 pF
DC Electrical Characeteristics
Parameter Description Test conditons Min. Typ Max Unit
IIL Input Leakage Vi = 0 to Vcc -1 - 1
IOCA Average operating Current CE = VIH -45 80
CE = VIH,IIO = 0mA - 1 3 mA
Ivcc Operating Supply current CE = VIL, IIO = 0mA - - 45 mA
ILO Output Leakage CE = VIH or Vcc -1 1 µA
Vi/o = Gnd to Vcc
VOH High level output voltage IOH = - 1.0 mA 2.4 Vcc - 0.1 - V
VOL Low level output voltage IOL = 2.1 mA - 0 .2 0.4 V
VTP Write protection voltage - 4.25 4.37 4.49 V
µA
µA
INNOVATIVE IM1225Y-150
8K X 8 Nonvolatile SRAM
Switching Characteristics over the operating range
Parameter Description Min Max Unit
tRC Read cycle time 150 - ns
tACC Address access time - 150 ns
tOE Output enable access time - 60 ns
tCO CE to output valid - 150 ns
tCOE OE or CE to output valid 5 - ns
tOD Output High Z from Deselection - 40 ns
tOH Output hold from adds change 5 - ns
tWC Write cycle time 150 - ns
tAW Address setup time 0 - ns
tWP Write pulse-width 70 - ns
tWR Write recovery time 10 - ns
tODW Output High Z from WE 35 ns
tOEW Output Active from WE 5 - ns
tDS Input data setup time 50 - ns
tDH Input data hold time 10 - ns
INNOVATIVE IM1225Y-150
8K X 8 Nonvolatile SRAM
VIL VIL
VIH VIH
VIH
VIL
VIL VIL
tAW
tWP tWR
tOEW
High
Impedance
tDS tDH
VIL
VIL
VIH
VIH Data In
Stable
DIN
CE
VIH VIH
VIL
VIH
VIH VIL
VIH
tCOE
tCOE
tOD
VOL
VOH
VOH
VOL
DOUT OUTPUT
DATA VALID
VIL VIL
OE
tCO
tRC
tWC
ADDRESS
tOE
READ CYCLE
WRITE CYCLE 1
VIL
tODW
DOUT
WE
VIH
tOD
CE
Address tACC tOH
INNOVATIVE IM1225Y-150
8K X 8 Nonvolatile SRAM
4.75V —————————————————————————————————————————————————
tFtR
3.2V ——————————————————————————————————————————————————
tPD tREC
LI Cell
Leakage Current Data Retention Time
tDR
Notes:
1. WE is to be high during read cycle.
2. During write cycle that is controlled by CE, output buffer is in high impedance state irrespective of whether OE
is high or low level.
3. During write cycle that is controlled by WE, output buffer is in high impedance state if OE is high.
VIH VIL VIL VIH
VIL VIL
tODW
tCOE
tDS tDH
VIL
VIL
VIH
VIH Data In
Stable
DIN
VIL VIL
VIH VIH
tAW tWP
tWR2
DOUT
WE
CE
ADDRESSES
WRITE CYCLE 2
FIG. D POWER – DOWN/ POWER –ON CONDITION
tWC
INNOVATIVE IM1225Y-150
8K X 8 Nonvolatile SRAM
J
H
A
C
G E
D
DIM IN INCHES MIN. MAX.
A 1.52 1.54
B 0.695 0.72
C 0.395 0.415
D 0.1 0.13
E 0.015 0.021
F 0.12 0.16
G 0.09 0.11
H 0.59 0.63
J 0.008 0.012
INNOVATIVE
IM 1225Y - 150
NO POWER SRAM
mm - yy
B
F
INNOVATIVE IM1225Y-150
8K X 8 Nonvolatile SRAM
