5-427
FAST AND LS TTL DATA
QUAD 2-INPUT MULTIPLEXER
WITH 3-STATE OUTPUTS
The LSTTL/MSI SN54/74LS257B and the SN54 /74LS258B are Quad
2-Input Multiplexers with 3-state outputs. Four bits of data from two sources
can be selected using a Common Data Select input. The four outputs present
the selected data in true (non-inverted) form. The outputs may be switched to
a high impedance state with a HIGH on the common Output Enable (EO) In-
put, allowing the outputs to interface directly with bus oriented systems. It is
fabricated with the Schottky barrier diode process for high speed and is com-
pletely compatible with all Motorola TTL families.
Schottky Process For High Speed
Multiplexer Expansion By Tying Outputs Together
Non-Inverting 3-State Outputs
Input Clamp Diodes Limit High Speed Termination Effects
Special Circuitry Ensures Glitch Free Multiplexing
ESD > 3500 Volts
   
 

CONNECTION DIAGRAM DIP (TOP VIEW)
SN54/74LS257B
SN54/74LS258B
 
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   
 

NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
SN54/74LS257B
SN54/74LS258B
QUAD 2-INPUT MULTIPLEXER
WITH 3-STATE OUTPUTS
LOW POWER SCHOTTKY
ORDERING INFORMATION
SN54LSXXXJ Ceramic
SN74LSXXXN Plastic
SN74LSXXXD SOIC
J SUFFIX
CERAMIC
CASE 620-09
N SUFFIX
PLASTIC
CASE 648-08
16 1
16
1
16 1
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SOIC
CASE 751B-03
5-428
FAST AND LS TTL DATA
SN54/74LS257B
D
SN54/74LS258B
LOGIC DIAGRAMS
SN54/74LS257B
SN54/74LS258B
 
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5-429
FAST AND LS TTL DATA
SN54/74LS257B
D
SN54/74LS258B
FUNCTIONAL DESCRIPTION
The LS257B and LS258B are Quad 2-Input Multiplexers
with 3-state outputs. They select four bits of data from two
sources each under control of a Common Data Select Input.
When the Select Input is LOW , the I0 inputs are selected and
when Select is HIGH, the I1 inputs are selected. The data on
the selected inputs appears at the outputs in true (non-
inverted) form for the LS257B and in the inverted form for the
LS258B.
The LS257B and LS258B are the logic implementation of a
4-pole, 2-position switch where the position of the switch is
determined by the logic levels supplied to the Select Input. The
logic equations for the outputs are shown below:
LS257B
Za = E0 (I1a S + I0a S) Zb = E0 (I1b S + I0b S)
Zc = E0 (I1c S + I0c S) Zd = E0 (I1d S + I0d S)
When the Output Enable Input (E0) is HIGH, the outputs are
forced to a high impedance “off” state. If the outputs are tied
together, all but one device must be in the high impedance
state to avoid high currents that would exceed the maximum
ratings. Designers should ensure that Output Enable signals
to 3-state devices whose outputs are tied together are
designed so there is no overlap.
LS258B
Za = E0 (I1a S + I0a S) Zb = E0 (I1b S + I0b S)
Zc = E0 (I1c S + I0c S) Zd = E0 (I1d S + I0d S)
TRUTH TABLE
OUTPUT
ENABLE SELECT
INPUT DATA
INPUTS OUTPUTS
LS257B OUTPUTS
LS258B
EOS I0I1Z Z
H X X X (Z) (Z)
L H X L L H
L H X H H L
L L L X L H
L L H X H L
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
(Z) = High Impedance (off)
GUARANTEED OPERATING RANGES
Symbol Parameter Min Typ Max Unit
VCC Supply Voltage 54
74 4.5
4.75 5.0
5.0 5.5
5.25 V
TAOperating Ambient Temperature Range 54
74 55
025
25 125
70 °C
IOH Output Current — High 54
74 1.0
2.6 mA
IOL Output Current — Low 54
74 12
24 mA
5-430
FAST AND LS TTL DATA
SN54/74LS257B
D
SN54/74LS258B
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Symbol
Parameter
Limits
Unit
Test Conditions
Symbol
Parameter
Min Typ Max
Unit
Test Conditions
VIH Input HIGH Voltage 2.0 V Guaranteed Input HIGH Voltage for
All Inputs
VIL
Input LOW Voltage
54 0.7
V
Guaranteed Input LOW Voltage for
All Inputs
VIL
Input LOW Voltage
74 0.8
V
Guaranteed Input LOW Voltage for
All Inputs
VIK Input Clamp Diode Voltage 0.65 1.5 V VCC = MIN, IIN = –18 mA
VOH
Output HIGH Voltage
54 2.4 3.4 V
V
CC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table
VOH
Output HIGH Voltage
74 2.4 3.1 V
VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table
VOL
Output LOW Voltage
54, 74 0.25 0.4 V IOL = 12 mA
VCC = VCC MIN,
VIN = VIL or VIH
per Truth Table
VOL
Output LOW Voltage
74 0.35 0.5 V IOL = 24 mA
VIN = VIL or VIH
per Truth Table
IOZH Output Off Current — HIGH 20 µA VCC = MAX, VOUT = 2.7 V
IOZL Output Off Current — LOW 20 µA VCC = MAX, VOUT = 0.4 V
I
IH
Input HIGH Current
Other Inputs
S Inputs 20
40 µA VCC = MAX, VIN = 2.7 V
IIH
Other Inputs
S Inputs 0.1
0.2 mA VCC = MAX, VIN = 7.0 V
IIL Input LOW Current
All Inputs 0.4 mA VCC = MAX, VIN = 0.4 V
IOS Short Circuit Current (Note 1) 30 130 mA VCC = MAX
ICC
Power Supply Current
Total, Output HIGH LS257B
LS258B 10
9.0 mA
VCC = MAX
ICC
Total, Output LOW LS257B
LS258B 16
14 mA
VCC = MAX
Total, Output 3-State LS257B
LS258B 19
16 mA
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V) See SN54LS251 for Waveforms
Symbol
Parameter
Limits
Unit
Test Conditions
Symbol
Parameter
Min Typ Max
Unit
Test Conditions
tPLH
tPHL Propagation Delay, Data to Output 10
12 13
15 ns Figures 1 & 2
tPLH
tPHL Propagation Delay, Select to Output 14
14 21
21 ns Figures 1 & 2
tPZH Output Enable Time to HIGH Level 20 25 ns Figures 4 & 5
C
tPZL Output Enable Time to LOW Level 20 25 ns Figures 3 & 5
tPLZ Output Disable Time to LOW Level 16 25 ns Figures 3 & 5
C
tPHZ Output Disable Time from HIGH Level 18 25 ns Figures 4 & 5
5-431
FAST AND LS TTL DATA
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5-432
FAST AND LS TTL DATA
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