87C51/87C52T2 8-Bit CMOS Microcontrollers PRELIMINARY DISTINCTIVE CHARACTERISTICS Software- and pin-compatible with 80C51 Beneficial for prototyping and initial production All 80C51BH and 80C52T2 features retained Flashrite/ EPROM programming Two-level Program Memory Lock 32-Byte Encryption Array In-Circuit Test Mode facilitates testing RAM EPROM (bytes) (bytes) 87C51 128 4K 87C52T2 256 8K 87C51 = User-programmable 80C51BH 87C52T2 = User-programmable 80C52T2 cl GENERAL DESCRIPTION The 87051 and 87C52T2 are CMOS EPROM versions of the 80C51BH and 80C52T2, respectively. The 87C51 includes 4K bytes of on-chip EPROM, and the 87C52T2 includes 8K bytes of EPROM. These user-programmable products are software- and pin- compatible with their ROM-based counterparts. All of the 80C52BH and 80C52T2 features are retained. For more information consult th 80C32T2 data sheet Additionally, several new features are offered on the EPROM versions. The 87C51 and 87C52T2 EPROM array support the Flashrite programming algorithm that allows a 4K-byte EPROM array to be programmed in approximately 12 seconds. A two-level programmable lock structure prevents externally fetched code from accessing internal Program Memory and can disable EPROM verification and programming. A a oye Encryption Array can be used to cone. during EPROM verification. REFERENCE COUNTERS AT | ee * aK/BK BYTES 128 BYTES/I96 BYTES TMERIEVENT TIMING COUNTERS 80051 _ CPU K PROGRAMMABLE 64K-8YTE BUS SERIAL PORT EXPANSION PROGRAMMABLE 1/0 + FULL DUPLEX CONTROL UART + SYNCHRONOUS SHIFTER INTERRUPTS i INTERRUPTS CONTROL PARALLEL PORTS SERIAL SERIAL ADORESS DATA BUS IN OUT AND VO PINS BD007254 Publication # Rev, Amendment 09743 B 87C51/87C52T2 Issue Date: October 1989 7-13CONNECTION DIAGRAMS Top View DIP tcc P10 e Y 407) Voc pur Coy 2 30 [F) Poo AD, px2 (3 3a [J Por Ad, Ps Poa p13 C4 37] Po.2 Ad, pra C5 36] Poa Ady P16 POS prs C6 35 [7] Poa AD, PL? P06 pis C17 34) Pos ADs RST po7 p78 33 [) P06 Ad, _ ast (] 9 32] P07 AD, P3.0 EANpp axp p30 [7] 10 31 [7] EAVpp NC Ves rxo p31 (11 30 [7] ALE/PROG INF, p32 (J 12 20") PSEh P31 ALE/PROG WWF, pss Co] 19 20 [7] par agg P32 PSEN Tg 63.4 [J 14 27 7) P28 Aig P33 P27 T, pas (715 26 {7} P25 agg WA eas [7] 18 25 [7] P24 Ay P34 P2.6 RG ps7 (17 24 [7] Pas Ay P35 P25 XTAL2 [] 18 23 [7] P22 Aj XTAL, (C] 19 22 [7) Pat Ap Vss [7] 20 21 [TJ P20 Ay CD005553 D010873 PLCC P18 EA/Vpp Vss ALE/PROG P2.7 P26 P2.5 Be ZZ 4 ie2earea cp009442 Notes: Pin 1 is marked for orientation. NC pins on the PLCC and LCC packages have been utilized as additional Voc and Vss connections to improve noise immunity. It is recommended that these pins (1, 23, and 37) be connected appropriately; however, they may be left floating to insure second source compatibility. 7-14 87C51/87C52T2LOGIC SYMBOL | (vee |" XTAL, i _ ca g ae Ve- % facets _ a _ TC / fs XTAL2 |{ zr rc |= ]} __ _ EA/Vpp ~1 nae | PSEN ~_ a ~ & ALE/PROG ~ a 2 nae __ RXD e1f romana _ -| = _- Rf, - | -] j- | | 8 =f itt; | oo i eo ES rc { Tt) - = Wr a e y ~_ -f be LS$001326 ORDERING INFORMATION Commodity Products AMD commodity products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of: a. Temperature Range b. Package Type c. Device Number d. Speed Option e. Optional Processing DB 87651 [L, OPTIONAL PROCESSING Blank = Standard processing d. SPEED OPTION Blank = 3.5 to 12 MHz -1=3.5 to 16 MHz . DEVICE NUMBER/DESCRIPTION 87C51/87C52T2 8-Bit CMOS Microcontrotlers 87C51 4K EPROM 87C52T2 8K EPROM a s PACKAGE TYPE D = 40-Pin Ceramic DIP (CDV040) R = 44-Pin Ceramic Leadless Chip Carrier (CLV044) P = 40-Pin Plastic DIP (PD 040) N = 44-Pin Plastic Leadiess Chip Carrier (PL 044) a. TEMPERATURE RANGE Blank = Commercial (0 to + 70C) | = Industrial (-40 to +85C) Valid Combinations Valid Combinations Valid Combinations list configurations planned to be 87051 supported in volume for this device. Consult the local AMD DORPN 8751-4 sales office to confirm availability of specific valid 1D, IR, iP, IN 87C52T2 combinations, to check on newly released combinations, and B7CSETOT to obtain additional data on AMD's standard military grade products. 87C51/87C52T2 7-15PIN DESCRIPTION Port 0 (Bidirectional; Open Drain) Port 0 is an open-drain I/O port. Port 0 pins that have is written to them float, and in that state can be used as high- impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external Program and Data Memory. In this application it uses strong internal pullups when emitting 1s. Port 0 also outputs the code bytes during program verification in the 87C51/87C52T2. External pullups are required during program verification. Port 1 (Bidirectional) Port 1 is an 8-bit bidirectional {/O port with internal pullups. The Port 1 output buffers can sink/source four LS TTL inputs. Port 1 pins that have 1s written to them are pulled High by the internal pullups and can be used as inputs white in this state. As inputs, Port 1 pins that are externally being pulled Low will source current (lj, on the data sheet) because of the internal pullups. Port 1 also receives the low-order address bytes during program verification. Port 2. (Bidirectional) Port 2 is an 8-bit bidirectional |/O port with internal pullups. The Port 2 output buffers can sink/source four LS TTL inputs. Port 2 pins having 1s written to them are pulled High by the internal pullups and can be used as inputs while in this state. As inputs, Port 2 pins externally being pulled Low will source current (Ij_) because of internal pullups. Port 2 emits the high-order address byte during fetches from external Program Memory and during accesses to external Oata Memory that use 16-bit addresses (MOVX @DPTR). In this application it uses strong internal pullups when emitting 1s. During accesses to external Data Memory that use 8-bit addresses (MOVX @Ri), Port 2 emits the contents of the P2 Special Function register. Port 2 also receives the high-order address bits during the programming of the EPROM and during program verification of the EPROM, as well as some control signals. Port 3 (Bidirectional) Port 3 is an 8-bit bidirectional 1/O port with internal pullups. The Port 3 output buffers can sink/source four LS TTL inputs. Port 3 pins having 1s written to them are pulled High by the internal pullups and can be used as inputs while in this state. As inputs, Port 3 pins externally being pulled Low will source current (Ij) because of the pullups. Port 3 also receives some control signals for EPROM programming and program verification. Port 3 also serves the functions of various special features as listed below: Port Pin Alternate Function P30 RxD (Serial input Port) P34 TxD (Serial Output Port) P32 INTo (External Interrupt 0) P33 INT; (External Interrupt 1) P34 To (Timer 0 External Input) P35 Ty (Timer 1 xternal Input) P36 WR (External Data Memory Write Strobe) P37 RD (External Data Memory Read Strobe) RST Reset (input; Active High) This pin is used to reset the device when held High for two machine cycles while the oscillator is running. A small internal resistor permits power-on reset using only a capacitor connected to Vcc. ALE/PROG Address Latch Enable/Program Pulse (Input/Output) Address Latch Enable is the output pulse for latching the low byte of the address during accesses to external memory. ALE can drive eight LS TTL inputs. In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, allowing use for external-timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory. This pin also accepts the program pulse input (PROG) when programming the EPROM. PSEN Program Store Enable (Output; Active Low) PSEN is the read strobe to external Program Memory. PSEN can drive eight LS TTL inputs. When the device is executing code from an external program memory, PSEN is activated twice each machine cycleexcept that two PSEN activations are skipped during each access to external Data Memory. PSEN is not activated during fetches from internal Program Memory. EA/Vpp__ External Access Enable/Programming Voltage (Input; Active Low) EA must be externally held Low to enable the device to fetch code from external Program Memory locations 0000H to OFFFH. If EA is held High, the 87C51/87C52T2 executes from internal Program Memory unless the program counter contains an address greater than OFFFH. This pin also receives the 12.75-V programming supply voltage during programming of the EPROM. XTAL; Crystal (Input) Input to the inverting-oscillator amplifier, and input to the internal clock-generator circuits. XTAL2 Crystal (Output) Output of the inverting-oscillator amplifier. Vcc Power Supply Power supply during normal, idle, and power-down operations. Vss__ Circuit Ground 7-16 87C051/87C52T2PROGRAMMING The 87C51/87C52T2 can be programmed with the Flashrite algorithm. It differs from other methods in the value used for Vpp (programming supply voltage) and in the width and number of the ALE/PROG pulses. To program the EPROM, either the internal or external oscillator must be running between 4 and 6 MHz, since the internal bus is used to transfer address and program data to the appropriate internal registers. Table 1 shows the various EPROM programming modes. TABLE 1. EPROM PROGRAMMING MODES FOR THE 87C51/87C52T2 Mode RST PSEN ALE/PROG EA/Vpp P2,7 P2.6 P3.7 P3.6 Program Code H L L Vpp H L H H Verify Code H L H Vppx L L H H Pgm Encryption Table H L L* Vpp H L H L Pgm Lock Bit 1 H L L* Vep H H H H Pgm Lock Bit 2 H L L* Vpp H H L L Read Silicon Signature H L H H L L L L Key: H = Logic High for that pin L = Logic Low for that pin Vpp = 12.75 V +0.25 V Veco =5 V 10% during programming and verification 2.0 V< Vppx < 13.0 V ALE/PROG receives 25 programming pulses while Vpp is held at 12.75 V. Each programming pulse is low for 100 us (10% ys) and high for a minimum of 10 ys. Programming The programming configuration is shown in Figure 1. The address of the EPROM location to be programmed is applied to Ports 1 and 2 as shown in the figure. The programming configuration of the 87C52T2 is identical except that P2.4 is also used as an address input. The code byte to be pro- grammed into that location is applied to Port 0. Once RST, PSEN, Port 2, and Port 3 are held to the levels indicated in Figure 1, ALE/PROG is pulsed low 25 times as shown in Figure 2. The maximum voltage applied to the EA/Vpp pin must not exceed 13 V at any time as specified for Vpp. Even a slight spike can cause permanent damage to the device. The Vpp source should thus be well regulated and glitch-free. When programming, a 0.1 uF capacitor is required across Vpp and ground to suppress spurious transients which may dam- age the device. ADDR Py QO00H-OFFFH Poo-Pag Vid Te P36 87C51 Par Va _ oH Pos Vid ___ Paz XTAL, s-emz [] FO C= wat, ss Yoo ALE [4 PROG (25, 100 us pulses to GND) Ea }o Vpp = 12.75 V trst [* Vin PSEN TC004691 Figure 1. 87C51 Programming Configuration 87C51/87C52T225 PULSES ALE/PROG: | |--- SS" WLU 100 ps 10 us M | } ems \ _ ome 1 WF025700 Figure 2. PROG Waveforms Program Verification The 87C51/87C52T2 provides a method of reading the programmed code bytes in the EPROM array for program verification. This function is possible as long as Lock Bit 2 has not been programmed. For program verification, the address of the Program Memory location to be read is applied to Ports 1 and 2 as shown in Figure 3. Verification of the 87C52T2 is identical except that P2.4 is also used as an address input. Once RST, PSEN, Port 2, and Port 3 are held to the levels indicated, the contents of the addressed location will be emitted on Port 0. External pullups are required on Port 0 for this operation. The EPROM Programming and verification waveforms provide further details. P97 Pag XTAL XTALy ss 87C51 Veo READ P DATA Q (USE 10k PULL-UPS) ALEPROG |* Yn Epp [* Vepx 20V< Vepx <13.0V RST F# Vi, PSEN TC004672 Figure 3. 87C51 Program Verification 7-18 87C51/87C52T2Program Encryption Tabie The 87C51/87C52T2 features a 32-byte Encryption Array. It can be programmed by the customer, thus encrypting the program code bytes read during EPROM verification. The EPROM verification procedure is performed as usual except that each code byte comes out fogically X-NORed with one of the 32 key bytes. The key byte used is the one whose address corresponds to the lower 5 bits of the EPROM verification address. Thus, when the EPROM is verified starting with address OOOOH, all 32 keys in their correct sequence must be known. Unpro- grammed bytes have the value FFH. Thus, if the Encryption Table is left unprogrammed, no encryption will be performed, since any byte X-NORed with FFH jeaves that byte un- changed. To program the Encryption Table, programming is set up as usual, except that P3.6 is held Low, as shown in Table 1. The 25-pulse programming sequence is applied to each address, 00 through 1FH. The programming of these bytes does not affect the standard 4K-byte EPROM array. When the Encryp- tion Table is programmed, the Program Verify operation will produce only encrypted data. The Encryption Table cannot be directly read. The program- ming of Lock Bit 1 will disable further Encryption Table programming. Security Lock Bits The 87C51 contains two Lock Bits which can be programmed to obtain additional security features. P = Programmed and U = Unprogrammed. Lock Bit 1 Lock Bit 2 Result U Normal Operation U + Externally fetched code cannot access internal Program Memory * All further Programming disabled (except Lock Bit 2) U P Reserved P P * Externally fetched code cannot access internal Program Memory * All further Programming disabled * Program Verification disabled To program the Lock Bits, a 100 pulse programming sequence is required using the levels shown in Table 1. After Lock Bit 1 is programmed, further programming of the Code Memory and Encryption Table is disabled. However, Lock Bit 2 may still be programmed, providing the highest level of security available on the 87C51/87C52T2. When Lock Bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. if the device is powered up without a reset, the latch initializes to a random value, and holds that value until reset is activated. It is necessary that the latched value of EA be in agreement with the current logic level at that pin in order for the device to function properly. Silicon Signature Verification AMD supports silicon signature verification for the 87C51/ 87C52T2. The manufacturer code and part code can be read from the device before any programming is done to enable the EPROM Programmer to recognize the device. To read the silicon signature, the external pins are set up as shown in Figure 4. This procedure is the same as a normal verification except that P3.6 and P3.7 are pulled to a logic Low. The values returned are: Manufacturer Code | Address: 0030H Code: 01H 87C51 Part Code Address: 0031H Code: BOH 87C52T2 Part Code | Address: 0031H Code: 31H Code 01H indicates AMD as the manufacturer. Code BOH indicates the device type is the 87C51, and Code 31H indicates a 87C52T2. In-Circuit Test Mode The In-Circuit Test Mode facilitates testing and debugging of systems using the 87C51 without the 87C51 having to be removed from the circuit. The In-Circuit Test Mode is invoked by: 1. Pulling ALE Low while RST is held High, and PSEN is High. 2. Holding ALE Low as RST is de-activated. While the device is in In-Circuit Test Mode, the Port 0 pins go into a float state, and the other port pins and ALE and PSEN are weakly pulled High. The oscillator circuit remains active. While the 87C51 is in this mode, an emulator or test CPU can be used to drive the circuit. Normal operation is restored when a Hardware Reset is applied. Erasure Characteristics Light and other forms of electromagnetic radiation can lead to erasure of the EPROM when exposed for extended periods of time. Wavelengths of light shorter than 4000 angstroms, such as sunlight or indoor fluorescent lighting, can ultimately cause inadvertent erasure and should, therefore, not be allowed to expose the EPROM for lengthy durations (approximately one week in sunlight or three years in room-level fluorescent lighting). It is suggested that the window be covered with an opaque label if an application is likely to subject the device to this type of radiation. It is recommended that ultraviolet tight (of 2537 angstroms) be used to a dose of at least 15 W-sec/cm? when erasing the EPROM. An ultraviolet lamp rated at 12,000 uW/om? held one inch away for 20-30 minutes should be sufficient. EPROM erasure leaves the Program Memory in an all ones state. 87C51/87C52T2 7-19ADOR OO00H-0001H ENABLE = Vj. -e V cc P. oz 1 READ Po DATA (USE 10 ka AgrA Poo-Pa3 PULL-UPS) Vie Pa 87051 v P ft ea "3.7 ALEPROG Ke Vay Vii m Poe Po7 Coq FArpe|e Vorx 2.0 V <Vppy < 13.0V 4-6MH2 [ ] +t XTALy RST }* Vis Vss PSEN (Address 0030) = Manufacture Code = 01H = AMD (Address 0031) = Part Code Lo = BOH = 87051 TC004683 Figure 4. 87C51 Silicon Signature Verification Configuration Oscillator Characteristics To drive the device from an external clock source, XTAL; should be driven while XTALg is left unconnected (see Figure XTAL4 and XTALg are the input and output, respectively, of an 6). There are no requirements on the duty cycle of the external inverting amplifier which is configured for use as an on-chip oscillator (see Figure 5). Either a quartz crystal or ceramic resonator may be used. clock signal since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum High and Low times specified on the data sheet must be observed. XTALg XTAL, Vss TC004710 Figure 5. Crystal Oscillator NC XTAL EXTERNAL OSCILLATOR XTAL SIGNAL ss 7004700 Figure 6. External Drive Configuration 7-20 87C51/87C52T2ABSOLUTE MAXIMUM RATINGS Storage Temperature ..................ccccccceee -65 to + 150C Voltage on EA/Vpp Pin to Vgg ........0.... -0.5 to +13.0 V Voltage on Vcc to Vgs ........... .-0.5 to +6.5 V Voltage on Any Other Pin to Vsgs. .-0.5 to +6.5 V Power Dissipation ...............cccccceseccceueseseeseenees 200 mW Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. OPERATING Commercial (C) Devices Ambient Temperature (Ta) .........0......00.008 0 to +70C Supply Voltage (Vcc) -+45 to +55 V Ground (VES) .......ccececcccccessseesscvecaecseeecuesausensees ov Industrial (1) Devices Ambient Temperature (Ta) Supply Voltage (Vcc) .... Ground (Vss) Operating ranges define those limits between which the RANGES DC CHARACTERISTICS over operating ranges functionality of the device is guaranteed. Parameter Symbol Parameter Description Test Conditions Min. Max. Unit Vit Input Low Voltage (Except EA) -0.5 0.2 Voc -0.1 Vv Vina Input Low Voltage (FA) 0 0.2 Voc -0.3 v Vi Input High Voltage (Except XTAL;, RST) Voo o9 Voc + 0.5 v Virt input High Voltage to XTAL;, RST 0.7 Voc Voc + 0.5 v VoL Output Low Voltage (Ports 1, 2, 3) lor =1 N 1) 0.45 Vv Vou Output Low Voltage (Port 0, ALE, PSEN) 3: te) 0.45 v Vou Output High Voltage (Ports 1, 2, 3), ALE, V 10% 24 v e 16H =-10 WA 0.9 Voc i loH = -800 yA, 24 VoH1 Voc =5 V +10% v lon =-80 wA (Note 2) he Vin = 0.45 V -50 nA te (Note 3) -650 uA tu Vin = Vitor Vin +10 uA a Note 4-- loo Ilo Mode @ 42 Mer tise 8) (ote 5) Nowa | Power-Down Mode 50 uA RRST Reset Pulldown Resistor 50 300 kQ Cio Pin Capacitance qt Frea= 1 MHz, 40 pF Notes: 1. Capacitive loading on Ports 0 and 2 may cause spurious noise Pulses to be superimposed on the Vocs of ALE and Ports 1 and 3. The noise 2. Capacitive loading on Ports 0 and 2 may cause the Vox on ALE and PSEN to momentarily fall below the 0.9 Vcc specification when the address bits are stabilizing. 3. Pins of Ports 1, 2, and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when Vin is approximately 2 V. 4. Iccmax at other frequencies is given by: Active Mode: Icc TYPICAL = 0.94 x Freq+ 19.71 loc MAX = 1.38x Freq + 20.4 Idle Mode: = Icc TYPICAL = 0.38 x Freq + 5.4 loc MAX = 0.38 x Freq + 11.9 where Freq is the external oscillator frequency in MHz. ICcMAx is given in mA (see Figure 5). 5. Active Mode Icc is measured with all output pins disconnected; XTALy is due to external bus capacitance discharging into the Port 0 and Port 2 Pins when these pins make 1-to-0 transitions during bus operations. In the worst cases (capacitive loading > 100 pF), the noise pulse on the ALE line may exceed 0.8 V. In such cases it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. driven with TCLCH, TCHCL=5 ns, Vii =Vgg+0.5 V, Vin = Voc - 0.5 V; XTALg N.C.; EA = RST = Port 0 = Voc. Idle Mode Icc is measured with alt output pins disconnected: XT, AL; driven with TCLCH, TCHCL =5 ns, ViH = Voc - 0.5 V; XTAL2 = N.C; Port 0 = Voc; EA = RST = Vgg. Power-Down Mode Icc is measured with all output pins disconnected; EA = Port 0 = Voc: XTAL2 NC; RST = Vss. ViL=Vss+0.5 V, 87C51/87C52T2 7-21SWITCHING CHARACTERISTICS over operating ranges (Load Capacitance for Port 0, ALE, and PSEN = 100 pF, Load Capacitance for All Other Outputs = 80 pF) 16 MHz Osc. 12 MHz Osc. Variable Oscillator Parameter Parameter Symbol Description Min. Max. Min. Max. Min. Max. Unit 1/TCLCL Oscillator Frequency 16 MHz TLHLL ALE Pulse Width 8 127 ns TAVLL Address Valid to ALE Low 7 28 ns TLLAX Address Hold After ALE Low 27 48 ns TLLIV ALE Low to Valid Instr. In 150 4TCLCL- 100 ns TLUPL ALE Low to PSEN Low 22 43 ns TPLPH PSEN Pulse Width 142 oa ns TPLIV PSEN Low to Valid Instr. in BS EE %, 3TCLCL- 105 ns TPXIX input Instr. Hold After PSEN 0 ta, [4 0 ns TPXIZ input instr. Float After PSEN a i TCLCL-25 ns TAVIV Address to Valid Instr. In pa 312 5TCLCL- 105 ns TPLAZ BSEN Low to Address Float Te, & 10 10 10 ns TALRH RD Pulse Width "| p7se 400 6TCLCL- 100 ns TWLWH Pulse Width " , 275 400 6TCLCL- 100 ns TRLDV FO Low to Valid Data, inal 148 252 STCLCL-165 ns TRHDX Data Hold Aft , al 0 0 0 ns TRHDZ Data Float Afte = 55 97 2TCLCL-70 ns TLLDV ALE Low to Validgigta in 350 517 |. BTCLCL- 150 ns TAVDV Address to Valid Dawe In 398 585 9TCLCL- 165 ns TLLWL ALE Low to AO or WR Low 137 238 200 300 3TCLCL50 3TCLCL+ 50 ns TAVWL Address Valid to RD or WA Low 120 203 4TCLCL- 130 ns TQVWX Data Valid to WA Transition 2 23 TCLCL-60 ns TOVWH Data Valid to WA High 287 433 7TCLCL- 150 ns TWHOX Data Hold After WR 12 33 TCLCL-50 ns TRLAZ AD Low to Address Float 0 0 0 ns TWHLH FG or WR High to ALE High 22 103 43 123 TCLCL-40 TCLCL+ 40 ns SWITCHING WAVEFORMS KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS. OUTPUTS MUST BE WILL BE STEADY STEADY may cHance = WILUBE CHANGING FROMHTOL FROMM TOL maycuance WIL BE FROML TOH CHANGING FROM L TOH DON'T CARE: CHANGING, ANY CHANGE STATE PERMITTED UNKNOWN CENTER te SE DOES NOT LINE 1S HIGH APPLY IMPEDANCE OFF STATE KS000010 7-22 87C51/87C52T2SWITCHING WAVEFORMS == TLHLL | ALE / \ TAVLL \ TAVLLE TLUPL TPLPH TLLIV \ TPLIV uy a - PORTO y PORT 2 AgrAis AgrArs External Program Memory Read Cycle TAVIV WF021962 TWHLH }-o ALE TLLDV -TLLWL TRALRAH \ J - TRLDV - TAVLL: f-~| TAHDZ FTLLAX=| =| l--TALAZ TRHOX> |- [ ADg~AD7 Y AD g-AD: PORTO + FROM Ri OR onl >_____{ DATA IN WB nce PCL nen TAVWL ADo-AD7 TAVDV PORT 2 P2.0-P2.7 OR Ag-Aig FROM DPH X AgrAig FROM PCH WFO020962 External Data Memory Read Cycle 87C051/87C52T2 7-23SWITCHING WAVEFORMS (continued) ALE PSEN WR TQVWH PORT 0 ao ae PL DATA OUT TAVWL - PORT 2 P2.0-P2.7 OR Ag-Ayg FROM DPH Ag-Ays FROM PCH WFO020932 External Data Memory Write Cycle werrucion | 0 ft fl 2 fll fl fe Gl Yt ee Txuxc-m| cLock TQVXH feor] eTxHiax | OUTPUT DATA VW Xt Ke Xs Ks XK Xs Xs t SET WRITE TO SBUF secre l. TXHOX . INPUT DATA > GED (>) GED (> D> > GD GD CD GD (CS) GD (> SET N CLEAR Rl WF020951 Shift Register Timing Waveforms 7-24 87C051/87C52T2EXTERNAL CLOCK DRIVE Parameter Parameter Symbol tian a Min. Max. Unit 1/TCLCL , MHz TCHCX Ti ns TCLOX se Low Ti ns TCLCH Rise Time ns TCHCL Fall Time ns - Le) / O45 0.2 Veg~0.1 P TCLCX |, TOLCH TCHCL TCLCL WF020910 External Clock Drive Waveform SERIAL PORT TIMING SHIFT REGISTER MODE (Test Conditions: Ta =0 to +70C; Voc = 5 V +10%; Vsgg =0 V; Load Capacitance = 80 pF) 16 MHz Ose. Variable Oscillator-~ Parameter Parameter Symbol Description Min. | Max. Min. Max. Unit TXLXL ne TQVXH 10 LCL ns TXHOX Hol r isi E LCL-f ns TXHOX Input Data Hold After Clock Rising Edge 0 0 ns TXHDV Clock Rising Edge to Input Data Valid 492 10TCLCL- 133 ns AC Testing a logic 0. Timing 02 Voc +00 02 Voc -0.1 AC inputs during testing are driven at Voc0.5 for a logic: and 0.45 V for WF020901 its are made at Vix min. for a jogic 1 and ViL Input/Output Waveform VLoap +0.1 V Vou 0.4 V VioaD (> TIMING REFERENCE POINTS VuLoaD0:1 V Vo +0.1 V Float Waveform 87C51/87C52T2EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS (Ta = +21 to +27C) Parameter Parameter Symbol Description i Max. Unit Vpp Programming Supply Voltage 13.0 v Ipp Programming Supply Current 50 mA 1/TCLCL Oscillator Frequency 4 6 MHz TAVGL Address Setup to @ 48TCLCL TGHAX Address Hold After 48TCLCL TDVGL Data Setup to 48TCLCL TGHDX Data Hi - 48TCLCL TEHSH Po. Vpp 48TCLCL TSHGL PROG 10 us TGHSL Hold after PROG 10 ys TGLGH Width 90 110 ys TAVQV Address to Data Valid 48TCLCL TELQV ENABLE to Data Valid 48TCLCL TEHQZ Data Float After ENABLE 0 48TCLCL TGHGL PROG High to PROG Low 10 us EPROM PROGRAMMING AND VERIFICATION WAVEFORMS PROGRAMMING VERIFICATION P1.0-P17 P2.0-P23 4 ADDRESS ADDRESS } + TAvav PORT 0 { = DATAIN 4 vaTAoUuT =} TDVGL +e ke > fe -TGHDX TAVGL 25 PULSES TGHAX ALE/PROG \ - TSHGL LTGHGL + TGLGH | TGHSL EMVpp _/f LOGIC 1 Locic 1 LOGIC 0 ae ete | +_ be TEHSH TELOV >| be }+- TEHOZ 7 @use, _/| WF025693 For Programming conditions, see Figures 1 and 2. For Verification conditions, see Figure 3. 7-26 87C51/87C52T2ADVANCED MICRO DEVICES 28 D mm 0257525 Q03e42eb 4 MM AMD CHAPTER 11 TGQ 0 zi Package Outlines yO PHYSICAL DIMENSIONS* Plastic Dual-In-Line Package (PD) PD 040 2,040 \ 2.080 - OOO mr oot oi cit pr 230 580 wl fa j |e .005 048 065 MIN, lo [3 i> = bh o g|2 alo ola yor Ble (| olo als hole Mh NES yas 218 =/(O aiiaa ge olp o {5 PID# 068238 * For reference only, NOTE: Package dimensions are given in inches. To convert to millimeters, multiply by 25.4,ADVANCED MICRO DEVICES ede D Me 0257525 G03ec4e7? & Mm AND roe .700 bax | CHAPTER 11 ~-~90~ Package Outlines T-90-20 Ceramic Hermetic Dual-In-Line Packages (CD/CDV) . CD 040 - oe - 098 MAX Dd 565 605 : 4 | | 100 | .050 . 065 BSC ,005 065 MIN 590 015 615 I .060 i 008 .160 o 012 220 { 1 15 125 | .150 160 Le? MIN .700 Pr rl|+ 218 700 ot 068246 CDV 040 2,035 ~ 2.080 i_ .098 | _ 565 1 .605 _ LL | _. _ .050 . 065 BSG .005 065 MIN ag _1990 015 {615 160 # 060 160 0 2204 { =e 15 07880C NOTE: Package dimensions are given in inches. To convert to millimeters, multiply by 25.4.nn eS ADVANCED MICRO DEVICES CSE D MM 0257525 0032425 & mm AND CHAPTER 11 Package Outlines Plastic Leaded Chip Carriers (PL) ~90+20 PL 044 T i 042 048 REF 04a _ _ee: 056 ng | if ~ ry 01S 025 ] i OOOO AoA 045 I] | ols co = 590 as | OE im sho 8 695 = 026 REF. Cy VI * (938 a A | 656 = 3 0 G J 021 ima 4 CI [] Ys . . ' gooocooccoc 009 | 650 | 090 015 = .120 165 .656 el 685 178 695 NOTE; Package dimensions are given in inches. To convert to millimeters, multiply by 25.4. | | | | 11-3ne ADVANCED MICRO DEVICES ~ 26E D Mm 0257525 oo32e4e9 T Mm AMD CHAPTER 11 : 7 Package Outlines T-90-20 Ceramic Leadiess Chip Carrier (CLV) CLV 044 44 PLAGES 045 58 PMT nN + th 2 8 022 022 FT 7 ZR a a 209 _ I i] ie 38 054 Hep 2054 (mili - 2 ew .860 q $-- 625 MAX, 640 860 PID #097030 NOTE: Package dimensions are given in inches. To convert to millimeters, multiply by 25.4.