DS1302ZN+T&R-W - Maxim Integrated Products, Inc.

DS1302

Trickle-Charge Timekeeping Chip

1 of 13 REV: 120208

FEATURES

 Real-Time Clock Counts Seconds, Minute s,

Hours, Date of the Month, Month, Day of the

Week, and Year with Leap-Year

Compensation Valid Up to 2100

 31 x 8 Battery-Backed General-Purpose RAM

 Serial I/O for Minimum Pin Count

 2.0V to 5.5V Full Operation

 Uses Less than 300nA at 2.0V

 Single-Byte or Multiple-Byte (Burst Mode)

Data Transfer for Read or Write of Clock or

RAM Data

 8-Pin DIP or Optional 8-Pin SO for Surface

Mount

 Simple 3-Wire Interface

 TTL-Compatible (VCC = 5V)

 Optional Industrial Temperature Range:

-40°C to +85 °C

 DS1202 Compatible

 Underwriters Laboratori es (UL®)

Recognized

PIN CONFIGURATIONS

ORDERING INFORMATION

PART TEMP RANGE PIN-PACKAGE TOP MARK*

DS1302+ 0°C to +70°C 8 PDIP (300 mils) DS1302

DS1302N+ -40°C to +85°C 8 PDIP (300 mils) DS1302

DS1302S+ 0°C to +70°C 8 SO (208 mils) DS1302S

DS1302SN+ -40°C to +85°C 8 SO (208 mils) DS1302S

DS1302Z+ 0°C to +70°C 8 SO (150 mils) DS1302Z

DS1302ZN+ -40°C to +85°C 8 SO (150 mils) DS1302ZN

+Denotes a lead-free/RoHS-compliant package.

*An N anywhere on the top mark indicates an industrial temperature grade device. A + anywhere on the top mark indicates a lead-free device.

UL is a registered trademark of Underwriters Laboratories, Inc.

www.maxim-ic.com

VCC1

SCLK

I/O

VCC2

GND

DIP (300 mils)

DS1302

VCC2

GND

VCC1

SCLK

I/O

SO (208 mils/150 mils)

DS1302

TOP VIEW

DS1302 Trickle-Charge Timekeeping Chip

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DETAILED DESCRIPTION

The DS1302 trickle-charge timekeeping chip contains a real-time clock/calendar and 31 bytes of static RAM. It

communicates with a microprocessor via a simple serial interface. The real-time clock/calendar provides seconds,

minutes, hours, day, date, month, and year information. The end of the month date is automatically adjusted for

months with fewer than 31 days, including corrections for leap year. The clock operates in either the 24-hour or

12-hour format with an AM/PM indicator.

Interfacing the DS1302 with a microprocessor is simplified by using synchronous serial communication. Only three

wires are required to communicate with the clock/RAM: CE, I/O (data line), and SCLK (serial clock). Data can be

transferred to and from the clock/RAM 1 byte at a time or in a burst of up to 31 bytes. The DS1302 is designed to

operate on very low power and retain data and clock information on less than 1μW.

The DS1302 is the successor to the DS1202. In addition to the basic timekeeping functions of the DS1202, the

DS1302 has the additional features of dual power pins for primary and backup power supplies, programmable

trickle charger for VCC1, and seven additional bytes of scratchpad memory.

OPERATION

Figure 1 shows the main elements of the serial timekeeper: shift register, control logic, oscillator, real-time clock,

and RAM.

TYPICAL OPERATING CIRCUIT

DS1302

CPU

VCC

CC2

SCLK

GND

X2 X1

VCC

I/O

CC1

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Figure 1. Block Diagram

POWER

CONTROL

CC1

CC2

GND

INPUT SHIFT

REGISTERS

I/O

SCLK

COMMAND AND

CONTROL LOGIC

REAL TIME

CLOCK

31 X 8 RAM

X1X2

1Hz

DS1302

TYPICAL OPERATING CHARACTERISTICS

(VCC = 3.3V, TA = +25°C, unless otherwise noted.)

ICC2T vs. VCC2T

2.03.04.05.0

VCC2 (V)

SUPPLY CURRENT (uA

)

ICC1T vs. VCC1T

100

150

200

250

300

350

400

2.0 3.0 4.0 5.0

VCC1 (V)

SUPPLY CURRENT (nA

)

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PIN DESCRIPTION

PIN NAME FUNCTION

1 VCC2

Primary Power-Supply Pin in Dual Supply Configuration. VCC1 is connected to a

backup source to maintain the time and date in the absence of primary power. The

DS1302 operates from the larger of VCC1 or VCC2. When VCC2 is greater than VCC1 +

0.2V, VCC2 powers the DS1302. When VCC2 is less than VCC1, VCC1 powers the

DS1302.

2 X1

3 X2

Connections for Standard 32.768kHz Quartz Crystal. The internal oscillator is

designed for operation with a crystal having a specified load capacitance of 6pF.

For more information on crystal selection and crystal layout considerations, refer to

Application Note 58: Crystal Considerations for Dallas Real-Time Clocks. The

DS1302 can also be driven by an external 32.768kHz oscillator. In this

configuration, the X1 pin is connected to the external oscillator signal and the X2 pin

is floated.

4 GND Ground

5 CE

Input. CE signal must be asserted high during a read or a write. This pin has an

internal 40kΩ (typ) pulldown resistor to ground. Note: Previous data sheet revisions

referred to CE as RST. The functionality of the pin has not changed.

6 I/O

Input/Push-Pull Output. The I/O pin is the bidirectional data pin for the 3-wire

interface. This pin has an internal 40kΩ (typ) pulldown resistor to ground.

7 SCLK

Input. SCLK is used to synchronize data movement on the serial interface. This pin

has an internal 40kΩ (typ) pulldown resistor to ground.

8 VCC1

Low-Power Operation in Single Supply and Battery-Operated Systems and Low-

Power Battery Backup. In systems using the trickle charger, the rechargeable

energy source is connected to this pin. UL recognized to ensure against reverse

charging current when used with a lithium battery. Go to www.maxim-

ic.com/TechSupport/QA/ntrl.htm.

DS1302 Trickle-Charge Timekeeping Chip

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OSCILLATOR CIRCUIT

The DS1302 uses an external 32.768kHz crystal. The oscillator circuit does not require any external resistors or

capacitors to operate. Table 1 specifies several crystal parameters for the external crystal. Figure 1 shows a

functional schematic of the oscillator circuit. If using a crystal with the specified characteristics, the startup time is

usually less than one second.

CLOCK ACCURACY

The accuracy of the clock is dependent upon the accuracy of the crystal and the accuracy of the match between

the capacitive load of the oscillator circuit and the capacitive load for which the crystal was trimmed. Additional

error will be added by crystal frequency drift caused by temperature shifts. External circuit noise coupled into the

oscillator circuit may result in the clock running fast. Figure 2 shows a typical PC board layout for isolating the

crystal and oscillator from noise. Refer to Application Note 58: Crystal Considerations for Dallas Real-Time Clocks

for detailed information.

Table 1. Crystal Specifications*

PARAMETER SYMBOL MIN TYP MAX UNITS

Nominal Frequency fO 32.768 kHz

Series Resistance ESR 45 kΩ

Load Capacitance CL 6 pF

*The crystal, traces, and crystal input pins should be isolated from RF generating signals. Refer to

Application Note 58: Crystal Considerations for Dallas Real-Time Clocks for additional specifications.

Figure 2. Typical PC Board Layout for Crystal

LOCAL GROUND PLANE (LAYER 2)

CRYSTAL

GND

NOTE:

VOID ROUTING SIGNALS IN THE

CROSSHATCHED AREA (UPPER LEFT-

HAND QUADRANT) OF THE PACKAGE

UNLESS THERE IS A GROUND PLANE

BETWEEN THE SIGNAL LINE AND THE

PACKAGE.

COMMAND BYTE

Figure 3 shows the command byte. A command byte initiates each data transfer. The MSB (bit 7) must be a logic

1. If it is 0, writes to the DS1302 will be disabled. Bit 6 specifies clock/calendar data if logic 0 or RAM data if logic 1.

Bits 1 to 5 specify the designated registers to be input or output, and the LSB (bit 0) specifies a write operation

(input) if logic 0 or read operation (output) if logic 1. The command byte is always input starting with the LSB (bit 0).

Figure 3. Address/Command Byte

1RAM

CK A4 A3 A2 A1 A0 RD

76543210

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CE AND CLOCK CONTROL

Driving the CE input high initiates all data transfers. The CE input serves two functions. First, CE turns on the

control logic that allows access to the shift register for the address/command sequence. Second, the CE signal

provides a method of terminating either single-byte or multiple-byte CE data transfer.

A clock cycle is a sequence of a rising edge followed by a falling edge. For data inputs, data must be valid during

the rising edge of the clock and data bits are output on the falling edge of clock. If the CE input is low, all data

transfer terminates and the I/O pin goes to a high-impedance state. Figure 4 shows data transfer. At power-up, CE

must be a logic 0 until VCC > 2.0V. Also, SCLK must be at a logic 0 when CE is driven to a logic 1 state.

DATA INPUT

Following the eight SCLK cycles that input a write command byte, a data byte is input on the rising edge of the next

eight SCLK cycles. Additional SCLK cycles are ignored should they inadvertently occur. Data is input starting with

bit 0.

DATA OUTPUT

Following the eight SCLK cycles that input a read command byte, a data byte is output on the falling edge of the

next eight SCLK cycles. Note that the first data bit to be transmitted occurs on the first falling edge after the last bit

of the command byte is written. Additional SCLK cycles retransmit the data bytes should they inadvertently occur

so long as CE remains high. This operation permits continuous burst mode read capability. Also, the I/O pin is tri-

stated upon each rising edge of SCLK. Data is output starting with bit 0.

BURST MODE

Burst mode can be specified for either the clock/calendar or the RAM registers by addressing location 31 decimal

(address/command bits 1 through 5 = logic 1). As before, bit 6 specifies clock or RAM and bit 0 specifies read or

write. There is no data storage capacity at locations 9 through 31 in the Clock/Calendar Registers or location 31 in

the RAM registers. Reads or writes in burst mode start with bit 0 of address 0.

When writing to the clock registers in the burst mode, the first eight registers must be written in order for the data to

be transferred. However, when writing to RAM in burst mode it is not necessary to write all 31 bytes for the data to

transfer. Each byte that is written to will be transferred to RAM regardless of whether all 31 bytes are written or not.

CLOCK/CALENDAR

The time and calendar information is obtained by reading the appropriate register bytes. Table 3 illustrates the RTC

registers. The time and calendar are set or initialized by writing the appropriate register bytes. The contents of the

time and calendar registers are in the binary-coded decimal (BCD) format.

The day-of-week register increments at midnight. Values that correspond to the day of week are user-defined but

must be sequential (i.e., if 1 equals Sunday, then 2 equals Monday, and so on.). Illogical time and date entries

result in undefined operation.

When reading or writing the time and date registers, secondary (user) buffers are used to prevent errors when the

internal registers update. When reading the time and date registers, the user buffers are synchronized to the

internal registers the rising edge of CE.

The countdown chain is reset whenever the seconds register is written. Write transfers occur on the falling edge of

CE. To avoid rollover issues, once the countdown chain is reset, the remaining time and date registers must be

written within 1 second.

The DS1302 can be run in either 12-hour or 24-hour mode. Bit 7 of the hours register is defined as the 12- or 24-

hour mode-select bit. When high, the 12-hour mode is selected. In the 12-hour mode, bit 5 is the AM/PM bit with

logic high being PM. In the 24-hour mode, bit 5 is the second 10-hour bit (20–23 hours). The hours data must be

re-initialized whenever the 12/24 bit is changed.

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CLOCK HALT FLAG

Bit 7 of the seconds register is defined as the clock halt (CH) flag. When this bit is set to logic 1, the clock oscillator

is stopped and the DS1302 is placed into a low-power standby mode with a current drain of less than 100nA. When

this bit is written to logic 0, the clock will start. The initial power-on state is not defined.

WRITE-PROTECT BIT

Bit 7 of the control register is the write-protect bit. The first seven bits (bits 0 to 6) are forced to 0 and always read 0

when read. Before any write operation to the clock or RAM, bit 7 must be 0. When high, the write-protect bit

prevents a write operation to any other register. The initial power-on state is not defined. Therefore, the WP bit

should be cleared before attempting to write to the device.

TRICKLE-CHARGE REGISTER

This register controls the trickle-charge characteristics of the DS1302. The simplified schematic of Figure 5 shows

the basic components of the trickle charger. The trickle-charge select (TCS) bits (bits 4 to 7) control the selection of

the trickle charger. To prevent accidental enabling, only a pattern of 1010 enables the trickle charger. All other

patterns will disable the trickle charger. The DS1302 powers up with the trickle charger disabled. The diode select

(DS) bits (bits 2 and 3) select whether one diode or two diodes are connected between VCC2 and VCC1. If DS is 01,

one diode is selected or if DS is 10, two diodes are selected. If DS is 00 or 11, the trickle charger is disabled

independently of TCS. The RS bits (bits 0 and 1) select the resistor that is connected between VCC2 and VCC1. The

resistor and diodes are selected by the RS and DS bits as shown in Table 2.

Table 2. Trickle Charger Resistor and Diode Select

TCS

BIT 7

TCS

BIT 6

TCS

BIT 5

TCS

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0 FUNCTION

X X X X X X 0 0 Disabled

X X X X 0 0 X X Disabled

X X X X 1 1 X X Disabled

1 0 1 0 0 1 0 1 1 Diode, 2kΩ

1 0 1 0 0 1 1 0 1 Diode, 4kΩ

1 0 1 0 0 1 1 1 1 Diode, 8kΩ

1 0 1 0 1 0 0 1 2 Diodes, 2kΩ

1 0 1 0 1 0 1 0 2 Diodes, 4kΩ

1 0 1 0 1 0 1 1 2 Diodes, 8kΩ

0 1 0 1 1 1 0 0 Initial power-on state

Diode and resistor selection is determined by the user according to the maximum current desired for battery or

super cap charging. The maximum charging current can be calculated as illustrated in the following example.

Assume that a system power supply of 5V is applied to VCC2 and a super cap is connected to VCC1. Also assume

that the trickle charger has been enabled with one diode and resistor R1 between VCC2 and VCC1. The maximum

current IMAX would therefore be calculated as follows:

IMAX = (5.0V – diode drop) / R1 ≈ (5.0V – 0.7V) / 2kΩ ≈ 2.2mA

As the super cap charges, the voltage drop between VCC2 and VCC1 decreases and therefore the charge current

decreases.

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CLOCK/CALENDAR BURST MODE

The clock/calendar command byte specifies burst mode operation. In this mode, the first eight clock/calendar

registers can be consecutively read or written (see Table 3) starting with bit 0 of address 0.

If the write-protect bit is set high when a write clock/calendar burst mode is specified, no data transfer will occur to

any of the eight clock/calendar registers (this includes the control register). The trickle charger is not accessible in

burst mode.

At the beginning of a clock burst read, the current time is transferred to a second set of registers. The time

information is read from these secondary registers, while the clock may continue to run. This eliminates the need to

re-read the registers in case of an update of the main registers during a read.

RAM

The static RAM is 31 x 8 bytes addressed consecutively in the RAM address space.

RAM BURST MODE

The RAM command byte specifies burst mode operation. In this mode, the 31 RAM registers can be consecutively

read or written (see Table 3) starting with bit 0 of address 0.

A register data format summary is shown in Table 3.

CRYSTAL SELECTION

A 32.768kHz crystal can be directly connected to the DS1302 via pins 2 and 3 (X1, X2). The crystal selected for

use should have a specified load capacitance (CL) of 6pF. For more information on crystal selection and crystal

layout consideration, refer to Application Note 58: Crystal Considerations for Dallas Real-Time Clocks.

Figure 4. Data Transfer Summary

A1 A2 A3 A4 R/C1

SCLK

I/O R/WA0 D1 D2 D3 D4 D5 D6 D7D0

SINGLE-BYTE READ

A1 A2 A3 A4 R/C1

SCLK

I/O R/WA0 D1 D2 D3 D4 D5 D6 D7D0

SINGLE-BYTE WRITE

NOTE: IN BURST MODE, CE IS KEPT HIGH AND ADDITIONAL SCLK CYCLES ARE SENT UNTIL THE END OF THE BURST.

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Table 3. Register Address/Definition

RTC

READ WRITE BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 RANGE

81h 80h CH 10 Seconds Seconds 00–59

83h 82h 10 Minutes Minutes 00–59

85h 84h

12/24 0 AM/PM Hour Hour 1–12/0–23

87h 86h 0 0 10 Date Date 1–31

89h 88h 0 0 0 10

Month Month 1–12

8Bh 8Ah 0 0 0 0 0 Day 1–7

8Dh 8Ch 10 Year Year 00–99

8Fh 8Eh WP 0 0 0 0 0 0 0 —

91h 90h TCS TCS TCS TCS DS DS RS RS —

CLOCK BURST

BFh BEh

RAM

C1h C0h 00-FFh

C3h C2h 00-FFh

C5h C4h 00-FFh

FDh FCh 00-FFh

RAM BURST

FFh FEh

Figure 5. Programmable Trickle Charger

2KΩ

4kΩ

8kΩ

VCC2 VCC1

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TCS3 TCS2 TCS1 TCS0 DS1 DS0 ROUT1 ROUT0

TRICKLE CHARGE REG ISTER (90h write, 91h read)

1 0F 16 SELECT

NOTE: ONLY 1010b ENABLES CHARGER

1 OF 2

SELECT

1 OF 3

SELECT

TCS0-3 = TRICKLE CHARGER SELECT

DS0-1 = DIODE SELECT

ROUT0-1 = RESISTOR SELECT

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ABSOLUTE MAXIMUM RATINGS

Voltage Range on Any Pin Relative to Ground……………………………………………………………….-0.5Vto +7.0V

Operating Temperature Range, Commercial………………………………………………………………….0°C to +70°C

Operating Temperature Range, Industrial (IND)……………………………………………………………-40°C to +85°C

Storage Temperature Range……………………………………………………………………………..….-55°C to +125°C

Soldering Temperature (leads, 10 seconds)………………………………………………………………..………….260°C

Soldering Temperature (surface mount)………………………………………………..…….See IPC/JEDEC J-STD-020

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only,

and functional operation of the device at these or any other conditions beyond thos e indicated in the operational sections of the specifications is

not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.

RECOMMENDED DC OPERATING CONDITIONS

(TA = 0°C to +70°C or TA = -40°C to +85°C.) (Note 1)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Supply Voltage VCC1, VCC2 VCC1,

VCC2 (Notes 2, 10) 2.0 3.3 5.5 V

Logic 1 Input VIH (Note 2) 2.0 VCC +

0.3 V

VCC = 2.0V -0.3 +0.3

Logic 0 Input VIL VCC = 5V (Note 2) -0.3 +0.8 V

DC ELECTRICAL CHARACTERISTICS

(TA = 0°C to +70°C or TA = -40°C to +85°C.) (Note 1)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Input Leakage ILI (Notes 5, 13) 85 500 μA

I/O Leakage ILO (Notes 5, 13) 85 500 μA

Logic 1 Output (IOH = -0.4mA) VCC = 2.0V 1.6

Logic 1 Output (IOH = -1.0mA) VOH VCC = 5V (Note 2) 2.4 V

Logic 0 Output (IOL = 1.5mA) VCC = 2.0V 0.4

Logic 0 Output (IOL = 4.0mA) VOL VCC = 5V (Note 2) 0.4

VCC1 = 2.0V 0.4

Active Supply Current

(Oscillator Enabled) ICC1A VCC1 = 5V

CH = 0

(Notes 4, 11) 1.2

VCC1 = 2.0V 0.2 0.3

Timekeeping Current

(Oscillator Enabled) ICC1T VCC1 = 5V

CH = 0

(Notes 3, 11,13) 0.45 1 μA

VCC1 = 2.0V 1 100

VCC1 = 5V 1 100

Standby Current (Oscillator

Disabled) ICC1S

IND

CH = 1

(Notes 9, 11, 13) 5 200

VCC2 = 2.0V 0.425

Active Supply Current

(Oscillator Enabled) ICC2A VCC2 = 5V

CH = 0

(Notes 4, 12) 1.28

VCC2 = 2.0V 25.3

Timekeeping Current

(Oscillator Enabled) ICC2T VCC2 = 5V

CH = 0

(Notes 3, 12) 81

μA

VCC2 = 2.0V CH = 1

(Notes 9, 12) 25

Standby Current (Oscillator

Disabled) ICC2S

VCC2 = 5V 80

μA

R1 2

R2 4

Trickle-Charge Resistors

R3 8

kΩ

Trickle-Charge Diode Voltage

Drop VTD 0.7 V

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CAPACITANCE

(TA = +25°C)

PARAMETER SYMBOL MIN TYP MAX UNITS

Input Capacitance CI 10 pF

I/O Capacitance CI/O 15 pF

AC ELECTRICAL CHARACTERISTICS

(TA = 0°C to +70°C or TA = -40°C to +85°C.) (Note 1)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

VCC = 2.0V 200

Data to CLK Setup tDC VCC = 5V (Note 6) 50 ns

VCC = 2.0V 280

CLK to Data Hold tCDH VCC = 5V (Note 6) 70 ns

VCC = 2.0V 800

CLK to Data Delay tCDD VCC = 5V (Notes 6, 7, 8) 200

VCC = 2.0V 1000

CLK Low Time tCL VCC = 5V (Note 6) 250 ns

VCC = 2.0V 1000

CLK High Time tCH VCC = 5V (Note 6) 250 ns

VCC = 2.0V 0.5

CLK Frequency tCLK VCC = 5V (Note 6) DC 2.0

MHz

VCC = 2.0V 2000

CLK Rise and Fall tR, tF VCC = 5V 500

VCC = 2.0V 4

CE to CLK Setup tCC VCC = 5V (Note 6) 1 μs

VCC = 2.0V 240

CLK to CE Hold tCCH VCC = 5V (Note 6) 60 ns

VCC = 2.0V 4

CE Inactive Time tCWH VCC = 5V (Note 6) 1 μs

VCC = 2.0V 280

CE to I/O High Impedance tCDZ VCC = 5V (Note 6) 70

VCC = 2.0V 280

SCLK to I/O High Impedance tCCZ VCC = 5V (Note 6) 70

Note 1: Limits at -40°C are guaranteed by design and are not production tested.

Note 2: All voltages are referenced to ground.

Note 3: ICC1T and ICC2T are specified with I/O open, CE and SCLK set to a logic 0.

Note 4: ICC1A and ICC2A are specified with the I/O pin open, CE high, SCLK = 2MHz at VCC = 5V; SCLK = 500kHz, VCC = 2.0V.

Note 5: CE, SCLK, and I/O all have 40kΩ pulldown resistors to ground.

Note 6: Measured at VIH = 2.0V or VIL = 0.8V and 10ns maximum rise and fall time.

Note 7: Measured at VOH = 2.4V or VOL = 0.4V.

Note 8: Load capacitance = 50pF.

Note 9: ICC1S and ICC2S are specified with CE, I/O, and SCLK open.

Note 10: VCC = VCC2, when VCC2 > VCC1 + 0.2V; VCC = VCC1, when VCC1 > VCC2.

Note 11: VCC2 = 0V.

Note 12: VCC1 = 0V.

Note 13: Typical values are at +25°C.

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Figure 6. Timing Diagram: Read Data Transfer

SCLK

I/O

CDH

CDZ

CDD

ADDRESS/COMMAND BYTE READ DATA BYTE

CCZ

Figure 7. Timing Diagram: Write Data Transfer

SCLK

I/O t

CDH

CCH

CWH

ADDRESS/COMMAND BYTE WRITE DATA BYTE

CHIP INFORMATION

TRANSISTOR COUNT: 11,500

THERMAL INFORMA TION

PACKAGE THETA-JA

(°C/W) THETA-JC

(°C/W)

8 DIP 110 40

8 SO (150 mils) 170 40

PACKAGE INFORMATION

For the latest package outline information and land patterns, go to www.maxim-ic.com/packages.

PACKAGE TYPE PACKAGE CODE DOCUMENT NO.

8 PDIP — 21-0043

8 SO (208 mils) — 21-0262

8 SO (150 mils) — 21-0041

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Maxim/Dallas Semiconductor cannot assume responsibili ty for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product.

No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor Corporation.

REVISION HISTORY

REVISION

DATE DESCRIPTION PAGES

CHANGED

Removed the leaded parts and references to the 16-pin SO package. 1, 4, 12

In the Features section, changed the 31 x 8 RAM feature to indicate that it is

battery backed. 1

Updated Figure 1 and removed original Figure 2 (oscillator circuit). 3, 5

Added a new Table 2 for the trickle charger resistor and diode select. 7

Replaced the timing diagrams (Figures 6 and 7). 12

120208

Added Package Information table. 12