dsPIC30F4011/4012 dsPIC30F4011/4012 Rev. A4 Silicon Errata The dsPIC30F4011/4012 (Rev. A4) samples that you have received were found to conform to the specifications and functionality described in the following documents: * DS70157 - "dsPIC30F/33F Programmer's Reference Manual" * DS70141 - "dsPIC30F3010/3011 Data Sheet" * DS70046 - "dsPIC30F Family Reference Manual" The exceptions to the specifications in the documents listed above are described in this section. These exceptions are described for the specific devices listed below: * dsPIC30F4011 * dsPIC30F4012 These devices may be identified by the following message that appears in the MPLAB(R) ICD 2 Output Window under MPLAB IDE, when a "Reset and Connect" operation is performed within MPLAB IDE: Setting Vdd source to target Target Device dsPIC30F3011 found, revision = Rev 0x1004 ...Reading ICD Product ID Running ICD Self Test ...Passed MPLAB ICD 2 Ready The errata described in this section will be addressed in future revisions of dsPIC30F4011 and dsPIC30F4012 devices. Silicon Errata Summary The following list summarizes the errata described in further detail throughout the remainder of this document: 1. MAC Class Instructions Modification with 4 Address Sequential MAC instructions, which prefetch data from Y data space using 4 address modification, will cause an address error trap. 2. Decimal Adjust Instruction The Decimal Adjust instruction, DAW.b, may improperly clear the Carry bit, C (SR<0>). 3. Special Function Registers Writes to certain unimplemented address locations can affect I/O Port register values. 4. PSV Operations Using SR In certain instructions, fetching one of the operands from program memory using Program Space Visibility (PSV) will corrupt specific bits in the STATUS Register, SR. 5. Early Termination of Nested DO loops When using two DO loops in a nested fashion, terminating the inner-level DO loop by setting the EDT (CORCON<11>) bit will produce unexpected results. 6. 4x PLL Operation The 4x PLL mode of operation may not function correctly for certain input frequencies. 7. Sequential Interrupts Sequential interrupts after modifying the CPU IPL, interrupt IPL, interrupt enable or interrupt flag may cause an address error trap. 8. DISI Instruction The DISI instruction will not disable interrupts if a DISI instruction is executed in the same instruction cycle that the DISI counter decrements to zero. 9. Output Compare Module in PWM Mode Output compare will produce a glitch when loading 0% duty cycle in PWM mode. It will also miss the next compare after the glitch. (c) 2008 Microchip Technology Inc. DS80398A-page 1 dsPIC30F4011/4012 10. Output Compare Module The output compare module will produce a glitch on the output when an I/O pin is initially set high and the module is configured to drive the pin low at a specified time. 11. INT0, ADC and Sleep Mode ADC event triggers from the INT0 pin will not wake-up the device from Sleep mode if the SMPI bits are non-zero. 12. 8x PLL Mode If 8x PLL mode is used, the input frequency range is 5 MHz-10 MHz instead of 4 MHz-10 MHz. 13. 10-bit ADC: Sampling Rate The 10-bit Analog-to-Digital Converter (ADC) has a maximum sampling rate of 750 ksps. 14. Quadrature Encoder Interface (QEI) Module The QEI module does not generate an interrupt in a particular overflow condition. 15. I2CTM Module The I2C module loses incoming data bytes when operating as an I2C slave. 16. I2C Module: 10-bit Addressing Mode When the I2C module is configured for 10-bit addressing using the same address bits (A10 and A9) as other I2C devices, the A10 and A9 bits may not work as expected. 17. I2C Module: 10-bit Addressing Mode The 10-bit slave does not set the RBF flag or load the I2CxRCV register on address match if the least significant bits of the address are the same as the 7-bit reserved addresses. DS80398A-page 2 18. I2C Module: 10-bit Addressing Mode When the I2C module is configured as a 10-bit slave with an address of 0x102, the I2CxRCV register content for the lower address byte is 0x01 rather than 0x02. 19. I2C Module When the I2C module is enabled, the dsPIC(R) DSC device generates a glitch on the SDA and SCL pins, causing a false communication start in a single-master configuration or a bus collision in a multi-master configuration. 20. Motor Control PWM - PWM Counter Register PTMR does not continue counting down after halting code execution in Debug mode. 21. I/O Port - Port Pin Multiplexed with IC1 The Port I/O pin multiplexed with the Input Capture 1 (IC1) function cannot be used as a digital input pin when the UART auto-baud feature is enabled. 22. Timer Module Clock switching prevents the device from waking up from Sleep. 23. PLL Lock Status Bit The PLL LOCK Status bit (OSCCON<5>) can occasionally get cleared and generate an oscillator failure trap even when the PLL is still locked and functioning correctly. 24. PSV Operations An address error trap occurs in certain addressing modes when accessing the first four bytes of any PSV page. The following sections describe the errata and work around to these errata, where they may apply. (c) 2008 Microchip Technology Inc. dsPIC30F4011/4012 1. Module: MAC Class Instructions with 4 Address Modification Sequential MAC class instructions, which prefetch data from Y data space using 4 address modification, will cause an address error trap. The trap occurs only when all of the following conditions are true: 1. Two sequential MAC class instructions (or a MAC class instruction executed in a REPEAT or DO loop) that prefetch from Y data space. 2. Both instructions prefetch data from Y data space using the + = 4 or - = 4 address modification. 3. Neither of the instruction uses an accumulator write back. Work around The problem described above can be avoided by using any of the following methods: 1. Inserting any other instruction between the two MAC class instructions. 2. Adding an accumulator write back (a dummy write back if needed) to either of the MAC class instructions. 3. Do not use the + = 4 or - = 4 address modification. 4. Do not prefetch data from Y data space. 3. Module: Special Function Registers The I/O Port register values can be changed by writing to the following address locations, which are located in unimplemented memory space. A write to these unimplemented addresses could cause an I/O pin configured as an output to change states. This state change could be confirmed by reading either the PORT or LAT register associated with the pin. PORTB will be modified by a write to address 0x0C8 PORTC will be modified by a write to address 0x0CE PORTD will be modified by a write to address 0x0D4 PORTE will be modified by a write to address 0x0DA PORTF will be modified by a write to address 0x0E0 Work around User software should avoid writing to the unimplemented locations listed above. 2. Module: CPU - DAW.b Instruction The Decimal Adjust instruction, DAW.b, may improperly clear the Carry bit, C (SR<0>), when executed. Work around Check the state of the Carry bit prior to executing the DAW.b instruction. If the Carry bit is set, set the Carry bit again after executing the DAW.b instruction. Example 1 shows how the application should process the Carry bit during a BCD addition operation. EXAMPLE 1: CHECK CARRY BIT BEFORE DAW.b .include "p30fxxxx.inc" ....... MOV.b #0x80, w0 ;First BCD number MOV.b #0x80, w1 ;Second BCD number ADD.b w0, w1, w2 ;Perform addition BRA NC, L0 ;If C set go to L0 DAW.b w2 ;If not,do DAW and BSET.b SR, #C ;set the carry bit BRA L1 ;and exit L0:DAW.b w2 L1: .... (c) 2008 Microchip Technology Inc. DS80398A-page 3 dsPIC30F4011/4012 4. Module: PSV Operations Using SR These instructions are identified in Table 1. Example 2 demonstrates one scenario where this occurs. When one of the operands of instructions shown in Table 1 is fetched from program memory using Program Space Visibility (PSV), the STATUS Register, SR and/or the results may be corrupted. TABLE 1: Also, always use Work around 2 if the C compiler is used to generate code for dsPIC30F4011/4012 devices. AFFECTED INSTRUCTIONS Instruction(1) Examples of Incorrect Operation(2) Data Corruption IN ADDC ADDC W0, [W1++], W2 ; SR<1:0> bits(3), Result in W2 SUBB SUBB.b W0, [++W1], W3 ; SR<1:0> bits(3), Result in W3 SUBBR SUBBR.b W0, [++W1], W3 ; SR<1:0> bits(3), Result in W3 CPB CPB W0, [W1++], W4 ; SR<1:0> bits(3) RLC RLC [W1], W4 ; SR<1:0> bits(3), Result in W4 RRC RRC [W1], W2 ; SR<1:0> bits(3), Result in W2 ADD (Accumulator-based) ADD [W1++], A ; SR<1:0> bits(3) LAC LAC [W1], A ; SR<15:10> bits(4) Note 1: 2: 3: 4: Refer to the "dsPIC30F/33F Programmer's Reference Manual" (DS70157) for details on the dsPIC30F instruction set. The errata only affects these instructions when a PSV access is performed to fetch one of the source operands in the instruction. A PSV access is performed when the Effective Address of the source operand is greater than 0x8000 and the PSV (CORCON<2>) bit is set to `1'. In the examples shown, the data access from program memory is made via the W1 register. SR<1:0> bits represent Sticky Zero and Carry Status bits, respectively. SR<15:10> bits represent Accumulator Overflow and Saturation Status bits. EXAMPLE 2: INCORRECT RESULTS .include "p30fxxxx.inc" ....... MOV.B #0x00, W0 ;Load PSVPAG register MOV.B WREG, PSVPAG BSET CORCON, #PSV ;Enable PSV .... MOV #0x8200, W1 ;Set up W1 for ;indirect PSV access ;from 0x000200 ADD W3, [W1++], W5 ;This instruction ;works ok ADDC W4, [W1++], W6 ;Carry flag and ;W6 gets ;corrupted here! Work arounds Work around 1: For Assembly Language Source Code To work around the erratum in the MPLAB ASM30 assembler, the application may perform a PSV access to move the source operand from program memory to RAM or a W register prior to performing the operations listed in Table 1. The work around for Example 2 is demonstrated in Example 3. DS80398A-page 4 EXAMPLE 3: CORRECT RESULTS .include "p30fxxxx.inc" ....... MOV.B #0x00, w0 ;Load PSVPAG register MOV.B WREG, PSVPAG BSET CORCON, #PSV ;Enable PSV .... MOV #0x8200, W1 ;Set up W1 for ;indirect PSV access ;from 0x000200 ADD W3, [W1++], W5 ;This instruction ;works ok MOV [W1++], W2 ;Load W2 with data ;from program memory ADDC W4, W2, W6 ;Carry flag and W4 ;results are ok! Work around 2: For C Language Source Code For applications using C language, MPLAB C30 versions 1.20.04 or higher provide the following command-line switch that implements a work around for the erratum. -merrata=psv Refer to the "readme.txt" file in the MPLAB C30 v1.20.04 toolsuite for further details. (c) 2008 Microchip Technology Inc. dsPIC30F4011/4012 5. Module: Early Termination of Nested DO Loops When using two DO loops in a nested fashion, terminating the inner-level DO loop by setting the EDT (CORCON<11>) bit will produce unexpected results. Specifically, the device may continue executing code within the outer DO loop forever. This erratum does not affect the operation of the MPLAB C30 compiler. 6. Module: 4x PLL Operation When the 4x PLL mode of operation is selected, the specified input frequency range of 4-10 MHz is not fully supported. When device VDD is 2.5-3.0V, the 4x PLL input frequency must be in the range of 4-5 MHz. When device VDD is 3.0-3.6V, the 4x PLL input frequency must be in the range of 4-6 MHz for both industrial and extended temperature ranges. Work around Work around The application should save the DCOUNT SFR prior to entering the inner DO loop and restore it upon exiting the inner DO loop. This work around is shown in Example 4. 1. Use 8x PLL or 16x PLL mode of operation and set final device clock speed using the POST<1:0> oscillator postscaler control bits (OSCCON<7:6>). 2. Use the EC without PLL Clock mode with a suitable clock frequency to obtain the equivalent 4x PLL clock rate. EXAMPLE 4: SAVE AND RESTORE DCOUNT .include "p30fxxxx.inc" ....... DO #CNT1, LOOP0 ;Outer loop start .... PUSH DCOUNT ;Save DCOUNT DO #CNT2, LOOP1 ;Inner loop .... ;starts BTSS Flag, #0 BSET CORCON, #EDT ;Terminate inner .... ;DO-loop early .... LOOP1: MOV W1, W5 ;Inner loop ends POP DCOUNT ;Restore DCOUNT ... LOOP0: MOV W5, W8 ;Outer loop ends Note: For details on the functionality of EDT bit, see section 2.9.2.4 in the dsPIC30F Family Reference Manual. (c) 2008 Microchip Technology Inc. DS80398A-page 5 dsPIC30F4011/4012 7. Module: Interrupt Controller - Sequential Interrupts When interrupt nesting is enabled (or NSTDIS (INTCON1<15>) bit is `0'), the following sequence of events will lead to an address error trap. The generic terms "Interrupt 1" and "Interrupt 2" are used to represent any two enabled dsPIC30F interrupts. 1. Interrupt 1 processing begins. 2. Interrupt 1 is negated by user software by one of the following methods: - CPU IPL is raised to Interrupt 1 IPL level or higher or - Interrupt 1 IPL is lowered to CPU IPL level or lower or - Interrupt 1 is disabled (Interrupt 1 IE bit set to `0') or - Interrupt 1 flag is cleared 3. Interrupt 2 occurs with a priority higher than Interrupt 1. EXAMPLE 5: Work around The user may disable interrupt nesting or execute a DISI instruction before modifying the CPU IPL or Interrupt 1 setting. A minimum DISI value of 2 is required if the DISI is executed immediately before the CPU IPL or Interrupt 1 is modified, as shown in Example 5. If the MPLAB C30 compiler is being used, one must inspect the Disassembly Listing in the MPLAB IDE file to determine the exact number of cycles to disable level 1-6 interrupts. One may use a large DISI value and then set the DISICNT register to zero, as shown in Example 6. A macro may also be used to perform this task, as shown in Example 7. USING DISI .include "p30fxxxx.inc" ... DISI#2 ; protect the disable of INT1 BCLRIEC1, #INT1IE; disable interrupt 1 ... ; next instruction protected by DISI EXAMPLE 6: RAISING CPU INTERRUPT PRIORITY LEVEL .include "p30fxxxx.h" ... __asm__ volatile ("DISI #0x1FFF"); SRbits.IPL = 0x5; DISICNT = 0x0; EXAMPLE 7: // protect CPU IPL modification // set CPU IPL to 5 // remove DISI protection USING MACRO #define DISI_PROTECT(X) {\ __asm__ volatile ("DISI #0x1FFF");\ X; \ DISICNT = 0; } DISI_PROTECT(SRbits.IPL = 0x5); DS80398A-page 6 // safely modify the CPU IPL (c) 2008 Microchip Technology Inc. dsPIC30F4011/4012 8. Module: DISI Instruction When a user executes a DISI #7, for example, this will disable interrupts for 7 + 1 cycles (7 + the DISI instruction itself). In this case, the DISI instruction uses a counter which counts down from 7 to 0. The counter is loaded with 7 at the end of the DISI instruction. If the user code executes another DISI on the instruction cycle where the DISI counter has become zero, the new DISI count is loaded, but the DISI state machine does not properly re-engage and continue to disable interrupts. At this point, all interrupts are enabled. The next time the user code executes a DISI instruction, the feature will act normally and block interrupts. In summary, it is only when a DISI execution is coincident with the current DISI count = 0, that the issue occurs. Executing a DISI instruction before the DISI counter reaches zero will not produce this error. In this case, the DISI counter is loaded with the new value, and interrupts remain disabled until the counter becomes zero. Work around When executing multiple DISI instructions within the source code, make sure that subsequent DISI instructions have at least one instruction cycle between the time that the DISI counter decrements to zero and the next DISI instruction. Alternatively, make sure that subsequent DISI instructions are called before the DISI counter decrements to zero. 9. Module: Output Compare in PWM Mode If the desired duty cycle is `0' (OCxRS = 0), the module will generate a high level glitch of 1 TCY. The second problem is that on the next cycle after the glitch, the OC pin does not go high, or in other words, it misses the next compare for any value written on OCxRS. Work around There are two possible solutions to this problem: 10. Module: Output Compare A glitch will be produced on an output compare pin under the following conditions: * The user software initially drives the I/O pin high using the output compare module or a write to the associated PORT register. * The output compare module is configured and enabled to drive the pin low at some later time (OCxCON = 0x0002 or OCxCON = 0x0003). When these events occur, the output compare module will drive the pin low for one instruction cycle (TCY) after the module is enabled. Work around None. However, the user may use a timer interrupt and write to the associated PORT register to control the pin manually. 11. Module: INT0, ADC and Sleep Mode ADC event triggers from the INT0 pin will not wake-up the device from Sleep mode if the SMPI bits are non-zero. This means that if the ADC is configured to generate an interrupt after a certain number of INT0 triggered conversions, the ADC conversions will not be triggered and the device will remain in Sleep. The ADC will perform conversions and wake-up the device only if it is configured to generate an interrupt after each INT0 triggered conversion (SMPI<3:0> = 0000). Work around None. If ADC event trigger from the INT0 pin is required, initialize SMPI<3:0> to `0000' (interrupt on every conversion). 12. Module: 8x PLL Mode If 8x PLL mode is used, the input frequency range is 5 MHz-10 MHz instead of 4 MHz-10 MHz. Work around None. If 8x PLL is used, make sure the input crystal or clock frequency is 5 MHz or greater. 1. Load a value greater than `0' to the OCxRS register when operating in PWM mode. In this case, no 0% duty cycle is achievable. 2. If the application requires 0% duty cycles, the output compare module can be disabled for 0% duty cycles, and re-enabled for non-zero percent duty cycles. (c) 2008 Microchip Technology Inc. DS80398A-page 7 dsPIC30F4011/4012 13. Module: 10-bit ADC: Sampling Rate The maximum sampling rate for the 10-bit Analog-to-Digital Conversion module is 750 ksps. This rate is only achievable when one A/D pin is being used. Configuring the ADC module to use multiple sample-and-hold circuits (see device data sheet), will not improve the conversion speed of the module. Table 2 shows the maximum ADC conversion rates possible using the 10-bit ADC module and the corresponding module configuration and operating conditions. TABLE 2: 10-BIT ADC RATE PARAMETERS dsPIC30F 10-bit ADC Conversion Rates A/D Speed Up to 750 ksps TAD Sampling Minimum Time Min 95.24 ns 2 TAD RS Max VDD Temperature 500 4.5V to 5.5V -40C to +85C A/D Channels Configuration VREF- VREF+ CHX ANx S/H Up to 500 ksps 153.85 ns 1 TAD 5.0 k 4.5V to 5.5V ADC -40C to +125C VREF- VREF+ or or AVSS AVDD CHX ANx S/H ADC ANx or VREF- Up to 300 ksps 256.41 ns 1 TAD 5.0 k 3.0V to 5.5V -40C to +125C VREF- VREF+ or or AVSS AVDD CHX ANx S/H ADC ANx or VREF- Work around None. DS80398A-page 8 (c) 2008 Microchip Technology Inc. dsPIC30F4011/4012 14. Module: QEI Interrupt Generation Work around The Quadrature Encoder Interface (QEI) module does not generate an interrupt when MAXCNT is set to 0xFFFF and the following events occur: To prevent this condition from occurring, set MAXCNT to 0x7FFF, which will cause an interrupt to be generated by the QEI module. 1. POSCNT underflows from 0x0000 to 0xFFFF. 2. POSCNT stops. 3. POSCNT overflows from 0xFFFF to 0x0000. In addition, a global variable could be used to keep track of bit 15, so that when an overflow or underflow condition is present on POSCNT, the variable will toggle bit 15. Example 8 shows the code required for this global variable. This sequence of events occurs when the motor is running in one direction, which causes POSCNT to underflow to 0xFFFF. Once this happens, the motor stops and starts to run in the opposite direction, which generates an overflow from 0xFFFF to 0x0000. The QEI module does not generate an interrupt when this condition occurs. EXAMPLE 8: unsigned int POSCNT_b15 = 0; unsigned int Motor_Position = 0; int main(void) { // ... User's code MAXCNT = 0x7FFF; // Instead of 0xFFFF Motor_Position = POSCNT_b15 + POSCNT; // ... User's code } void __attribute__((__interrupt__)) _QEIInterrupt(void) { IFSxbits.QEIIF = 0; // Clear QEI interrupt flag // x=2 for dsPIC30F // x=3 for dsPIC33F POSCNT_b15 ^= 0x8000; // Overflow or Underflow } (c) 2008 Microchip Technology Inc. DS80398A-page 9 dsPIC30F4011/4012 15. Module: I2C Work around 2: When the I2C module is configured as a slave, either in single-master or multi-master mode, the I2C receiver buffer is filled whether a valid slave address is detected or not. Therefore, an I2C receiver overflow condition occurs and this condition is indicated by the I2COV flag in the I2CSTAT register. Use this work around for applications in which the I2C receiver interrupt is required. Assuming that the RBF and the I2COV flags in the I2CSTAT register are set due to previous data transfers in the I2C bus (i.e., between master and other slaves); the following procedure can be used to receive valid data bytes: This overflow condition inhibits the ability to set the I2C receive interrupt flag (SI2CF) when the last valid data byte is received. Therefore, the I2C slave Interrupt Service Routine (ISR) is not called and the I2C receiver buffer is not read prior receiving the next data byte. 1. When a valid slave address byte is detected, SI2CF bit is set and the I2C slave interrupt service routine is called; however, the RBF and I2COV bits are already set due to data transfers between other I2C nodes. 2. Check the status of the D_A flag and the I2COV flag in the I2CSTAT register when executing the I2C slave service routine. 3. If the D_A flag is cleared and the I2COV flag are set, an invalid data byte was received but a valid address byte was received. The overflow condition occurred because the I2C receive buffer was overflowing with previous I2C data transfers between other I2C nodes. This condition only occurs after a valid slave address was detected. 4. Clear the I2COV flag and perform a dummy read of the I2C receiver buffer, I2CRCV, to clear the RBF bit and recover the valid address byte. This action will also avoid the loss of the next data byte due to an overflow condition. 5. Verify that the recovered address byte matches the current slave address byte. If they match, the next data to be received is a valid data byte. 6. If the D_A flag and the I2COV flag are both set, a valid data byte was received and a previous valid data byte was lost. It will be necessary to code for handling this overflow condition. Work arounds To avoid this issue, either of the following two work arounds can be implemented, depending on the application requirements. Work around 1: For applications in which the I2C receiver interrupt is not required, the following procedure can be used to receive valid data bytes: 1. Wait until the RBF flag is set. 2. Poll the I2C receiver interrupt SI2CIF flag. 3. If SI2CF is not set in the corresponding Interrupt Flag Status (IFSx) register, a valid address or data byte has not been received for the current slave. Execute a dummy read of the I2C receiver buffer, I2CRCV; this will clear the RBF flag. Go back to step 1 until SI2CF is set and then continue to Step 4. 4. If the SI2CF is set in the corresponding Interrupt Flag Status (IFSx) register, valid data has been received. Check the D_A flag to verify that an address or a data byte has been received. 5. Read the I2CRCV buffer to recover valid data bytes. This will also clear the RBF flag. 6. Clear the I2C receiver interrupt flag SI2CF. 7. Go back to step 1 to continue receiving incoming data bytes. DS80398A-page 10 (c) 2008 Microchip Technology Inc. dsPIC30F4011/4012 16. Module: I2C 19. Module: I2C If there are two I2C devices on the bus, one of them is acting as the Master receiver and the other as the Slave transmitter. If both devices are configured for 10-bit addressing mode, and have the same value in the A10 and A9 bits of their addresses, then when the Slave select address is sent from the Master, both the Master and Slave acknowledge it. When the Master sends out the read operation, both the Master and the Slave enter into Read mode and both of them transmit the data. The resultant data will be the ANDing of the two transmissions. When the I2C module is enabled by setting the I2CEN bit in the I2CCON register, the dsPIC DSC device generates a glitch on the SDA and SCL pins. This glitch falsely indicates "Communication Start" to all devices on the I2C bus, and can cause a bus collision in a multi-master configuration. Work around To avoid this issue, either of the following two work arounds can be implemented, depending on the application requirements. In all I2C devices, the addresses as well as bits A10 and A9 should be different. 17. Module: I2C In 10-bit Addressing mode, some address matches don't set the RBF flag or load the receive register I2CxRCV, if the lower address byte matches the reserved addresses. In particular, these include all addresses with the form XX0000XXXX and XX1111XXXX, with the following exceptions: * * * * 001111000X 011111001X 101111010X 111111011X Work around Ensure that the lower address byte in 10-bit Addressing mode does not match any 7-bit reserved addresses. 18. Module: I2C When the I2C module is configured as a 10-bit slave with and address of 0x102, the I2CxRCV register content for the lower address byte is 0x01 rather than 0x02; however, the module acknowledges both address bytes. Work around None. (c) 2008 Microchip Technology Inc. Additionally, when the I2CEN bit is set, the S and P bits of the I2C module are set to values `1' and `0', respectively, which indicate a "Communication Start" condition. Work arounds Work around 1: In a single-master environment, add a delay between enabling the I2C module and the first data transmission. The delay should be equal to or greater than the time it takes to transmit two data bits. In the multi-master configuration, in addition to the delay, all other I2C masters should be synchronized and wait for the I2C module to be initialized before initiating any kind of communication. Work around 2: In dsPIC DSC devices in which the I2C module is multiplexed with other modules that have precedence in the use of the pin, it is possible to avoid this glitch by enabling the higher priority module before enabling the I2C module. Use the following procedure to implement this work around: 1. Enable the higher priority peripheral module that is multiplexed on the same pins as the I2C module. 2. Set up and enable the I2C module. Disable the higher priority peripheral module that was enabled in step 1. Note: Work around 2 works only for devices that share the SDA and SCL pins with another peripheral that has a higher precedence over the port latch, such as the UART. The priority is shown in the pin diagram located in the data sheet. For example, if the SDA and SCL pins are shared with the UART and SPI pins, and the UART has higher precedence on the port latch pin. DS80398A-page 11 dsPIC30F4011/4012 20. Module: Motor Control PWM - PWM Counter Register If the PTDIR bit is set (when PTMR is counting down), and the CPU execution is halted (after a breakpoint is reached), PTMR will start counting up as if PTDIR was zero. Work around None. 21. Module: I/O Port - Port Pin Multiplexed with IC1 If the user application enables the auto-baud feature in the UART module, the I/O pin multiplexed with the IC1 (Input Capture) pin cannot be used as a digital input. Work around None. 22. Module: Timer When the timer is being operated in Asynchronous mode using the secondary oscillator (32.768 kHz) and the device is put into Sleep mode, a clock switch to any other oscillator mode before putting the device to Sleep prevents the timer from waking the device from Sleep. Work around Do not clock switch to any other oscillator mode if the timer is being used in Asynchronous mode using the secondary oscillator (32.768 kHz). DS80398A-page 12 23. Module: PLL Lock Status Bit The PLL LOCK Status bit (OSCCON<5>) can occasionally get cleared and generate an oscillator failure trap even when the PLL is still locked and functioning correctly. Work around The user application must include an oscillator failure trap service routine. In the trap service routine, first inspect the status of the Clock Failure Status bit (OSCCON<3>). If this bit is clear, return from the trap service routine immediately and continue program execution. 24. Module: PSV Operations An address error trap occurs in certain addressing modes when accessing the first four bytes of an PSV page. This only occurs when using the following addressing modes: * MOV.D * Register Indirect Addressing (word or byte mode) with pre/post-decrement Work around Do not perform PSV accesses to any of the first four bytes using the above addressing modes. For applications using the C language, MPLAB C30 version 3.11 or higher, provides the following command-line switch that implements a work around for the erratum. -merrata=psv_trap Refer to the readme.txt file in the MPLAB C30 v3.11 tool suite for further details. (c) 2008 Microchip Technology Inc. dsPIC30F4011/4012 APPENDIX A: REVISION HISTORY Revision A (9/2008) Initial version of this document. (c) 2008 Microchip Technology Inc. DS80398A-page 13 dsPIC30F4011/4012 NOTES: DS80398A-page 14 (c) 2008 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: * Microchip products meet the specification contained in their particular Microchip Data Sheet. * Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. * There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. * Microchip is willing to work with the customer who is concerned about the integrity of their code. * Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC, SmartShunt and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM, PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2008, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. (c) 2008 Microchip Technology Inc. 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