DSPIC30F4011-20E/ML - Microchip Technology

dsPIC30F4011/4012

The dsPIC30F4011/4012 (Rev. A4) samples that you

have received were found to conform to the

specifications and functionality described in the

following documents:

• DS70157 – “dsPI C30F/33F Progr ammer’s

Reference Manual”

• DS70141 – “dsPIC30F3010/3011 Data Sheet”

• DS7004 6 – “ds PIC30F Family Re fere nc e Ma nua l”

The exceptions to the specifications in the documents

listed above are described in this section. These

exceptions are described for the specific devices listed

below:

•dsPIC30F4011

• dsPIC30F4012

These devices may be identified by the following

message that appears in the MPLAB® ICD 2 Output

Window under MPLAB IDE, when a “Reset and

Connect” operation is performed within MPLAB IDE:

Setting Vdd source to target

Target Device dsPIC30F3011 found,

revision = Rev 0x1004

...Reading ICD Product ID

Running ICD Self Test

...Passed

MPLAB ICD 2 Ready

The errata described in this section will be addressed

in future revisions of dsPIC30F4011 and

dsPIC30F4012 devices.

Silicon Errata Summary

The following list summarizes the errata described in

further detail throughout the remainder of this

document:

1. MAC Class Instructions with ±4 Address

Modification

Sequential MAC instructions, which prefetch data

from Y data space us ing ±4 addr ess modi fic ati on,

will cause an address error trap.

2. Decimal Adjust Inst ruction

The Decimal Adjust instruction, DAW.b, may

improperly clear the Carry bit, C (SR<0>).

3. Special Function Registers

Writes to certain unimplemented address locations

can affect I/O Port register values.

4. PSV Operations Using SR

In certain instructions, fetching one of the

operands from program memory using Program

Space Visibility (PSV) will corrupt specific bits in

the STATUS Register, SR.

5. Early Termination of Nested DO loops

When using two DO loops in a nested fashion,

terminating the inner-level DO loop by setting the

EDT (CORCON<11>) bit will produce unexpected

results.

6. 4x PLL Operation

The 4x PLL mode of operation may not function

correctly for certain input frequencies.

7. Sequential Interrupts

Sequenti al i nterrupt s after modifying the CPU IPL,

interrupt IPL, interrupt enabl e o r int errup t fl ag may

cause an address error trap.

8. DISI Instruction

The DISI instruction will not disable interrupts if a

DISI instruction is executed in the same

instruction cycle that the DISI counter

dec rements to zero.

9. Output Compare Module in PWM Mode

Output compare will produce a glitch when

loading 0% duty cycle in PWM mode. It will also

miss the next compare after the glitch.

dsPIC30F4011/4012 Rev. A4 Silicon Errata

dsPIC30F4011/4012

10. Output Co mpare Modul e

The output compare module will produce a glitch

on the output when an I/O pin is initially set high

and t he module i s configured to drive the p in low at

a specified time.

11. INT0, ADC and Sleep Mode

ADC event triggers from the INT0 pin will not

wake-up the device from Sleep mode if the SMPI

bits are non-zero.

12. 8x PLL Mode

If 8x PLL mo de is used, the input freque nc y rang e

is 5 MHz-10 MHz instead of 4 MHz-10 MHz.

13. 10-bit ADC: Sampling Rate

The 10-bit Analog-to-Digital Converter (ADC) has

a maximum sampling rate of 750 ksps.

14. Quadrat ure Enc ode r Interfac e (QEI ) Modul e

The QEI module does not generate an interrupt in

a particular ove rflow condition.

15. I2C™ Module

The I2C module loses incoming data bytes when

operating as an I2C slave.

16. I2C Modul e: 10-bit Ad dressing Mode

When the I2C module is configured for 10-bit

addressing using the same address bits (A10 and

A9) as othe r I2C devic es, th e A10 and A9 bit s ma y

not work as expe cted.

17. I2C Modul e: 10-bit Ad dressing Mode

The 10-bit slave does not set the RBF flag or load

the I2CxRCV register on address match if the least

significant bits of the address are the s ame as the

7-bit reserved addresses.

18. I2C Module: 10-bit Addressing Mode

When the I2C module is configured as a 10-bit

slave with an address of 0x102, the I2CxRCV

rather than 0x02.

19. I2C Module

When t he I2C mo dule is enabl ed, the dsPI C® DSC

device generates a glitch on the SDA and SCL

pins, causing a false communication start in a

single-master configuration or a bus collision in a

multi-master configuration.

20. Motor Control PWM – PWM Counter Register

PTMR does not continue counting down after

halting code execution in Debug mode.

21. I/O Port – Port Pin Multiplexed with IC1

The Port I/O pin multiplex ed with the Input Ca pture

1 (IC1) function cannot be used as a digital input

pin when the UART auto-baud feature is enabled.

22. Timer Module

Clock switching prevents the device from waking

up from Sleep.

23. PLL Lock Status Bit

The PLL LOCK Status bit (OSCCON<5>) can

occasionally get cleared and generate an

oscillator failure trap even when the PLL is still

locked and functioning correctly.

24. PSV Operations

An addre ss e rror trap o cc urs i n certain a ddr ess in g

modes when accessing the first four bytes of any

PSV page.

The following sections describe the errata and work

around to these errata, where they may apply.

dsPIC30F4011/4012

1. Module: MAC Class Instructions with ±4

Address Modification

Sequential MAC class instructions, which prefetch

data from Y data space using ±4 address

modificat ion , w il l caus e a n a ddre ss error trap. The

trap occurs only when all of the following

conditions are true:

1. Two sequential MAC class instructions (or a

MAC class in struction executed in a REPEAT or

DO loop) that prefetch from Y data space.

2. Both instructions prefetch data from Y data

space using the + = 4 or - = 4 address

modification.

3. Neither of the instruction uses an accumulator

write back.

Work around

The problem described above can be avoided by

using any of the following methods:

1. Insertin g any oth er instructio n betwe en the two

MAC class in st r uc tion s.

2. Adding an accumulator write back (a dummy

write ba ck if needed) to e ith er of the MAC cl as s

instructions.

3. Do not use the + = 4 or - = 4 address

modification.

4. Do not prefetch data from Y data space.

2. Module: CPU – DAW.b Instruction

The Decimal Adjust instruction, DAW.b, may

improperly clear the Carry bit, C (SR<0>), when

executed.

Work around

Check the state of the Carry bit prior to executing

the DAW.b instruct ion. If the Carry bit is set, set the

Carry bit again after executing the DAW.b

instruction. Example 1 shows how the application

should process the Carry bit during a BCD addition

operation.

EXAMPLE 1: CHECK CARRY BIT BEFORE

DAW.b

3. Module: Special Function Registers

The I/O Port register values can be changed by

writing to the following address locations, which

are located in unimplemented memory space. A

write to these unimplemented addresses could

cause an I/O pin configured as an output to

change states. This state change could be

confirmed by reading either the PORT or LAT

PORTB will be modified by a write to address

0x0C8

PORTC will be modified by a write to address

0x0CE

PORTD will be modified by a write to address

0x0D4

PORTE will be modified by a write to address

0x0DA

PORTF will be modified by a write to address

0x0E0

Work around

User software should avoid writing to the

unimplemented locations listed above.

.include “p30fxxxx.inc”

.......

MOV.b #0x80, w0 ;First BCD number

MOV.b #0x80, w1 ;Second BCD number

ADD.b w0, w1, w2 ;Perform addition

BRA NC, L0 ;If C set go to L0

DAW.b w2 ;If not,do DAW and

BSET.b SR, #C ;set the carry bit

BRA L1 ;and exit

L0:DAW.b w2

L1: ....

dsPIC30F4011/4012

4. Module: PSV Operations Using SR

When one of the ope rands of ins tructions sh own in

Table 1 is fetched from program memory using

Program Space Visibility (PSV), the STATUS

These instructions are identified in Table 1.

Example 2 demonstrates one scenario where this

occurs.

Also, always use Work around 2 if the C compiler

is used to generate code for dsPIC30F4011/4012

devices.

EXAMPLE 2: INCORRECT RESULT S

Work around s

Work around 1: For Assembly Language

Source Code

To work around t he erratum i n the M PLAB ASM30

assembler, the application may perform a PSV

access to move the source operand from program

memory to RAM or a W regi ster prior t o performing

the operations listed in Table 1. The work around

for Example 2 is demonstrated in Example 3.

EXAMPLE 3: CORRECT RESULT S

Work around 2: For C Language Source Code

For applications using C language, MPLAB C30

versions 1.20.04 or higher provide the following

command-line switch that implements a work

around for the erratum.

-merrata=psv

Refer to the “readme.txt” file in the M PLAB C30

v1.20.04 toolsuite for further details.

TABLE 1: AFFECTED INSTRUCTIONS

Instruction(1) Examples of Incorrect Operation(2) Data Corruption IN

ADDC ADDC W0, [W1++], W2 ; SR<1:0> bit s(3), Result in W2

SUBB SUBB.b W0, [++W1], W3 ; SR<1:0> bit s(3), Result in W3

SUBBR SUBBR.b W0, [++W1], W3 ; SR<1:0> bit s(3), Result in W3

CPB CPB W0, [W1++], W4 ; SR<1:0> bit s(3)

RLC RLC [W1], W4 ; SR<1:0> bit s(3), Result in W4

RRC RRC [W1], W2 ; SR<1:0> bit s(3), Result in W2

ADD (Accumula tor-b as ed) ADD [W1++], A ; SR<1:0> bit s(3)

LAC LAC [W1], A ; SR<15:10> bits(4)

Note 1: Refer to the “dsPIC30F/33F Programmer’s Reference Manual” (DS70157) for details on the dsPIC30F

instr uction set.

2: The errata only affects these instructions when a PSV access is performed to fetch one of the source

operands in the in struction . A PSV a ccess is pe rformed wh en the Ef fectiv e Addre ss o f the source o perand

is greater than 0x8000 and the PSV (CORCON<2>) bit is set to ‘1’. In the examples shown, the data

access from program memory is made via the W1 register.

3: SR< 1:0> b its represent Sticky Zero an d Carry Status bits, respectively.

4: SR<15:10> bits represent Accumulator Overflow and Saturation Status bits.

.include “p30fxxxx.inc”

.......

MOV.B #0x00, W0 ;Load PSVPAG register

MOV.B WREG, PSVPAG

BSET CORCON, #PSV ;Enable PSV

....

MOV #0x8200, W1 ;Set up W1 for

;indirect PSV access

;from 0x000200

ADD W3, [W1++], W5 ;This instruction

;works ok

ADDC W4, [W1++], W6 ;Carry flag and

;W6 gets

;corrupted here!

.include “p30fxxxx.inc”

.......

MOV.B #0x00, w0 ;Load PSVPAG register

MOV.B WREG, PSVPAG

BSET CORCON, #PSV ;Enable PSV

....

MOV #0x8200, W1 ;Set up W1 for

;indirect PSV access

;from 0x000200

ADD W3, [W1 ++], W5 ;This instruction

;works ok

MOV [W1++], W2 ;Load W2 with data

;from program memory

ADDC W4, W2, W6 ;Carry flag and W4

;results are ok!

dsPIC30F4011/4012

5. Module: Early Termination of Nested DO

Loops

When using two DO loops in a nested fashion,

terminating the inner-level DO loop by setting the

EDT (CORCON<11>) bit will produce unexpected

results. Specifically, the device may continue

executing code within the outer DO loop forever.

This erratum does not affect the operation of the

MPLAB C30 compiler.

Work around

The application should save the DCOUNT SFR

prior to entering the inner DO loop and restore it

upon exiting the inner DO loop . This wo rk around is

shown in Example 4.

EXAMPLE 4: SAVE AND RESTORE

DCOUNT

6. Module: 4x PLL Operation

When the 4x PLL mode of operation is selected,

the speci fied inp ut frequency rang e of 4-10 MHz is

not fully supported.

When device VDD is 2.5-3.0V, the 4x PLL input

frequenc y m us t be in th e range of 4-5 MHz . When

devi ce VDD is 3.0-3.6V , the 4x PLL input frequency

must be in the range of 4-6 MHz for both ind ustria l

and extended temperature ranges.

Work around

1. Use 8x PLL or 1 6x PLL m ode of op eration an d

set final device clock speed using the

POST<1:0> oscillator postscaler control bits

(OSCCON<7:6>).

2. Use the EC without PLL Clock mode with a

suitable clock frequency to obtain the equivalent

4x PLL clock rate.

.include “p30fxxxx.inc”

.......

DO #CNT1, LOOP0 ;Outer loop start

....

PUSH DCOUNT ;Save DCOUNT

DO #CNT2, LOOP1 ;Inner loop

.... ;starts

BTSS Flag, #0

BSET CORCON, #EDT ;Terminate inner

.... ;DO-loop early

....

LOOP1: MOV W1, W5 ;Inner loop ends

POP DCOUNT ;Restore DCOUNT

...

LOOP0: MOV W5, W8 ;Outer loop ends

Note: For details on the functionality of

EDT bit, see section 2.9.2.4

in the dsPIC30F Family Reference

Manual.

dsPIC30F4011/4012

7. Module: Interrupt Controlle r – Sequential

Interrupts

When interrupt nesting is enabled (or NSTDIS

(INTCON1<15>) bit is ‘0’), the follow i ng se qu enc e

of events will lead to an address error trap. The

generic terms “Interrupt 1” and “Interrupt 2” are

used to represent any two enabled dsPIC30F

interrupts.

1. Inte rrupt 1 processing begins.

2. Interrupt 1 is negated by user software by one

of the following methods:

- CPU IPL is raised to Interrupt 1 IPL level or

higher or

- Interrupt 1 IPL is lo were d to CPU IPL le ve l or

lower or

- Interrupt 1 is disabled (Interrupt 1 IE bit set

to ‘0’) or

- Interrupt 1 flag is cleared

3. Interrupt 2 occurs with a priority higher than

Interrupt 1.

Work around

The user may disable interrupt nesting or execute

a DISI instruction before modifying the CPU IPL

or Interrupt 1 setting. A minimum DISI value of 2

is required if the DISI is executed immediately

before the CPU IPL or Interrupt 1 is modified, as

shown in Example 5. If the MPLAB C30 compiler

is being used, one must inspect the Disassembly

Listing in the MPLAB IDE file to determine the

exact number of cycles to disable level 1-6

interrupts. One may use a large DISI value and

then se t the DISI CNT reg ister to z ero, a s shown i n

Example 6. A macro may also be used to perform

this task, as shown in Example 7.

EXAMPLE 5: USING DISI

EXAMPLE 6: RAISING CPU INTERRUPT PRIORI TY LEVEL

EXAMPLE 7: USING MACRO

.include “p30fxxxx.inc”

...

DISI#2 ; protect the disable of INT1

BCLRIEC1, #INT1IE; disable interrupt 1

... ; next instruction protected by DISI

.include “p30fxxxx.h”

...

__asm__ volatile (“DISI #0x1FFF”); // protect CPU IPL modification

SRbits.IPL = 0x5; // set CPU IPL to 5

DISICNT = 0x0; // remove DISI protection

#define DISI_PROTECT(X) {\

__asm__ volatile (“DISI #0x1FFF”);\

X; \

DISICNT = 0; }

DISI_PROTECT(SRbits.IPL = 0x5); // safely modify the CPU IPL

dsPIC30F4011/4012

8. Module: DISI Instruction

When a user executes a DISI #7, for example,

this will disable interrupts for 7 + 1 cycles (7 + the

DISI instruction itself). In this case, the DISI

instruc tion uses a c ounter which co unts dow n from

7 to 0. The counter is loaded with 7 at the end of

the DISI instruction.

If the user code executes another DISI on the

instruction cycle where the DISI counter has

become zero, the new DISI count is loaded, but

the DISI state machine does not properly

re-engage and continue to disable interrupts. At

this po in t, all in terru pt s are enab led . T he nex t tim e

the user code executes a DISI instruction, the

feature will act normally and block interrupts.

In summary, it is only when a DISI execution is

coincident with the current DISI count = 0, that

the issue occurs. Executing a DISI instruction

before the DISI counter reaches zero will not

produce this error. In this case, the DISI counter

is loaded with the new value, and interrupts

remain dis abled until the co unte r beco me s zero .

Work around

When ex ecuting multiple DISI inst ructions wi thin

the sou rce code, make sure that subs equent DISI

instructions have at least one instruction cycle

between the time that the DISI counter

decr em ent s to ze ro and the n ex t DISI instruction.

Alternatively, make sure that subsequent DISI

instructions are called before the DISI counter

decrements to zero.

9. Module: Output Compare in PWM Mode

If the desired duty cycle is ‘0’ (OCxRS = 0), the

module will generate a high level glitch of 1 TCY.

The seco nd problem is that o n the nex t cy cl e after

the glitch, the OC pin does not go hi gh, or in other

words, it misses the next compare for any value

written on OCxRS.

Work around

There are two possible solutions to this problem:

1. Load a value greater than ‘0’ to the OCxRS

case, no 0% duty cycle is achievable.

2. If the application requires 0% duty cycles, the

output compare module can be disabled

for 0% duty cycles, and re-enabled for

non-zero percent duty cycles.

10. Module: Output Compare

A glitch will be produced on an outpu t comp are pin

under the foll owing conditions:

• The user software initially drives the I/O pin

high using the outp ut com p a r e module or a

write to the associated PORT register.

• The output compare module is configured and

enabled to drive the pin low at some later time

(OCxCON = 0x0002 or OCxCON = 0x0003).

When these events occur, the output compare

module will drive the pin low for one instruction

cycle (TCY) after the module is enabled.

Work around

None. However , the user may use a timer interrupt

and write to the associated PORT register to

control the pin manuall y.

11. Module: INT0, ADC and Sleep Mode

ADC event triggers from the INT0 pin will not

wake-up the device from Sleep mode if the SMPI

bits are non-zero. This means that if the ADC is

configured to generate an interrupt after a certain

number of INT0 triggered conversions, the ADC

conversions will not be triggered and the device

will remain in Sleep. The ADC will perform

conversions and wake-up the device only if it is

configured to generate an interrupt after each INT0

triggered conversion (SMPI<3:0> = 0000).

Work around

None. If ADC event trigger from the INT0 pin is

required, initialize SMPI<3:0> to ‘0000’ (interrupt

on every conversion).

12. Module: 8x PLL Mode

If 8x PLL mode is used , the in put fre que nc y rang e

is 5 MHz-10 MHz instead of 4 MHz-10 MHz.

Work around

None. If 8x PLL is used, make sure the input

crystal or clock frequency is 5 MHz or greater.

dsPIC30F4011/4012

13. Module: 10-bit ADC: Sampling Rate

The maximum sampling rate for the 10-bit

Analog-to - Digi t al C onv ers io n mo dul e i s 75 0 k sp s .

This rate is only achievable when one A/D pin is

being used. Configuring the ADC module to use

multipl e sample -and-ho ld circ uit s (see dev ice dat a

sheet), will not improve the conversion speed of

the module.

Table 2 shows the maximum ADC conversion

rates possible using the 10-bit ADC module and

the corresponding module configuration and

operating conditions.

Work around

None.

TABLE 2: 10-BIT ADC RATE PARAMETERS

dsPIC30F 10-bit ADC Conversion Rates

A/D Speed TAD

Minimum Sampling

Time Min RS Max VDD Temperature A/D Channels Configuration

Up to

750 ksps 95.24 ns 2 TAD 500Ω4.5V to 5.5V -40°C to +85°C

Up to

500 ksps 153.85 ns 1 TAD 5.0 kΩ4.5V to 5.5V -40°C to +125°C

Up to

300 ksps 256.41 ns 1 TAD 5.0 kΩ3.0V to 5.5V -40°C to +125°C

REF

-V

REF

ADC

ANx S/H CH

REF

-V

REF

ADC

ANx S/H CH

ANx or V

REF

-V

REF

ADC

ANx S/H CH

ANx or V

REF

dsPIC30F4011/4012

14. Module: QEI Interrupt Generation

The Quadrature Encoder Interface (QEI) module

does not generate an interrupt when MAXCNT is

set to 0xFFFF and the following events occur:

1. POSCNT underflows from 0x0000 to 0xFFFF.

2. POSCNT stops.

3. POSCNT overflows from 0xFFFF to 0x0000.

This se quenc e of eve nts occur s whe n the mo tor is

running in one direction, which causes POSCNT to

underflow to 0xFFFF. Once this happens, the

motor stops and starts to run in the opposite

direction, which generates an overflow from

0xFFFF to 0x0000. The QEI module does not

generate an interrupt when this condition occurs.

Work around

To prevent this condition from occurring, set

MAXCNT to 0x7FFF, which will cause an interrupt

to be generated by the QEI module.

In additi on, a global variable could be used to keep

track of bit 15, so that when an overflow or

underflow condition is present on POSCNT, the

variable will toggle bit 15. Example 8 shows the

code required for this global variable.

EXAMPLE 8:

unsigned int POSCNT_b15 = 0;

unsigned int Motor_Position = 0;

int main(void)

{// ... User's code

MAXCNT = 0x7FFF; // Instead of 0xFFFF

Motor_Position = POSCNT_b15 + POSCNT;

// ... User's code

}

void __attribute__((__interrupt__)) _QEIInterrupt(void)

{IFSxbits.QEIIF = 0; // Clear QEI interrupt flag

// x=2 for dsPIC30F

// x=3 for dsPIC33F

POSCNT_b15 ^= 0x8000; // Overflow or Underflow

}

dsPIC30F4011/4012

15. Module: I2C

When the I2C module is configured as a slave,

either in single-master or multi-master mode, the

I2C receiver buffer is filled whether a valid slave

address is detected or not. Therefore, an I2C

receiver overflow condition occurs and this

condition is indicated by the I2COV flag in the

I2CSTAT registe r.

This ov erflow conditio n inhibit s the ability to set the

I2C receive interrupt flag (SI2CF) when the last

valid data byte is received. Therefore, the I2C

slave Interrupt Service Routine (ISR) is not called

and the I2C receiver buffer is not read prior

receiving the next data byte.

Work around s

To avoid this i ssue, eithe r of the following two work

arounds can be implemented, depending on the

application requirements.

Work around 1:

For appli ca tions in wh ic h th e I2C re ceive r in terru pt

is not required, the following procedure can be

used to receive valid data bytes:

1. Wait until the RBF flag is set.

2. Poll the I2C receiver interrupt SI2CIF flag.

3. If SI2CF is not set in the corresponding

Interrupt Flag Status (IFSx) register, a valid

address or da t a byte h as no t been re ceive d for

the current slave. Execute a dummy read of

the I2C receiver buffer, I2CRCV; this will cl ear

the RBF flag. Go back to step 1 until SI2CF is

set and then continue to Step 4.

4. If the SI2CF is set in the corresponding

Interrupt Flag Status (IFSx) register, valid data

has been received. Check the D_A flag to

verify that an address or a data byte has been

received.

5. Read th e I2CRCV b uffer to re cover va lid data

bytes. This will also clear the RBF flag.

6. Clear the I2C receiver interrupt flag SI2CF.

7. Go back to step 1 to continue receiving

incoming data bytes.

Work around 2:

Use this work around for applications in which the

I2C receiver interrupt is required. Assuming that

the RBF and the I2COV flags in the I2CSTAT

the I2C bus (i.e., between master and other

slaves); the following procedure can be used to

receive valid data bytes:

1. When a valid slave address byte is detected,

SI2CF bit is set and the I2C slave interrupt

service routine is called; howeve r, the RBF and

I2COV bits are already set due to data

transfers between other I2C nodes.

2. Check the status of the D_A flag and the

I2COV flag in the I2CSTAT register when

executing the I2C slave service routine.

3. If the D_A flag is cleared and the I2COV flag

are se t, an i nvalid data byte wa s recei ved but a

valid add res s by te was rec ei ved . The ov erfl ow

condition occurred because the I2C receive

buffer was overflowing with previous I2C data

transfers between other I2C nodes. This

condition only occurs after a valid slave

address was detected.

4. Clear the I2COV flag and perform a dummy

read of the I2C receiver buffer, I2CRCV, to

clear the RBF bit and recov er the valid a ddress

byte. This action will also avoid the loss of the

next data byte due to an overflow condition.

5. Verify that the recovered address byte

matche s the current slave ad dress byte. If they

match, the next data to be received is a valid

data by te.

6. If the D_A fl ag and the I2COV fl ag are both se t,

a valid data byte was received and a previous

valid dat a byte was lost. It will be neces sa ry to

code for handling this overflow condition.

dsPIC30F4011/4012

16. Module: I2C

If there are two I2C devices on the bus, one of

them is acting as t he Master receiv er and the oth er

as the Sl ave transmitter. If both devices are config-

ured for 10-bit addressing mode, and have the

same value in the A10 and A9 bits of their

addresses, then when the Slave select address is

sent from the Master, both the Master and Slave

acknowledge it. When the Master sends out the

read operation, both the Master and the Slave

enter into Read mode and both of them transmit

the data. The resultant data will be the ANDing of

the two transmissions.

Work around

In all I2C devices, the addresses as well as bits

A10 and A9 should be different.

17. Module: I2C

In 10-bit Addressing mode, some address

matche s d on' t s et the RB F fl ag o r lo ad the rec eive

matches the reserved addresses. In particular,

these include all addresses with the form

XX0000XXXX and XX1111XXXX, with the

following exceptions:

• 001111000X

• 011111001X

• 101111010X

• 111111011X

Work around

Ensure that the lower address byte in 10-bit

Addressing mode does not match any 7-bit

reserved addresses.

18. Module: I2C

When the I2C module is configured as a 10-bit

slave with and address of 0x102, the I2CxRCV

rather than 0x02; however, the module

acknowledges both address bytes.

Work around

None.

19. Module: I2C

When the I2C module is enabled by setting the

I2CEN bit in the I2CCON register, the dsPIC DSC

device generates a glitch on the SDA and SCL

pins. This glitch falsely indicates “Communication

Start” to all de vi ces on th e I2C bus , an d c an cause

a bus collision in a multi-master configuration.

Additionally, when the I2CEN bit is set, the S and

P bits of the I2C modul e are s et to va lues ‘1’ and

‘0’, respectively, which indicate a “Communication

Start” condition.

Work arounds

To avoid this i ssue, ei ther of the following t wo wor k

arounds can be implemented, depending on the

application requirements.

Work around 1:

In a single-master environment, add a delay

between enabling the I2C module and the first dat a

transmission. The delay should be equal to or

greater than the time it takes to transmit two data

bits.

In the mult i-mas ter confi guratio n, in add ition to th e

delay, all other I2C masters should be synchro-

nized and wait for the I2C module to be initialized

before initiating any kind of communication.

Work around 2:

In dsPIC DSC devices in which the I2C module is

multiplexed with other modules that have

precedence in the use of the pin, it is possible to

avoid this glitch by enabling the higher priority

module before enabling the I2C module.

Use the following procedure to implement this

work around:

1. Enable the higher priority peripheral module

that is mu ltiple xe d on the sa me pin s as the I2C

module.

2. Set up and enable the I2C module.

Disable the higher priority peripheral module that

was enabled in s tep 1.

Note: W ork aro un d 2 w ork s onl y for dev ic es th at

share the SDA and SCL pins with another

peripheral that has a higher precedence

over the port latc h, such as the UAR T. The

priority is shown in the pin diagram locate d

in the dat a s hee t. Fo r exa mp le, if the SDA

and SCL pins are shared with the UART

and SPI pins, and the UART has higher

precedence on the port latch pin.

dsPIC30F4011/4012

20. Module: Motor Control PWM – PWM

Counter Register

If the PTDIR bit is set (when PTMR is counting

down), and the CPU execution is halted (after a

breakpoint is reached), PTMR will start counting

up as if PTDIR was zero.

Work around

None.

21. Module: I/O Port – Port Pin Multiplexed

with IC1

If the user application enables the auto-baud

feature in the UART module, the I/O pin

multiplexed with the IC1 (Input Capture) pin cannot

be used as a digital input.

Work around

None.

22. Module: Timer

When the timer is being o perated in Asy nchronous

mode using the secondary oscillator (32.768 kHz)

and the device is put into Sleep mode, a clock

switch to any other oscillator mode before putting

the devi ce to Sleep prev ents the t imer from wakin g

the device from Sleep.

Work around

Do not clock switch to any other oscillator mode if

the timer is being used in Asynchronous mode

using the secondary oscillator (32.768 kHz).

23. Module: PLL Lock Status Bit

The PLL LOCK Status bit (OSCCON<5>) can

occasionally get cleared and generate an

oscillator failure trap even when the PLL is still

locked and functioning correctly.

Work around

The user application must include an oscillator

failure trap service routine. In the trap service

routine, firs t inspec t the st atus of the Cloc k Failu re

Status bit (OSCCON<3>). If this bit is clear, return

from the trap service routine immediately and

continue program execution.

24. Module: PSV Opera tions

An addre ss e rror trap o cc urs i n certain a ddr ess in g

modes when accessing the first four bytes of an

PSV page. This only occurs when using the

following addressing modes:

•MOV.D

• Register Indirect Addressing (word or byte

mode) with pre/ pos t-de cre me nt

Work around

Do not perform PSV accesses to any of the first

four byt es using the a bove addres sing modes . For

applications using the C language, MPLAB C30

version 3.11 or higher, provides the following

command-line switch that implements a work

around for the erratum.

-merrata=psv_trap

Refer to the readme.txt file in the MPLAB C30

v3.11 tool suite for further details.

dsPIC30F4011/4012

APPENDIX A: REVISION HISTORY

Revision A (9/2008)

Initial version of this document.

dsPIC30F4011/4012

NOTES:

Information contained in this publication regarding device

applications a nd t he like is p rovided only for your convenience

and may be su persed ed by upda te s . I t is y our respo nsibility to

ensure that your application meets with your specifications.

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Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,

PICSTA RT, rfPI C, SmartS hunt and UNI/O are registered

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Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

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Code protection is c onstantly evolving. We a t Microc hip are co m mitted to continuously improving the code prot ect ion featur es of our

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