1
Features
•Low-voltage and Standard-voltage Operation
–2.7 (V
CC = 2.7V to 5.5V)
–1.8 (V
CC = 1.8V to 5.5V)
•User-selectable Internal Organization
– 1K: 128 x 8 or 64 x 16
– 2K: 256 x 8 or 128 x 16
– 4K: 512 x 8 or 256 x 16
•Three-wire Serial Interface
•2 MHz Clock Rate (5V)
•Self-timed Write Cycle (10 ms max)
•High Reliability
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
•Automotive Grade, Extended Temperature and Lead-Free/Halogen-Free
Devices Available
•8-lead PDIP, 8-lead JEDEC SOIC, 8-lead EIAJ SOIC, 8-lead MAP, 8-lead TSSOP,
and 8-ball dBGA2™ Packages
Description
The AT93C46/56/66 provides 1024/2048/4096 bits of serial electrically erasable pro-
grammable read-only memory (EEPROM), organized as 64/128/256 words of 16 bits
each (when the ORG pin is connected to VCC), and 128/256/512 words of 8 bits each
(when the ORG pin is tied to ground). The device is optimized for use in many indus-
trial and commercial applications where low-power and low-voltage operations are
essential. The AT93C46/56/66 is available in space-saving 8-lead PDIP, 8-lead
JEDEC SOIC, 8-lead EIAJ SOIC, 8-lead MAP, 8-lead TSSOP, and 8-lead dBGA2™
packages.
The AT93C46/56/66 is enabled through the Chip Select pin (CS) and accessed via a
three-wire serial interface consisting of Data Input (DI), Data Output (DO), and Shift
Clock (SK). Upon receiving a Read instruction at DI, the address is decoded and the
data is clocked out serially on the DO pin. The Write cycle is completely self-timed,
and no separate Erase cycle is required before Write. The Write cycle is only enabled
when the part is in the Erase/Write Enable state. When CS is brought high following
the initiation of a Write cycle, the DO pin outputs the Ready/Busy status of the part.
The AT93C46/56/66 is available in 2.7V to 5.5V and 1.8V to 5.5V versions.
Table 1. Pin Configurations
Pin Name Function
CS Chip Select
SK Serial Data Clock
DI Serial Data Input
DO Serial Data Output
GND Ground
VCC Power Supply
ORG Internal Organization
DC Don’t Connect
Three-wire
Serial
EEPROMs
1K (128 x 8 or 64 x 16)
2K (256 x 8 or 128 x 16)
4K (512 x 8 or 256 x 16)
AT93C46
AT93C56(1)
AT93C66(2)
Note: 1. This device is not recom-
mended for new designs.
Please refer to AT93C56A.
2. This device is not recom-
mended for new designs.
Please refer to AT93C66A.
Rev. 0172Y–SEEPR–11/04
1
2
3
4
8
7
6
5
CS
SK
DI
DO
VCC
DC
ORG
GND
VCC
DC
ORG
GND
CS
SK
D1
D0
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
CS
SK
DI
DO
VCC
DC
ORG
GND
1
2
3
4
8
7
6
5
DC
VCC
CS
SK
ORG
GND
DO
DI
1
2
3
4
8
7
6
5
VCC
DC
ORG
GND
CS
SK
DI
DO
1
2
3
4
8
7
6
5
CS
SK
DI
DO
VCC
DC
ORG
GND
8-lead SOIC 8-lead dBGA2
8-lead PDIP
8-lead SOIC
Rotated (R)
(1K JEDEC Only)
8-lead MAP 8-lead TSSOP
2AT93C46/56/66
0172Y–SEEPR–11/04
Figure 1. Block Diagram
Note: When the ORG pin is connected to VCC, the “x 16” organization is selected. When it is
connected to ground, the “x 8” organization is selected. If the ORG pin is left uncon-
nected and the application does not load the input beyond the capability of the internal 1
Meg ohm pullup, then the “x 16” organization is selected. The feature is not available on
the 1.8V devices.
For the AT93C46, if “x 16” organization is the mode of choice and Pin 6 (ORG) is left
unconnected, Atmel recommends using the AT93C46A device. For more details, see the
AT93C46A datasheet.
Absolute Maximum Ratings*
Operating Temperature......................................−55°C to +125°C*NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only, and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability
Storage Temperature .........................................−65°C to +150°C
Voltage on Any Pin
with Respect to Ground........................................ −1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
3
AT93C46/56/66
0172Y–SEEPR–11/04
Note: 1. This parameter is characterized and is not 100% tested.
Note: 1. VIL min and VIH max are reference only and are not tested.
Table 2. Pin Capacitance(1)
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted)
Symbol Test Conditions Max Units Conditions
COUT Output Capacitance (DO) 5 pF VOUT = 0V
CIN Input Capacitance (CS, SK, DI) 5 pF VIN = 0V
Table 3. DC Characteristics
Applicable over recommended operating range from: TAI = −40°C to +85°C, VCC = +1.8V to +5.5V,
TAE = -40°C to +125°C, VCC = +1.8V to +5.5V (unless otherwise noted)
Symbol Parameter Test Condition Min Typ Max Unit
VCC1 Supply Voltage 1.8 5.5 V
VCC2 Supply Voltage 2.7 5.5 V
VCC3 Supply Voltage 4.5 5.5 V
ICC Supply Current VCC = 5.0V READ at 1.0 MHz 0.5 2.0 mA
WRITE at 1.0 MHz 0.5 2.0 mA
ISB1 Standby Current VCC = 1.8V CS = 0V 0 0.1 µA
ISB2 Standby Current VCC = 2.7V CS = 0V 6.0 10.0 µA
ISB3 Standby Current VCC = 5.0V CS = 0V 17 30 µA
IIL Input Leakage VIN = 0V to VCC 0.1 1.0 µA
IOL Output Leakage VIN = 0V to VCC 0.1 1.0 µA
VIL1(1) Input Low Voltage 2.7V ≤ VCC ≤ 5.5V −0.6 0.8 V
VIH1(1) Input High Voltage 2.0 VCC + 1
VIL2(1) Input Low Voltage 1.8V ≤ VCC ≤ 2.7V −0.6 VCC x 0.3 V
VIH2(1) Input High Voltage VCC x 0.7 VCC + 1
VOL1 Output Low Voltage 2.7V ≤ VCC ≤ 5.5V IOL = 2.1 mA 0.4 V
VOH1 Output High Voltage IOH = −0.4 mA 2.4 V
VOL2 Output Low Voltage 1.8V ≤ VCC ≤ 2.7V IOL = 0.15 mA 0.2 V
VOH2 Output High Voltage IOH = −100 µA VCC – 0.2 V
4AT93C46/56/66
0172Y–SEEPR–11/04
Note: 1. This parameter is characterized and is not 100% tested.
Table 4. AC Characteristics
Applicable over recommended operating range from TAI = −40°C to + 85°C, VCC = As Specified,
CL = 1 TTL Gate and 100 pF (unless otherwise noted)
Symbol Parameter Test Condition Min Typ Max Units
fSK
SK Clock
Frequency
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
0
0
0
2
1
0.25
MHz
tSKH SK High Time
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
250
250
1000
ns
tSKL SK Low Time
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
250
250
1000
ns
tCS
Minimum CS
Low Time
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
250
250
1000
ns
tCSS CS Setup Time Relative to SK
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
50
50
200
ns
tDIS DI Setup Time Relative to SK
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
100
100
400
ns
tCSH CS Hold Time Relative to SK 0 ns
tDIH DI Hold Time Relative to SK
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
100
100
400
ns
tPD1
Output Delay to
“1” AC Test
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
250
250
1000
ns
tPD0
Output Delay to
“0” AC Test
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
250
250
1000
ns
tSV
CS to Status
Valid AC Test
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
250
250
1000
ns
tDF
CS to DO in High
Impedance
AC Test
CS = VIL
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
100
100
400
ns
tWP Write Cycle Time 10 ms
4.5V ≤ VCC ≤ 5.5V 0.1 3 ms
Endurance(1) 5.0V, 25°C 1M Write Cycles
5
AT93C46/56/66
0172Y–SEEPR–11/04
Note: The Xs in the address field represent
DON’T CARE
values and must be clocked.
Note: 1. This device is not recommended for new designs. Please refer to AT93C56A.
2. This device is not recommended for new designs. Please refer to AT93C66A.
Table 5. Instruction Set for the AT93C46
Instruction SB
Op
Code
Address Data
Commentsx 8 x 16 x 8 x 16
READ 1 10 A6 – A0A5 – A0
Reads data stored in memory, at
specified address
EWEN 1 00 11XXXXX 11XXXX Write enable must precede all
programming modes
ERASE 1 11 A6 – A0A5 – A0Erases memory location An – A0
WRITE 1 01 A6 – A0A5 – A0D7 – D0D15 – D0Writes memory location An – A0
ERAL 1 00 10XXXXX 10XXXX Erases all memory locations. Valid
only at VCC = 4.5V to 5.5V
WRAL 1 00 01XXXXX 01XXXX D7 – D0D15 – D0
Writes all memory locations. Valid
only at VCC = 4.5V to 5.5V
EWDS 1 00 00XXXXX 00XXXX Disables all programming instructions
Table 6. Instruction Set for the AT93C56(1) and AT93C66(2)
Instruction SB
Op
Code
Address Data
Commentsx 8 x 16 x 8 x 16
READ 1 10 A8 – A0A7 – A0
Reads data stored in memory, at
specified address
EWEN 1 00 11XXXXXXX 11XXXXXX Write enable must precede all
programming modes
ERASE 1 11 A8 – A0A7 – A0Erases memory location An – A0
WRITE 1 01 A8 – A0A7 – A0D7 – D0D15 – D0Writes memory location An– A0
ERAL 1 00 10XXXXXXX 10XXXXXX Erases all memory locations. Valid
only at VCC = 4.5V to 5.5V
WRAL 1 00 01XXXXXXX 01XXXXXX D7 – D0D15 – D0
Writes all memory locations. Valid
only at VCC = 5.0V ±10% and Disable
Register cleared
EWDS 1 00 00XXXXXXX 00XXXXXX Disables all programming instructions
6AT93C46/56/66
0172Y–SEEPR–11/04
Functional
Description
The AT93C46/56/66 is accessed via a simple and versatile three-wire serial communi-
cation interface. Device operation is controlled by seven instructions issued by the host
processor.
A valid instruction starts with a rising edge of CS
and consists of a start bit
(logic “1”) followed by the appropriate op code and the desired memory address
location.
READ (READ): The Read (READ) instruction contains the address code for the mem-
ory location to be read. After the instruction and address are decoded, data from the
selected memory location is available at the serial output pin DO. Output data changes
are synchronized with the rising edges of serial clock SK. It should be noted that a
dummy bit (logic “0”) precedes the 8- or 16-bit data output string.
ERASE/WRITE ENABLE (EWEN): To assure data integrity, the part automatically goes
into the Erase/Write Disable (EWDS) state when power is first applied. An Erase/Write
Enable (EWEN) instruction must be executed first before any programming instructions
can be carried out. Please note that once in the EWEN state, programming remains
enabled until an EWDS instruction is executed or VCC power is removed from the part.
ERASE (ERASE): The Erase (ERASE) instruction programs all bits in the specified
memory location to the logical “1” state. The self-timed erase cycle starts once the
Erase instruction and address are decoded. The DO pin outputs the Ready/Busy status
of the part if CS is brought high after being kept low for a minimum of 250 ns (tCS). A
logic “1” at pin DO indicates that the selected memory location has been erased and the
part is ready for another instruction.
WRITE (WRITE): The Write (WRITE) instruction contains the 8 or 16 bits of data to be
written into the specified memory location. The self-timed programming cycle tWP starts
after the last bit of data is received at serial data input pin DI. The DO pin outputs the
Read/Busy status of the part if CS is brought high after being kept low for a minimum of
250 ns (tCS). A logic “0” at DO indicates that programming is still in progress. A logic “1”
indicates that the memory location at the specified address has been written with the
data pattern contained in the instruction and the part is ready for further instructions.
A
Ready/Busy status cannot be obtained if the CS is brought high after the end of the self-
timed programming cycle tWP.
ERASE ALL (ERAL): The Erase All (ERAL) instruction programs every bit in the mem-
ory array to the logic “1” state and is primarily used for testing purposes. The DO pin
outputs the Ready/Busy status of the part if CS is brought high after being kept low for a
minimum of 250 ns (tCS). The ERAL instruction is valid only at VCC = 5.0V ± 10%.
WRITE ALL (WRAL): The Write All (WRAL) instruction programs all memory locations
with the data patterns specified in the instruction. The DO pin outputs the Ready/Busy
status of the part if CS is brought high after being kept low for a minimum of 250 ns (tCS).
The WRAL instruction is valid only at VCC = 5.0V ± 10%.
ERASE/WRITE DISABLE (EWDS): To protect against accidental data disturb, the
Erase/Write Disable (EWDS) instruction disables all programming modes and should be
executed after all programming operations. The operation of the Read instruction is
independent of both the EWEN and EWDS instructions and can be executed at any
time.
7
AT93C46/56/66
0172Y–SEEPR–11/04
Timing Diagrams
Figure 2. Synchronous Data Timing
Note: 1. This is the minimum SK period.
Notes: 1. This device is not recommended for new designs. Please refer to AT93C56A.
2. This device is not recommended for new designs. Please refer to AT93C66A.
3. A8 is a
don’t care
value, but the extra clock is required.
4. A7 is a
don’t care
value, but the extra clock is required.
µs
Table 7. Organization Key for Timing Diagrams
I/O
AT93C46 (1K) AT93C56 (2K)(1) AT93C66 (4K)(2)
x 8 x 16 x 8 x 16 x 8 x 16
ANA6A5A8(3) A7(4) A8A7
DND7D15 D7D15 D7D15
8AT93C46/56/66
0172Y–SEEPR–11/04
Figure 3. READ Timing
Figure 4. EWEN Timing
Figure 5. EWDS Timing
High Impedance
tCS
CS
11 ...
001
SK
DI
tCS
CS t
CS
SK
DI 1 0 000 ...
9
AT93C46/56/66
0172Y–SEEPR–11/04
Figure 6. WRITE Timing
Figure 7. WRAL Timing(1)
Note: 1. Valid only at VCC = 4.5V to 5.5V.
Figure 8. ERASE Timing
SK
CS tCS
tWP
11
ANDN
0A0D0
... ...
DI
DO HIGH IMPEDANCE BUSY READY
CS
SK
DI
DO
HIGH IMPEDANCE BUSY
READY
1 0 0 1 ... DN
tCS
tWP
... D00
SK
1 1 ...1
CS
DI AN
tCS
tSV tDF
tWP
AN-1 AN-2 A0
CHECK
STATUS
STANDBY
READY
BUSY
DO HIGH IMPEDANCE HIGH IMPEDANCE
11
AT93C46/56/66
0172Y–SEEPR–11/04
Notes: 1. For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the Table 3 on page 3 and Table 4 on
page 4.
2. Available in waffle pack and wafer form, order as SL719 for wafer form. Bumped die available upon request.
AT93C46 Ordering Information(1)
Ordering Code Package Operation Range
AT93C46-10PI-2.7
AT93C46-10SI-2.7
AT93C46R-10SI-2.7
AT93C46W-10SI-2.7
AT93C46-10TI-2.7
8P3
8S1
8S1
8S2
8A2
Industrial
(−40°C to 85°C)
AT93C46-10PI-1.8
AT93C46-10SI-1.8
AT93C46R-10SI-1.8
AT93C46W-10SI-1.8
AT93C46-10TI-1.8
8P3
8S1
8S1
8S2
8A2
Industrial
(−40°C to 85°C)
AT93C46-10PU-2.7
AT93C46-10PU-1.8
AT93C46-10SU-2.7
AT93C46-10SU-1.8
AT93C46-10TU-2.7
AT93C46-10TU-1.8
AT93C46Y1-10YU-2.7
AT93C46Y1-10YU-1.8
AT93C46Y5-10YU-2.7
AT93C46Y5-10YU-1.8
AT93C46U3-10UU-2.7
AT93C46U3-10UU-1.8
8P3
8P3
8S1
8S1
8A2
8A2
8Y1
8Y1
8Y5
8Y5
8U3-1
8U3-1
Lead-free/Halogen-free/
Industrial Temperature
(−40°C to 85°C)
AT93C46-W2.7-11(2)
AT93C46-W1.8-11(2)
Die Sale
Die Sale
Industrial
(−40°C to 85°C)
Package Type
8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8S2 8-lead, 0.200" Wide, Plastic Gull Wing Small Outline (EIAJ SOIC)
8A2 8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)
8U3-1 8-ball, Die Ball Grid Array Package (dBGA2)
8Y1 8-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP)
8Y5 8-lead, 2.00 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP)
Options
−2.7 Low Voltage (2.7V to 5.5V)
−1.8 Low Voltage (1.8V to 5.5V)
RRotated Pinout
12 AT93C46/56/66
0172Y–SEEPR–11/04
Note: 1. This device is not recommended for new designs. Please refer to AT93C56A.
2. For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in Table 3 on page 3 and Table 4 on
page 4.
AT93C56(1) Ordering Information
Ordering Code(2) Package Operation Range
AT93C56-10PI-2.7
AT93C56-10SI-2.7
AT93C56W-10SI-2.7
AT93C56-10TI-2.7
AT93C56Y1-10YI-2.7
8P3
8S1
8S2
8A2
8Y1
Industrial
(−40°C to 85°C)
AT93C56-10PI-1.8
AT93C56-10SI-1.8
AT93C56W-10SI-1.8
AT93C56-10TI-1.8
AT93C56Y1-10YI-1.8
8P3
8S1
8S2
8A2
8Y1
Industrial
(−40°C to 85°C)
Package Type
8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8S2 8-lead, 0.200" Wide, Plastic Gull Wing Small Outline (EIAJ SOIC)
8A2 8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)
8Y1 8-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP)
Options
−2.7 Low Voltage (2.7V to 5.5V)
1.8 Low Voltage (1.8V to 5.5V)
13
AT93C46/56/66
0172Y–SEEPR–11/04
Notes: 1. This device is not recommended for new designs. Please refer to AT93C66A.
2. For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in Table 3 on page 3 and Table 4 on
page 4.
AT93C66(1) Ordering Information
Ordering Code(2) Package Operation Range
AT93C66-10PI-2.7
AT93C66-10SI-2.7
AT93C66W-10SI-2.7
AT93C66-10TI-2.7
AT93C66Y1-10YI-2.7
8P3
8S1
8S2
8A2
8Y1
Industrial
(−40°C to 85°C)
AT93C66-10PI-1.8
AT93C66-10SI-1.8
AT93C66W-10SI-1.8
AT93C66-10TI-1.8
AT93C66Y1-10YI-1.8
8P3
8S1
8S2
8A2
8Y1
Industrial
(−40°C to 85°C)
Package Type
8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8S2 8-lead, 0.200" Wide, Plastic Gull Wing Small Outline (EIAJ SOIC)
8A2 8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)
8Y1 8-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP)
Options
−2.7 Low Voltage (2.7V to 5.5V)
−1.8 Low Voltage (1.8V to 5.5V)
14 AT93C46/56/66
0172Y–SEEPR–11/04
Packaging Information
8P3 – PDIP
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
8P3, 8-lead, 0.300" Wide Body, Plastic Dual
In-line Package (PDIP)
01/09/02
8P3 B
D
D1
E
E1
e
L
b2
b
A2 A
1
N
eA
c
b3
4 PLCS
Top View
Side View
End View
COMMON DIMENSIONS
(Unit of Measure = inches)
SYMBOL MIN NOM MAX NOTE
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
A 0.210 2
A2 0.115 0.130 0.195
b 0.014 0.018 0.022 5
b2 0.045 0.060 0.070 6
b3 0.030 0.039 0.045 6
c 0.008 0.010 0.014
D 0.355 0.365 0.400 3
D1 0.005 3
E 0.300 0.310 0.325 4
E1 0.240 0.250 0.280 3
e 0.100 BSC
eA 0.300 BSC 4
L 0.115 0.130 0.150 2
15
AT93C46/56/66
0172Y–SEEPR–11/04
8S1 – JEDEC SOIC
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TITLE DRAWING NO.
R
REV.
Note:
10/7/03
8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing
Small Outline (JEDEC SOIC) 8S1 B
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
A1 0.10 – 0.25
These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.
A 1.35 – 1.75
b 0.31 – 0.51
C 0.17 – 0.25
D 4.80 – 5.00
E1 3.81 – 3.99
E 5.79 – 6.20
e 1.27 BSC
L 0.40 – 1.27
∅ 0˚ – 8˚
∅
Top View
End View
Side View
eB
D
A
A1
N
E
1
C
E1
L
16 AT93C46/56/66
0172Y–SEEPR–11/04
8S2 – EIAJ SOIC
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
8S2, 8-lead, 0.209" Body, Plastic Small
Outline Package (EIAJ)
10/7/03
8S2 C
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
Notes: 1. This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information.
2. Mismatch of the upper and lower dies and resin burrs are not included.
3. It is recommended that upper and lower cavities be equal. If they are different, the larger dimension shall be regarded.
4. Determines the true geometric position.
5. Values b and C apply to pb/Sn solder plated terminal. The standard thickness of the solder layer shall be 0.010 +0.010/−0.005 mm.
A 1.70 2.16
A1 0.05 0.25
b 0.35 0.48 5
C 0.15 0.35 5
D 5.13 5.35
E1 5.18 5.40 2, 3
E 7.70 8.26
L 0.51 0.85
∅
0˚ 8˚
e 1.27 BSC 4
End View
Side View
eb
A
A1
D
E
N
1
C
E1
∅
L
Top View
17
AT93C46/56/66
0172Y–SEEPR–11/04
8A2 – TSSOP
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
5/30/02
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
D 2.90 3.00 3.10 2, 5
E 6.40 BSC
E1 4.30 4.40 4.50 3, 5
A – – 1.20
A2 0.80 1.00 1.05
b 0.19 – 0.30 4
e 0.65 BSC
L 0.45 0.60 0.75
L1 1.00 REF
8A2, 8-lead, 4.4 mm Body, Plastic
Thin Shrink Small Outline Package (TSSOP)
Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances,
datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15 mm (0.006 in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm
(0.010 in) per side.
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the
b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between
protrusion and adjacent lead is 0.07 mm.
5. Dimension D and E1 to be determined at Datum Plane H.
8A2 B
Side View
End View
Top View
A2
A
L
L1
D
123
E1
N
b
Pin 1 indicator
this corner
E
e
18 AT93C46/56/66
0172Y–SEEPR–11/04
8U3-1 – dBGA2
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TITLE DRAWING NO.
R
REV.
PO8U3-1 A
6/24/03
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
8U3-1, 8-ball, 1.50 x 2.00 mm Body, 0.50 mm pitch,
Small Die Ball Grid Array Package (dBGA2)
A 0.71 0.81 0.91
A1 0.10 0.15 0.20
A2 0.40 0.45 0.50
b 0.20 0.25 0.30
D 1.50 BSC
E 2.00 BSC
e 0.50 BSC
e1 0.25 REF
d 1.00 BSC
d1 0.25 REF
1. Dimension “b” is measured at the maximum solder ball diameter.
This drawing is for general information only.
Bottom View
8 SOLDER BALLS
b
D
E
Top View
PIN 1 BALL PAD CORNER
A
Side View
A
2
A
1
4
5
PIN 1 BALL PAD CORNER
31
e
2
67
8
d
(e1)
(d1)
1.
19
AT93C46/56/66
0172Y–SEEPR–11/04
8Y1 – MAP
A – – 0.90
A1 0.00 – 0.05
D 4.70 4.90 5.10
E 2.80 3.00 3.20
D1 0.85 1.00 1.15
E1 0.85 1.00 1.15
b 0.25 0.30 0.35
e 0.65 TYP
L 0.50 0.60 0.70
PIN 1 INDEX AREA
D
E
A
A1 b
876
e
5
L
D1
E1
PIN 1 INDEX AREA
1234
A
Top View End View Bottom View
Side View
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
8Y1, 8-lead (4.90 x 3.00 mm Body) MSOP Array Package
(MAP) Y1 C
8Y1
2/28/03
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
MIN NOM MAX
NOTE
20 AT93C46/56/66
0172Y–SEEPR–11/04
8Y5 – MAP
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
8Y5, 8-lead 2.0 x 3.0 mm Body, 0.50 mm Pitch, Mini-Map, Dual
No Lead Package (DFN) A
8Y5
11/12/03
Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-229, for proper dimensions,
tolerances, datums, etc.
2. Dimension b applies to metallized terminal and is measured between 0.15 mm and 0.30 mm from the terminal tip. If the
terminal has the optional radius on the other end of the terminal, the dimension should not be measured in that radius area.
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
D 2.00 BSC
E 3.00 BSC
D2 1.40 1.50 1.60
E2 1.75 1.85 1.95
A – – 0.90
A1 0.0 0.02 0.05
A2 – – 0.85
A3 0.20 REF
L 0.20 0.30 0.40
e 0.50 BSC
b 0.20 0.25 0.30 2
Pin 1
Index
Area
E
D
A3
A
A2 A1
D2 b
(8x)
Pin 1 ID
E2
L (8x)
e (6x)
1.50 REF.
Bottom View
Top View
Side View
Printed on recycled paper.
0172Y–SEEPR–11/04
Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any
intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI-
TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY
WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDEN-
TAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT
OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no
representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications
and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Atmel’s products are not
intended, authorized, or warranted for use as components in applications intended to support or sustain life.
Atmel Corporation Atmel Operations
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600
Regional Headquarters
Europe
Atmel Sarl
Route des Arsenaux 41
Case Postale 80
CH-1705 Fribourg
Switzerland
Tel: (41) 26-426-5555
Fax: (41) 26-426-5500
Asia
Room 1219
Chinachem Golden Plaza
77 Mody Road Tsimshatsui
East Kowloon
Hong Kong
Tel: (852) 2721-9778
Fax: (852) 2722-1369
Japan
9F, Tonetsu Shinkawa Bldg.
1-24-8 Shinkawa
Chuo-ku, Tokyo 104-0033
Japan
Tel: (81) 3-3523-3551
Fax: (81) 3-3523-7581
Memory
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 436-4314
Microcontrollers
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 436-4314
La Chantrerie
BP 70602
44306 Nantes Cedex 3, France
Tel: (33) 2-40-18-18-18
Fax: (33) 2-40-18-19-60
ASIC/ASSP/Smart Cards
Zone Industrielle
13106 Rousset Cedex, France
Tel: (33) 4-42-53-60-00
Fax: (33) 4-42-53-60-01
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906, USA
Tel: 1(719) 576-3300
Fax: 1(719) 540-1759
Scottish Enterprise Technology Park
Maxwell Building
East Kilbride G75 0QR, Scotland
Tel: (44) 1355-803-000
Fax: (44) 1355-242-743
RF/Automotive
Theresienstrasse 2
Postfach 3535
74025 Heilbronn, Germany
Tel: (49) 71-31-67-0
Fax: (49) 71-31-67-2340
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906, USA
Tel: 1(719) 576-3300
Fax: 1(719) 540-1759
Biometrics/Imaging/Hi-Rel MPU/
High Speed Converters/RF Datacom
Avenue de Rochepleine
BP 123
38521 Saint-Egreve Cedex, France
Tel: (33) 4-76-58-30-00
Fax: (33) 4-76-58-34-80
Literature Requests
www.atmel.com/literature
© Atmel Corporation 2004. All rights reserved. Atmel®, logo and combinations thereof, are registered trademarks, Everywhere You AreSM and
dBGATM are the trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others.
