MAX9710/MAX9711
Power Dissipation and Heat Sinking
Under normal operating conditions, the MAX9710/
MAX9711 dissipate a significant amount of power. The
maximum power dissipation for each package is given
in the
Absolute Maximum Ratings
section under
Continuous Power Dissipation or can be calculated by
the following equation:
where TJ(MAX) is +150°C, TAis the ambient temperature,
and θJA is the reciprocal of the derating factor in °C/W as
specified in the
Absolute Maximum Ratings
section. For
example, θJA of the 20-pin thin QFN package is
48.1°C/W.
The increase in power delivered by the BTL configura-
tion directly results in an increase in internal power dis-
sipation over the single-ended configuration. The
maximum power dissipation for a given VDD and load is
given by the following equation:
If the power dissipation for a given application exceeds
the maximum allowed for a given package, either reduce
VDD, increase load impedance, decrease the ambient
temperature, or add heat sinking to the device (see
Layout and Grounding
section). Large output, supply,
and ground PC board traces improve the maximum
power dissipation in the package.
Thermal-overload protection limits total power dissipa-
tion in the MAX9710/MAX9711. When the junction
temperature exceeds +160°C, the thermal protection
circuitry disables the amplifier output stage. The
amplifiers are enabled once the junction temperature
cools by 15°C. A pulsing output under continuous
thermal-overload conditions results as the device heats
and cools.
Component Selection
Gain-Setting Resistors
External feedback components set the gain of both
devices. Resistors RFand RIN (
Functional Diagrams
)
set the gain of the amplifier as follows:
Input Filter
The input capacitor (CIN), in conjunction with RIN, forms
a highpass filter that removes the DC bias from an
incoming signal. The AC-coupling capacitor allows the
amplifier to bias the signal to an optimum DC level.
Assuming zero-source impedance, the -3dB point of
the highpass filter is given by:
For optimum click-and-pop suppression, choose:
RIN x CIN < RBIAS x CBIAS
where RBIAS = 50kΩ.
Setting f-3dB too high affects the low-frequency
response of the amplifier. Use capacitors with
dielectrics that have low-voltage coefficients, such as
tantalum or aluminum electrolytic. Capacitors with high-
voltage coefficients, such as ceramics, may result in an
increase of distortion at low frequencies.
BIAS Capacitor
BIAS is the output of the internally generated 2.5VDC
bias voltage. The BIAS bypass capacitor, CBIAS,
improves PSRR and THD+N by reducing power supply
and other noise sources at the common-mode bias
node, and also generates the clickless/popless startup
DC bias waveform for the speaker amplifiers. Bypass
BIAS with a 1µF capacitor to GND. Smaller values of
CBIAS produce faster tON/tOFF times but may result in
increased click/pop levels.
Supply Bypassing
Proper power-supply bypassing ensures low-noise,
low-distortion performance. Place a 0.1µF ceramic
capacitor from VDD to PGND. Add additional bulk
capacitance as required by the application. Locate the
bypass capacitor as close to the device as possible.
Piezoelectric Speaker Driver
Low-profile piezoelectric speakers can provide quality
sound for portable electronics. However, piezoelectric
speakers typically require large voltage swings
(>8VP-P) across the speaker element to produce
audible sound pressure levels. The MAX9711 can be
configured to drive a piezoelectric speaker with up to
10VP-P while operating from a single 5V supply.
Figure 2 shows the THD+N of the MAX9711 driving a
piezoelectric speaker. Note that as frequency increas-
es, the THD+N increases. This is due to the capacitive
nature of the piezoelectric speaker; as frequency
increases, the speaker impedance decreases, resulting
in a larger current draw from the amplifier.