M dsPIC30F Data Sheet Motor Control and Power Conversion Family High Performance Digital Signal Controllers 2002 Microchip Technology Inc. Advance Information DS70082A Note the following details of the code protection feature on PICmicro(R) MCUs. * * * * * * The PICmicro family meets the specifications contained in the Microchip Data Sheet. Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the PICmicro microcontroller in a manner outside the operating specifications contained in the data sheet. The person doing so may be engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable". Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our product. If you have any further questions about this matter, please contact the local sales office nearest to you. Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, FilterLab, KEELOQ, microID, MPLAB, PIC, PICmicro, PICMASTER, PICSTART, PRO MATE, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, MXDEV, MXLAB, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2002, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999. The Company's quality system processes and procedures are QS-9000 compliant for its PICmicro(R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs and microperipheral products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001 certified. DS70082A - page ii Advance Information 2002 Microchip Technology Inc. M dsPIC30F dsPIC30F Enhanced FLASH 16-bit Digital Signal Controllers Motor Control and Power Conversion Family High Performance Modified RISC CPU: Peripheral Features (Continued): * * * * * * Addressable UART modules supporting: - Interrupt on address bit - Wake-up on START bit - 4 characters deep TX and RX FIFO buffers * CAN bus modules * * * * * * * * * * * * * * Modified Harvard architecture C compiler optimized instruction set architecture 88 base instructions 24-bit wide instructions, 16-bit wide data path Linear program memory addressing up to 4M Instruction Words Linear data memory addressing up to 64 Kbytes Up to 144 Kbytes on-chip FLASH program space - Up to 48K Instruction Words Up to 8 Kbytes of on-chip data RAM Up to 4 Kbytes of non-volatile data EEPROM 16 x 16-bit working register array Three Address Generation Units that enable: - Dual data fetch - Accumulator write back for DSP operations Flexible Addressing modes supporting: - Indirect, Modulo and Bit-Reversed modes Two, 40-bit wide accumulators with optional saturation logic 17-bit x 17-bit single cycle hardware fractional/ integer multiplier Single cycle Multiply-Accumulate (MAC) operation 40-stage Barrel Shifter Up to 30 MIPs operation: - DC to 40 MHz external clock input - 4 MHz - 10 MHz oscillator input with PLL active (4x, 8x, 16x) Up to 42 interrupt sources - 8 user selectable priority levels Vector table with up to 62 vectors - 54 interrupt vectors - 8 processor exceptions and software traps Peripheral Features: * High current sink/source I/O pins: 25 mA/25 mA * Up to 5 external interrupt sources * Timer module with programmable prescaler: - Up to five 16-bit timers/counters; optionally pair up 16-bit timers into 32-bit timer modules * 16-bit Capture input functions * 16-bit Compare/PWM output functions - Dual Compare mode available * 3-wire SPITM modules (supports 4 Frame modes) * I2CTM module supports Multi-Master/Slave mode and 7-bit/10-bit addressing 2002 Microchip Technology Inc. Motor Control PWM Module Features: * Up to 8 PWM output channels - Complementary or Independent Output modes - Edge and Center Aligned modes * 4 duty cycle generators * Dedicated time-base with 4 modes * Programmable output polarity * Dead-time control for Complementary mode * Manual output control * Trigger for A/D conversions Quadrature Encoder Interface Module Features: * * * * * * * Phase A, Phase B and Index Pulse input 16-bit up/down position counter Count direction status Position Measurement (x2 and x4) mode Programmable digital noise filters on inputs Alternate 16-bit Timer/Counter mode Interrupt on position counter rollover/underflow Input Capture Module Features: * Captures 16-bit timer value - Capture every 1st, 4th or 16th rising edge - Capture every falling edge - Capture every rising and falling edge * Resolution of 33 ns at 30 MIPs * Timer2 or Timer3 time-base selection * Input Capture during IDLE * Interrupt on input capture event Analog Features: * 10-bit Analog-to-Digital Converter (A/D) with: - 500 Ksps (for 10-bit A/D) conversion rate - Up to 16 input channels - Conversion available during SLEEP and IDLE * Programmable Low Voltage Detection (PLVD) * Programmable Brown-out Detection and Reset generation Advance Information DS70082A-page 1 dsPIC30F Special Microcontroller Features: CMOS Technology: * Enhanced FLASH program memory - 10,000 erase/write cycle (typical) for industrial temperature range * Data EEPROM memory - 100,000 erase/write cycle (typical) industrial temperature range * Self-reprogrammable under software control * Power-on Reset (POR), Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) * Flexible Watchdog Timer (WDT) with on-chip low power RC oscillator for reliable operation * Fail-Safe clock monitor operation - Detects clock failure and switches to on-chip low power RC oscillator * Programmable code protection * In-Circuit Serial ProgrammingTM (ICSPTM) via 3 pins and power/ground * Selectable Power Management modes - SLEEP, IDLE and Alternate Clock modes * * * * 2002 Microchip Technology Inc. Low power, high speed FLASH technology Wide operating voltage range (2.5V to 5.5V) Industrial and Extended temperature ranges Low power consumption Advance Information DS70082A-page 2 dsPIC30F dsPIC30F Motor Control and Power Conversion Family Pins UART SPITM I2CTM CAN Program Output Motor SRAM EEPROM Timer Input A/D 10-bit Quad Mem. Bytes/ Comp/Std Control Bytes Bytes 16-bit Cap 500 Ksps Enc Instructions PWM PWM Device dsPIC30F2010 28 12K/4K 512 1024 3 4 2 6 ch 6 ch Yes 1 1 1 - dsPIC30F3010 28 24K/8K 1024 1024 5 4 2 6 ch 6 ch Yes 1 1 1 - dsPIC30F4012 28 48K/16K 2048 1024 5 4 2 6 ch 6 ch Yes 1 1 1 1 dsPIC30F3011 40/44 24K/8K 1024 1024 5 4 4 6 ch 9 ch Yes 2 1 1 - dsPIC30F4011 40/44 48K/16K 2048 1024 5 4 4 6 ch 9 ch Yes 2 1 1 1 dsPIC30F5015* 64 66K/22K 2048 1024 5 4 4 8 ch 16 ch Yes 1 2 1 1 dsPIC30F6010 80 144K/48K 8192 4096 5 8 8 8 ch 16 ch Yes 2 2 1 2 * Pinout for dsPIC30F5015 will be provided at a later date. Pin Diagrams 28-Pin SDIP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 dsPIC30F2010 dsPIC30F3010 dsPIC30F4012 MCLR PGD/EMUD/AN0/VREF+/CN2/RB0 PGC/EMUC/AN1/VREF-/CN3/RB1 AN2/SS1/LVDIN/CN4/RB2 AN3/INDX/CN5/RB3 AN4/QEA/IC7/CN6/RB4 AN5/QEB/IC8/CN7/RB5 VSS OSC1/CLKI OSC2/CLKO/RC15 EMUD1/SOSC2/T2CK/U1ATX/CN1/RC13 EMUC1/SOSC1/T1CK/U1ARX/CN0/RC14 VDD EMUD2/OC2/IC2/INT2/RD1 28 27 26 25 24 23 22 21 20 19 18 17 16 15 AVDD AVSS PWM1L/RE0 PWM1H/RE1 PWM2L/RE2 PWM2H/RE3 PWM3L/RE4 PWM3H/RE5 VDD VSS U1RX/SDI1/SDA/C1RX/RF2 EMUD3/U1TX/SDO1/SCL/C1TX/RF3 EMUC3/FLTA/INT0/SCK1/OCFA/RE8 EMUC2/OC1/IC1/INT1/RD0 Note: Pinout subject to change. 40-Pin PDIP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 dsPIC30F3011 dsPIC30F4011 MCLR PGD/EMUD/AN0/VREF+/CN2/RB0 PGC/EMUC/AN1/VREF-/CN3/RB1 AN2/SS1/LVDIN/CN4/RB2 AN3/INDX/CN5/RB3 AN4/QEA/IC7/CN6/RB4 AN5/QEB/IC8/CN7/RB5 AN6/OCFA/RB6 AN7/RB7 AN8/RB8 VDD VSS OSC1/CLKI OSC2/CLKO/RC15 EMUD1/SOSC2/T2CK/U1ATX/CN1/RC13 EMUC1/SOSC1/T1CK/U1ARX/CN0/RC14 FLTA/INT0/RE8 EMUD2/OC2/IC2/INT2/RD1 OC4/RD3 VSS 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 AVDD AVSS PWM1L/RE0 PWM1H/RE1 PWM2L/RE2 PWM2H/RE3 PWM3L/RE4 PWM3H/RE5 VDD VSS C1RX/RF0 C1TX/RF1 U2RX/RF4 U2TX/RF5 U1RX/SDI1/SDA/RF2 EMUD3/U1TX/SDO1/SCK/RF3 EMUC3/SCK1/RF6 EMUC2/OC1/IC1/INT1/RD0 OC3/RD2 VDD Note: Pinout subject to change. 2002 Microchip Technology Inc. Advance Information DS70082A-page 3 dsPIC30F 44 43 42 41 40 39 38 37 36 35 34 44-Pin TQFP AN3/INDX/CN5/RB3 AN2/SS1/LVDIN/CN4/RB2 PGC/EMUC/AN1/VREF-/CN3/RB1 PGD/EMUD/AN0/VREF+/CN2/RB0 MCLR NC AVDD AVSS PWM1L/RE0 PWM1H/RE1 PWM2L/RE2 Pin Diagrams (Continued) 1 2 3 4 5 6 7 8 9 10 11 dsPIC30F3011 dsPIC30F4011 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 AN4/QEA/IC7/CN6/RB4 AN5/QEB/IC8/CN7/RB5 AN6/OCFA/RB6 AN7/RB7 AN8/RB8 NC VDD VSS OSC1/CLKI OSC2/CLKO/RC15 EMUD1/SOSC2/T2CK/U1ATX/CN1/RC13 PWM2H/RE3 PWM3L/RE4 PWM3H/RE5 VDD VSS NC C1RX/RF0 C1TX/RF1 U2RXRF4 U2TX/RF5 U1RX/SDI1/SDA/RF2 EMUD3/U1TX/SDO1/SCL/RF3 EMUC3/SCK1/TC1/RF6 EMUC2/OC1/IC1/INT1/RD0 OC3/RD2 VDD NC VSS OC4/RD3 EMUD2/OC2/IC2/INT2/RD1 FLTA/INT0/RE8 EMUC1/SOSC1/T1CK/U1ARX/CN0/RC14 Note: Pinout subject to change. 2002 Microchip Technology Inc. Advance Information DS70082A-page 4 dsPIC30F Pin Diagrams (Continued) IC5/RD12 OC4/RD3 OC3/RD2 EMUD2/OC2/RD1 OC6/CN14/RD5 OC5/CN13/RD4 IC6/CN19/RD13 OC7/CN15/RD6 C2RX/RG0 C2TX/RG1 C1TX/RF1 C1RX/RF0 VDD VSS OC8/CN16/UPDN/RD7 PWM2L/RE2 PWM1H/RE1 PWM1L/RE0 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 PWM3L/RE4 PWM2H/RE3 80-Pin TQFP PWM3H/RE5 1 60 EMUC1/SOSC1/ T1CK/CN0/RC14 PWM4L/RE6 2 59 EMUD1/SOSC2/CN1/RC13 PWM4H/RE7 3 58 EMUC2/OC1/RD0 T2CK/RC1 T4CK/RC3 4 57 5 56 IC4/RD11 IC3/RD10 SCK2/CN8/RG6 6 55 IC2/RD9 SDI2/CN9/RG7 7 54 IC1/RD8 SDO2/CN10/RG8 MCLR 8 53 INT4/RA15 9 52 SS2/CN11/RG9 VSS 10 51 INT3/RA14 VSS VDD 12 49 OSC2/CLKO/RC15 OSC1/CLKI dsPIC30F6010 11 50 FLTA/INT1/RE8 13 48 VDD FLTB/INT2/RE9 14 47 AN5/QEB/CN7/RB5 15 46 SCL/RG2 SDA/RG3 AN4/QEA/CN6/RB4 AN3/INDX/CN5/RB3 16 45 EMUC3/SCK1/INT0/RF6 17 44 SDI1/RF7 28 29 30 31 32 33 34 35 36 37 38 39 40 AN9/RB9 AN11/RB11 VSS VDD AN12/RB12 AN13/RB13 AN14/RB14 AN15/OCFB/CN12/RB15 IC7/CN20/RD14 IC8/CN21/RD15 U2RX/CN17/RF4 U2TX/CN18/RF5 27 AN10/RB10 26 AN8/RB8 25 AVDD AVSS 24 U1TX/RF3 VREF+/RA10 41 23 20 22 U1RX/RF2 PGD/EMUD/AN0/CN2/RB0 VREF-/RA9 EMUD3/SDO1/RF8 42 21 43 19 AN7/RB7 18 AN6/OCFA/RB6 AN2/SS1/LVDIN/CN4/RB2 PGC/EMUC/AN1/CN3/RB1 Note: Pinout subject to change. 2002 Microchip Technology Inc. Advance Information DS70082A-page 5 dsPIC30F Table of Contents 1.0 Device Overview ...................................................................................................................................................................... 9 2.0 Core Architecture Overview ................................................................................................................................................... 13 3.0 Memory Organization............................................................................................................................................................. 25 4.0 Address Generator Units........................................................................................................................................................ 37 5.0 Exception Processing............................................................................................................................................................. 45 6.0 FLASH Program Memory ....................................................................................................................................................... 51 7.0 Data EEPROM Memory ......................................................................................................................................................... 57 8.0 I/O Ports ................................................................................................................................................................................. 61 9.0 Timer1 Module ....................................................................................................................................................................... 67 10.0 Timer2/3 Module .................................................................................................................................................................... 71 11.0 Timer4/5 Module .................................................................................................................................................................... 77 12.0 Input Capture Module............................................................................................................................................................. 81 13.0 Output Compare Module........................................................................................................................................................ 85 14.0 Quadrature Encoder Interface (QEI) Module ......................................................................................................................... 89 15.0 Motor Control PWM Module ................................................................................................................................................... 95 16.0 SPI Module........................................................................................................................................................................... 107 17.0 I2C Module........................................................................................................................................................................... 111 18.0 Universal Asynchronous Receiver Transmitter (UART) Module .......................................................................................... 119 19.0 CAN Module......................................................................................................................................................................... 127 20.0 10-bit High speed Analog-to-Digital Converter (A/D) Module .............................................................................................. 133 21.0 System Integration ............................................................................................................................................................... 141 22.0 Instruction Set Summary ...................................................................................................................................................... 153 23.0 Development Support .......................................................................................................................................................... 161 24.0 Electrical Characteristics ...................................................................................................................................................... 163 25.0 DC and AC Characteristics Graphs and Tables................................................................................................................... 165 26.0 Packaging Information ......................................................................................................................................................... 167 Index .................................................................................................................................................................................................. 175 On-Line Support................................................................................................................................................................................. 181 Reader Response .............................................................................................................................................................................. 182 Product Identification System ............................................................................................................................................................ 183 2002 Microchip Technology Inc. Advance Information DS70082A-page 6 dsPIC30F TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@mail.microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: * Microchip's Worldwide Web site; http://www.microchip.com * Your local Microchip sales office (see last page) * The Microchip Corporate Literature Center; U.S. FAX: (480) 792-7277 When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com/cn to receive the most current information on all of our products. 2002 Microchip Technology Inc. Advance Information DS70082A-page 7 dsPIC30F NOTES: 2002 Microchip Technology Inc. Advance Information DS70082A-page 8 dsPIC30F 1.0 DEVICE OVERVIEW Figure 1-1 shows a sample device block diagram. This document contains device family specific information for the dsPIC30F family of Digital Signal Controller (DSC) devices. The dsPIC30F devices contain extensive Digital Signal Processor (DSP) functionality within a high performance 16-bit Microcontroller (MCU) architecture. 2002 Microchip Technology Inc. Note: Advance Information The device(s) depicted in this block diagram are representative of the corresponding device family. Other devices of the same family may vary in terms of number of pins and multiplexing of pin functions. Typically, smaller devices in the family contain a subset of the peripherals present in the device(s) shown in this diagram. DS70082A-page 9 dsPIC30F FIGURE 1-1: dsPIC30F6010 BLOCK DIAGRAM Y Data Bus X Data Bus 16 16 Interrupt Controller PSV & Table Data Access 24 Control Block 8 16 Data Latch Y Data RAM (4 Kbytes) Address Latch 16 24 Address Latch Program Memory (144 Kbytes) Data EEPROM (4 Kbytes) VREF-/RA9 VREF+/RA10 INT3/RA14 INT4/RA15 PORTA PGD/EMUD/AN0/CN2/RB0 PGC/EMUC/AN1/CN3/RB1 AN2/SS1/LVDIN/CN4/RB2 AN3/INDX/CN5/RB3 AN4/QEA/CN6/RB4 AN5/QEB/CN7/RB5 AN6/OCFA/RB6 AN7/RB7 AN8/RB8 AN9/RB9 AN10/RB10 AN11/RB11 AN12/RB12 AN13/RB13 AN14/RB14 AN15/OCFB/CN12/RB15 16 X RAGU X WAGU Y AGU PCU PCH PCL Program Counter Loop Stack Control Control Logic Logic 16 Data Latch X Data RAM (4 Kbytes) Address Latch 16 16 24 16 Effective Address 16 Data Latch ROM Latch 16 24 PORTB T2CK/RC1 T4CK/RC3 EMUD1/SOSC2/CN1/RC13 EMUC1/SOSC1/T1CK/CN0/RC14 OSC2/CLKO/RC15 IR 16 16 16 x 16 W Reg Array Decode PORTC Instruction Decode & Control 16 16 Control Signals to Various Blocks OSC1/CLKI DSP Engine Power-up Timer ALU<16> POR/BOR Reset MCLR VDD, VSS AVDD, AVSS SPI1, SPI2 Divide Unit Oscillator Start-up Timer Timing Generation CAN1, CAN2 EMUC2/OC1/RD0 EMUD2/OC2/RD1 OC3/RD2 OC4/RD3 OC5/CN13/RD4 OC6/CN14/RD5 OC7/CN15/RD6 OC8/CN16/UPDN/RD7 IC1/RD8 IC2/RD9 IC3/RD10 IC4/RD11 IC5/RD12 IC6/CN19/RD13 IC7/CN20/RD14 IC8/CN21/RD15 Watchdog Timer Low Voltage Detect 16 16 PORTD 10-bit ADC Input Capture Module Output Compare Module I C Timers QEI Motor Control PWM UART1, UART2 PWM1L/RE0 PWM1H/RE1 PWM2L/RE2 PWM2H/RE3 PWM3L/RE4 PWM3H/RE5 PWM4L/RE6 PWM4H/RE7 FLTA/INT1/RE8 FLTB/INT2/RE9 2 PORTE C1RX/RF0 C1TX/RF1 U1RX/RF2 U1TX/RF3 U2RX/CN17/RF4 U2TX/CN18/RF5 EMUC3/SCK1/INT0/RF6 SDI1/RF7 EMUD3/SDO1/RF8 C2RX/RG0 C2TX/RG1 SCL/RG2 SDA/RG3 SCK2/CN8/RG6 SDI2/CN9/RG7 SDO2/CN10/RG8 SS2/CN11/RG9 PORTG DS70082A-page 10 Advance Information PORTF 2002 Microchip Technology Inc. dsPIC30F Table 1-1 provides a brief description of device I/O pinouts and the functions that may be multiplexed to a port pin. Multiple functions may exist on one port pin. TABLE 1-1: When multiplexing occurs, the peripheral module's functional requirements may force an override of the data direction of the port pin. PINOUT I/O DESCRIPTIONS Pin Type Buffer Type AN0 - AN15 I Analog AVDD P P Positive supply for analog module. AVSS P P Ground reference for analog module. CLKI CLKO I O CN0 - CN23 I ST Input change notification inputs. Can be software programmed for internal weak pull-ups on all inputs. COFS CSCK CSDI CSDO I/O I/O I O ST ST ST -- Data Converter Interface frame synchronization pin. Data Converter Interface serial clock input/output pin. Data Converter Interface serial data input pin. Data Converter Interface serial data output pin. C1RX C1TX C2RX C2TX I O I O ST -- ST -- CAN1 bus receive pin. CAN1 bus transmit pin. CAN2 bus receive pin. CAN2 bus transmit pin. EMUD EMUC EMUD1 EMUC1 EMUD2 EMUC2 EMUD3 EMUC3 I/O I I/O I I/O I I/O I ST ST ST ST ST ST ST ST ICD Primary Communication Channel data input/output pin. ICD Primary Communication Channel clock input pin. ICD Secondary Communication Channel data input/output pin. ICD Secondary Communication Channel clock input pin. ICD Tertiary Communication Channel data input/output pin. ICD Tertiary Communication Channel clock input pin. ICD Quaternary Communication Channel data input/output pin. ICD Quaternary Communication Channel clock input pin. IC1 - IC8 I ST Capture inputs 1 through 8. INDX QEA I I ST ST QEB I ST UPDN O CMOS Quadrature Encoder Index Pulse input. Quadrature Encoder Phase A input in QEI mode. Auxiliary Timer External Clock/Gate input in Timer mode. Quadrature Encoder Phase A input in QEI mode. Auxiliary Timer External Clock/Gate input in Timer mode. Position Up/Down Counter Direction State. INT0 INT1 INT2 INT3 INT4 I I I I I ST ST ST ST ST LVDIN I Analog FLTA FLTB PWM1L PWM1H PWM2L PWM2H PWM3L PWM3H PWM4L PWM4H I I O O O O O O O O ST ST -- -- -- -- -- -- -- -- Pin Name Legend: Description Analog input channels. AN0 and AN1 are also used for device programming data and clock inputs, respectively. ST/CMOS External clock source input. Always associated with OSC1 pin function. -- Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. Always associated with OSC2 pin function. External interrupt 0. External interrupt 1. External interrupt 2. External interrupt 3. External interrupt 4. Low Voltage Detect Reference Voltage input pin. PWM Fault A input. PWM Fault B input. PWM 1 Low output. PWM 1 High output. PWM 2 Low output. PWM 2 High output. PWM 3 Low output. PWM 3 High output. PWM 4 Low output. PWM 4 High output. CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input 2002 Microchip Technology Inc. Analog = Analog input O = Output P = Power Advance Information DS70082A-page 11 dsPIC30F TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Type Buffer Type MCLR I/P ST Master Clear (Reset) input or programming voltage input. This pin is an active low RESET to the device. OCFA OCFB OC1 - OC8 I I O ST ST -- Compare Fault A input (for Compare channels 1, 2, 3 and 4). Compare Fault B input (for Compare channels 5, 6, 7 and 8). Compare outputs 1 through 8. OSC1 OSC2 I I/O PGD PGC I/O I ST ST In-Circuit Serial Programming data input/output pin. In-Circuit Serial Programming clock input pin. RA9 - RA10 RA14 - RA15 I/O I/O ST ST PORTA is a bi-directional I/O port. RB0 - RB15 I/O ST PORTB is a bi-directional I/O port. RC1 RC3 RC13 - RC15 I/O I/O I/O ST ST ST PORTC is a bi-directional I/O port. RD0 - RD15 I/O ST PORTD is a bi-directional I/O port. RE0 - RE9 I/O ST PORTE is a bi-directional I/O port. RF0 - RF8 I/O ST PORTF is a bi-directional I/O port. RG0 - RG3 RG6 - RG9 I/O I/O ST ST PORTG is a bi-directional I/O port. SCK1 SDI1 SDO1 SS1 SCK2 SDI2 SDO2 SS2 I/O I O I I/O I O I ST ST -- ST ST ST -- ST Synchronous serial clock input/output for SPI1. SPI1 Data In. SPI1 Data Out. SPI1 Slave Synchronization. Synchronous serial clock input/output for SPI2. SPI2 Data In. SPI2 Data Out. SPI2 Slave Synchronization. SCL SDA I/O I/O ST ST Synchronous serial clock input/output for I2C. Synchronous serial data input/output for I2C. SOSC1 SOSC2 I O T1CK T2CK T3CK T4CK T5CK I I I I I ST ST ST ST ST Timer1 external clock input. Timer2 external clock input. Timer3 external clock input. Timer4 external clock input. Timer5 external clock input. U1RX U1TX U1ARX U1ATX U2RX U2TX I O I O I O ST -- ST -- ST -- UART1 Receive. UART1 Transmit. UART1 Alternate Receive. UART1 Alternate Transmit. UART2 Receive. UART2 Transmit. VDD P -- Positive supply for logic and I/O pins. VSS P -- Ground reference for logic and I/O pins. VREF+ I Analog Analog Voltage Reference (High) input. I Analog Analog Voltage Reference (Low) input. Pin Name VREFLegend: Description ST/CMOS Oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise. -- Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. ST/CMOS 32 kHz low power oscillator crystal input; CMOS otherwise. -- 32 kHz low power oscillator crystal output. CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input DS70082A-page 12 Analog = Analog input O = Output P = Power Advance Information 2002 Microchip Technology Inc. dsPIC30F 2.0 CORE ARCHITECTURE OVERVIEW 2.1 Core Overview The X AGU also supports bit-reversed addressing on destination effective addresses, to greatly simplify input or output data reordering for radix-2 FFT algorithms. Refer to Section 4.0 for details on modulo and bit-reversed addressing. The core has a 24-bit instruction word. The Program Counter (PC) is 23-bits wide with the Least Significant (LS) bit always clear (see Section 3.1), and the Most Significant (MS) bit is ignored during normal program execution, except for certain specialized instructions. Thus, the PC can address up to 4M instruction words of user program space. An instruction pre-fetch mechanism is used to help maintain throughput. Unconditional overhead free program loop constructs are supported using the DO and REPEAT instructions, both of which are interruptible at any point. The working register array consists of 16 x 16-bit registers, each of which can act as data, address or offset registers. One working register (W15) operates as a software stack pointer for interrupts and calls. The data space is 64 Kbytes (32K words), and is split into two blocks, referred to as X and Y data memory. Each block has its own independent Address Generation Unit (AGU). Most instructions operate solely through the X memory AGU, which provides the appearance of a single unified data space. The Multiply-Accumulate (MAC) class of dual source DSP instructions operate through both the X and Y AGUs, splitting the data address space into two parts (see Section 3.2). The X and Y data space boundary is device specific and cannot be altered by the user. Each data word consists of 2 bytes, and most instructions can address data either as words or bytes. There are two methods of accessing data stored in program memory: * The upper 32 Kbytes of data space memory can optionally be mapped into the lower half (user space) of program space at any 16K program word boundary, defined by the 8-bit Program Space Visibility Page (PSVPAG) register. This lets any instruction access program space as if it were data space, with the sole limitation that the access requires an additional cycle. Moreover, only the lower 16 bits of each instruction word can be accessed using this method. * Linear indirect access of 32K word pages within program space is also possible using any working register, via table read and write instructions. Table read and write instructions can be used to access all 24 bits of an instruction word. The core supports Inherent (no operand), Relative, Literal, Memory Direct, Register Direct, Register Indirect, Register Offset and Literal Offset Addressing modes. Instructions are associated with predefined Addressing modes, depending upon their functional requirements. For most instructions, the core is capable of executing a data (or program data) memory read, a working register (data) read, a data memory write and a program (instruction) memory read per instruction cycle. As a result, 3-operand instructions are supported, allowing C = A+B operations to be executed in a single cycle. A DSP engine has been included to significantly enhance the core arithmetic capability and throughput. It features a high speed 17-bit by 17-bit multiplier, a 40-bit ALU, two 40-bit saturating accumulators and a 40-bit bi-directional barrel shifter. Data in the accumulator or any working register can be shifted up to 15 bits right or 16 bits left in a single cycle. The DSP instructions operate seamlessly with all other instructions and have been designed for optimal real-time performance. The MAC class of instructions can concurrently fetch two data operands from memory, while multiplying two W registers. To enable this concurrent fetching of data operands, the data space is split for these instructions and linear for all others. This is achieved in a transparent and flexible manner, through dedicating certain working registers to each address space for the MAC class of instructions. The core does not support a multi-stage instruction pipeline. However, a single stage instruction pre-fetch mechanism is used, which accesses and partially pre-decodes instructions a cycle ahead to maximize available execution time. Most instructions execute in a single cycle, with certain exceptions as outlined in Section 2.3. The core features a vectored exception processing structure for traps and interrupts, with 62 independent vectors. The exceptions consist of up to 8 traps (of which 4 are reserved) and 54 interrupts. Each interrupt is prioritized based on a user assigned priority between 1 and 7 (1 being the lowest priority and 7 being the highest) in conjunction with a predetermined `natural order'. Traps have fixed priorities, ranging from 8 to 15. Overhead-free circular buffers (modulo addressing) are supported in both X and Y address spaces. This is primarily intended to remove the loop overhead for DSP algorithms. 2002 Microchip Technology Inc. Advance Information DS70082A-page 13 dsPIC30F 2.2 2.2.2 Programmer's Model The programmer's model is shown in Figure 2-1 and consists of 16 x 16-bit working registers (W0 through W15), 2 x 40-bit accumulators (AccA and AccB), STATUS register (SR), Data Table Page register (TBLPAG), Program Space Visibility Page register (PSVPAG), DO and REPEAT registers (DOSTART, DOEND, DCOUNT and RCOUNT), and Program Counter (PC). The working registers can act as data, address or offset registers. All registers are memory mapped. W0 acts as the W register for file register addressing. Most of these registers have a shadow register associated with each of them, as shown in Figure 2-1. The shadow register is used as a temporary holding register and can transfer its contents to or from its host register upon some the occurrence of an event. None of the shadow registers are accessible directly. The following rules apply for transfer of registers into and out of shadows. * PUSH.S and POP.S W0...W14, TBLPAG, PSVPAG, SR (DC, N, OV, Z and C bits only) transferred * DO instruction DOSTART, DOEND, DCOUNT shadows pushed on loop start, popped on loop end When a byte operation is performed on a working register, only the Least Significant Byte of the target register is affected. However, a benefit of memory mapped working registers is that both the Least and Most Significant Bytes can be manipulated through byte wide data memory space accesses. 2.2.1 SOFTWARE STACK POINTER/ FRAME POINTER The dsPICTM devices contain a software stack. W15 is the dedicated software stack pointer (SP), and will be automatically modified by exception processing and subroutine calls and returns. However, W15 can be referenced by any instruction in the same manner as all other W registers. This simplifies the reading, writing and manipulation of the stack pointer (e.g., creating stack frames). Note: In order to protect against misaligned stack accesses, W15<0> is always clear. W15 is initialized to 0x0800 during a RESET. The user may reprogram the SP during initialization to any location within data space. W14 has been dedicated as a stack frame pointer as defined by the LNK and ULNK instructions. However, W14 can be referenced by any instruction in the same manner as all other W registers. DS70082A-page 14 STATUS REGISTER The dsPIC core has a 16-bit status register (SR), the LS Byte of which is referred to as the SR Low Byte (SRL) and the MS Byte as the SR High Byte (SRH). See Figure 2-1 for SR layout. SRL contains all the MCU ALU operation status flags (including the Z bit), as well as the CPU Interrupt Priority Level status bits, IPL<2:0>, and the REPEAT active status bit, RA. During exception processing, SRL is concatenated with the MS Byte of the PC to form a complete word value which is then stacked. The upper byte of the STATUS register contains the DSP Adder/Subtractor status bits, the DO Loop Active bit (DA) and the Digit Carry (DC) status bit. Most SR bits are read/write. Exceptions are: 1. 2. 3. 4. The DA bit: DA is read and clear only, because accidentally setting it could cause erroneous operation. The RA bit: RA is a read only bit, because accidentally setting it could cause erroneous operation. RA is only set on entry into a repeat loop, and cannot be directly cleared by software. The OV, OA, OB and OAB bits: These bits are read only and can only be set by the DSP engine overflow logic. The SA, SB and SAB bits: These are read and clear only and can only be set by the DSP engine saturation logic. Once set, these flags remain set until cleared by the user, irrespective of the results from any subsequent DSP operations. Note 1: Clearing the SAB bit will also clear both the SA and SB bits. 2: When the memory mapped status register (SR) is the destination address for an operation which affects any of the SR bits, data writes are disabled to all bits. 2.2.2.1 Z Status Bit Instructions that use a carry/borrow input (ADDC, CPB, SUBB and SUBBR) will only be able to clear Z (for a non-zero result) and can never set it. A multiprecision sequence of instructions (starting with an instruction with no carry/borrow input) will thus, automatically logically AND the successive results of the zero test. All results must be zero for the Z flag to remain set by the end of the sequence. All other instructions can set as well as clear the Z bit. 2.2.3 PROGRAM COUNTER The Program Counter is 23-bits wide. Bit 0 is always clear. Therefore, the PC can address up to 4M instruction words. Advance Information 2002 Microchip Technology Inc. dsPIC30F FIGURE 2-1: PROGRAMMER'S MODEL D15 D0 W0/WREG PUSH.S Shadow W1 DO Shadow W2 W3 Legend W4 DSP Operand Registers W5 W6 W7 Working Registers W8 W9 DSP Address Registers W10 W11 W12/DSP Offset W13/DSP Write Back W14/Frame Pointer W15/Stack Pointer SPLIM AD39 Stack Pointer Limit Register AD15 AD31 AD0 AccA DSP Accumulators AccB PC22 PC0 Program Counter 0 0 7 TABPAG TBLPAG 7 Data Table Page Address 0 PSVPAG Program Space Visibility Page Address 15 0 RCOUNT REPEAT Loop Counter 15 0 DCOUNT DO Loop Counter 22 0 DOSTART DO Loop Start Address DOEND DO Loop End Address 22 15 0 Core Configuration Register CORCON OA OB SA SB OAB SAB DA SRH 2002 Microchip Technology Inc. DC IPL2 IPL1 IPL0 RA N OV Z C Status Register SRL Advance Information DS70082A-page 15 dsPIC30F 2.3 Instruction Flow There are 8 types of instruction flows: 1. Normal one-word, one-cycle instructions. These instructions take one effective cycle to execute, as shown in Figure 2-2. FIGURE 2-2: INSTRUCTION PIPELINE FLOW: 1-WORD, 1-CYCLE TCY0 Fetch 1 1. MOV.b #0x55,W0 TCY1 One-word, two-cycle (or three-cycle) instructions. These instructions include the relative branches, relative call, skips and returns. When an instruction changes the PC (other than to increment it), the pipelined fetch is discarded. This causes the instruction to take two effective FIGURE 2-3: TCY4 Execute 3 cycles to execute as shown in Figure 2-3. Some program flow change instructions, such as skip instructions that skip over 2-word instructions, and the RETURN, RETFIE and RETLW instructions that are used to return from a subroutine call or Interrupt Service Routine, require 3 cycles. INSTRUCTION PIPELINE FLOW: 1-WORD, 2-CYCLE TCY0 Fetch 1 1. MOV #0x55,W0 TCY1 TCY2 TCY3 TCY4 Execute 2 Skip Taken Fetch 3 3. ADD W0,W1,W2 Flush Fetch 4 4. BRA SUB_1 Execute 4 Fetch 5 5. SUB W0,W1,W3 Flush Fetch SUB_1 6. Instruction @ address SUB_1 One-word, two-cycle instructions that are not flow control instructions. The only instructions of FIGURE 2-4: TCY5 Execute 1 Fetch 2 2. BTSC W1,#3 3. TCY5 Execute 2 Fetch 3 3. ADD.b W0,W1,W2 2. TCY3 Execute 1 Fetch 2 2. MOV.b #0x35,W1 TCY2 this type are the MOV.D (load and store double word) instructions, as shown in Figure 2-4. INSTRUCTION PIPELINE FLOW: 1-WORD, 2-CYCLE MOV.D OPERATIONS TCY0 1. MOV W0,0x1234 2. MOV.D [W0++],W1 Fetch 1 TCY1 TCY2 TCY3 TCY4 TCY5 Execute 1 Fetch 2 Execute 2 R/W Cycle 1 3. MOV W1,0x00AA Fetch 3 Execute 2 R/W Cycle2 3a. Stall Stall DS70082A-page 16 Execute 3 Fetch 4 4. MOV 0x0CC, W0 Advance Information Execute 4 2002 Microchip Technology Inc. dsPIC30F 4. Table read/write instructions. These instructions will suspend the fetching to insert a read or write cycle to the program memory. The instruction fetched while executing the table operation is FIGURE 2-5: saved for 1 cycle and executed in the cycle immediately after the table operation, as shown in Figure 2-5. INSTRUCTION PIPELINE FLOW: 1-WORD, 2-CYCLE TABLE OPERATIONS TCY0 Fetch 1 1. MOV #0x1234,W0 TCY1 TCY3 Execute 2 Read Cycle Bus Read 3a. Table Operation Two-word instructions for CALL and GOTO. In these instructions, the fetch after the instruction provides the remainder of the jump or call destination address. These instructions require 2 Fetch 1 1. MOV #0x1234,W0 TCY1 cycles to execute, 1 for fetching the 2 instruction words (enabled by a high speed path on the second fetch), and 1 for the subsequent pipeline flush, as shown in Figure 2-6. TCY2 TCY3 TCY4 TCY5 Execute 1 Fetch 2L 2. GOTO LABEL Update PC Fetch 2H 2a. Second Word NOP Fetch LABEL 3. Instruction @ address LABEL Execute LABEL Fetch 4 4. BSET W1, #BIT3 Two-word instructions for DO. In these instructions, the fetch after the instruction contains an address offset. This address offset is added to the first instruction address to generate the last FIGURE 2-7: Execute 4 INSTRUCTION PIPELINE FLOW: 2-WORD, 2-CYCLE GOTO, CALL TCY0 6. Execute 3 Fetch 4 4. MOV #0x0CC,W0 FIGURE 2-6: TCY5 Execute 2 Fetch 3 3. MOV #0x00AA,W1 5. TCY4 Execute 1 Fetch 2 2. TBLRDL [W0++],W1 TCY2 Execute 4 loop instruction address. Therefore, these instructions require two cycles, as shown in Figure 2-7. INSTRUCTION PIPELINE FLOW: 2-WORD, 2-CYCLE DO, DOW TCY0 1. PUSH DOEND Fetch 1 2. DO LABEL,#COUNT 2a. Second Word 3. 1st Instruction of Loop 2002 Microchip Technology Inc. TCY1 TCY2 TCY3 TCY4 Execute 1 Fetch 2L NOP Fetch 2H Execute 2 Fetch 3 Advance Information Execute 3 DS70082A-page 17 dsPIC30F 7. Instructions that are subjected to a stall due to a data dependency between the X RAGU and X WAGU. An additional cycle is inserted to resolve FIGURE 2-8: INSTRUCTION PIPELINE FLOW: 1-WORD, 2-CYCLE WITH INSTRUCTION STALL 1. MOV.b W0,[W1] TCY0 TCY1 Fetch 1 Execute 1 TCY2 Fetch 2 2. MOV.b [W1],PORTB Interrupt recognition execution. Refer Section 5.0 for details on interrupts. to Divide Support The dsPIC devices feature a 16/16-bit signed fractional divide operation, as well as 32/16-bit and 16/16-bit signed and unsigned integer divide operations, in the form of single instruction iterative divides. The following instructions and data sizes are supported: 1. 2. 3. 4. 5. DIVF - 16/16 signed fractional divide DIV.sd - 32/16 signed divide DIV.ud - 32/16 unsigned divide DIV.sw - 16/16 signed divide DIV.uw - 16/16 unsigned divide The 16/16 divides are similar to the 32/16 (same number of iterations), but the dividend is either zero-extended or sign-extended during the first iteration. The quotient for all divide instructions ends up in W0, and the remainder in W1. DIV and DIVF can specify any W register for both the 16-bit dividend and divisor. All other divides can specify any W register for the 16-bit divisor, but the 32-bit dividend must be in an aligned W register pair, such as W1:W0, W3:W2, etc. TABLE 2-1: TCY4 TCY5 Execute 2 Fetch 3 3. MOV.b W0,PORTB 2.4 TCY3 NOP Stall 2a. Stall (NOP) 8. the resource conflict, as shown in Figure 2-7. Instruction stalls caused by data dependencies are further discussed in Section 4.0. Execute 3 The non-restoring divide algorithm requires one cycle for an initial dividend shift (for integer divides only), one cycle per divisor bit, and a remainder/quotient correction cycle. The correction cycle is the last cycle of the iteration loop, but must be performed (even if the remainder is not required) because it may also adjust the quotient. A consequence of this is that DIVF will also produce a valid remainder (though it is of little use in fractional arithmetic). The divide instructions must be executed within a REPEAT loop. Any other form of execution (e.g. a series of discrete divide instructions) will not function correctly because the instruction flow depends on RCOUNT. The divide instruction does not automatically set up the RCOUNT value, and it must, therefore, be explicitly and correctly specified in the REPEAT instruction, as shown in Table 2-1 (REPEAT will execute the target instruction {operand value+1} times). The REPEAT loop count must be set up for 18 iterations of the DIV/DIVF instruction. Thus, a complete divide operation requires 19 cycles. Note: The Divide flow is interruptible. However, the user needs to save the context as appropriate. DIVIDE INSTRUCTIONS Instruction Function DIVF Signed fractional divide: Wm/Wn W0; Rem W1 DIV.sd Signed divide: (Wm+1:Wm)/Wn W0; Rem W1 DIV.sw Signed divide: Wm/Wn W0; Rem W1 DIV.ud Unsigned divide: (Wm+1:Wm)/Wn W0; Rem W1 DIV.uw Unsigned divide: Wm/Wn W0; Rem W1 DS70082A-page 18 Advance Information 2002 Microchip Technology Inc. dsPIC30F 2.5 DSP Engine Concurrent operation of the DSP engine with MCU instruction flow is not possible, though both the MCU ALU and DSP engine resources may be used concurrently by the same instruction (e.g., ED and EDAC instructions). The DSP engine consists of a high speed 17-bit x 17-bit multiplier, a barrel shifter and a 40-bit adder/ subtractor with two target accumulators, round and saturation logic. Data input to the DSP engine is derived from one of the following: 1. 2. 3. Directly from the W array (registers W4, W5, W6 or W7) via the X and Y data buses for the MAC class of instructions (MAC, MSC, MPY, MPY.N, ED, EDAC, CLR and MOVSAC). From the X bus for all other DSP instructions. From the X bus for all MCU instructions which use the barrel shifter. The DSP engine also has the capability to perform inherent accumulator-to-accumulator operations, which require no additional data. These instructions are ADD, SUB and NEG. The DSP engine has various options selected through various bits in the CPU Core Configuration Register (CORCON), as listed below: 1. 2. 3. 4. 5. 6. Fractional or integer multiply (IF). Conventional or convergent rounding (RND). Automatic saturation on/off for AccA (SATA). Automatic saturation on/off for AccB (SATB). Automatic saturation on/off for writes to data memory (SATDW). Accumulator Saturation mode selection (ACCSAT). Note: For CORCON layout, see Table 4-3. A block diagram of the DSP engine is shown in Figure 2-9. Data output from the DSP engine is written to one of the following: 1. 2. 3. The target accumulator, as defined by the DSP instruction being executed. The X bus for MAC, MSC, CLR and MOVSAC accumulator writes, where the EA is derived from W13 only. (MPY, MPY.N, ED and EDAC do not offer an accumulator write option.) The X bus for all MCU instructions which use the barrel shifter. 2002 Microchip Technology Inc. Advance Information DS70082A-page 19 dsPIC30F FIGURE 2-9: DSP ENGINE BLOCK DIAGRAM 40 S a 40 Round t 16 u Logic r a t e 40-bit Accumulator A 40-bit Accumulator B Carry/Borrow Out Carry/Borrow In Saturate Adder Negate 40 40 40 Barrel Shifter X Data Bus 16 40 Y Data Bus Sign-Extend 32 16 Zero Backfill 32 33 17-bit Multiplier/Scaler 16 16 To/From W Array DS70082A-page 20 Advance Information 2002 Microchip Technology Inc. dsPIC30F 2.5.1 MULTIPLIER to 32767 (0x7FFF), including 0 (see Figure 2-10). For a 32-bit integer, the data range is -2,147,483,648 (0x8000 0000) to 2,147,483,645 (0x7FFF FFFF). The 17x17-bit multiplier is capable of signed or unsigned operation and can multiplex its output using a scaler to support either 1.31 fractional (Q31), or 32-bit integer results. Unsigned operands are zero-extended into the 17th bit of the multiplier input value. Signed operands are sign-extended into the 17th bit of the multiplier input value. The output of the 17x17-bit multiplier/scaler is a 33-bit value, which is sign-extended to 40 bits. The respective number representation formats are shown in Figure 2-10. Integer data is inherently represented as a signed two's complement value, where the MSB is defined as a sign bit. Generally speaking, the range of an N-bit two's complement integer is -2N-1 to 2N-1 - 1. For a 16-bit integer, the data range is -32768 (0x8000) FIGURE 2-10: When the multiplier is configured for Fractional multiplication, the data is represented as a two's complement fraction, where the MSB is defined as a sign bit and the radix point is implied to lie just after the sign bit (QX format). The range of an N-bit two's complement fraction with this implied radix point is -1.0 to (1-21-N). For a 16-bit fraction, the Q15 data range is -1.0 (0x8000) to 0.999969482 (0x7FFF), including 0 and has a precision of 3.01518x10-5. In Fractional mode, a 16x16 multiply operation generates a 1.31 product, which has a precision of 4.65661x10-10. 16-BIT INTEGER AND FRACTIONAL MODES Different Representations of 0x4001 Integer: 0 1 0 0 0 20 214 213 212 211 0 0 0 0 0 0 0 0 0 0 1 20 .... 0x4001 = 214 + 20 = 16385 1.15 Fractional: 0 1 0 0 0 -20 -1 -2 -3 ... 2 2 2 0 0 0 0 0 0 0 0 0 0 1 2-15 0x4001 = 2-1 + 2-15 = 0.500030518 Certain multiply operations always operate on signed data. These include the MAC/MSC, MPY[.N] and ED[AC] instructions. The 40-bit adder/subtractor may also optionally negate one of its operand inputs to change the result sign (without changing the operands). This is used to create a multiply and subtract (MSC) or multiply and negate (MPY.N) operation. result. However, multiplying two 1.15 values generates a 2.30 result. Since the dsPIC30F uses 1.31 format for the accumulators, a DSP multiply in Fractional mode also includes a left shift by one bit to keep the radix point properly aligned. This feature reduces the resolution of the DSP multiplier to 2-30, but has no other effect on the computation. In the special case when both input operands are 1.15 fractions and equal to 0x8000 (-110), the result of the multiplication is corrected to 0x7FFFFFFF (as the closest approximation to +1) by hardware, before it is used. The same multiplier is used to support the MCU multiply instructions, which include integer 16-bit signed, unsigned and mixed sign multiplies. Additional data paths are provided to allow these instructions to write the result back into the W array and X data bus (via the W array). These paths are placed prior to the data scaler. The IF bit in the CORCON register, therefore, only affects the result of the MAC and MPY instructions. All other multiply operations are assumed to be integer operations. If the user executes a MAC or MPY instruction on fractional data, without clearing the IF bit, the result must be explicitly shifted left by the user program after multiplication, in order to obtain the correct result. It should be noted that with the exception of DSP multiplies, the dsPIC30F ALU operates identically on integer and fractional data. Namely, an addition of two integers will yield the same result (binary number) as the addition of two fractional numbers. The only difference is how the result is interpreted by the user. However, multiplies performed by DSP operations are different. In these instructions, data format selection is made by the IF bit (CORCON<0>), and it must be set accordingly (`0' for Fractional mode, `1' for Integer mode). This is required because of the implied radix point used by dsPIC30F fractions. In Integer mode, multiplying two 16-bit integers produces a 32-bit integer 2002 Microchip Technology Inc. The MUL instruction may be directed to use byte or word sized operands. Byte operands will direct a 16-bit result, and word operands will direct a 32-bit result to the specified register(s) in the W array. Advance Information DS70082A-page 21 dsPIC30F 2.5.2 DATA ACCUMULATORS AND ADDER/SUBTRACTOR The data accumulator consists of a 40-bit adder/ subractor with automatic sign extension logic. It can select one of two accumulators (A or B) as its preaccumulation source and post-accumulation destination. For the ADD and LAC instructions, the data to be accumulated or loaded can be optionally scaled via the barrel shifter, prior to accumulation. 2.5.2.1 Adder/Subtractor, Overflow and Saturation The adder/subtractor is a 40-bit adder with an optional zero input into one side and either true, or complement data into the other input. In the case of addition, the carry/borrow input is active high and the other input is true data (not complemented), whereas in the case of subtraction, the carry/borrow input is active low and the other input is complemented. The adder/subtractor generates overflow status bits SA/SB and OA/OB, which are latched and reflected in the status register: * Overflow from bit 39: this is a catastrophic overflow in which the sign of the accumulator is destroyed. * Overflow into guard bits 32 through 39: this is a recoverable overflow. This bit is set whenever all the guard bits bits are not identical to each other. The adder has an additional saturation block which controls accumulator data saturation, if selected. It uses the result of the adder, the overflow status bits described above, and the SATA/B (CORCON<7:6>) and ACCSAT (CORCON<4>) mode control bits to determine when to saturate and to what value to saturate. The OA and OB bits are modified each time data passes through the adder/subtractor. When set, they indicate that the most recent operation has overflowed into the accumulator guard bits (bits 32 through 39). The OA and OB bits can also optionally generate an arithmetic warning trap when set and the corresponding overflow trap flag enable bit (OVATEN, OVBTEN) in the INTCON1 register (refer to Section 5.0) is set. This allows the user to take immediate action, for example, to correct system gain. The SA and SB bits are modified each time data passes through the adder/subtractor, but can only be cleared by the user. When set, they indicate that the accumulator has overflowed its maximum range (bit 31 for 32-bit saturation, or bit 39 for 40-bit saturation) and will be saturated (if saturation is enabled). When saturation is not enabled, the SA and SB default to bit 39 overflow and thus, indicate that a catastrophic overflow has occurred. If the COVTE bit in the INTCON1 register is set, SA and SB bits will generate an arithmetic warning trap when saturation is disabled. The overflow and saturation status bits can optionally be viewed in the Status Register (SR) as the logical OR of OA and OB (in bit OAB) and the logical OR of SA and SB (in bit SAB). This allows programmers to check one bit in the Status Register to determine if either accumulator has overflowed, or one bit to determine if either accumulator has saturated. This would be useful for complex number arithmetic which typically uses both the accumulators. The device supports three Saturation and Overflow modes. 1. Six status register bits have been provided to support saturation and overflow; they are: 1. 2. 3. 4. 5. 6. OA: AccA overflowed into guard bits OB: AccB overflowed into guard bits SA: AccA saturated (bit 31 overflow and saturation) or AccA overflowed into guard bits and saturated (bit 39 overflow and saturation) SB: AccB saturated (bit 31 overflow and saturation) or AccB overflowed into guard bits and saturated (bit 39 overflow and saturation) OAB: Logical OR of OA and OB SAB: Logical OR of SA and SB DS70082A-page 22 2. 3. Bit 39 Overflow and Saturation: When bit 39 overflow and saturation occurs, the saturate logic loads the maximally positive 9.31 (0x7FFFFFFFFF) or maximally negative 9.31 value (0x8000000000) into the target accumulator. The SA or SB bit is set and remains set until cleared by the user. This is referred to as `super saturation' and provides protection against erroneous data, or unexpected algorithm problems (e.g., gain calculations). Bit 31 Overflow and Saturation: When bit 31 overflow and saturation occurs, the saturate logic then loads the maximally positive 1.31 value (0x007FFFFFFF) or maximally negative 1.31 value (0x0080000000) into the target accumulator. The SA or SB bit is set and remains set until cleared by the user. When this Saturation mode is in effect, the guard bits are not used (so the OA, OB or OAB bits are never set). Bit 39 Catastrophic Overflow The bit 39 overflow status bit from the adder is used to set the SA or SB bit, which remain set until cleared by the user. No saturation operation is performed and the accumulator is allowed to overflow (destroying its sign). If the COVTE bit in the INTCON1 register is set, a catastrophic overflow can initiate a trap exception. Advance Information 2002 Microchip Technology Inc. dsPIC30F 2.5.2.2 Accumulator `Write Back' 2.5.2.4 The MAC class of instructions (with the exception of MPY, MPY.N, ED and EDAC) can optionally write a rounded version of the high word (bits 31 through 16) of the accumulator, that is not targeted by the instruction into data space memory. The write is performed across the X bus into combined X and Y address space. The following Addressing modes are supported. 1. 2. W13, Register Direct: The rounded contents of the non-target accumulator are written into W13 as a 1.15 fraction. [W13]+=2, Register Indirect with Post-Increment: The rounded contents of the non-target accumulator are written into the address pointed to by W13 as a 1.15 fraction. W13 is then incremented by 2 (for a word write). 2.5.2.3 Round Logic The round logic is a combinational block, which performs a conventional (biased) or convergent (unbiased) round function during an accumulator write (store). The Round mode is determined by the state of the RND bit in the CORCON register. It generates a 16-bit, 1.15 data value which is passed to the data space write saturation logic. If rounding is not indicated by the instruction, a truncated 1.15 data value is stored and the LS Word is simply discarded. The two Rounding modes are shown in Figure 7-7. Conventional rounding takes bit 15 of the accumulator, zero-extends it and adds it to the ACCxH word (bits 16 through 31 of the accumulator). If the ACCxL word (bits 0 through 15 of the accumulator) is between 0x8000 and 0xFFFF (0x8000 included), ACCxH is incremented. If ACCxL is between 0x0000 and 0x7FFF, ACCxH is left unchanged. A consequence of this algorithm is that over a succession of random rounding operations, the value will tend to be biased slightly positive. Convergent (or unbiased) rounding operates in the same manner as conventional rounding, except when ACCxL equals 0x8000. If this is the case, the LS bit (bit 16 of the accumulator) of ACCxH is examined. If it is 1, ACCxH is incremented. If it is 0, ACCxH is not modified. Assuming that bit 16 is effectively random in nature, this scheme will remove any rounding bias that may accumulate. Data Space Write Saturation In addition to adder/subtractor saturation, writes to data space may also be saturated, but without affecting the contents of the source accumulator. The data space write saturation logic block accepts a 16-bit, 1.15 fractional value from the round logic block as its input, together with overflow status from the original source (accumulator) and the 16-bit round adder. These are combined and used to select the appropriate 1.15 fractional value as output to write to data space memory. If the SATDW bit in the CORCON register is set, data (after rounding or truncation) is tested for overflow and adjusted accordingly, For input data greater than 0x007FFF, data written to memory is forced to the maximum positive 1.15 value, 0x7FFF. For input data less than 0xFF8000, data written to memory is forced to the maximum negative 1.15 value, 0x8000. The MS bit of the source (bit 39) is used to determine the sign of the operand being tested. If the SATDW bit in the CORCON register is not set, the input data is always passed through unmodified under all conditions. 2.5.3 BARREL SHIFTER The barrel shifter is capable of performing up to 15-bit arithmetic or logic right shifts, or up to 16-bit left shifts in a single cycle. The source can be either of the two DSP accumulators, or the X bus (to support multi-bit shifts of register or memory data). The shifter requires a signed binary value to determine both the magnitude (number of bits) and direction of the shift operation. A positive value will shift the operand right. A negative value will shift the operand left. A value of 0 will not modify the operand. The barrel shifter is 40 bits wide, thereby obtaining a 40-bit result for DSP shift operations and a 16-bit result for MCU shift operations. Data from the X bus is presented to the barrel shifter between bit positions 16 to 31 for right shifts, and bit positions 0 to 15 for left shifts. The SAC and SAC.R instructions store either a truncated (SAC) or rounded (SAC.R) version of the contents of the target accumulator to data memory, via the X bus (subject to data saturation, see Section 2.5.2.4). Note that for the MAC class of instructions, the accumulator write back operation will function in the same manner, addressing combined MCU (X and Y) data space though the X bus. For this class of instructions, the data is always subject to rounding. 2002 Microchip Technology Inc. Advance Information DS70082A-page 23 dsPIC30F NOTES: DS70082A-page 24 Advance Information 2002 Microchip Technology Inc. dsPIC30F 3.0 MEMORY ORGANIZATION 3.1 Program Address Space User program space access is restricted to the lower 4M instruction word address range (0x000000 to 0x7FFFFE), for all accesses other than TBLRD/TBLWT, which use TBLPAG<7> to determine user or configuration space access. In Table 3-1, Read/Write instructions, bit 23 allows access to the Device ID, the User ID and the configuration bits. Otherwise, bit 23 is always clear. The program address space is 4M instruction words. It is addressable by a 24-bit value from either the PC, table instruction EA, or data space EA, when program space is mapped into data space, as defined by Table 3-1. Note that the program space address is incremented by two between successive program words, in order to provide compatibility with data space addressing. TABLE 3-1: The address map shown in Figure 3-5 is conceptual, and the actual memory configuration may vary across individual devices depending on available memory. PROGRAM SPACE ADDRESS CONSTRUCTION Program Space Address <23> <22:16> <15> <14:1> 0 PC<22:1> TBLPAG<7:0> Data EA <15:0> Access Space Access Type Instruction Access TBLRD/TBLWT TBLRD/TBLWT Program Space Visibility FIGURE 3-1: Note: User User (TBLPAG<7> = 0) Configuration (TBLPAG<7> = 1) User TBLPAG<7:0> 0 <0> 0 Data EA <15:0> PSVPAG<7:0> Data EA <14:0> DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION 24-bits Using Program Counter Program Counter 0 Select Using Program Space Visibility 0 1 0 EA PSVPAG Reg 8-bits 15-bits EA Using Table Instruction 1/0 TBLPAG Reg 8-bits User/ Configuration Space Select 16-bits 24-bit EA Byte Select Note: Program Space Visibility cannot be used to access bits <23:16> of a word in program memory. 2002 Microchip Technology Inc. Advance Information DS70082A-page 25 dsPIC30F 3.1.1 PROGRAM SPACE ALIGNMENT AND DATA ACCESS USING TABLE INSTRUCTIONS A set of Table Instructions are provided to move byte or word sized data to and from program space. 1. This architecture fetches 24-bit wide program memory. Consequently, instructions are always aligned. However, as the architecture is modified Harvard, data can also be present in program space. There are two methods by which program space can be accessed: via special table instructions, or through the remapping of a 16K word program space page into the upper half of data space (see Section 3.1.2). The TBLRDL and TBLWTL instructions offer a direct method of reading or writing the LS Word of any address within program space, without going through data space. The TBLRDH and TBLWTH instructions are the only method whereby the upper 8 bits of a program space word can be accessed as data. 2. 3. The PC is incremented by two for each successive 24-bit program word. This allows program memory addresses to directly map to data space addresses. Program memory can thus be regarded as two 16-bit word wide address spaces, residing side by side, each with the same address range. TBLRDL and TBLWTL access the space which contains the LS Data Word, and TBLRDH and TBLWTH access the space which contains the MS Data Byte. 4. TBLRDL: Table Read Low Word: Read the LS Word of the program address; P<15:0> maps to D<15:0>. Byte: Read one of the LS Bytes of the program address; P<7:0> maps to the destination byte when byte select = 0; P<15:8> maps to the destination byte when byte select = 1. TBLWTL: Table Write Low (refer to Section 6.0 for details on FLASH Programming). TBLRDH: Table Read High Word: Read the MS Word of the program address; P<23:16> maps to D<7:0>; D<15:8> always be = 0. Byte: Read one of the MS Bytes of the program address; P<23:16> maps to the destination byte when byte select = 0; The destination byte will always be = 0 when byte select = 1. TBLWTH: Table Write High (refer to Section 6.0 for details on FLASH Programming). Figure 3-1 shows how the EA is created for table operations and data space accesses (PSV = 1). Here, P<23:0> refers to a program space word, whereas D<15:0> refers to a data space word. FIGURE 3-2: PROGRAM DATA TABLE ACCESS (LS WORD) PC Address 0x000000 0x000002 0x000004 0x000006 Program Memory `Phantom' Byte (Read as `0'). DS70082A-page 26 23 8 16 0 00000000 00000000 00000000 00000000 TBLRDL.B (Wn<0> = 0) TBLRDL.W TBLRDL.B (Wn<0> = 1) Advance Information 2002 Microchip Technology Inc. dsPIC30F FIGURE 3-3: PROGRAM DATA TABLE ACCESS (MS BYTE) TBLRDH.W PC Address 0x000000 0x000002 0x000004 0x000006 23 16 8 0 00000000 00000000 00000000 00000000 TBLRDH.B (Wn<0> = 0) Program Memory `Phantom' Byte (Read as `0') 3.1.2 TBLRDH.B (Wn<0> = 1) PROGRAM SPACE VISIBILITY FROM DATA SPACE The upper 32 Kbytes of data space may optionally be mapped into any 16K word program space page. This provides transparent access of stored constant data from X data space, without the need to use special instructions (i.e., TBLRDL/H, TBLWTL/H instructions). Program space access through the data space occurs if the MS bit of the data space EA is set and program space visibility is enabled, by setting the PSV bit in the Core Control register (CORCON). The functions of CORCON are discussed in Section 6.0, DSP Engine. Data accesses to this area add an additional cycle to the instruction being executed, since two program memory fetches are required. Note that the upper half of addressable data space is always part of the X data space. Therefore, when a DSP operation uses program space mapping to access this memory region, Y data space should typically contain state (variable) data for DSP operations, whereas X data space should typically contain coefficient (constant) data. Although each data space address, 0x8000 and higher, maps directly into a corresponding program memory address (see Figure 3-4), only the lower 16-bits of the 24-bit program word are used to contain the data. The upper 8 bits should be programmed to force an illegal instruction to maintain machine robustness. Refer to the Programmer's Reference Manual (DS70030) for details on instruction encoding. 2002 Microchip Technology Inc. Note that by incrementing the PC by 2 for each program memory word, the LS 15 bits (16 bits for the TBLRDL/H, TBLWTL/H instructions) of data space addresses directly map to the LS 15 bits in the corresponding program space addresses. The remaining bits are provided by the Program Space Visibility Page register, PSVPAG<7:0>, as shown in Figure 3-4. Note: PSV access is temporarily disabled during Table Reads/Writes. 3.1.2.1 Data Pre-Fetch from Program Space Within a REPEAT Loop Consider the special case of any instruction executed within the REPEAT loop. When pre-fetching data resident in program space, via the data space window from within a REPEAT loop, all iterations of the repeated instruction will reload the instruction from the Instruction Latch without re-fetching it, thereby releasing the program bus for a data pre-fetch. In this example, the initial 2 data words for the first iteration of the instruction to be repeated (MAC) are fetched by a prior instruction (e.g., CLR instruction). The subsequent MAC instructions, therefore, only need to fetch two more data pairs to complete the loop. The initial fetch of the MAC instruction is performed by the REPEAT instruction. As a result, only the last iteration of the REPEAT loop requires 2 cycles to execute. Each of the other iterations executes in 1 cycle. Advance Information DS70082A-page 27 dsPIC30F EXAMPLE 3-1: PROGRAM SPACE DATA READ THROUGH DATA SPACE WITHIN A REPEAT LOOP ; In this example, data for MAC operations is stored in Program Space. CLR A, [W8]+=2, W4, [W10]+=2, W5 ; Acc. A cleared, data prefetched (2 cycles) REPEAT #99 ; Repeat the MAC operation 100 times (1 cycle) MAC W4*W5, A, [W8]+=2, W4, [W10]+=2, W5 ; MAC operation within REPEAT loop (2 cycles for 1st and 100th iterations, 1 cycle for 2nd - 99th iterations) FIGURE 3-4: DATA SPACE WINDOW INTO PROGRAM SPACE OPERATION Program Space Data Space 0x0000 PSVPAG(1) 0x21 8 15 EA<15> = 0 Data Space EA 16 15 EA<15> = 1 0x8000 Address 15 Concatenation 23 23 15 0 0x108000 0x108200 Upper Half of Data Space is Mapped into Program Space 0x10FFFF 0xFFFF BSET MOV MOV MOV CORCON,#2 #0x21, W0 W0, PSVPAG 0x8200, W0 ; PSV bit set ; Set PSVPAG register ; Access program memory location ; using a data space access Data Read Note: PSVPAG is an 8-bit register, containing bits <22:15> of the program space address (i.e., it defines the page in program space to which the upper half of data space is being mapped). DS70082A-page 28 Advance Information 2002 Microchip Technology Inc. dsPIC30F FIGURE 3-5: SAMPLE PROGRAM SPACE MEMORY MAP RESET - GOTO Instruction RESET - Target Address 000000 000002 000004 Vector Tables 3.2 Data Address Space The core has two data spaces. The data spaces can be considered either separate (for some DSP instructions), or as one unified linear address range (for MCU instructions). The data spaces are accessed using two Address Generation Units (AGUs) and separate data paths. Interrupt Vector Table User Memory Space 3.2.1 Reserved Alternate Vector Table User FLASH Program Memory (48K instructions) Reserved (Read 0's) Data FLASH (4 Kbytes) 00007E 000080 000084 0000FE 000100 017FFE 018000 7FEFFE 7FF000 7FFFFE 800000 Configuration Memory Space Reserved UNITID (32 instr.) 8005BE 8005C0 8005FE 800600 Reserved Device Configuration Registers F7FFFE F80000 F8000E F80010 Reserved DEVID (2) DATA SPACES The X data space is used by all instructions and supports all Addressing modes. There are separate read and write data buses. The X read data bus is the return data path for all instructions that view data space as combined X and Y address space. It is also the X address space data path for the dual operand read instructions (MAC class). The X write data bus is the only write path to data space for all instructions. The X data space also supports Modulo Addressing for all instructions, subject to Addressing mode restrictions. Bit-Reversed Addressing is only supported for writes to X data space. The Y data space is used in concert with the X data space by the MAC class of instructions (CLR, ED, EDAC, MAC, MOVSAC, MPY, MPY.N and MSC) to provide two concurrent data read paths. No writes occur across the Y bus. This class of instructions dedicates two W register pointers, W10 and W11, to always address Y data space, independent of X data space, whereas W8 and W9 always address X data space. Note that during accumulator write back, the data address space is considered a combination of X and Y data spaces, so the write occurs across the X bus. Consequently, it can be to any address in the entire data space. The Y data space can only be used for the data prefetch operation associated with the MAC class of instructions. It also supports Modulo Addressing for automated circular buffers. Of course, all other instructions can access the Y data address space through the X data path, as part of the composite linear space. The boundary between the X and Y data spaces is defined as shown in Figure 3-8 and is not user programmable. Should an EA point to data outside its own assigned address space, or to a location outside physical memory, an all-zero word/byte will be returned. For example, although Y address space is visible by all non-MAC instructions using any Addressing mode, an attempt by a MAC instruction to fetch data from that space, using W8 or W9 (X space pointers), will return 0x0000. FEFFFE FF0000 FFFFFE Note: These address boundaries may vary from one device to another. 2002 Microchip Technology Inc. Advance Information DS70082A-page 29 dsPIC30F TABLE 3-2: EFFECT OF INVALID MEMORY ACCESSES FIGURE 3-6: 15 DATA ALIGNMENT MS Byte 87 LS Byte 0 Data Returned 0001 Byte 1 Byte 0 0000 EA = an unimplemented address 0x0000 0003 Byte 3 Byte 2 0002 W8 or W9 used to access Y data space in a MAC instruction 0x0000 0005 Byte 5 Byte 4 0004 W10 or W11 used to access X data space in a MAC instruction 0x0000 Attempted Operation All effective addresses are 16-bits wide and point to bytes within the data space. Therefore, the data space address range is 64 Kbytes or 32K words. 3.2.2 DATA SPACE WIDTH The core data width is 16-bits. All internal registers are organized as 16-bit wide words. Data space memory is organized in byte addressable, 16-bit wide blocks. 3.2.3 DATA ALIGNMENT To help maintain backward compatibility with PICmicro(R) devices and improve data space memory usage efficiency, the dsPIC30F instruction set supports both word and byte operations. Data is aligned in data memory and registers as words, but all data space EAs resolve to bytes. Data byte reads will read the complete word, which contains the byte, using the LS bit of any EA to determine which byte to select. The selected byte is placed onto the LS Byte of the X data path (no byte accesses are possible from the Y data path as the MAC class of instruction can only fetch words). That is, data memory and registers are organized as two parallel byte wide entities with shared (word) address decode, but separate write lines. Data byte writes only write to the corresponding side of the array or register which matches the byte address. As a consequence of this byte accessibility, all effective address calculations (including those generated by the DSP operations, which are restricted to word sized data) are internally scaled to step through word aligned memory. For example, the core would recognize that Post-Modified Register Indirect Addressing mode [Ws++], will result in a value of Ws+1 for byte operations and Ws+2 for word operations. All word accesses must be aligned to an even address. Misaligned word data fetches are not supported, so care must be taken when mixing byte and word operations, or translating from 8-bit MCU code. Should a misaligned read or write be attempted, an Address Error trap will be generated. If the error occurred on a read, the instruction underway is completed, whereas if it occurred on a write, the instruction will be inhibited and the PC will not be incremented. In either case, a trap will then be executed, allowing the system and/or user to examine the machine state prior to execution of the address fault. DS70082A-page 30 All byte loads into any W register are loaded into the LS Byte. The MSB is not modified. A sign-extend (SE) instruction is provided to allow users to translate 8-bit signed data to 16-bit signed values. Alternatively, for 16-bit unsigned data, users can clear the MSB of any W register, by executing a zero-extend (ZE) instruction on the appropriate address. Although most instructions are capable of operating on word or byte data sizes, it should be noted that some instructions, including the DSP instructions, operate only on words. 3.2.4 DATA SPACE MEMORY MAP The data space memory is split into two blocks, X and Y data space. A key element of this architecture is that Y space is a subset of X space, and is fully contained within X space. In order to provide an apparent linear addressing space, X and Y spaces have contiguous addresses. When executing any instruction other than one of the MAC class of instructions, the X block consists of the entire 64 Kbyte data address space (including all Y addresses). When executing one of the MAC class of instructions, the X block consists of the entire 64 Kbyte data address space excluding the Y address block (for data reads only). In other words, all other instructions regard the entire data memory as one composite address space. The MAC class instructions extract the Y address space from data space and addresses it using EAs sourced from W10 and W11. The remaining X data space is addressed using W8 and W9. Both address spaces are concurrently accessed only by the MAC class instructions. An example data space memory map is shown in Figure 3-8. Advance Information 2002 Microchip Technology Inc. dsPIC30F 3.2.5 NEAR DATA SPACE 3.2.6 An 8 Kbyte `near' data space is reserved in X address memory space between 0x0000 and 0x1FFF, which is directly addressable via a 13-bit absolute address field within all memory direct instructions. The remaining X address space and all of the Y address space is addressable indirectly. Additionally, the whole of X data space is addressable using MOV instructions, which support memory direct addressing with a 16-bit address field. The stack pointer always points to the first available free word and grows from lower addresses towards higher addresses. It pre-decrements for stack pops (reads) and post-increments for stack pushes (writes), as shown in Figure 3-7. Note that for a PC push during any CALL instruction, the MSB of the PC is zeroextended before the push, ensuring that the MSB is always clear. A PC push during exception processing will concatenate the SRL register to the MSB of the PC prior to the push. The dsPIC contains a software stack. W15 is used as the Stack Pointer. There is a Stack Limit register (SPLIM) associated with the stack pointer. SPLIM is uninitialized at RESET. As is the case for the stack pointer, SPLIM<0> is forced to 0, because all stack operations must be word aligned. Whenever an effective address (EA) is generated using W15 as a source or destination pointer, the address thus generated is compared with the value in SPLIM. If the EA is found to be greater than the contents of SPLIM, then a Stack Pointer Overflow (Stack Error) trap is generated. Similarly, a Stack Pointer Underflow (Stack Error) trap is generated when the stack pointer address is found to be less than 0x0800, thus preventing the stack from interfering with the Special Function Register (SFR) space. FIGURE 3-7: CALL STACK FRAME 0x0000 15 Stack Grows Towards Higher Address Note: SOFTWARE STACK 0 PC<15:0> W15 (before CALL) 000000000 PC<22:16> <Free Word> W15 (after CALL) POP : [--W15] PUSH : [W15++] 2002 Microchip Technology Inc. Advance Information DS70082A-page 31 dsPIC30F FIGURE 3-8: SAMPLE DATA SPACE MEMORY MAP MS Byte Address MSB 2 Kbyte SFR Space 0x0001 LS Byte Address 16-bits LSB SFR Space 0x0000 0x07FE 0x0800 0x07FF 0x0801 Near Data Space X Data RAM (X) 8 Kbyte SRAM Space 0x17FF 0x1801 0x17FE 0x1800 0x1FFF 0x1FFE Y Data RAM (Y) 8 Kbyte SRAM boundary 0x27FF 0x27FE 0x2801 0x2800 0x8001 0x8000 X Data Unimplemented (X) Optionally Mapped into Program Memory 0xFFFE 0xFFFF Note: The address map shown in Figure 3-8 is conceptual, and may vary across individual devices depending on available memory. DS70082A-page 32 Advance Information 2002 Microchip Technology Inc. dsPIC30F DATA SPACE FOR MCU AND DSP (MAC CLASS) INSTRUCTIONS EXAMPLE SFR SPACE SFR SPACE X SPACE FIGURE 3-9: Y SPACE UNUSED X SPACE (Y SPACE) X SPACE UNUSED UNUSED Non-MAC Class Ops (Read) Indirect EA from any W 2002 Microchip Technology Inc. MAC Class Ops (Read) Indirect EA from W8, W9 Advance Information Indirect EA from W10, W11 DS70082A-page 33 DS70082A-page 34 Advance Information -- -- 0042 SR -- CORCON 0044 -- Legend: u = uninitialized bit 0040 DOENDH -- -- -- -- OB 003E DOENDL -- -- -- -- Bit 14 OA 003C 0032 TBLPAG DOSTARTH 0030 PCH 003A 002E PCL DOSTARTL 002C ACCBU 0038 002A ACCBH DCOUNT 0028 ACCBL 0036 0026 ACCAU RCOUNT 0024 ACCAH 0034 0022 ACCAL PSVPAG 0020 SPLIM 0014 W10 001E 0012 W9 W15 0010 W8 001C 000E W7 W14 000C W6 001A 000A W5 W13 0008 W4 0018 0006 W3 W12 0004 W2 0016 0002 W1 W11 0000 Bit 15 Bit 12 Bit 11 -- SA -- -- -- -- -- -- SB -- -- -- -- -- EDT OAB -- -- -- -- -- Sign-Extension (ACCB<39>) DL2 SAB -- -- -- -- -- Bit 10 Sign-Extension (ACCA<39>) Bit 13 CORE REGISTER MAP Address (Home) W0 SFR Name TABLE 3-3: DL0 DC -- DOENDL -- IPL2 -- -- SATA DCOUNT RCOUNT -- -- -- PCL ACCBH ACCBL ACCAH ACCAL SPLIM W15 W14 W13 W12 W11 W10 W9 W8 W7 W6 W5 W4 W3 W2 W1 -- Bit 7 W0 / WREG Bit 8 DOSTARTL DL1 DA -- -- -- -- -- Bit 9 SATB IPL1 Bit 6 Bit 3 RA IPL3 N DOENDH DOSTARTH PSVPAG TBLPAG PCH ACCBU ACCAU Bit 4 SATDW ACCSAT IPL0 Bit 5 PSV OV Bit 2 RND Z Bit 1 IF C 0 0 Bit 0 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0uuu uuuu uuuu uuuu uuuu uuu0 0000 0000 0uuu uuuu uuuu uuuu uuuu uuu0 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 RESET State dsPIC30F 2002 Microchip Technology Inc. 004A 004C 004E 0050 XMODEND YMODSRT YMODEND XBREV BREN XMODEN Bit 15 0052 -- u = uninitialized bit 0048 XMODSRT DISICNT Legend: 0046 MODCON SFR Name -- YMODEN Bit 14 -- Bit 13 -- Bit 12 Bit 11 CORE REGISTER MAP (CONTINUED) Address (Home) TABLE 3-3: Bit 9 BWM<3:0> Bit 10 YE<15:1> YS<15:1> XE<15:1> XS<15:1> Bit 8 Bit 5 YWM<3:0> Bit 6 DISICNT<13:0> XB<14:0> Bit 7 Bit 4 Bit 3 Bit 1 XWM<3:0> Bit 2 1 0 1 0 Bit 0 0000 0000 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuu1 uuuu uuuu uuuu uuu0 uuuu uuuu uuuu uuu1 uuuu uuuu uuuu uuu0 0000 0000 0000 0000 RESET State dsPIC30F 2002 Microchip Technology Inc. Advance Information DS70082A-page 35 dsPIC30F NOTES: DS70082A-page 36 Advance Information 2002 Microchip Technology Inc. dsPIC30F 4.0 ADDRESS GENERATOR UNITS The dsPIC core contains two independent address generator units: the X AGU and Y AGU. Further, the X AGU has two parts: X RAGU (Read AGU) and X WAGU (Write AGU). The X RAGU and X WAGU support byte and word sized data space reads and writes, respectively, for both MCU and DSP instructions. The Y AGU supports word sized data reads for the DSP MAC class of instructions only. They are each capable of supporting two types of data addressing: * Linear Addressing * Modulo (Circular) Addressing In addition, the X WAGU can support: * Bit-Reversed Addressing Linear and Modulo Data Addressing modes can be applied to data space or program space. Bit-Reversed addressing is only applicable to data space addresses. 4.1 Data Space Organization Although the data space memory is organized as 16-bit words, all effective addresses (EAs) are byte addresses. Instructions can thus access individual bytes as well as properly aligned words. Word addresses must be aligned at even boundaries. Misaligned word accesses are not supported, and if attempted, will initiate an address error trap. When executing instructions which require just one source operand to be fetched from data space, the X RAGU and X WAGU are used to calculate the effective address. The X RAGU and X WAGU can generate any address in the 64 Kbyte data space. They support all MCU Addressing modes and Modulo Addressing for TABLE 4-1: low overhead circular buffers. The X WAGU also supports Bit-Reversed Addressing to facilitate FFT data reorganization. When executing instructions which require two source operands to be concurrently fetched (i.e., the MAC class of DSP instructions), both the X RAGU and Y AGU are used simultaneously and the data space is split into 2 independent address spaces, X and Y. The Y AGU supports Register Indirect Post-Modified and Modulo Addressing only. Note that the data write phase of the MAC class of instruction does not split X and Y address space. The write EA is calculated using the X WAGU and the data space is configured for full 64 Kbyte access. In the Split Data Space mode, some W register address pointers are dedicated to X RAGU, and others to Y AGU. The EAs of each operand must, therefore, be restricted to be within different address spaces. If they are not, one of the EAs will be outside the address space of the corresponding data space (and will fetch the bus default value, 0x0000). 4.2 Instruction Addressing Modes The Addressing modes in Table 4-1 form the basis of the Addressing modes optimized to support the specific features of individual instructions. The Addressing modes provided in the MAC class of instructions are somewhat different from those in the other instruction types. Some Addressing mode combinations may lead to a one-cycle stall during instruction execution, or are not allowed, as discussed in Section 4.3. FUNDAMENTAL ADDRESSING MODES SUPPORTED Addressing Mode Description File Register Direct The address of the file register is specified explicitly. Register Direct The contents of a register are accessed directly. Register Indirect The contents of Wn forms the EA. Register Indirect Post-modified The contents of Wn forms the EA. Wn is post-modified (incremented or decremented) by a constant value. Register Indirect Pre-modified Wn is pre-modified (incremented or decremented) by a signed constant value to form the EA. Register Indirect with Register Offset The sum of Wn and Wb forms the EA. Register Indirect with Literal Offset 2002 Microchip Technology Inc. The sum of Wn and a literal forms the EA. Advance Information DS70082A-page 37 dsPIC30F 4.2.1 FILE REGISTER INSTRUCTIONS Most file register instructions use a 13-bit address field (f) to directly address data present in the first 8192 bytes of data memory. These memory locations are known as File Registers. Most file register instructions employ a working register W0, which is denoted as WREG in these instructions. The destination is typically either the same file register, or WREG (with the exception of the MUL instruction), which writes the result to a register or register pair. The MOV instruction can use a 16-bit address field. 4.2.2 In summary, the following Addressing modes are supported by Move and Accumulator instructions: * * * * * * * * Register Direct Register Indirect Register Indirect Post-modified Register Indirect Pre-modified Register Indirect with Register Offset (Indexed) Register Indirect with Literal Offset 8-bit Literal 16-bit Literal Note: MCU INSTRUCTIONS The three-operand MCU instructions are of the form: Operand 3 = Operand 1 <function> Operand 2 Not all instructions support all the Addressing modes given above. Individual instructions may support different subsets of these Addressing modes. where Operand 1 is always a working register (i.e., the Addressing mode can only be register direct), which is referred to as Wb. Operand 2 can be W register, fetched from data memory, or 5-bit literal. In twooperand instructions, the result location is the same as that of one of the operands. Certain MCU instructions are one-operand operations. The following Addressing modes are supported by MCU instructions: 4.2.4 * * * * * The 2 source operand pre-fetch registers must be a member of the set {W8, W9, W10, W11}. For data reads, W8 and W9 will always be directed to the X RAGU and W10 and W11 will always be directed to the Y AGU. The effective addresses generated (before and after modification) must, therefore, be valid addresses within X data space for W8 and W9, and Y data space for W10 and W11. Register Direct Register Indirect Register Indirect Post-modified Register Indirect Pre-modified 5-bit or 10-bit Literal Note: 4.2.3 Not all instructions support all the Addressing modes given above. Individual instructions may support different subsets of these Addressing modes. MOVE AND ACCUMULATOR INSTRUCTIONS Move instructions and the DSP accumulator class of instructions provide a greater degree of addressing flexibility than other instructions. In addition to the Addressing modes supported by most MCU instructions, Move and Accumulator instructions also support Register Indirect with Register Offset Addressing mode, also referred to as Register Indexed mode. Note: For the MOV instructions, the Addressing mode specified in the instruction can differ for the source and destination EA. However, the 4-bit Wb (Register Offset) field is shared between both source and destination (but typically only used by one). DS70082A-page 38 MAC INSTRUCTIONS The dual source operand DSP instructions (CLR, ED, EDAC, MAC, MPY, MPY.N, MOVSAC and MSC), also referred to as MAC instructions, utilize a simplified set of Addressing modes to allow the user to effectively manipulate the data pointers through register indirect tables. Note: Register Indirect with Register Offset Addressing is only available for W9 (in X space) and W11 (in Y space). In summary, the following Addressing modes are supported by the MAC class of instructions: * * * * * Register Indirect Register Indirect Post-modified by 2 Register Indirect Post-modified by 4 Register Indirect Post-modified by 6 Register Indirect with Register Offset (Indexed) 4.2.5 OTHER INSTRUCTIONS Besides the various Addressing modes outlined above, some instructions use literal constants of various sizes. For example, BRA (branch) instructions use 16-bit signed literals to specify the branch destination directly, whereas the DISI instruction uses a 14-bit unsigned literal field. In some instructions, such as ADD Acc, the source of an operand or result is implied by the opcode itself. Certain operations, such as NOP, do not have any operands. Advance Information 2002 Microchip Technology Inc. dsPIC30F 4.3 4.3.1 4.3.2 Instruction Stalls During the instruction pre-decode, the core determines if any address register dependency is imminent across an instruction boundary. The stall detection logic compares the W register (if any) used for the destination EA of the instruction currently being executed, with the W register to be used by the source EA (if any) of the prefetched instruction. As the W registers are also memory mapped, the stall detection logic also derives an SFR address from the W register being used by the destination EA, and determines whether this address is being issued during the write phase of the instruction currently being executed. INTRODUCTION In order to maximize data space, EA calculation and operand fetch time, the X data space read and write accesses are partially pipelined. The latter half of the read phase overlaps the first half of the write phase of an instruction, as shown in Section 2. Address register data dependencies, also known as `Read After Write' (RAW) dependencies, may therefore arise between successive read and write operations using common registers. They occur across instruction boundaries and are detected by the hardware. When it observes a match between the destination and source registers, a set of rules are applied to decide whether or not to stall the instruction by one cycle. Table 4-2 lists out the various RAW conditions which cause an instruction execution stall. An example of a RAW dependency is a write operation (in the current instruction) that modifies W5, followed by a read operation (in the next instruction) that uses W5 as a source address pointer. W5 will not be valid for the read operation until the earlier write completes. This problem is resolved by stalling the instruction execution for one instruction cycle, thereby allowing the write to complete before the next read is started. TABLE 4-2: RAW DEPENDENCY DETECTION RAW DEPENDENCY RULES (DETECTION BY HARDWARE) Destination Source Addressing Addressing Mode Mode Using Wn Using Wn Examples (Wn = W2) Status Direct Direct Direct Indirect Stall ADD.w MOV.w W0, W1, W2 [W2], W3 Direct Indirect with Pre- or Post-Modification Stall ADD.w MOV.w W0, W1, W2 [W2++], W3 Indirect Direct No Stall ADD.w MOV.w W0, W1, [W2] W2, W3 Indirect Indirect No Stall ADD.w MOV.w W0, W1, [W2] [W2], W3 Indirect Indirect Indirect Indirect with Pre- or Post-Modification Indirect Indirect with Pre- or Post-Modification Indirect with Pre- or Direct Post-Modification No Stall ADD.w MOV.w Stall ADD.w MOV.w No Stall ADD.w MOV.w Stall ADD.w MOV.w No Stall ADD.w MOV.w W0, W1, W2 W2, W3 W0, W1, [W2] ; W2=0x0004 (mapped W2) [W2], W3 ; (i.e., if W2 = addr. of W2) W0, W1, [W2] [W2++], W3 W0, W1, [W2] ; W2=0x0004 (mapped W2) [W2++], W3 ; (i.e., if W2 = addr. of W2) W0, W1, [W2++] W2, W3 Indirect with Pre- or Indirect Post-Modification Stall ADD.w MOV.w W0, W1, [W2++] [W2], W3 Indirect with Pre- or Indirect with Pre- or Post-Modification Post-Modification Stall ADD.w MOV.w W0, W1, [W2++] [W2++], W3 2002 Microchip Technology Inc. Advance Information DS70082A-page 39 dsPIC30F 4.4 Modulo Addressing Modulo addressing is a method of providing an automated means to support circular data buffers using hardware. The objective is to remove the need for software to perform data address boundary checks when executing tightly looped code, as is typical in many DSP algorithms. Modulo Addressing can operate in either data or program space (since the data pointer mechanism is essentially the same for both). One circular buffer can be supported in each of the X (which also provides the pointers into Program space) and Y data spaces. Modulo Addressing can operate on any W register pointer. However, it is not advisable to use W14 or W15 for Modulo Addressing, since these two registers are used as the Stack Frame Pointer and Stack Pointer, respectively. In general, any particular circular buffer can only be configured to operate in one direction, as there are certain restrictions on the buffer start address (for incrementing buffers) or end address (for decrementing buffers), based upon the direction of the buffer. The only exception to the usage restrictions is for buffers which have a power-of-2 length. As these buffers satisfy the start and end address criteria, they may operate in a Bi-Directional mode, i.e., address boundary checks will be performed on both the lower and upper address boundaries. 4.4.1 START AND END ADDRESS The Modulo Addressing scheme requires that a starting and an end address be specified and loaded into the 16-bit modulo buffer address registers: XMODSRT, XMODEND, YMODSRT, YMODEND (see Table 3-3). Note: The start and end addresses are the first and last byte addresses of the buffer (irrespective of whether it is a word or byte buffer, or an increasing or decreasing buffer). Moreover, the start address must be even and the end address must be odd (for both word and byte buffers). If the length of an incrementing buffer is greater than M = 2N-1, but not greater than M = 2N bytes, then the last 'N' bits of the data buffer start address must be zeros. There are no such restrictions on the end address of an incrementing buffer. For example, if the buffer size (modulus value) is chosen to be 100 bytes (0x64), then the buffer start address for an incrementing buffer must contain 7 Least Significant zeros. Valid start addresses may, therefore, be 0xXX00 and 0xXX80, where `X' is any hexadecimal value. Adding the buffer length to this value and subtracting 1 will give the end address to be written into X/YMODEND. DS70082A-page 40 For example, if the start address was chosen to be 0x2000, then the X/YMODEND would be set to (0x2000 + 0x0064 - 1) = 0x2063. Note: `Start address' refers to the smallest address boundary of the circular buffer. The first access of the buffer may be at any address within the modulus range (see Section 4.4.4). In the case of a decrementing buffer, the last `N' bits of the data buffer end address must be ones. There are no such restrictions on the start address of a decrementing buffer. For example, if the buffer size (modulus value) is chosen to be 100 bytes (0x64), then the buffer end address for a decrementing buffer must contain 7 Least Significant ones. Valid end addresses may, therefore, be 0xXXFF and 0xXX7F, where `X' is any hexadecimal value. Subtracting the buffer length from this value and adding 1 will give the start address to be written into X/YMODSRT. For example, if the end address was chosen to be 0x207F, then the start address would be (0x207F - 0x0064+1) = 0x201C, which is the first physical address of the buffer. Note: Y-space Modulo Addressing EA calculations assume word sized data (LS bit of every EA is always clear). The length of a circular buffer is not directly specified. It is determined by the difference between the corresponding start and end addresses. The maximum possible length of the circular buffer is 32K words (64 Kbytes). 4.4.2 W ADDRESS REGISTER SELECTION The Modulo and Bit-Reversed Addressing control register MODCON<15:0> contains enable flags plus W register field to specify the W address registers. The XWM and YWM fields select which registers will operate with Modulo Addressing. If XWM = 15, X RAGU and X WAGU Modulo Addressing are disabled. Similarly, if YWM = 15, Y AGU Modulo Addressing is disabled. Note: The XMODSRT and XMODEND registers, and the XWM register selection, are shared between X RAGU and X WAGU. The X address space pointer W register (XWM) to which Modulo Addressing is to be applied, is stored in MODCON<3:0> (see Table 3-3). Modulo Addressing is enabled for X data space when XWM is set to any value other than 15 and the XMODEN bit is set at MODCON<15>. The Y address space pointer W register (YWM) to which Modulo Addressing is to be applied, is stored in MODCON<7:4>. Modulo addressing is enabled for Y data space when YWM is set to any value other than 15 and the YMODEN bit is set at MODCON<14>. Advance Information 2002 Microchip Technology Inc. dsPIC30F FIGURE 4-1: INCREMENTING BUFFER MODULO ADDRESSING OPERATION EXAMPLE Byte Address 0x1100 MOV MOV MOV MOV MOV MOV #0x1100,W0 W0,XMODSRT #0x1163,W0 W0,MODEND #0x8001,W0 W0,MODCON MOV #0x0000,W0 ;W0 holds buffer fill value MOV #0x1110,W1 ;point W1 to buffer DO AGAIN,#0x31 MOV W0,[W1++] AGAIN: INC W0,W0 ;set modulo start address ;set modulo end address ;enable W1, X AGU for modulo ;fill the 50 buffer locations ;fill the next location ;increment the fill value 0x1163 Start Addr = 0x1100 End Addr = 0x1163 Length = 0x0032 words 2002 Microchip Technology Inc. Advance Information DS70082A-page 41 dsPIC30F FIGURE 4-2: DECREMENTING BUFFER MODULO ADDRESSING OPERATION EXAMPLE Byte Address MOV MOV MOV MOV MOV MOV #0x11D0,W0 #0,XMODSRT 0x11FF,W0 W0,XMODEND #0x8001,W0 W0,MODCON MOV #0x000F,W0 ;W0 holds buffer fill value MOV #0x11E0,W1 ;point W1 to buffer ;set modulo start address ;set modulo end address ;enable W1, X AGU for modulo 0x11D0 DO AGAIN,#0x17 MOV W0,[W1--] AGAIN: DEC W0,W0 ;fill the 24 buffer locations ;fill the next location ; decrement the fill value 0x11FF Start Addr = 0x11D0 End Addr = 0x11FF Length = 0x0018 words 4.4.3 . MODULO ADDRESSING APPLICABILITY Note: Modulo Addressing can be applied to the effective address (EA) calculation associated with any W register. It is important to realize that the address boundaries check for addresses less than or greater than the upper (for incrementing buffers), and lower (for decrementing buffers) boundary addresses (not just equal to). Address changes may, therefore, jump over boundaries and still be adjusted correctly (see Section 4.4.4 for restrictions) DS70082A-page 42 Advance Information The modulo corrected effective address is written back to the register only when PreModify or Post-Modify Addressing mode is used to compute the Effective Address. When an address offset (e.g., [W7+W2] ) is used, modulo address correction is performed, but the contents of the register remains unchanged. 2002 Microchip Technology Inc. dsPIC30F 4.4.4 MODULO ADDRESSING RESTRICTIONS 4.5.1 BIT-REVERSED ADDRESSING IMPLEMENTATION As stated in Section 4.4.1, for an incrementing buffer, the circular buffer start address (lower boundary) is arbitrary, but must be at a `zero' power-of-two boundary. For a decrementing buffer, the circular buffer end address is arbitrary, but must be at a `ones' boundary. Bit-Reversed Addressing is enabled when: There are no restrictions regarding how much an EA calculation can exceed the address boundary being checked, and still be successfully corrected. 2. 3. Once configured, the direction of successive addresses into a buffer should not be changed. Although all EAs will continue to be generated correctly irrespective of offset sign, only one address boundary is checked for each type of buffer. Thus, if a buffer is set up to be an incrementing buffer by choosing an appropriate starting address, then correction of the effective address will be performed by the AGU at the upper address boundary, but no address correction will occur if the EA crosses the lower address boundary. Similarly, for a decrementing boundary, address correction will be performed by the AGU at the lower address boundary, but no address correction will take place if the EA crosses the upper address boundary. The circular buffer pointer may be freely modified in both directions without a possibility of out-of-range address access only when the start address satisfies the condition for an incrementing buffer (last `N' bits are zeroes) and the end address satisfies the condition for a decrementing buffer (last `N' bits are ones). Thus, the Modulo Addressing capability is truly bi-directional only for modulo-2 length buffers. XB<14:0> is the Bit-Reversed Address modifier or `pivot point' which is typically a constant. In the case of an FFT computation, its value is equal to half of the FFT data buffer size. 1. BWM (W register selection) in the MODCON register is any value other than 15 (the stack can not be accessed using Bit-Reversed Addressing) and the BREN bit is set in the XBREV register and the Addressing mode used is Register Indirect with Pre-Increment or Post-Increment. Note: When enabled, Bit-Reversed Addressing will only be executed with register indirect with Pre-Increment or Post-Increment Addressing and word sized data writes. It will not function for any other Addressing mode or for byte-sized data, and normal addresses will be generated instead. When Bit-Reversed Addressing is active, the W address pointer will always be added to the address modifier (XB) and the offset associated with the register Indirect Addressing mode will be ignored. In addition, as word sized data is a requirement, the LS bit of the EA is ignored (and always clear). Note: 4.5 Bit-Reversed Addressing Bit-Reversed Addressing is intended to simplify data re-ordering for radix-2 FFT algorithms. It is supported by the X WAGU only, i.e., for data writes only. The modifier, which may be a constant value or register contents, is regarded as having its bit order reversed. The address source and destination are kept in normal order. Thus, the only operand requiring reversal is the modifier. FIGURE 4-3: All Bit-Reversed EA calculations assume word sized data (LS bit of every EA is always clear). The XB value is scaled accordingly to generate compatible (byte) addresses. Modulo Addressing and Bit-Reversed Addressing should not be enabled together. In the event that the user attempts to do this, bit reversed addressing will assume priority when active for the X WAGU, and X WAGU Modulo Addressing will be disabled. However, Modulo Addressing will continue to function in the X RAGU. BIT-REVERSED ADDRESS EXAMPLE Sequential Address b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 0 Bit Locations Swapped Left-to-Right Around Center of Binary Value b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b1 b2 b3 b4 0 Bit-Reversed Address Pivot Point XB = 0x0008 for a 16-word Bit-Reversed Buffer 2002 Microchip Technology Inc. Advance Information DS70082A-page 43 dsPIC30F TABLE 4-3: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY) Normal Address Bit-Reversed Address A3 A2 A1 A0 Decimal A3 A2 A1 A0 Decimal 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 8 0 0 1 0 2 0 1 0 0 4 0 0 1 1 3 1 1 0 0 12 0 1 0 0 4 0 0 1 0 2 0 1 0 1 5 1 0 1 0 10 0 1 1 0 6 0 1 1 0 6 0 1 1 1 7 1 1 1 0 14 1 0 0 0 8 0 0 0 1 1 1 0 0 1 9 1 0 0 1 9 1 0 1 0 10 0 1 0 1 5 1 0 1 1 11 1 1 0 1 13 1 1 0 0 12 0 0 1 1 3 1 1 0 1 13 1 0 1 1 11 1 1 1 0 14 0 1 1 1 7 1 1 1 1 15 1 1 1 1 15 TABLE 4-4: DS70082A-page 44 BIT-REVERSED ADDRESS MODIFIER VALUES Buffer Size (Words) XB<14:0> Bit-Reversed Address Modifier Value 32768 0x4000 16384 0x2000 8192 0x1000 4096 0x0800 2048 0x0400 1024 0x0200 512 0x0100 256 0x0080 128 0x0040 64 0x0020 32 0x0010 16 0x0008 8 0x0004 4 0x0002 2 0x0001 Advance Information 2002 Microchip Technology Inc. dsPIC30F 5.0 EXCEPTION PROCESSING The dsPIC30F Motor Control and Power Conversion Family has up to 44 interrupt sources and 4 processor exceptions (traps), which must be arbitrated based on a priority scheme. The processor core is responsible for reading the Interrupt Vector Table (IVT) and transferring the address contained in the interrupt vector to the program counter. The interrupt vector is transferred from the program data bus into the program counter, via a 24-bit wide multiplexer on the input of the program counter. The Interrupt Vector Table (IVT) and Alternate Interrupt Vector Table (AIVT) are placed near the beginning of program memory (0x000004). The IVT and AIVT are shown in Table 5-2. The interrupt controller is responsible for preprocessing the interrupts and processor exceptions, prior to their being presented to the processor core. The peripheral interrupts and traps are enabled, prioritized, and controlled using centralized special function registers: * IFS0<15:0>, IFS1<15:0>, IFS2<15:0> All interrupt request flags are maintained in these three registers. The flags are set by their respective peripherals or external signals, and they are cleared via software. * IEC0<15:0>, IEC1<15:0>, IEC2<15:0> All interrupt enable control bits are maintained in these three registers. These control bits are used to individually enable interrupts from the peripherals or external signals. * IPC0<15:0> ... IPC11<7:0> The user assignable priority level associated with each of these 44 interrupts is held centrally in these twelve registers. * IPL<3:0> The current CPU priority level is explicitly stored in the IPL bits. IPL<3> is present in the CORCON register, whereas IPL<2:0> are present in the status register (SR) in the processor core. * INTCON1<15:0>, INTCON2<15:0> Global interrupt control functions are derived from these two registers. INTCON1 contains the control and status flags for the processor exceptions. The INTCON2 register controls the external interrupt request signal behavior and the use of the alternate vector table. Note: Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. 2002 Microchip Technology Inc. All interrupt sources can be user assigned to one of 7 priority levels, 1 through 7, via the IPCx registers. Each interrupt source is associated with an interrupt vector, as shown in Table 5-2. Levels 7 and 1 represent the highest and lowest maskable priorities, respectively. Note: Assigning a priority level of 0 to an interrupt source is equivalent to disabling that interrupt. If the NSTDIS bit (INTCON1<15>) is set, nesting of interrupts is prevented. Thus, if an interrupt is currently being serviced, processing of a new interrupt is prevented, even if the new interrupt is of higher priority than the one currently being serviced. Certain interrupts have specialized control bits for features like edge or level triggered interrupts, interrupton-change, etc. Control of these features remains within the peripheral module which generates the interrupt. The DISI instruction can be used to disable the processing of interrupts of priorities 6 and lower for a certain number of instructions, during which the DISI bit (INTCON2<14>) remains set. When an interrupt is serviced, the PC is loaded with the address stored in the vector location in Program memory that corresponds to the interrupt. There are 63 different vectors within the IVT (refer to Table 5-2). These vectors are contained in locations 0x000004 through 0x0000FE of program memory (refer to Table 5-2). These locations contain 24-bit addresses, and in order to preserve robustness, an address error trap will take place should the PC attempt to fetch any of these words during normal execution. This prevents execution of random data through accidentally decrementing a PC into vector space, accidentally mapping a data space address into vector space, or the PC rolling over to 0x000000 after reaching the end of implemented program memory space. Execution of a GOTO instruction to this vector space will also generate an address error trap. 5.1 Interrupt Priority The user assignable Interrupt Priority (IP<2:0>) bits for each individual interrupt source are located in the LS 3-bits of each nibble, within the IPCx register(s). Bit 3 of each nibble is not used and is read as a `0'. These bits define the priority level assigned to a particular interrupt by the user. Note: The user selectable priority levels start at 0 as the lowest priority and level 7, as the highest priority. Since more than one interrupt request source may be assigned to a specific user specified priority level, a means is provided to assign priority within a given level. This method is called "Natural Order Priority". Advance Information DS70082A-page 45 dsPIC30F Table 5-1 lists the interrupt numbers and interrupt sources for the dsPIC devices, and their associated vector numbers. Note 1: The natural order priority scheme has 0 as the highest priority and 53 as the lowest priority. 2: The natural order priority number is the same as the INT number. The ability for the user to assign every interrupt to one of seven priority levels implies that the user can assign a very high overall priority level to an interrupt with a low natural order priority. For example, the PLVD (Low Voltage Detect) can be given a priority of 7. The INT0 (external interrupt 0) may be assigned to priority level 1, thus giving it a very low effective priority. TABLE 5-1: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 - 53 DS70082A-page 46 NATURAL ORDER PRIORITY INT Vector Number Number Advance Information Interrupt Source Highest Natural Order Priority 8 INT0 - External Interrupt 0 9 IC1 - Input Capture 1 10 OC1 - Output Compare 1 11 T1 - Timer 1 12 IC2 - Input Capture 2 13 OC2 - Output Compare 2 14 T2 - Timer 2 15 T3 - Timer 3 16 SPI1 17 U1RX - UART1 Receiver 18 U1TX - UART1 Transmitter 19 ADC - ADC Convert Done 20 NVM - NVM Write Complete 21 I2C - I2C Transfer Complete 22 BCL - I2C Bus Collision 23 Input Change Interrupt 24 INT1 - External Interrupt 1 25 IC7 - Input Capture 7 26 IC8 - Input Capture 8 27 OC3 - Output Compare 3 28 OC4 - Output Compare 4 29 T4 - Timer 4 30 T5 - Timer 5 31 INT2 - External Interrupt 2 32 U2RX - UART2 Receiver 33 U2TX - UART2 Transmitter 34 SPI2 35 C1 - Combined IRQ for CAN1 36 IC3 - Input Capture 3 37 IC4 - Input Capture 4 38 IC5 - Input Capture 5 39 IC6 - Input Capture 6 40 OC5 - Output Compare 5 41 OC6 - Output Compare 6 42 OC7 - Output Compare 7 43 OC8 - Output Compare 8 44 INT3 - External Interrupt 3 45 INT4 - External Interrupt 4 46 C2 - Combined IRQ for CAN2 47 PWM - PWM Period Match 48 QEI - QEI Interrupt 49 Reserved 50 LVD - Low Voltage Detect 51 FLTA - PWM Fault A 52 FLTB - PWM Fault B 53 - 61 Reserved Lowest Natural Order Priority 2002 Microchip Technology Inc. dsPIC30F 5.2 RESET Sequence A RESET is not a true exception, because the interrupt controller is not involved in the RESET process. The processor initializes its registers in response to a RESET, which forces the PC to zero. The processor then begins program execution at location 0x000000. A GOTO instruction is stored in the first program memory location, immediately followed by the address target for the GOTO instruction. The processor executes the GOTO to the specified address and then begins operation at the specified target (start) address. 5.2.1 RESET SOURCES In addition to external, Power-on Resets (POR) and software Reset, there are four sources of error conditions which `trap' to the RESET vector. * Watchdog Time-out: The watchdog has timed out, indicating that the processor is no longer executing the correct flow of code. * Uninitialized W Register Trap: An attempt to use an uninitialized W register as an address pointer will cause a RESET. * Illegal Instruction Trap: Attempted execution of any unused opcodes will result in an illegal instruction trap. Note that a fetch of an illegal instruction does not result in an illegal instruction trap if that instruction is flushed prior to execution due to a flow change. * Brown-out Reset (BOR): A momentary dip in the power supply to the device has been detected, which may result in malfunction. 5.3 Traps Traps can be considered as non-maskable, non-stable interrupts, which adhere to a predefined priority as shown in Table 5-2. They are intended to provide the user a means to correct erroneous operation during debug and when operating within the application. Note: If the user does not intend to take corrective action in the event of a trap error condition, these vectors must be loaded with the RESET vector address. If, on the other hand, one of the vectors containing an invalid address is called, an address error trap is generated. Note that many of these trap conditions can only be detected when they occur. Consequently, the questionable instruction is allowed to complete prior to trap exception processing. If the user chooses to recover from the error, the result of the erroneous action that caused the trap may have to be corrected. 2002 Microchip Technology Inc. There are 8 fixed priority levels for traps: Level 8 through Level 15, which implies that the IPL3 is always set during processing of a trap. If the user is not currently executing a trap, and he sets the IPL<3:0> bits to a value of `0111' (Level 7), then all interrupts are disabled, but traps can still be processed. Note: 5.3.1 The IPL3 bit is read only, which implies that the user can not manually set the IPL<3:0> bits to a value greater than 7. TRAP SOURCES The following traps are provided with increasing priority. However, since all traps can be nested, priority has little effect. * Math Error Trap: The Math Error trap executes under the following three circumstances. 1. Should an attempt be made to divide by zero, the divide operation will be aborted on a cycle boundary and the trap taken. 2. If enabled, a Math Error trap will be taken when an arithmetic operation on either accumulator A or B, causes an overflow from bit 31 and the accumulator guard bits are not utilized. 3. If enabled, a Math Error trap will be taken when an arithmetic operation on either accumulator A or B causes a catastrophic overflow from bit 39 and all saturation is disabled. * Address Error Trap: This trap is initiated when any of the following circumstances occurs: 1. A misaligned data word fetch is attempted. 2. A data fetch from unused data address space is attempted. 3. A program fetch from unimplemented user program address space is attempted. 4. A program fetch from vector address space is attempted. * Stack Error Trap This trap is initiated under the following conditions: 1. The stack pointer is loaded with a value which is greater than the (user programmable) limit value written into the SPLIM register (stack overflow). 2. The stack pointer is loaded with a value which is less than 0x0800 (simple stack underflow). * Oscillator Fail Trap: This trap is initiated if the external oscillator fails and operation becomes reliant on an internal RC backup. Advance Information DS70082A-page 47 dsPIC30F HARD AND SOFT TRAPS 5.4 It is possible that multiple traps can become active within the same cycle (e.g., a misaligned word stack write to an overflowed address). In such a case, the fixed priority shown in Figure 5-2 is implemented, which may require the user to check if other traps are pending, in order to completely correct the fault. `Soft' traps include exceptions of priority level 8 through level 11, inclusive. The arithmetic error trap (level 11) falls into this category of traps. Soft traps can be treated like non-maskable sources of interrupt that adhere to the priority assigned by their position in the IVT. Soft traps are processed like interrupts and require 2 cycles to be sampled and Acknowledged prior to exception processing. Therefore, additional instructions may be executed before a soft trap is Acknowledged. `Hard' traps include exceptions of priority level 12 through level 15, inclusive. The address error (level 12), stack error (level 13), and oscillator error (level 14) traps fall into this category. Like soft traps, hard traps can also be viewed as nonmaskable sources of interrupt. The difference between hard traps and soft traps is that hard traps force the CPU to stop code execution after the instruction causing the trap has completed. Normal program execution flow will not resume until after the trap has been acknowledged and processed. If a higher priority trap occurs while any lower priority trap is in progress, processing of the lower priority trap will be suspended and the higher priority trap will be acknowledged and processed. The lower priority trap will remain pending until processing of the higher priority trap completes. Each hard trap that occurs must be acknowledged before code execution of any type may continue. If a lower priority hard trap occurs while a higher priority trap is pending, acknowledged, or is being processed, a hard trap conflict will occur. The conflict occurs because the lower priority trap cannot be Acknowledged until processing for the higher priority trap completes. The device is automatically RESET in a hard trap conflict condition. The TRAPR status bit (RCON<15> ) is set when the RESET occurs, so that the condition may be detected in software. Interrupt Sequence All interrupt event flags are sampled in the beginning of each instruction cycle by the IFSx registers. A pending interrupt request (IRQ) is indicated by the flag bit being equal to a `1' in an IFSx register. The IRQ will cause an interrupt to occur if the corresponding bit in the interrupt enable (IECx) register is set. For the remainder of the instruction cycle, the priorities of all pending interrupt requests are evaluated. If there is a pending IRQ with a priority level greater than the current processor priority level in the IPL bits, the processor will be interrupted. The processor then stacks the current program counter and the low byte of the processor status register (SRL), as shown in Figure 5-1. The low byte of the status register contains the processor priority level at the time, prior to the beginning of the interrupt cycle. The processor then loads the priority level for this interrupt into the status register. This action will disable all lower priority interrupts until the completion of the Interrupt Service Routine. FIGURE 5-1: INTERRUPT STACK FRAME 0x0000 15 Stack Grows Towards Higher Address 5.3.2 0 PC<15:0> SRL IPL3 PC<22:16> W15 (before CALL) <Free Word> W15 (after CALL) POP : [--W15] PUSH : [W15++] Note 1: The user can always lower the priority level by writing a new value into SR. The Interrupt Service Routine must clear the interrupt flag bits in the IFSx register before lowering the processor interrupt priority, in order to avoid recursive interrupts. 2: The IPL3 bit (CORCON<3>) is always clear when interrupts are being processed. It is set only during execution of traps. The RETFIE (Return from Interrupt) instruction will unstack the program counter and status registers to return the processor to its state prior to the interrupt sequence. DS70082A-page 48 Advance Information 2002 Microchip Technology Inc. dsPIC30F Decreasing Priority TABLE 5-2: IVT AIVT EXCEPTION VECTORS RESET - GOTO Instruction RESET - GOTO Address Reserved Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector Reserved Vector Reserved Vector Reserved Vector Interrupt 0 Vector Interrupt 1 Vector -- -- -- Interrupt 52 Vector Interrupt 53 Vector Reserved Reserved Reserved Oscillator Fail Trap Vector Stack Error Trap Vector Address Error Trap Vector Math Error Trap Vector Reserved Vector Reserved Vector Reserved Vector Interrupt 0 Vector Interrupt 1 Vector -- -- -- Interrupt 52 Vector Interrupt 53 Vector 5.6 0x000000 0x000002 0x000004 A context saving option is available using shadow registers. Shadow registers are provided for the DC, N, OV, Z and C bits in SR, the TBLPAG and PSVPAG registers, and the registers W0 through W14. The shadows are only one level deep. The shadow registers are accessible using the PUSH.S and POP.S instructions only. 0x000014 When the processor vectors to an interrupt, the PUSH.S instruction can be used to store the current value of the aforementioned registers into their respective shadow registers. 0x00007E 0x000080 0x000082 0x000084 If an ISR of a certain priority uses the PUSH.S and POP.S instructions for fast context saving, then a higher priority ISR should not include the same instructions. Users must save the key registers in software during a lower priority interrupt, if the higher priority ISR uses fast context saving. 5.7 0x000094 0x0000FE Alternate Vector Table In Program Memory, the Interrupt Vector Table (IVT) is followed by the Alternate Interrupt Vector Table (AIVT), as shown in Table 5-2. Access to the Alternate Vector Table is provided by the ALTIVT bit in the INTCON2 register. If the ALTIVT bit is set, all interrupt and exception processes will use the alternate vectors instead of the default vectors. The alternate vectors are organized in the same manner as the default vectors. The AIVT supports emulation and debugging efforts by providing a means to switch between an application and a support environment, without requiring the interrupt vectors to be reprogrammed. This feature also enables switching between applications for evaluation of different software algorithms at run time. External Interrupt Requests The interrupt controller supports up to five external interrupt request signals, INT0 - INT4. These inputs are edge sensitive, i.e., they require a low-to-high or a highto-low transition to generate an interrupt request. The INTCON2 register has five bits, INT0EP - INT4EP, that select the polarity of the edge detection circuitry. 5.8 5.5 Fast Context Saving Wake-up from SLEEP and IDLE The interrupt controller may be used to wake up the processor from either SLEEP or IDLE modes, if SLEEP or IDLE mode is active when the interrupt is generated. If an enabled interrupt request of sufficient priority is received by the interrupt controller, then the standard interrupt request is presented to the processor. At the same time, the processor will wake-up from SLEEP or IDLE and begin execution of the Interrupt Service Routine (ISR), needed to process the interrupt request. If the AIVT is not required, the program memory allocated to the AIVT may be used for other purposes. AIVT is not a protected section and may be freely programmed by the user. 2002 Microchip Technology Inc. Advance Information DS70082A-page 49 0086 0088 008C 008E 0090 0094 0096 0098 009A 009C 009E 00A0 00A2 00A4 00A6 00A8 00AA -- -- u = uninitialized bit IFS1 DS70082A-page 50 IFS2 IEC0 IEC1 IEC2 IPC0 IPC1 IPC2 IPC3 IPC4 IPC5 IPC6 IPC7 IPC8 IPC9 IPC10 IPC11 Legend: -- -- -- -- -- -- -- -- -- -- -- -- IC6IE CNIE -- IC6IF CNIF 0084 IFS0 -- IC5IE C1IE ADIE FLTAIF C1IF ADIF -- -- Bit 11 FLTAIP<2:0> -- -- -- -- -- -- -- -- -- -- -- -- -- FLTBIE FLTAIE IC3IE NVMIE PWMIP<2:0> -- IC3IF FLTBIF OC8IP<2:0> IC6IP<2:0> C1IP<2:0> -- -- Bit 12 NVMIF OC3IP<2:0> CNIP<2:0> ADIP<2:0> T31P<2:0> T1IP<2:0> -- IC4IE I2CIE -- IC4IF I2CIF -- -- Bit 13 INT2IP<2:0> BCLIE -- IC5IF BCLIF -- -- 0082 ALTIVT Bit 14 0080 NSTDIS Bit 15 INTCON2 ADR -- U2TXIF U1RXIF -- OVBTE Bit 9 -- LVDIE SPI2IE SPI1IF SPI1IE -- LVDIP<2:0> C2IP<2:0> OC7IP<2:0> IC5IP<2:0> SPI2IP<2:0> T5IP<2:0> QEIIF -- QEIIE U2RXIE BCLIP<2:0> IC8IP<2:0> -- U2RXIF U1TXIP<2:0> T2IP<2:0> Bit 8 COVTE OC1IP<2:0> -- U2TXIE U1TXIE U1RXIE LVDIF SPI2IF U1TXIF -- OVATE Bit 10 INTERRUPT CONTROLLER REGISTER MAP INTCON1 SFR Name TABLE 5-3: -- -- -- -- -- -- -- -- -- -- -- -- PWMIE INT2IE T3IE PWMIF INT2IF T3IF -- -- Bit 7 -- -- C2IE T5IE T2IE C2IF T5IF T2IF -- -- Bit 6 Bit 4 -- -- INT41IP<2:0> OC6IP<2:0> IC4IP<2:0> U2TXIP<2:0> T4IP<2:0> IC7IP<2:0> I2CIP<2:0> U1RXIP<2:0> OC2IP<2:0> -- -- INT3IE OC4IE IC2IE INT3IF OC4IF IC2IF INT4EP MATHERR IC1IP<2:0> INT4IE T4IE OC2IE INT4IF T4IF OC2IF -- -- Bit 5 -- -- -- -- -- -- -- -- -- -- -- -- OC8IE OC3IE T1IE OC8IF OC3IF T1IF INT3EP ADDRERR Bit 3 Bit 1 OC7IE IC8IE OC1IE OC7IF IC8IF OC1IF INT2EP FLTBIP<2:0> QEIIP<2:0> INT3IP<2:0> OC5IP<2:0> IC3IP<2:0> U2RXIP<2:0> OC4IP<2:0> INT1IP<2:0> NVMIP<2:0> SPI1IP<2:0> IC2IP<2:0> INT0IP<2:0> OC6IE IC7IE IC1IE OC6IF IC7IF IC1IF INT1EP STKERR OSCFAIL Bit 2 0000 0000 0000 0000 RESET State OC5IE INT1IE INT0IE OC5IF INT1IF INT0 0000 0000 0000 0100 0100 0100 0000 0100 0100 0100 0100 0100 0100 0100 0100 0100 0100 0100 0100 0100 0100 0100 0100 0100 0100 0100 0100 0100 0100 0100 0100 0100 0100 0100 0100 0100 0100 0100 0100 0100 0100 0100 0100 0100 0100 0100 0100 0100 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 INT0EP 0000 0000 0000 0000 -- Bit 0 dsPIC30F Advance Information 2002 Microchip Technology Inc. dsPIC30F 6.0 FLASH PROGRAM MEMORY With RTSP, the user may erase program memory, 32 instructions (96 bytes) at a time and can write program memory data, 4 instructions (12 bytes) at a time. The dsPIC30F family of devices contains internal program FLASH memory for executing user code. There are two methods by which the user can program this memory: 1. 2. 6.1 6.3 The TBLRDL and the TBLWTL instructions are used to read or write to bits <15:0> of program memory. TBLRDL and TBLWTL can access program memory in Word or Byte mode. Run Time Self-Programming (RTSP) In-Circuit Serial ProgrammingTM (ICSPTM) In-Circuit Serial Programming (ICSP) The TBLRDH and TBLWTH instructions are used to read or write to bits<23:16> of program memory. TBLRDH and TBLWTH can access program memory in Word or Byte mode. The details of ICSP will be provided at a later date. 6.2 Table Instruction Operation Summary Run Time Self-Programming (RTSP) A 24-bit program memory address is formed using bits<7:0> of the TBLPAG register and the effective address (EA) from a W register specified in the table instruction, as shown in Figure 6-1. RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions, and the following control registers: * NVMCON: Non-Volatile Memory Control Register * NVMKEY: Non-Volatile Memory Key Register * NVMADR: Non-Volatile Memory Address Register FIGURE 6-1: ADDRESSING FOR TABLE AND NVM REGISTERS 24-bits Using Program Counter Program Counter 0 0 NVMADR Reg EA Using NVMADR Addressing 1/0 TBLPAG Reg 8-bits 16-bits Working Reg EA Using Table Instruction User/Configuration Space Select 2002 Microchip Technology Inc. 1/0 TBLPAG Reg 8-bits 16-bits 24-bit EA Advance Information Byte Select DS70032D-page 51 dsPIC30F 6.4 RTSP Operation 6.5 Control Registers The dsPIC30F FLASH program memory is organized into rows and panels. Each row consists of 32 instructions, or 96 bytes. Each panel consists of 128 rows, or 4K x 24 instructions. Run Time Self Programming (RTSP) allows the user to erase one row (32 instructions) at a time and to program four instructions at one time. RTSP may be used to program multiple program memory panels, but the table pointer must be changed at each panel boundary. The three SFRs used to read and write the program FLASH memory are: Each panel of program memory contains write latches that hold four instructions of programming data. Prior to the actual programming operation, the write data must be loaded into the panel write latches. The data to be programmed into the panel is loaded in sequential order into the write latches: instruction 0, instruction 1, etc. The instruction words loaded must always be from a group of four boundary (e.g., loading of instructions 3, 4, 5, 6 is not allowed). The NVMCON register controls which blocks are to be erased, which memory type is to be programmed, and start of the programming cycle. The basic sequence for RTSP programming is to set up a table pointer, then do a series of TBLWT instructions to load the write latches. Programming is performed by setting the special bits in the NVMCON register. Four TBLWTL and four TBLWTH instructions are required to load the four instructions. To fully program a row of program memory, eight cycles of four TBLWTL and four TBLWTH are required. If multiple panel programming is required, the table pointer needs to be changed and the next set of multiple write latches written. All of the table write operations are single word writes (2 instruction cycles), because only the table latches are written. A total of 8 programming passes, each writing 4 instruction words, are required per row. A 128 row panel requires 1024 programming cycles. The FLASH Program Memory is readable, writable, and erasable during normal operation, over the entire VDD range. DS70032D-page 52 * * * * NVMCON NVMADR NVMADRU NVMKEY 6.5.1 NVMCON REGISTER 6.5.2 NVMADR REGISTER The NVMADR register is used to hold the lower two bytes of the effective address. The NVMADR register captures the EA<15:0> of the last table instruction that has been executed and selects the row to write. 6.5.3 NVMADRU REGISTER The NVMADRU register is used to hold the upper byte of the effective address. The NVMADRU register captures the EA<23:16> of the last table instruction that has been executed. 6.5.4 NVMKEY REGISTER NVMKEY is a write only register that is used for write protection. To start a programming or an erase sequence, the user must consecutively write 0x55 and 0xAA, to the NVMKEY register. Refer to Section 6.6 for further details. 6.6 Programming Operations A complete programming sequence is necessary for programming or erasing the internal FLASH in RTSP mode. A programming operation is nominally 2 msec in duration and the processor stalls (waits) until the operation is finished. Setting the WR bit (NVMCON<15>) starts the operation, and the WR bit is automatically cleared when the operation is finished. Advance Information 2002 Microchip Technology Inc. dsPIC30F 6.6.1 PROGRAMMING ALGORITHM FOR PROGRAM FLASH 5. The user can erase one row of program FLASH memory at a time. The user can program one block (4 instruction words) of FLASH memory at a time. The general process is: 1. 2. 3. 4. Read one row of program FLASH (32 instruction words) and store into data RAM as a data "image". Update the data image with the desired new data. Erase program FLASH row. a. Setup NVMCON register for multi-word, program FLASH, erase, and set WREN bit. b. Write address of row to be erased into NVMADR. c. Write `55' to NVMKEY. d. Write `AA' to NVMKEY. e. Set the WR bit. This will begin erase cycle. f. CPU will stall for the duration of the erase cycle. g. The WR bit is cleared when erase cycle ends. Write four instruction words of data from data RAM into the program FLASH write latches. EXAMPLE 6-1: 6. 7. Program 4 instruction words into program FLASH. a. Setup NVMCON register for multi-word, program FLASH, program, and set WREN bit. b. Write `55' to NVMKEY. c. Write `AA' to NVMKEY. d. Set the WR bit. This will begin program cycle. e. CPU will stall for duration of the program cycle. f. The WR bit is cleared by the hardware when program cycle ends. Repeat steps (4 - 5) seven more times to finish programming FLASH row. Repeat steps 1 through 6 as needed to program desired amount of program FLASH memory. 6.6.2 ERASING A ROW OF PROGRAM MEMORY The following is a code sequence that can be used to erase a row (32 instructions) of program memory. ERASING A ROW OF PROGRAM MEMORY ; Setup NVMCON for erase operation, multi word ; program memory selected, and writes enabled MOV #0x4041,W0 ; MOV W0,NVMCON ; ; Init pointer to row to be ERASED MOV #tblpage(PROG_ADDR),W0 ; ; MOV W0,TBLPAG MOV #tbloffset(PROG_ADDR),W0 ; MOV W0, NVMADR ; MOV #0x55,W0 ; MOV #0xAA,W1 ; ; MOV W0,NVMKEY ; MOV W1,NVMKEY NOP ; BSET NVMCON,#WR ; NOP ; NOP ; 2002 Microchip Technology Inc. write Init NVMCON SFR Initialize PM Page Boundary SFR Intialize in-page EA[15:0] pointer Intialize NVMADR SFR Write the 0x55 key Write the 0xAA key Start the erase sequence Insert two NOPs after the erase command is asserted Advance Information DS70032D-page 53 dsPIC30F 6.6.3 LOADING WRITE LATCHES The following is a sequence of instructions that can be used to load the 96 bits of write latches. Four TBLWTL and four TBLWTH instructions are needed to load the write latches selected by the table pointer. EXAMPLE 6-2: LOADING WRITE LATCHES ; Set up a pointer to the first program memory location to be written ; program memory selected, and writes enabled MOV #0x0000,W0 ; ; Initialize PM Page Boundary SFR MOV W0,TBLPAG MOV #0x6000,W0 ; An example program memory address ; Perform the TBLWT instructions to write the latches ; 0th_program_word MOV #LOW_WORD_0,W2 ; MOV #HIGH_BYTE_0,W3 ; ; Write PM low word into program latch TBLWTL W2,[W0] TBLWTH W3,[W0++] ; Write PM high byte into program latch ; 1st_program_word MOV #LOW_WORD_1,W2 ; MOV #HIGH_BYTE_1,W3 ; ; Write PM low word into program latch TBLWTL W2,[W0] ; Write PM high byte into program latch TBLWTH W3,[W0++] ; 2nd_program_word MOV #LOW_WORD_2,W2 ; MOV #HIGH_BYTE_2,W3 ; ; Write PM low word into program latch TBLWTL W2, [W0] TBLWTH W3, [W0++] ; Write PM high byte into program latch ; 3rd_program_word MOV #LOW_WORD_3,W2 ; MOV #HIGH_BYTE_3,W3 ; ; Write PM low word into program latch TBLWTL W2, [W0] ; Write PM high byte into program latch TBLWTH W3, [W0++] Note: In Example 6-2, the contents of the upper byte of W3 has no effect. DS70032D-page 54 Advance Information 2002 Microchip Technology Inc. dsPIC30F 6.6.4 INITIATING THE PROGRAMMING SEQUENCE For protection, the write initiate sequence for NVMKEY must be used to allow any erase or program operation to proceed. After the programming command has been executed, the user must wait for the programming time until programming is complete. The two instructions following the start of the programming sequence should be NOPs. EXAMPLE 6-3: MOV MOV MOV MOV NOP BSET NOP NOP INITIATING A PROGRAMMING SEQUENCE #0x55,W0 #0xAA,W1 W0,NVMKEY W1,NVMKEY NVMCON,#WR 2002 Microchip Technology Inc. ; ; ; ; ; ; ; ; Write the 0x55 key Write the 0xAA key Start the erase sequence Insert two NOPs after the erase command is asserted Advance Information DS70032D-page 55 -- NVMKEY 0766 -- Legend: u = uninitialized bit 0764 NVMADRU Bit 14 WREN -- 0762 NVMADR WR Bit 15 -- -- WRERR Bit 13 NVM REGISTER MAP -- 0760 Addr. NVMCON File Name TABLE 6-1: -- -- -- -- -- -- -- -- -- Bit 12 Bit 11 Bit 10 -- -- -- Bit 9 -- Bit 7 -- -- NVMADR<15:0> -- Bit 8 Bit 6 Bit 5 Bit 3 Bit 2 KEY<7:0> NVMADR<23:16> PROGOP<6:0> Bit 4 Bit 1 Bit 0 All RESETS 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 0000 0000 DSPIC30F DS70032D-page 56 Advance Information 2002 Microchip Technology Inc. dsPIC30F 7.0 DATA EEPROM MEMORY The Data EEPROM Memory is readable and writable during normal operation over the entire VDD range. The data EEPROM memory is directly mapped in the program memory address space. The four SFRs used to read and write the program FLASH memory are used to access data EEPROM memory, as well. As described in Section 4.0, these registers are: * * * * NVMCON NVMADR NVMADRU NVMKEY 7.1 Reading the Data EEPROM A TBLRD instruction reads a word at the current program word address. This example uses W0 as a pointer to data EEPROM. The result is placed in register W4, as shown in Example 7-1. EXAMPLE 7-1: MOV MOV MOV TBLRDL DATA EEPROM READ #LOW_ADDR_WORD,W0 ; Init Pointer #HIGH_ADDR_WORD,W1 W1,TBLPAG [ W0 ], W4 ; read data Flash The EEPROM data memory allows read and write of single words and 16-word blocks. When interfacing to data memory, NVMADR in conjunction with the TBLPAG register, are used to address the EEPROM location being accessed. TBLRDL and TBLWTL instructions are used to read and write data EEPROM. The dsPIC30F devices have up to 8 Kbytes (4K words) of data EEPROM, with an address range from 0x7FF000 to 0x7FFFFE. A word write operation should be preceded by an erase of the corresponding memory location(s). The write typically requires 2 ms to complete. However, the write time varies with voltage and temperature. A program or erase operation on the data EEPROM does not stop the instruction flow. The user is responsible for waiting for the appropriate duration of time before initiating another data EEPROM write/erase operation. Attempting to read the data EEPROM, while a programming or erase operation is in progress, results in unspecified data. Control bit WR initiates write operations, similar to program FLASH writes. This bit cannot be cleared, only set, in software. This bit is cleared in hardware at the completion of the write operation. The inability to clear the WR bit in software prevents the accidental or premature termination of a write operation. The WREN bit, when set, will allow a write operation. On power-up, the WREN bit is clear. The WRERR bit is set when a write operation is interrupted by a MCLR Reset, or a WDT Time-out Reset, during normal operation. In these situations, following Reset, the user can check the WRERR bit and rewrite the location. The address register NVMADR remains unchanged. Note: Interrupt flag bit NVMIF in the IFS0 register is set when write is complete. It must be cleared in software. 2002 Microchip Technology Inc. Advance Information DS70082A-page 57 dsPIC30F 7.2 7.2.1 Erasing Data EEPROM ERASING A BLOCK OF DATA EEPROM In order to erase a block of data EEPROM, the TBLPAG and NVMADR registers must initially point to the block of memory to be erased. Configure NVMCON for erasing a block of data EEPROM, and set the ERASE and WREN bits in NVMCON register. Setting the WR bit initiates the erase, as shown in Example 7-2. EXAMPLE 7-2: DATA EEPROM BLOCK ERASE ; Select data EEPROM block, ERASE, WREN bits MOV #4045,W0 ; Initialize NVMCON SFR MOV W0,NVMCON ; Start erase cycle by setting WR after writing key sequence MOV #0x55,W0 ; MOV #0xAA,W1 ; MOV W0,NVMKEY ; Write the 0x55 key MOV W1,NVMKEY ; Write the 0xAA key NOP ; BSET NVMCON,#WR ; Initiate erase sequence ; Erase cycle will complete in 2mS. CPU is not stalled for the Data Erase Cycle ; User can poll WR bit, use NVMIF or Timer IRQ to determine erasure complete 7.2.2 ERASING A WORD OF DATA EEPROM The TBLPAG and NVMADR registers must point to the block. Select erase a block of data FLASH, and set the ERASE and WREN bits in NVMCON register. Setting the WR bit initiates the erase, as shown in Example 7-3. EXAMPLE 7-3: DATA EEPROM WORD ERASE ; Select data EEPROM word, ERASE, WREN bits MOV #4044,W0 MOV W0,NVMCON ; Start erase cycle by setting WR after writing key sequence MOV #0x55,W0 ; MOV #0xAA,W1 ; MOV W0,NVMKEY ; Write the 0x55 key MOV W1,NVMKEY ; Write the 0xAA key NOP ; BSET NVMCON,#WR ; Initiate erase sequence ; Erase cycle will complete in 2mS. CPU is not stalled for the Data Erase Cycle ; User can poll WR bit, use NVMIF or Timer IRQ to determine erasure complete DS70082A-page 58 Advance Information 2002 Microchip Technology Inc. dsPIC30F 7.3 Writing to the Data EEPROM To write an EEPROM data location, the following sequence must be followed: 1. 2. 3. Erase data EEPROM word. a. Select word, data EEPROM, erase, and set WREN bit in NVMCON register. b. Write address of word to be erased into NVMADR. c. Optionally, enable NVM interrupt. d. Write `55' to NVMKEY. e. Write `AA' to NVMKEY. f. Set the WR bit. This will begin erase cycle. g. Either poll NVMIF bit or wait for NVMIF interrupt. h. The WR bit is cleared when the erase cycle ends. Write data word into data EEPROM write latches. Program 1 data word into data EEPROM. a. Select word, data EEPROM, program, and set WREN bit in NVMCON register. b. Optionally, enable NVM write done interrupt. c. Write `55' to NVMKEY. d. Write `AA' to NVMKEY. e. Set The WR bit. This will begin program cycle. f. Either poll NVMIF bit or wait for NVM interrupt. g. The WR bit is cleared when the write cycle ends. EXAMPLE 7-4: The write will not initiate if the above sequence is not exactly followed (write 0x55 to NVMKEY, write 0xAA to NVMCON, then set WR bit) for each word. It is strongly recommended that interrupts be disabled during this code segment. Additionally, the WREN bit in NVMCON must be set to enable writes. This mechanism prevents accidental writes to data EEPROM, due to unexpected code execution. The WREN bit should be kept clear at all times, except when updating the EEPROM. The WREN bit is not cleared by hardware. After a write sequence has been initiated, clearing the WREN bit will not affect the current write cycle. The WR bit will be inhibited from being set unless the WREN bit is set. The WREN bit must be set on a previous instruction. Both WR and WREN cannot be set with the same instruction. At the completion of the write cycle, the WR bit is cleared in hardware and the Non-Volatile Memory Write Complete Interrupt Flag bit (NVMIF) is set. The user may either enable this interrupt, or poll this bit. NVMIF must be cleared by software. 7.3.1 WRITING A WORD OF DATA EEPROM Assuming the user has erased the word to be programmed, then, use a table write instruction to write one write latch, as shown in Example 7-4. DATA EEPROM WORD WRITE ; Point to data memory MOV #LOW_ADDR_WORD,W0 MOV #HIGH_ADDR_WORD,W1 MOV W1,TBLPAG MOV #LOW(WORD),W2 TBLWTL W2,[ W0] ; The NVMADR captures last table access address ; Select data EEPROM for 1 word op MOV #0x4004,W0 MOV W0,NVMCON ; Operate key to allow write operation MOV #0x55,W0 MOV #0xAA,W1 MOV W0,NVMKEY MOV W1,NVMKEY NOP BSET NVMCON,#WR ; Init pointer ; Get data ; Write data ; Write the 0x55 key ; Write the 0xAA key ; Initiate program sequence ; Write cycle will complete in 2mS. CPU is not stalled for the Data Write Cycle ; User can poll WR bit, use NVMIF or Timer IRQ to determine write complete 2002 Microchip Technology Inc. Advance Information DS70082A-page 59 dsPIC30F 7.3.2 WRITING A BLOCK OF DATA EEPROM To write a block of data EEPROM, write to all sixteen latches first, then set the NVMCON register and program the block. EXAMPLE 7-5: MOV MOV MOV MOV TBLWTL MOV TBLWTL MOV TBLWTL MOV TBLWTL MOV TBLWTL MOV TBLWTL MOV TBLWTL MOV TBLWTL MOV TBLWTL MOV TBLWTL MOV TBLWTL MOV TBLWTL MOV TBLWTL MOV TBLWTL MOV TBLWTL MOV TBLWTL MOV MOV MOV MOV MOV MOV BSET 7.4 DATA EEPROM BLOCK WRITE #LOW_ADDR_WORD,W0 #HIGH_ADDR_WORD,W1 W1,TBLPAG #data1,W2 W2,[ W0]++ #data2,W2 W2,[ W0]++ #data3,W2 W2,[ W0]++ #data4,W2 W2,[ W0]++ #data5,W2 W2,[ W0]++ #data6,W2 W2,[ W0]++ #data7,W2 W2,[ W0]++ #data8,W2 W2,[ W0]++ #data9,W2 W2,[ W0]++ #data10,W2 W2,[ W0]++ #data11,W2 W2,[ W0]++ #data12,W2 W2,[ W0]++ #data13,W2 W2,[ W0]++ #data14,W2 W2,[ W0]++ #data15,W2 W2,[ W0]++ #data16,W2 W2,[ W0]++ #0x400A,W0 W0,NVMCON #0x55,W0 #0xAA,W1 W0,NVMKEY W1,NVMKEY NVMCON,#WR ; Init pointer ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; Get 1st data write data Get 2nd data write data Get 3rd data write data Get 4th data write data Get 5th data write data Get 6th data write data Get 7th data write data Get 8th data write data Get 9th data write data Get 10th data write data Get 11th data write data Get 12th data write data Get 13th data write data Get 14th data write data Get 15th data write data Get 16th data write data. The NVMADR captures last table access address. Select data EEPROM for multi word op Operate Key to allow program operation ; Write the 0x55 key ; Write the 0xAA key ; Start write cycle Write Verify 7.5 Depending on the application, good programming practice may dictate that the value written to the memory should be verified against the original value. This should be used in applications where excessive writes can stress bits near the specification limit. Protection Against Spurious Write There are conditions when the device may not want to write to the data EEPROM memory. To protect against spurious EEPROM writes, various mechanisms have been built-in. On power-up, the WREN bit is cleared; also, the Power-up Timer prevents EEPROM write. The write initiate sequence and the WREN bit together, help prevent an accidental write during brown-out, power glitch, or software malfunction. DS70082A-page 60 Advance Information 2002 Microchip Technology Inc. dsPIC30F 8.0 I/O PORTS Writes to the latch, write the latch (LATx). Reads from the port (PORTx), read the port pins, and writes to the port pins, write the latch (LATx). All of the device pins (except VDD, VSS, MCLR, and OSC1/CLKIN) are shared between the peripherals and the parallel I/O ports. Any bit and its associated data and control registers that is not valid for a particular device will be disabled. That means the corresponding LATx and TRISx registers and the port pin will read as zeros. All I/O input ports feature Schmitt Trigger inputs for improved noise immunity. 8.1 When a pin is shared with another peripheral or function that is defined as an input only, it is nevertheless regarded as a dedicated port because there is no other competing source of outputs. An example is the INT4 pin. Parallel I/O (PIO) Ports When a peripheral is enabled, the use of any associated pin as a general purpose output pin is disabled. The I/O pin may be read, but the output driver for the parallel port bit will be disabled. If a peripheral is enabled, but the peripheral is not actively driving a pin, that pin may be driven by a port. The format of the registers for PORTA are shown in Table 8-1. The TRISA (Data Direction Control) register controls the direction of the RA<7:0> pins, as well as the INTx pins and the VREF pins. The LATA register supplies data to the outputs, and is readable/writable. Reading the PORTA register yields the state of the input pins, while writing the PORTA register modifies the contents of the LATA register. All port pins have three registers directly associated with the operation of the port pin. The data direction register (TRISx) determines whether the pin is an input or an output. If the Data Direction bit is a `1', then the pin is an input. All port pins are defined as inputs after a RESET. Reads from the latch (LATx), read the latch. FIGURE 8-1: BLOCK DIAGRAM OF A DEDICATED PORT STRUCTURE Dedicated Port Module Read TRIS I/O Cell TRIS Latch Data Bus D WR TRIS CK Q Data Latch D WR LAT + WR Port Q I/O Pad CK Read LAT Read Port 2002 Microchip Technology Inc. Advance Information DS70082A-page 61 02C4 LATA15 LATA14 u = uninitialized bit RA14 LATA Legend: RA15 TRISA15 TRISA14 02C2 Bit 14 02C0 Bit 15 PORTA Addr. -- -- -- Bit 13 -- -- -- Bit 12 PORTA REGISTER MAP TRISA SFR Name TABLE 8-1: -- -- -- Bit 11 Bit 9 LATA10 RA10 LATA9 RA9 TRISA10 TRISA9 Bit 10 -- -- -- Bit 8 -- -- -- Bit 7 -- -- -- Bit 6 -- -- -- Bit 5 -- -- -- Bit 4 -- -- -- Bit 3 -- -- -- Bit 2 -- -- -- Bit 1 -- -- -- Bit 0 0000 0000 0000 0000 0000 0000 0000 0000 1100 0110 0000 0000 RESET State dsPIC30F DS70082A-page 62 Advance Information 2002 Microchip Technology Inc. dsPIC30F A parallel I/O (PIO) port that shares a pin with a peripheral is, in general, subservient to the peripheral. The peripheral's output buffer data and control signals are provided to a pair of multiplexers. The multiplexers select whether the peripheral or the associated port has ownership of the output data and control signals of the I/O pad cell. Figure 8-2 shows how ports are shared with other peripherals, and the associated I/O cell (pad) to which they are connected. Table 8-2 through Table 8-7 show the formats of the registers for the shared ports, PORTB through PORTG. Note: The actual bits in use vary between devices. FIGURE 8-2: BLOCK DIAGRAM OF A SHARED PORT STRUCTURE Output Multiplexers Peripheral Module Peripheral Input Data Peripheral Module Enable I/O Cell Peripheral Output Enable 1 Peripheral Output Data 0 PIO Module 1 Output Enable Output Data 0 Read TRIS I/O Pad Data Bus D WR TRIS Q CK TRIS Latch D WR LAT + WR Port Q CK Data Latch Read LAT Input Data Read Port 8.2 Configuring Analog Port Pins The use of the ADPCFG and TRIS registers control the operation of the A/D port pins. The port pins that are desired as analog inputs must have their corresponding TRIS bit set (input). If the TRIS bit is cleared (output), the digital output level (VOH or VOL) will be converted. Pins configured as digital inputs, will not convert an analog input. Analog levels on any pin that is defined as a digital input (including the ANx pins), may cause the input buffer to consume current that exceeds the device specifications. When reading the PORT register, all pins configured as analog input channel will read as cleared (a low level). 2002 Microchip Technology Inc. Advance Information DS70082A-page 63 DS70082A-page 64 02CB LATB15 LATB14 u = uninitialized bit LATB Legend: 02D0 LATC Bit 11 Bit 10 RB14 LATB13 RB13 LATB12 RB12 Bit 14 Bit 13 LATC15 RC15 LATC13 RC13 RD14 Advance Information 02DC LATD13 RD13 LATD12 RD12 Bit 12 -- -- -- Bit 15 -- -- -- Bit 14 -- -- -- Bit 13 -- -- -- Bit 12 Bit 10 Bit 9 -- -- -- -- -- -- RD9 LATE9 RE9 TRISE9 Bit 8 -- -- -- TRISE8 Bit 7 LATD7 RD7 LATE7 RE7 Bit 6 LATD6 RD6 Bit 5 LATE6 RE6 Bit 5 -- -- -- Bit 4 Bit 3 LATE5 RE5 TRISE5 Bit 5 LATD5 RD5 RB3 LATB3 Bit 4 LATE4 RE4 TRISE4 Bit 4 LATD4 RD4 LATE3 RE3 TRISE3 Bit 3 LATD3 RD3 TRISD3 Bit 3 LATC3 RC3 TRISC3 Bit 3 LATB4 RB4 TRISD4 Bit 4 LATB5 RB5 TRISD5 -- -- -- Bit 5 TRISD6 Bit 6 -- -- -- RB6 TRISE6 TRISD7 Bit 7 -- -- -- TRISE7 LATD8 RD8 LATE8 Bit 6 LATB6 Bit 6 LATB7 RB7 Bit 7 LATB8 RB8 TRISD8 RE8 Bit 7 Bit 2 Bit 1 Bit 0 Bit 2 LATE2 RE2 RC1 LATE1 RE1 TRISE1 Bit 1 LATD1 RD1 TRISD1 Bit 1 LATC1 TRISE2 Bit 2 LATD2 RD2 Bit 1 LATB1 RB1 TRISC1 TRISD2 -- -- -- Bit 2 LATB2 RB2 RESET State 0000 0000 0000 0000 0000 0000 0000 0000 1110 0000 0000 1010 RESET State 0000 0000 0000 0000 0000 0000 0000 0000 1111 1111 1111 1111 RESET State RESET State 0000 0000 0000 0000 0000 0000 0000 0000 LATE0 RE0 0000 0000 0000 0000 0000 0000 0000 0000 TRISE0 0000 0011 1111 1111 Bit 0 LATD0 RD0 TRISD0 1111 1111 1111 1111 Bit 0 -- -- -- Bit 0 LATB0 RB0 TRISB8 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 Bit 8 Bit 8 Bit 8 LATD9 Bit 9 LATD10 RD10 Bit 10 LATD11 RD11 Bit 11 PORTE REGISTER MAP u = uninitialized bit LATE Legend: 02D8 02DB PORTE Addr. TRISE SFR Name TABLE 8-5: LATD 02D6 LATD15 LATD14 Legend: u = uninitialized bit RD15 Bit 13 02D2 TRISD15 TRISD14 TRISD13 TRISD12 TRISD11 TRISD10 TRISD9 PORTD 02D4 Bit 14 -- -- -- Bit 9 LATB9 RB9 TRISB9 TRISD Bit 15 -- -- -- Bit 10 LATB10 RB10 Addr. -- -- -- Bit 11 Bit 11 -- -- -- Bit 12 PORTD REGISTER MAP LATC14 RC14 TRISC15 TRISC14 TRISC13 Bit 15 LATB11 RB11 Bit 9 SFR Name TABLE 8-4: Bit 12 PORTC REGISTER MAP RB15 u = uninitialized bit 02CE Legend: 02CC PORTC Addr. TRISC SFR Name TABLE 8-3: 02C8 Bit 13 TRISB15 TRISB14 TRISB13 TRISB12 TRISB11 TRISB10 02C6 PORTB Bit 14 TRISB Bit 15 Addr. PORTB REGISTER MAP SFR Name TABLE 8-2: dsPIC30F 2002 Microchip Technology Inc. 02E0 02E2 PORTF LATF 2002 Microchip Technology Inc. 02E4 02E6 02E8 TRISG PORTG LATG -- -- -- Bit 13 -- -- -- Bit 12 -- -- -- Bit 15 -- -- -- Bit 14 -- -- -- Bit 13 -- -- -- Bit 12 PORTG REGISTER MAP -- -- -- Bit 14 u = uninitialized bit Addr. SFR Name TABLE 8-7: Legend: -- -- -- Bit 15 PORTF REGISTER MAP u = uninitialized bit 02EE TRISF Legend: Addr. SFR Name TABLE 8-6: -- -- -- -- -- -- Bit 10 -- -- -- Bit 10 Bit 11 -- -- -- Bit 11 LATG9 RG9 Bit 8 LATG8 RG8 Bit 7 LATG7 RG7 Bit 6 RF5 -- -- -- Bit 5 LATF5 LATG6 RG6 Bit 5 TRISF5 TRISG6 Bit 6 LATF6 RF6 TRISF6 TRISG7 Bit 7 LATF7 RF7 TRISF7 TRISG8 Bit 8 LATF8 RF8 TRISF8 TRISG9 Bit 9 -- -- -- Bit 9 -- -- -- Bit 4 LATF4 RF4 TRISF4 Bit 4 LATG3 RG3 TRISG3 Bit 3 LATF3 RF3 TRISF3 Bit 3 LATG2 RG2 TRISG2 Bit 2 LATF2 RF2 TRISF2 Bit 2 LATG1 RG1 TRISG1 Bit 1 LATF1 RF1 TRISF1 Bit 1 LATG0 RG0 TRISG0 Bit 0 LATF0 RF0 TRISF0 Bit 0 0000 0000 0000 0000 0000 0000 0000 0000 0000 0011 1100 1111 RESET State 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001 1111 1111 RESET State dsPIC30F Advance Information DS70082A-page 65 dsPIC30F 8.3 Input Change Notification Module The Input Change Notification module provides the dsPIC30F devices the ability to generate interrupt requests to the processor in response to a change of state on selected input pins. This module is capable of detecting input change of states even in SLEEP mode, when the clocks are disabled. There are up to 22 external signals (CN0 through CN21) that may be selected (enabled) for generating an interrupt request on a change of state. TABLE 8-8: INPUT CHANGE NOTIFICATION REGISTER MAP (BITS 15-8) SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 RESET State CNEN1 00C0 CN15IE CN14IE CN13IE CN12IE CN11IE CN10IE CN9IE CN8IE 0000 0000 0000 0000 CNEN2 00C2 -- -- -- -- -- -- CNPU1 00C4 CNPU2 Legend: 00C6 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE -- -- -- -- -- -- -- -- 0000 0000 0000 0000 CN9PUE CN8PUE 0000 0000 0000 0000 -- -- 0000 0000 0000 0000 Bit 0 RESET State u = uninitialized bit TABLE 8-9: INPUT CHANGE NOTIFICATION REGISTER MAP (BITS 7-0) SFR Name Addr. Bit 7 Bit 6 CNEN1 00C0 CN7IE CN6IE CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE 0000 0000 0000 0000 CNEN2 00C2 -- -- CN21IE CN20IE CN19IE CN18IE CN17IE CN16IE 0000 0000 0000 0000 CNPU1 00C4 CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE 0000 0000 0000 0000 CNPU2 00C6 -- -- CN21PUE CN20PUE CN19PUE CN18PUE CN17PUE CN16PUE 0000 0000 0000 0000 Legend: Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 u = uninitialized bit DS70082A-page 66 Advance Information 2002 Microchip Technology Inc. dsPIC30F 9.0 TIMER1 MODULE This section describes the 16-bit General Purpose (GP) Timer1 module and associated Operational modes. Figure 9-1 depicts the simplified block diagram of the 16-bit Timer1 Module. The following sections provide a detailed description, including setup and control registers along with associated block diagrams for the Operational modes of the timers. The Timer1 module is a 16-bit timer which can serve as the time counter for the real-time clock, or operate as a free running interval timer/counter. The 16-bit timer has the following modes: * 16-bit Timer * 16-bit Synchronous Counter * 16-bit Asynchronous Counter Further, the following operational characteristics are supported: * Timer gate operation * Selectable prescaler settings * Timer operation during CPU IDLE and SLEEP modes * Interrupt on 16-bit period register match or falling edge of external gate signal When the CPU goes into the IDLE mode, the timer will stop incrementing, unless the TSIDL (T1CON<13>) bit = 0. If TSIDL = 1, the timer module logic will resume the incrementing sequence upon termination of the CPU IDLE mode. 16-bit Synchronous Counter Mode: In the 16-bit Synchronous Counter mode, the timer increments on the rising edge of the applied external clock signal, which is synchronized with the internal phase clocks. The timer counts up to a match value preloaded in PR1, then resets to 0 and continues. When the CPU goes into the IDLE mode, the timer will stop incrementing, unless the respective TSIDL bit = 0. If TSIDL = 1, the timer module logic will resume the incrementing sequence upon termination of the CPU IDLE mode. 16-bit Asynchronous Counter Mode: In the 16-bit Asynchronous Counter mode, the timer increments on every rising edge of the applied external clock signal. The timer counts up to a match value preloaded in PR1, then resets to 0 and continues. These Operating modes are determined by setting the appropriate bit(s) in the 16-bit SFR, T1CON. Figure 9-1 presents a block diagram of the 16-bit timer module. FIGURE 9-1: 16-bit Timer Mode: In the 16-bit Timer mode, the timer increments on every instruction cycle up to a match value, preloaded into the period register PR1, then resets to 0 and continues to count. When the timer is configured for the Asynchronous mode of operation and the CPU goes into the IDLE mode, the timer will stop incrementing if TSIDL = 1. 16-BIT TIMER1 MODULE BLOCK DIAGRAM PR1 Equal Comparator x 16 TSYNC 1 RESET Sync (3) TMR1 0 0 1 Q D Q CK TGATE TCS TGATE T1IF Event Flag TGATE TON SOSC1/ T1CK TCKPS<1:0> 2 1X LPOSCEN SOSC2 2002 Microchip Technology Inc. Gate Sync 01 TCY 00 Advance Information Prescaler 1, 8, 64, 256 DS70082A-page 67 dsPIC30F 9.1 Timer Gate Operation The 16-bit timer can be placed in the Gated Time Accumulation mode. This mode allows the internal TCY to increment the respective timer when the gate input signal (T1CK pin) is asserted high. Control bit TGATE (T1CON<6>) must be set to enable this mode. The timer must be enabled (TON = 1) and the timer clock source set to internal (TCS = 0). When the CPU goes into the IDLE mode, the timer will stop incrementing, unless TSIDL = 0. If TSIDL = 1, the timer will resume the incrementing sequence upon termination of the CPU IDLE mode. 9.2 Timer Prescaler The input clock (FOSC/4 or external clock) to the 16-bit Timer, has a prescale option of 1:1, 1:8, 1:64, and 1:256 selected by control bits TCKPS<1:0> (T1CON<5:4>). The prescaler counter is cleared when any of the following occurs: * a write to the TMR1 register * a write to the T1CON register * device RESET such as POR and BOR When the Gated Time Accumulation mode is enabled, an interrupt will also be generated on the falling edge of the gate signal (at the end of the accumulation cycle). Enabling an interrupt is accomplished via the respective timer interrupt enable bit, T1IE. The timer interrupt enable bit is located in the IEC0 control register in the Interrupt Controller. 9.5 Real-Time Clock Timer1, when operating in Real-Time Clock (RTC) mode, provides time-of-day and event time stamping capabilities. Key operational features of the RTC are: * * * * * Operation from 32 KHz LP oscillator 8-bit prescaler Low power Real-Time Clock Interrupts These Operating modes are determined by setting the appropriate bit(s) in the T1CON Control register 9.5.1 RTC OSCILLATOR OPERATION However, if the timer is disabled (TON = 0), then the timer prescaler cannot be reset since the prescaler clock is halted. When the TON = 1, TCS = 1 and TGATE = 0, the timer increments on the rising edge of the 32 kHz LP oscillator output signal, up to the value specified in the period register, and is then reset to `0'. TMR1 is not cleared when T1CON is written. It is cleared by writing to the TMR1 register. The TSYNC bit must be asserted to a logic 0 (Asynchronous mode) for correct operation. 9.3 Enabling LPOSCEN (OSCCON<1>) will disable the normal Timer and Counter modes and enable a timer carry-out wake-up event. Timer Operation During SLEEP Mode During CPU SLEEP mode, the timer will operate if: * The timer module is enabled (TON = 1) and * The timer clock source is selected as external (TCS = 0) and * The TSYNC bit (T1CON<2>) is asserted to a logic 0, which defines the external clock source as asynchronous. When all three conditions are true, the timer will continue to count up to the period register and be reset to 0x0000. When a match between the timer and the period register occurs, an interrupt can be generated, if the respective timer interrupt enable bit is asserted. 9.4 Timer Interrupt The 16-bit timer has the ability to generate an interrupt on period match. When the timer count matches the period register, the T1IF bit is asserted and an interrupt will be generated, if enabled. The T1IF bit must be cleared in software. The timer interrupt flag T1IF is located in the IFS0 control register in the Interrupt Controller. DS70082A-page 68 When the CPU enters SLEEP or IDLE mode, the timer will continue to increment, provided the external clock is active and the control bits have not been changed. The TSIDL bit is excluded from the control of the timer module for this mode. 9.5.2 RTC INTERRUPTS When an interrupt event occurs, the respective interrupt flag, T1IF, is asserted and an interrupt will be generated, if enabled. The T1IF bit must be cleared in software. The respective Timer interrupt flag, T1IF, is located in the IFS0 status register in the Interrupt Controller. Enabling an interrupt is accomplished via the respective timer interrupt enable bit, T1IE. The Timer interrupt enable bit is located in the IEC0 control register in the Interrupt Controller. Advance Information 2002 Microchip Technology Inc. 0102 PR1 Bit 15 -- Bit 14 TSIDL Bit 13 -- Bit 12 TIMER1 REGISTER MAP 0104 TON u = uninitialized bit 0100 T1CON Legend: Addr. SFR Name TMR1 TABLE 9-1: -- Bit 11 -- Bit 10 -- Bit 9 -- Bit 7 Bit 6 -- TGATE Period Register 1 Timer 1 Register Bit 8 Bit 4 TCKPS1 TCKPS0 Bit 5 -- Bit 3 TSYNC Bit 2 TCS Bit 1 -- Bit 0 RESET State 0000 0000 0000 0000 1111 1111 1111 1111 uuuu uuuu uuuu uuuu dsPIC30F 2002 Microchip Technology Inc. Advance Information DS70082A-page 69 dsPIC30F NOTES: DS70082A-page 70 Advance Information 2002 Microchip Technology Inc. dsPIC30F 10.0 TIMER2/3 MODULE This section describes the 32-bit General Purpose (GP) Timer module (Timer2/3) and associated Operational modes. Figure 10-1 depicts the simplified block diagram of the 32-bit Timer2/3 Module. Figure 10-2 and Figure 10-3 show Timer2/3 configured as two independent 16-bit timers, Timer2 and Timer3, respectively. The Timer2/3 module is a 32-bit timer (which can be configured as two 16-bit timers) with selectable operating modes. These timers are utilized by other peripheral modules such as: * Input Capture * Output Compare/Simple PWM The following sections provide a detailed description, including setup and control registers, along with associated block diagrams for the Operational modes of the timers. The 32-bit timer has the following modes: * Two independent 16-bit timers (Timer2 and Timer3) with all 16-bit Operating modes (except Asynchronous Counter mode) * Single 32-bit Timer operation * Single 32-bit Synchronous Counter Further, the following operational characteristics are supported: * * * * * ADC Event Trigger Timer Gate Operation Selectable Prescaler Settings Timer Operation during IDLE and SLEEP modes Interrupt on a 32-bit Period Register Match These Operating modes are determined by setting the appropriate bit(s) in the 16-bit T2CON and T3CON SFRs. 16-bit Mode: In the 16-bit mode, Timer2 and Timer3 can be configured as two independent 16-bit timers. Each timer can be set up in either 16-bit Timer mode or 16-bit Synchronous Counter mode. See the Timer1 section for details on these two Operating modes. The only functional difference between Timer2 and Timer3 is that Timer2 provides synchronization of the clock prescaler output. This is useful for high frequency external clock inputs. 32-bit Timer Mode: In the 32-bit Timer mode, the timer increments on every instruction cycle up to a match value, preloaded into the combined 32-bit period register PR3/PR2, then resets to 0 and continues to count. For synchronous 32-bit reads of the Timer2/Timer3 pair, reading the LS word (TMR2 register) will cause the MS word to be read and latched into a 16-bit holding register, termed TMR3HLD. For synchronous 32-bit writes, the holding register (TMR3HLD) must first be written to. When followed by a write to the TMR2 register, the contents of TMR3HLD will be transferred and latched into the MSB of the 32-bit timer (TMR3). 32-bit Synchronous Counter Mode: In the 32-bit Synchronous Counter mode, the timer increments on the rising edge of the applied external clock signal, which is synchronized with the internal phase clocks. The timer counts up to a match value preloaded in the combined 32-bit period register PR3/PR2, then resets to `0' and continues. When the timer is configured for the Synchronous Counter mode of operation and the CPU goes into the IDLE mode, the timer will stop incrementing, unless the TSIDL (T2CON<13>) bit = 0. If TSIDL = 1, the timer module logic will resume the incrementing sequence upon termination of the CPU IDLE mode. For 32-bit timer/counter operation, Timer2 is the LS Word and Timer3 is the MS Word of the 32-bit timer. Note: For 32-bit timer operation, T3CON control bits are ignored. Only T2CON control bits are used for setup and control. Timer 2 clock and gate inputs are utilized for the 32-bit timer module, but an interrupt is generated with the Timer3 interrupt flag (T3IF) and the interrupt is enabled with the Timer3 interrupt enable bit (T3IE). 2002 Microchip Technology Inc. Advance Information DS70082A-page 71 dsPIC30F FIGURE 10-1: 32-BIT TIMER2/3 BLOCK DIAGRAM Data Bus<15:0> TMR3HLD 16 16 Write TMR2 Read TMR2 16 RESET TMR3 TMR2 MSB LSB Sync ADC Event Trigger Equal Comparator x 32 PR3 PR2 0 T3IF Event Flag 1 D Q CK TGATE(T2CON<6>) TCS TGATE TGATE (T2CON<6>) Q TON T2CK 1X Gate Sync TCY Note 1: TCKPS<1:0> 2 01 Prescaler 1, 8, 64, 256 00 Timer configuration bit T32, T2CON(<3>) must be set to 1 for a 32-bit timer/counter operation. All control bits are respective to the T2CON register. DS70082A-page 72 Advance Information 2002 Microchip Technology Inc. dsPIC30F FIGURE 10-2: 16-BIT TIMER2 BLOCK DIAGRAM PR2 Equal Comparator x 16 RESET Sync 0 1 Q D Q CK TGATE TCS TGATE T2IF Event Flag TMR2 TGATE TON T2CK FIGURE 10-3: TCKPS<1:0> 2 1X Gate Sync 01 TCY 00 Prescaler 1, 8, 64, 256 16-BIT TIMER3 BLOCK DIAGRAM PR3 ADC Event Trigger Equal RESET TMR3 0 1 Q D Q CK TGATE T3CK TGATE TCS TGATE T3IF Event Flag Comparator x 16 Sync TON 1X 01 TCY 2002 Microchip Technology Inc. TCKPS<1:0> 2 Advance Information Prescaler 1, 8, 64, 256 00 DS70082A-page 73 dsPIC30F 10.1 Timer Gate Operation 10.4 The 32-bit timer can be placed in the Gated Time Accumulation mode. This mode allows the internal TCY to increment the respective timer when the gate input signal (T2CK pin) is asserted high. Control bit TGATE (T2CON<6>) must be set to enable this mode. When in this mode, Timer2 is the originating clock source. The TGATE setting is ignored for Timer3. The timer must be enabled (TON = 1) and the timer clock source set to internal (TCS = 0). The falling edge of the external signal terminates the count operation, but does not reset the timer. The user must reset the timer in order to start counting from zero. 10.2 ADC Event Trigger When a match occurs between the 32-bit timer (TMR3/ TMR2) and the 32-bit combined period register (PR3/ PR2), a special ADC trigger event signal is generated by Timer3. 10.3 Timer Operation During SLEEP Mode During CPU SLEEP mode, the timer will not operate, because the internal clocks are disabled. 10.5 Timer Interrupt The 32-bit timer module can generate an interrupt on period match, or on the falling edge of the external gate signal. When the 32-bit timer count matches the respective 32-bit period register, or the falling edge of the external "gate" signal is detected, the T3IF bit (IFS0<7>) is asserted and an interrupt will be generated if enabled. In this mode, the T3IF interrupt flag is used as the source of the interrupt. The T3IF bit must be cleared in software. Enabling an interrupt is accomplished via the respective timer interrupt enable bit, T3IE (IEC0<7>). Timer Prescaler The input clock (FOSC/4 or external clock) to the timer has a prescale option of 1:1, 1:8, 1:64, and 1:256 selected by control bits TCKPS<1:0> (T2CON<5:4> and T3CON<5:4>). For the 32-bit timer operation, the originating clock source is Timer2. The prescaler operation for Timer3 is not applicable in this mode. The prescaler counter is cleared when any of the following occurs: * a write to the TMR2/TMR3 register * a write to the T2CON/T3CON register * device RESET such as POR and BOR However, if the timer is disabled (TON = 0), then the Timer 2 prescaler cannot be reset, since the prescaler clock is halted. TMR2/TMR3 is not cleared when T2CON/T3CON is written. DS70082A-page 74 Advance Information 2002 Microchip Technology Inc. 010E 0110 PR2 PR3 T2CON TON 0112 TON u = uninitialized bit 010C TMR3 T3CON Legend: 0108 010A TMR3HLD -- -- Bit 14 TSIDL TSIDL Bit 13 -- -- Bit 12 -- -- Bit 11 Bit 15 0106 SFR Name Addr. TMR2 TIMER2/3 REGISTER MAP TABLE 10-1: Bit 9 Bit 7 Timer2 Register Bit 8 Bit 6 Bit 5 -- -- -- -- -- -- -- -- TGATE TGATE Period Register 3 Period Register 2 Timer3 Register Bit 4 TCKPS1 TCKPS0 TCKPS1 TCKPS0 Timer3 Holding Register (For 32-bit timer operations only) Bit 10 -- T32 Bit 3 -- -- Bit 2 TCS TCS Bit 1 -- -- Bit 0 RESET State 0000 0000 0000 0000 0000 0000 0000 0000 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu dsPIC30F 2002 Microchip Technology Inc. Advance Information DS70082A-page 75 dsPIC30F NOTES: DS70082A-page 76 Advance Information 2002 Microchip Technology Inc. dsPIC30F 11.0 TIMER4/5 MODULE This section describes the second 32-bit General Purpose (GP) Timer module (Timer4/5) and associated Operational modes. Figure 11-1 depicts the simplified block diagram of the 32-bit Timer4/5 Module. Figure 11-2 and Figure 11-3 show Timer4/5 configured as two independent 16-bit timers, Timer4 and Timer5, respectively. The Operating modes of the Timer4/5 module are determined by setting the appropriate bit(s) in the 16-bit T4CON and T5CON SFRs. For 32-bit timer/counter operation, Timer4 is the LS Word and Timer5 is the MS Word of the 32-bit timer. Note: The Timer4/5 module is similar in operation to the Timer 2/3 module. However, there are some differences, which are listed below: * The Timer4/5 module does not support the ADC Event Trigger feature * Timer4/5 can not be utilized by other peripheral modules such as Input Capture and Output Compare FIGURE 11-1: For 32-bit timer operation, T5CON control bits are ignored. Only T4CON control bits are used for setup and control. Timer4 clock and gate inputs are utilized for the 32-bit timer module, but an interrupt is generated with the Timer5 interrupt flag (T5IF) and the interrupt is enabled with the Timer5 interrupt enable bit (T5IE). 32-BIT TIMER4/5 BLOCK DIAGRAM Data Bus<15:0> TMR5HLD 16 16 Write TMR4 Read TMR4 16 RESET Equal TMR5 TMR4 MSB LSB Comparator x 32 PR5 T5IF Event Flag Sync PR4 0 1 D CK TGATE(T4CON<6>) TCS TGATE TGATE (T4CON<6>) Q Q TON T4CK Note 1: TCKPS<1:0> 2 1X Gate Sync 01 TCY 00 Prescaler 1, 8, 64, 256 Timer configuration bit T32, T4CON(<3>) must be set to `1' for a 32-bit timer/counter operation. All control bits are respective to the T4CON register. 2002 Microchip Technology Inc. Advance Information DS70082A-page 77 dsPIC30F FIGURE 11-2: 16-BIT TIMER4 BLOCK DIAGRAM PR4 Equal Comparator x 16 RESET Sync 0 1 Q D Q CK TGATE TCS TGATE T4IF Event Flag TMR4 TGATE TCKPS<1:0> 2 TON T4CK 1X FIGURE 11-3: Gate Sync 01 TCY 00 Prescaler 1, 8, 64, 256 16-BIT TIMER5 BLOCK DIAGRAM PR5 Equal ADC Event Trigger RESET TMR5 0 1 Q D Q CK TGATE TCS TGATE T5IF Event Flag Comparator x 16 TGATE T5CK Sync 1X 01 TCY DS70082A-page 78 Advance Information TON TCKPS<1:0> 2 Prescaler 1, 8, 64, 256 00 2002 Microchip Technology Inc. 0118 011A 011C 011E TMR5 PR4 PR5 T4CON TON Bit 15 -- -- Bit 14 TSIDL TSIDL Bit 13 -- -- Bit 12 TIMER4/5 REGISTER MAP 0120 TON u = uninitialized bit 0116 TMR5HLD T5CON Legend: 0114 Addr. TMR4 SFR Name TABLE 11-1: -- -- Bit 11 Bit 9 Bit 7 Bit 6 Timer 4 Register Bit 8 Bit 5 -- -- -- -- -- -- -- -- TGATE TGATE Period Register 5 Period Register 4 Timer 5 Register TCKPS1 TCKPS1 Timer 5 Holding Register (For 32-bit operations only) Bit 10 TCKPS0 TCKPS0 Bit 4 -- T45 Bit 3 -- -- Bit 2 TCS TCS Bit 1 -- -- Bit 0 RESET State 0000 0000 0000 0000 0000 0000 0000 0000 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu dsPIC30F 2002 Microchip Technology Inc. Advance Information DS70082A-page 79 dsPIC30F NOTES: DS70082A-page 80 Advance Information 2002 Microchip Technology Inc. dsPIC30F 12.0 INPUT CAPTURE MODULE The key operational features of the Input Capture module are: This section describes the Input Capture module and associated Operational modes. The features provided by this module are useful in applications requiring Frequency (Period) and Pulse measurement. Figure 12-1 depicts a block diagram of the Input Capture Module. Input capture is useful for such modes as: * Simple Capture Event mode * Timer2 and Timer3 mode selection * Interrupt on input capture event These operating modes are determined by setting the appropriate bits in the ICxCON register (where x = 1,2,...,N). The dsPIC devices contain up to 8 capture channels, i.e., the maximum value of N is 8. * Frequency/Period/Pulse Measurements * Additional sources of External Interrupts FIGURE 12-1: INPUT CAPTURE MODE BLOCK DIAGRAM From GP Timer Module T3_CNT T2_CNT 16 ICx Pin 16 ICTMR 1 Prescaler 1, 4, 16 3 Edge Detection Logic Clock Synchronizer 0 FIFO R/W Logic ICM<2:0> Mode Select ICxBUF ICBNE, ICOV ICI<1:0> Interrupt Logic ICxCON Data Bus Note 1: 12.1 Set Flag ICxIF Where `x' is shown, reference is made to the registers or bits associated to the respective input capture channels 1 through N. Simple Capture Event Mode The simple capture events in the dsPIC30F product family are: * * * * * Capture every falling edge Capture every rising edge Capture every 4th rising edge Capture every 16th rising edge Capture every rising and falling edge 12.1.1 CAPTURE PRESCALER There are four input capture prescaler settings, specified by bits ICM<2:0> (ICxCON<2:0>). Whenever the capture channel is turned off, the prescaler counter will be cleared. In addition, any RESET will clear the prescaler counter. These simple Input Capture modes are configured by setting the appropriate bits ICM<2:0> (ICxCON<2:0>). 2002 Microchip Technology Inc. Advance Information DS70082A-page 81 dsPIC30F 12.1.2 CAPTURE BUFFER OPERATION Each capture channel has an associated FIFO buffer, which is four 16-bit words deep. There are two status flags, which provide status on the FIFO buffer: * ICBFNE - Input Capture Buffer Not Empty * ICOV - Input Capture Overflow The ICBFNE will be set on the first input capture event and remain set until all capture events have been read from the FIFO. As each word is read from the FIFO, the remaining words are advanced by one position within the buffer. In the event that the FIFO is full with four capture events and a fifth capture event occurs prior to a read of the FIFO, an overflow condition will occur and the ICOV bit will be set to a logic 1. The fifth capture event is lost and is not stored in the FIFO. No additional events will be captured till all four events have been read from the buffer. If a FIFO read is performed after the last read and no new capture event has been received, the read will yield indeterminate results. 12.1.3 TIMER2 AND TIMER3 SELECTION MODE The input capture module consists of up to 8 input capture channels. Each channel can select between one of two timers for the time-base, Timer2 or Timer3. Selection of the timer resource is accomplished through SFR bit ICTMR (ICxCON<7>). Timer3 is the default timer resource available for the input capture module. 12.1.4 HALL SENSOR MODE When the input capture module is set for capture on every edge, rising and falling, ICM<2:0> = 001, the following operations are performed by the input capture logic: * The input capture interrupt flag is set on every edge, rising and falling. * The interrupt on Capture mode setting bits, ICI<1:0>, is ignored, since every capture generates an interrupt. * A capture overflow condition is not generated in this mode. 12.2 Input Capture Operation During SLEEP and IDLE Modes An input capture event will generate a device wake-up or interrupt, if enabled, if the device is in CPU IDLE or SLEEP mode. Independent of the timer being enabled, the input capture module will wake-up from the CPU SLEEP or IDLE mode when a capture event occurs, if ICM<2:0> = 111 and the interrupt enable bit is asserted. The same wake-up can generate an interrupt, if the conditions for processing the interrupt have been satisfied. The wake-up feature is useful as a method of adding extra external pin interrupts. 12.2.1 INPUT CAPTURE IN CPU SLEEP MODE CPU SLEEP mode allows input capture module operation with reduced functionality. In the CPU SLEEP mode, the ICI<1:0> bits are not applicable, and the input capture module can only function as an external interrupt source. The capture module must be configured for interrupt only on the rising edge (ICM<2:0> = 111), in order for the input capture module to be used while the device is in SLEEP mode. The prescale settings of 4:1 or 16:1 are not applicable in this mode. 12.2.2 INPUT CAPTURE IN CPU IDLE MODE CPU IDLE mode allows input capture module operation with full functionality. In the CPU IDLE mode, the interrupt mode selected by the ICI<1:0> bits are applicable, as well as the 4:1 and 16:1 capture prescale settings, which are defined by control bits ICM<2:0>. This mode requires the selected timer to be enabled. Moreover, the ICSIDL bit must be asserted to a logic `0'. If the input capture module is defined as ICM<2:0> = 111 in CPU IDLE mode, the input capture pin will serve only as an external interrupt pin. 12.3 Input Capture Interrupts The input capture channels have the ability to generate an interrupt, based upon the selected number of capture events. The selection number is set by control bits ICI<1:0> (ICxCON<6:5>). Each channel provides an interrupt flag (ICxIF) bit. The respective capture channel interrupt flag is located in the corresponding IFSx Status register. Enabling an interrupt is accomplished via the respective capture channel interrupt enable (ICxIE) bit. The capture interrupt enable bit is located in the corresponding IEC Control register. DS70082A-page 82 Advance Information 2002 Microchip Technology Inc. 2002 Microchip Technology Inc. 0144 0146 0148 014A 014C 014E 0150 0152 0154 IC2BUF IC2CON IC3BUF IC3CON IC4BUF IC4CON IC5BUF IC5CON IC6BUF 015E IC8BUF IC8CON -- -- -- -- -- -- -- -- Bit 15 -- -- -- -- -- -- -- -- Bit 14 ICSIDL ICSIDL ICSIDL ICSIDL ICSIDL ICSIDL ICSIDL ICSIDL Bit 13 -- -- -- -- -- -- -- -- Bit 12 -- -- -- -- -- -- -- -- Bit 11 INPUT CAPTURE REGISTER MAP u = uninitialized bit 015C IC7CON Legend: 0158 015A IC7BUF 0156 0142 IC1CON IC6CON 0140 IC1BUF SFR Name Addr. TABLE 12-1: -- -- -- -- -- -- -- -- Bit 10 Bit 8 Bit 7 -- ICTMR -- ICTMR -- ICTMR -- ICTMR -- ICTMR -- ICTMR -- ICTMR -- -- ICTMR Input 8 Capture Register -- Input 7 Capture Register -- Input 6 Capture Register -- Input 5 Capture Register -- Input 4 Capture Register -- Input 3 Capture Register -- Input 2 Capture Register -- Input 1 Capture Register Bit 9 Bit 5 ICI<1:0> ICI<1:0> ICI<1:0> ICI<1:0> ICI<1:0> ICI<1:0> ICI<1:0> ICI<1:0> Bit 6 ICOV ICOV ICOV ICOV ICOV ICOV ICOV ICOV Bit 4 ICBNE ICBNE ICBNE ICBNE ICBNE ICBNE ICBNE ICBNE Bit 3 Bit 2 ICM<2:0> ICM<2:0> ICM<2:0> ICM<2:0> ICM<2:0> ICM<2:0> ICM<2:0> ICM<2:0> Bit 1 Bit 0 RESET State 0000 0000 0000 0000 uuuu uuuu uuuu uuuu 0000 0000 0000 0000 uuuu uuuu uuuu uuuu 0000 0000 0000 0000 uuuu uuuu uuuu uuuu 0000 0000 0000 0000 uuuu uuuu uuuu uuuu 0000 0000 0000 0000 uuuu uuuu uuuu uuuu 0000 0000 0000 0000 uuuu uuuu uuuu uuuu 0000 0000 0000 0000 uuuu uuuu uuuu uuuu 0000 0000 0000 0000 uuuu uuuu uuuu uuuu dsPIC30F Advance Information DS70082A-page 83 dsPIC30F NOTES: DS70082A-page 84 Advance Information 2002 Microchip Technology Inc. dsPIC30F 13.0 OUTPUT COMPARE MODULE The key operational features of the Output Compare module include: This section describes the Output Compare module and associated Operational modes. The features provided by this module are useful in applications requiring Operational modes such as: * Generation of Variable Width Output Pulses * Power Factor Correction Figure 13-1 depicts a block diagram of the Output Compare module. * * * * * * Timer2 and Timer3 Selection mode Simple Output Compare Match mode Dual Output Compare Match mode Simple PWM mode Output Compare during SLEEP and IDLE modes Interrupt on Output Compare/PWM Event These operating modes are determined by setting the appropriate bits in the 16-bit OCxCON SFR (where x = 1,2,3,...,N). The dsPIC devices contain up to 8 compare channels, i.e., the maximum value of N is 8. OCxRS and OCxR in the figure represent the dual compare registers. In the Dual Compare mode, the OCxR register is used for the first compare and OCxRS is used for the second compare. FIGURE 13-1: OUTPUT COMPARE MODE BLOCK DIAGRAM Set Flag bit OCxIF OCxRS Output Logic OCxR 3 OCM<2:0> Mode Select Comparator S Q R OCx Output Enable OCFA (for x = 1, 2, 3 or 4) 0 1 OCTSEL 0 1 or OCFB (for x = 5, 6, 7 or 8) From GP Timer Module TMR2<15:0 Note: TMR3<15:0> T2P2_MATCH T3P3_MATCH Where `x' is shown, reference is made to the registers associated with the respective output compare channels 1 through N. 2002 Microchip Technology Inc. Advance Information DS70082A-page 85 dsPIC30F 13.1 Timer2 and Timer3 Selection Mode Each output compare channel can select between one of two 16-bit timers, Timer2 or Timer3. The selection of the timers is controlled by the OCTSEL bit (OCxCON<3>). Timer2 is the default timer resource for the Output Compare module. 13.2 Simple Output Compare Match Mode When control bits OCM<2:0> (OCxCON<2:0>) = 001, 010 or 011, the selected output compare channel is configured for one of three simple Output Compare Match modes: * Compare forces I/O pin low * Compare forces I/O pin high * Compare toggles I/O pin Dual Output Compare Match Mode When control bits OCM<2:0> (OCxCON<2:0>) = 100 or 101, the selected output compare channel is configured for one of two Dual Output Compare modes, which are: 13.3.1 * Determine instruction cycle time TCY. * Calculate desired pulse value based on TCY. * Calculate timer to start pulse width from timer start value of 0x0000. * Write pulse width start and stop times into OCxR and OCxRS (x denotes channel 1, 2, ...,N) compare registers, respectively. * Set timer period register to value equal to, or greater than, value in OCxRS compare register. * Set OCM<2:0> = 101. * Enable timer, TON (TxCON<15>) = 1. The user must perform the following steps in order to configure the output compare module for PWM operation: 1. 3. SINGLE PULSE MODE For the user to configure the module for the generation of a single output pulse, the following steps are required (assuming timer is off): * Determine instruction cycle time TCY. * Calculate desired pulse width value based on TCY. * Calculate time to start pulse from timer start value of 0x0000. * Write pulse width start and stop times into OCxR and OCxRS compare registers (x denotes channel 1, 2, ...,N). * Set timer period register to value equal to, or greater than, value in OCxRS compare register. * Set OCM<2:0> = 100. * Enable timer, TON (TxCON<15>) = 1. To initiate another single pulse, issue another write to set OCM<2:0> = 100. DS70082A-page 86 Simple PWM Mode When control bits OCM<2:0> (OCxCON<2:0>) = 110 or 111, the selected output compare channel is configured for the PWM mode of operation. When configured for the PWM mode of operation, OCxR is the Main latch (read only) and OCxRS is the Secondary latch. This enables glitchless PWM transitions. 2. * Single Output Pulse mode * Continuous Output Pulse mode CONTINUOUS PULSE MODE For the user to configure the module for the generation of a continuous stream of output pulses, the following steps are required: 13.4 The OCxR register is used in these modes. The OCxR register is loaded with a value and is compared to the selected incrementing timer count. When a compare occurs, one of these Compare Match modes occurs. If the counter resets to zero before reaching the value in OCxR, the state of the OCx pin remains unchanged. 13.3 13.3.2 4. Set the PWM period by writing to the appropriate period register. Set the PWM duty cycle by writing to the OCxRS register. Configure the output compare module for PWM operation. Set the TMRx prescale value and enable the Timer, TON (TxCON<15>) = 1. 13.4.1 INPUT PIN FAULT PROTECTION FOR PWM When control bits OCM<2:0> (OCxCON<2:0>) = 111, the selected output compare channel is again configured for the PWM mode of operation, with the additional feature of input fault protection. While in this mode, if a logic 0 is detected on the OCFA/B pin, the respective PWM output pin is placed in the high impedance input state. The OCFLT bit (OCxCON<4>) indicates whether a FAULT condition has occurred. This state will be maintained until: * The external FAULT condition has been removed and * The PWM mode is re-enabled by writing to the appropriate control bits. Advance Information 2002 Microchip Technology Inc. dsPIC30F 13.4.2 PWM PERIOD The PWM period is specified by writing to the PRx register. The PWM period can be calculated using the following formula. EQUATION 13-1: PWM period = [(PRx) + 1] * 4 * TOSC * (TMRx prescale value) PWM frequency is defined as 1 / [PWM period]. When the selected TMRx is equal to its respective period register, PRx, the following four events occur on the next increment cycle: * TMRx is cleared. * The OCx pin is set. - Exception 1: If PWM duty cycle is 0x0000, the OCx pin will remain low. - Exception 2: If duty cycle is greater than PRx, the pin will remain high. * The PWM duty cycle is latched from OCxRS into OCxR. * The corresponding timer interrupt flag is set. See Figure 13-2 for key PWM period comparisons. Timer3 is referred to in the figure for clarity. FIGURE 13-2: PWM OUTPUT TIMING Period Duty Cycle TMR3 = PR3 T3IF = 1 (Interrupt Flag) OCxR = OCxRS 13.5 TMR3 = PR3 T3IF = 1 (Interrupt Flag) OCxR = OCxRS TMR3 = Duty Cycle (OCxR) TMR3 = Duty Cycle (OCxR) Output Compare Operation During CPU SLEEP Mode When the CPU enters the SLEEP mode, all internal clocks are stopped. Therefore, when the CPU enters the SLEEP state, the output compare channel will drive the pin to the active state that was observed prior to entering the CPU SLEEP state. For example, if the pin was high when the CPU entered the SLEEP state, the pin will remain high. Likewise, if the pin was low when the CPU entered the SLEEP state, the pin will remain low. In either case, the output compare module will resume operation when the device wakes up. 13.6 Output Compare Operation During CPU IDLE Mode When the CPU enters the IDLE mode, the output compare module can operate with full functionality. The output compare channel will operate during the CPU IDLE mode if the OCSIDL bit (OCxCON<13>) is at logic 0 and the selected time-base (Timer2 or Timer3) is enabled and the TSIDL bit of the selected timer is set to logic 0. 2002 Microchip Technology Inc. The selected time-base for the output compare can be configured for: * Internal Instruction Cycle * External Synchronous 13.7 Output Compare Interrupts The output compare channels have the ability to generate an interrupt on a compare match, for whichever Match mode has been selected. For all modes except the PWM mode, when a compare event occurs, the respective interrupt flag (OCxIF) bit is asserted and an interrupt will be generated, if enabled. The OCxIF bit is located in the corresponding IFS Status register, and must be cleared in software. The interrupt is enabled via the respective compare interrupt enable (OCxIE) bit, located in the corresponding IEC Control register. For the PWM mode, when an event occurs, the respective timer interrupt flag (T2IF or T3IF) is asserted and an interrupt will be generated, if enabled. The IF bit is located in the IFS0 Status register, and must be cleared in software. The interrupt is enabled via the respective timer interrupt enable bit (T2IE or T3IE), located in the IEC0 Control register. The output compare interrupt flag is never set during the PWM mode of operation. Advance Information DS70082A-page 87 0184 0186 0188 018A 018C 018E 0190 0192 0194 0196 0198 019A 019C 019E 01A0 01A2 01A4 01A6 01A8 01AA 01AC OC2RS OC2R OC2CON OC3RS OC3R OC3CON DS70082A-page 88 OC4RS OC4R OC4CON OC5RS OC5R OC5CON OC6RS OC6R OC6CON OC7RS OC7R OC7CON OC8RS OC8R Advance Information OC8CON 01AE -- Legend: u = uninitialized bit -- -- -- -- -- -- -- 0182 -- -- -- -- -- -- -- -- OCSIDL OCSIDL OCSIDL OCSIDL OCSIDL OCSIDL OCSIDL OCSIDL -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 10 OC1CON Bit 11 OC1R Bit 12 0180 Bit 13 Bit 15 Addr. SFR Name OC1RS Bit 14 OUTPUT COMPARE REGISTER MAP TABLE 13-1: Bit 8 Bit 7 Bit 6 -- -- -- Output Compare 1 Main Register -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Output Compare 8 Main Register Output Compare 8 Secondary Register -- Output Compare 7 Main Register Output Compare 7 Secondary Register -- Output Compare 6 Main Register Output Compare 6 Secondary Register -- Output Compare 5 Main Register Output Compare 5 Secondary Register -- Output Compare 4 Main Register Output Compare 4 Secondary Register -- Output Compare 3 Main Register Output Compare 3 Secondary Register -- Output Compare 2 Main Register Output Compare 2 Secondary Register -- -- -- -- -- -- -- -- -- Bit 5 Output Compare 1 Secondary Register Bit 9 OCFLT OCFLT OCFLT OCFLT OCFLT OCFLT OCFLT OCFLT Bit 4 OCTSEL OCTSEL OCTSEL OCTSEL OCTSEL OCTSEL OCTSE OCTSEL Bit 3 Bit 2 OCM<2:0> OCM<2:0> OCM<2:0> OCM<2:0> OCM<2:0> OCM<2:0> OCM<2:0> OCM<2:0> Bit 1 Bit 0 RESET State 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 dsPIC30F 2002 Microchip Technology Inc. dsPIC30F 14.0 QUADRATURE ENCODER INTERFACE (QEI) MODULE * Three input channels for two phase signals and index pulse * 16-bit up/down position counter * Count direction status * Position Measurement (x2 and x4) mode * Programmable digital noise filters on inputs * Alternate 16-bit Timer/Counter mode * Quadrature Encoder Interface interrupts This section describes the Quadrature Encoder Interface (QEI) module and associated Operational modes. The QEI module provides the interface to incremental encoders for obtaining motor positioning data. Incremental encoders are very useful in motor control applications. The Quadrature Encoder Interface (QEI) is a key feature requirement for several motor control applications, such as Switched Reluctance (SR) and AC Induction Motor (ACIM). The operational features of the QEI are, but not limited to: FIGURE 14-1: These Operating modes are determined by setting the appropriate bits QEIM<2:0> (QEICON<10:8>). Figure 14-1 depicts the Quadrature Encoder Interface block diagram. QUADRATURE ENCODER INTERFACE BLOCK DIAGRAM TQCKPS<1:0> SLEEP Input TQCS TCY Synchronize Det 2 0 Prescaler 1, 8, 64, 256 1 1 QEIM<2:0> 0 TQGATE QEA Programmable Digital Filter UPDN_CNT 0 QEICON<11> 2 Quadrature Encoder Interface Logic QEB Programmable Digital Filter INDX Programmable Digital Filter Q CK Q QEIIF Event Flag 16-bit Up/Down Counter (POSCNT) RESET Comparator/ Zero Detect Equal 3 QEIM<2:0> Mode Select 1 D Max Count Register (MAXCNT) 3 PCDOUT Existing Pin Logic 0 UPDN 1 2002 Microchip Technology Inc. Up/Down Advance Information DS70082A-page 89 dsPIC30F 14.1 Quadrature Encoder Interface Logic A typical incremental (a.k.a. optical) encoder has three outputs: Phase A, Phase B, and an index pulse. These signals are useful and often required in position and speed control of ACIM and SR motors. The two channels, Phase A (QEA) and Phase B (QEB), have a unique relationship. If Phase A leads Phase B, then the direction (of the motor) is deemed positive or forward. If Phase A lags Phase B, then the direction (of the motor) is deemed negative or reverse. A third channel, termed index pulse, occurs once per revolution and is used as a reference to establish an absolute position. The index pulse coincides with Phase A and Phase B, both low. 14.2 16-bit Up/Down Position Counter Mode The 16-bit Up/Down Counter counts up or down on every count pulse, which is generated by the difference of the Phase A and Phase B input signals. The counter acts as an integrator, whose count value is proportional to position. The direction of the count is determined by the UPDN signal, which is generated by the Quadrature Encoder Interface Logic. 14.2.1 POSITION COUNTER ERROR CHECKING Position count error checking in the QEI is provided for and indicated by the CNTERR bit (QEICON<15>). The error checking only applies when the position counter is configured for RESET on the Index Pulse modes (QEIM<2:0> = `110' or `100'). In these modes, the contents of the POSCNT register is compared with the values (0xFFFF or MAXCNT depending on direction). If these values are detected, an error condition is generated by setting the CNTERR bit and a QEI count error interrupt is generated. The position counter continues to count encoder edges after an error has been detected. The POSCNT register continues to count up/ down until a natural rollover/underflow. No interrupt is generated for the natural rollover/underflow event. The CNTERR bit is a read/write bit and reset in software by the user. 14.2.2 POSITION COUNTER RESET The position counter RESET enable bit, POSRES (QEI<2>) controls whether the position counter is reset when the index pulse is detected. This bit is only applicable when QEIM<2:0> = `100' or `110'. The interrupt is still generated on the detection of the index pulse and not on the position counter overflow/ underflow. 14.2.3 COUNT DIRECTION STATUS As mentioned in the previous section, the QEI logic generates an UPDN signal, based upon the relationship between Phase A and Phase B. In addition to the output pin, the state of this internal UPDN signal is supplied to a SFR bit UPDN (QEICON<11>) as a read only bit. To place the state of this signal on an I/O pin, the SFR bit PCDOUT (QEICON<6>) must be 1. 14.3 Position Measurement Mode There are two Measurement modes which are supported and are termed x2 and x4. These modes are selected by the QEIM<2:0> mode select bits located in SFR QEICON<10:8>. When control bits QEIM<2:0> = 100 or 101, the x2 Measurement mode is selected and the QEI logic only looks at the Phase A input for the position counter increment rate. Every rising and falling edge of the Phase A signal causes the position counter to be incremented or decremented. The Phase B signal is still utilized for the determination of the counter direction, just as in the x4 mode. Within the x2 Measurement mode, there are two variations of how the position counter is reset: 1. 2. Position counter reset by detection of index pulse, QEIM<2:0> = 100. Position counter reset by match with MAXCNT, QEIM<2:0> = 101. When control bits QEIM<2:0> = 110 or 111, the x4 Measurement mode is selected and the QEI logic looks at both edges of the Phase A and Phase B input signals. Every edge of both signals causes the position counter to increment or decrement. Within the x4 Measurement mode, there are two variations of how the position counter is reset: 1. 2. Position counter reset by detection of index pulse, QEIM<2:0> = 110. Position counter reset by match with MAXCNT, QEIM<2:0> = 111. The x4 Measurement mode provides for finer resolution data (more position counts) for determining motor position. If the POSRES bit is set to `1', then the position counter is reset when the index pulse is detected. If the POSRES bit is set to `0', then the position counter is not reset when the index pulse is detected. The position counter will continue counting up or down, and will be reset on the rollover or underflow condition. DS70082A-page 90 Advance Information 2002 Microchip Technology Inc. dsPIC30F 14.4 Programmable Digital Noise Filters The digital noise filter section is responsible for rejecting noise on the incoming capture or quadrature signals. Schmitt Trigger inputs and a three-clock cycle delay filter combine to reject low level noise and large, short duration noise spikes that typically occur in noise prone applications, such as a motor system. In addition, control bit UPDN_CNT (QEICON<0>) determines whether the timer count direction state is based on the logic state, written into the UPDN control/ status bit (QEICON<11>), or the QEB pin state. When UPDN_CNT = 1, the timer count direction is controlled from the QEB pin. Likewise, when UPDN_CNT = 0, the timer count direction is controlled by the UPDN bit. Note: This Timer does not support the External Asynchronous Counter mode of operation. If using an external clock source, the clock will automatically be synchronized to the internal instruction cycle. The filter ensures that the filtered output signal is not permitted to change until a stable value has been registered for three consecutive clock cycles. QEA and QEB is programmed by bits QECK<2:0> (DFLTCON<6:4>) and is derived from the base instruction cycle TCY. For the index channel the clock divide frequency for the digital filter is programmed by bits INDCK<2:0> (DFLTCON<2:0>), and is also derived from the base instruction cycle TCY. 14.6 QEI Module Operation During CPU SLEEP Mode 14.6.1 QEI OPERATION DURING CPU SLEEP MODE To enable the filter output for channels QEA and QEB, the QEOUT bit must be 1. To enable the filter output for the index channel, the INDOUT bit must be 1. The filter network for all channels is disabled on POR and BOR Reset. The QEI module will be halted during the CPU SLEEP mode. 14.5 During CPU SLEEP mode, the timer will not operate, because the internal clocks are disabled. Alternate 16-bit Timer/Counter When the QEI module is not configured for the QEI mode QEIM<2:0> = 001, the module can be configured for a simple 16-bit timer/counter. The setup and control for the auxiliary timer is accomplished through the QEICON SFR register. This timer functions identical to Timer1. The QEA pin is used as the timer clock input. When configured as a timer, the POSCNT register serves as the Timer Count Register and the MAXCNT register serves as the Period Register. When a timer/ period register match occur, the QEI interrupt flag will be asserted. The only exception between the general purpose timers and this timer is the added feature of external up_down input select. When the UPDN pin is asserted high, the timer will increment up. When the UPDN pin is asserted low, the timer will be decremented. Note: 14.6.2 14.7 TIMER OPERATION DURING CPU SLEEP MODE QEI Module Operation During CPU IDLE Mode Since the QEI module can function as a quadrature encoder interface, or as a 16-bit timer, the following section describes operation of the module in both modes. 14.7.1 QEI OPERATION DURING CPU IDLE MODE When the CPU is placed in the IDLE mode, the QEI module will operate if the QEISIDL bit (QEICON<13>) = 0. This bit defaults to a logic `0' upon executing POR and BOR. For halting the QEI module during the CPU IDLE mode, QEISIDL should be set to `1'. Changing the Operational mode, i.e., from QEI to Timer or vice versa, will not affect the Timer/Position Count Register contents. The UPDN control/status bit (QEICON<11>) can be used to select the count direction state of the Timer register. When UPDN = 1, the timer will count up. When UPDN = 0, the timer will count down. 2002 Microchip Technology Inc. Advance Information DS70082A-page 91 dsPIC30F 14.7.2 TIMER OPERATION DURING CPU IDLE MODE When the CPU is placed in the IDLE mode and the QEI module is configured in the 16-bit Timer mode, the 16-bit timer will operate if the QEISIDL bit (QEICON<13>) = 0. This bit defaults to a logic `0' upon executing POR and BOR. For halting the timer module during the CPU IDLE mode, QEISIDL should be set to 1. If the QEISIDL bit is cleared, the timer will function normally, as if the CPU IDLE mode had not been entered. 14.8 Quadrature Encoder Interface Interrupts The quadrature encoder interface has the ability to generate an interrupt on occurrence of the following events: * Interrupt on 16-bit up/down position counter rollover/underflow * Detection of qualified index pulse, or if CNTERR bit is set * Timer period match event (overflow/underflow) * Gate accumulation event The QEI interrupt flag bit, QEIIF, is asserted upon occurrence of any of the above events. The QEIIF bit must be cleared in software. QEIIF is located in the IFS2 Status register. Enabling an interrupt is accomplished via the respective enable bit, QEIIE. The QEIIE bit is located in the IEC2 Control register. DS70082A-page 92 Advance Information 2002 Microchip Technology Inc. Bit 6 -- CNTERR -- -- -- QEISIDL -- INDX -- UPDN Bit 5 Bit 4 Bit 3 Bit 2 -- -- -- QEOUT QECK2 QECK1 QECK0 INDOUT TQCS Bit 1 INDCK2 INDCK1 QEIM2 QEIM1 QEIM0 SWPAB PCDOUT TQGATE TQCKPS1 TQCKPS0 POSRES Maximun Count<15:0> Bit 7 MAXCNT 0128 Legend: u = uninitialized bit Bit 8 Position Counter<15:0> Bit 9 0126 Bit 10 POSCNT Bit 11 0124 Bit 12 0122 Bit 13 DFLTCON Bit 14 QEICON Bit 15 Addr. QEI REGISTER MAP SFR Name TABLE 14-1: RESET State INDCK0 1111 1111 1111 1111 0000 0000 0000 0000 0000 0000 0000 0000 UPDN_CNT 0000 0000 0000 0000 Bit 0 dsPIC30F 2002 Microchip Technology Inc. Advance Information DS70082A-page 93 dsPIC30F NOTES: DS70082A-page 94 Advance Information 2002 Microchip Technology Inc. dsPIC30F 15.0 MOTOR CONTROL PWM MODULE This module contains 4 duty cycle generators, numbered 1 through 4. The module has 8 PWM output pins, numbered PWM1H/PWM1L through PWM4H/PWM4L. The eight I/O pins are grouped into High/Low numbered pairs, denoted by the suffix H or L, respectively. For complementary loads, the low PWM pins are always the complement of the corresponding High I/O pin. This module simplifies the task of generating multiple, synchronized Pulse Width Modulated (PWM) outputs. In particular, the following power and motion control applications are supported by the PWM module: * * * * Three Phase AC Induction Motor Switched Reluctance (SR) Motor Brushless DC (BLDC) Motor Uninterruptible Power Supply (UPS) There are two versions of the PWM module depending on the particular dsPIC30F device selected. There is an 8-output module in some devices and a 6-output PWM module in others. The PWM module has the following features: Simplified block diagrams of the 8-output and 6-output Motor Control PWM modules are shown in Figure 15-1 and Figure 15-2 , respectively. * * * * * * 8 PWM I/O pins with 4 duty cycle generators Up to 16-bit resolution `On-the-Fly' PWM frequency changes Edge and Center Aligned Output modes Single Pulse Generation mode Interrupt support for asymmetrical updates in Center Aligned mode * Output override control for Electrically Commutative Motor (ECM) operation * `Special Event' comparator for scheduling other peripheral events * FAULT pins to optionally drive each of the PWM I/ O pins to a defined state TABLE 15-1: FEATURE SUMMARY: 6-OUTPUT PWM VS. 8-OUTPUT PWM Feature I/O Pins PWM Generators FAULT Input Pins Dead-Time Generators 2002 Microchip Technology Inc. 6-Output PWM Module 8-Output PWM Module 6 3 1 1 8 4 2 2 Advance Information DS70082A-page 95 dsPIC30F FIGURE 15-1: 8-OUTPUT PWM MODULE BLOCK DIAGRAM PWMCON1 PWM Enable and Mode SFRs PWMCON2 DTCON1 Dead-Time Control SFRs DTCON2 FLTACON FAULT Pin Control SFRs FLTBCON OVDCON PWM Manual Control SFR PWM Generator #4 16-bit Data Bus PDC4 Buffer PDC4 Comparator PWM Generator #3 PTMR PWM4H Channel 4 Dead-Time Generator and Override Logic Channel 3 Dead-Time Generator and Override Logic Comparator PWM4L PWM3H Output Driver PWM3L Block PWM Generator #2 Channel 2 Dead-Time Generator and Override Logic PTPER PWM Generator #1 Channel 1 Dead-Time Generator and Override Logic PTPER Buffer PWM2H PWM2L PWM1H PWM1L FLTA PTCON FLTB Comparator SEVTDIR SEVTCMP Special Event Postscaler Special Event Trigger PTDIR PWM Time-Base Note: Details of PWM Generator #1, #2, and #3 not shown for clarity. DS70082A-page 96 Advance Information 2002 Microchip Technology Inc. dsPIC30F FIGURE 15-2: 6-OUTPUT PWM BLOCK DIAGRAM PWMCON1 PWM Enable and Mode SFRs PWMCON2 DTCON1 Dead-Time Control SFR FLTACON FAULT Pin Control SFR OVDCON PWM Manual Control SFR PWM Generator #3 16-bit Data Bus PDC3 Buffer PDC3 Comparator PWM Generator #2 PTMR PWM3H Channel 3 Dead-Time Generator and Override Logic Channel 2 Dead-Time Generator and Override Logic PWM3L Output Driver Block PWM2H PWM2L Comparator PWM Generator #1 PTPER Channel 1 Dead-Time Generator and Override Logic PWM1H PWM1L FLTA PTPER Buffer PTCON Comparator SEVTDIR SEVTCMP Special Event Postscaler Special Event Trigger PTDIR PWM Time-Base Note: Details of PWM Generator #1 and #2 not shown for clarity. 2002 Microchip Technology Inc. Advance Information DS70082A-page 97 dsPIC30F The PWM module allows several modes of operation, which are beneficial for specific power control applications. Each mode of operation is described subsequently. 15.1 PWM Time-Base The PWM time-base is provided by a 15-bit timer with a prescaler and postscaler. The time-base is accessible via the PTMR SFR. PTMR<15> is a read only status bit, PTDIR, that indicates the present count direction of the PWM time-base. If PTDIR is cleared, PTMR is counting upwards, whereas PTDIR set, indicates that PTMR is counting downwards. The PWM time-base is configured via the PTCON SFR. The timebase is enabled/disabled by setting/clearing the PTEN bit in the PTCON SFR. PTMR is not cleared when the PTEN bit is cleared in software. The PTPER SFR sets the counting period for PTMR. The user must write a 15-bit value to PTPER<14:0>. When the value in PTMR<14:0> matches the value in PTPER<14:0>, the time-base will either reset to 0, or reverse the count direction on the next occurring clock cycle. The action taken depends on the Operating mode of the time-base. Note: If the period register is set to 0x0000, the timer will stop counting, and the interrupt and the special event trigger will not be generated, even if the special event value is also 0x0000. The module will not update the period register, if it is already at 0x0000; therefore, the user must disable the module in order to update the period register. The PWM time-base can be configured for four different modes of operation: * * * * Free Running mode Single Shot mode Continuous Up/Down Count mode Continuous Up/Down Count mode with interrupts for double updates These four modes are selected by the PTMOD<1:0> bits in the PTCON SFR. The Up/Down Counting modes support center aligned PWM generation. The Single Shot mode allows the PWM module to support pulse control of certain Electronically Commutative Motors (ECMs). 15.1.1 FREE RUNNING MODE In the Free Running mode, the PWM time-base counts upwards until the value in the time-base period register (PTPER) is matched. The PTMR register is reset on the following input clock edge and the time-base will continue to count upwards as long as the PTEN bit remains set. When the PWM time-base is in the Free Running mode (PTMOD<1:0> = 00), an interrupt event is generated each time a match with the PTPER register occurs and the PTMR register is reset to zero. The postscaler selection bits may be used in this mode of the timer to reduce the frequency of the interrupt events. 15.1.2 SINGLE SHOT MODE In the Single Shot Counting mode, the PWM time-base begins counting upwards when the PTEN bit is set. When the value in the PTMR register matches the PTPER register, the PTMR register will be reset on the following input clock edge and the PTEN bit will be cleared by the hardware to halt the time-base. When the PWM time-base is in the Single Shot mode (PTMOD<1:0> = 01), an interrupt event is generated when a match with the PTPER register occurs, the PTMR register is reset to zero on the following input clock edge, and the PTEN bit is cleared. The postscaler selection bits have no effect in this mode of the timer. 15.1.3 CONTINUOUS UP/DOWN COUNTING MODES In the Continuous Up/Down Counting modes, the PWM time-base counts upwards until the value in the PTPER register is matched. The timer will begin counting downwards on the following input clock edge. The PTDIR bit in the PTCON SFR is read only and indicates the counting direction The PTDIR bit is set when the timer counts downwards. In the Up/Down Counting mode (PTMOD<1:0> = 10), an interrupt event is generated each time the value of the PTMR register becomes zero and the PWM timebase begins to count upwards. The postscaler selection bits may be used in this mode of the timer to reduce the frequency of the interrupt events. The interrupt signals generated by the PWM time-base depend on the mode selection bits (PTMOD<1:0>) and the postscaler bits (PTOPS<3:0>) in the PTCON SFR. DS70082A-page 98 Advance Information 2002 Microchip Technology Inc. dsPIC30F 15.1.4 DOUBLE UPDATE MODE In the Double Update mode (PTMOD<1:0> = 11), an interrupt event is generated each time the PTMR register is equal to zero, as well as each time a period match occurs. The postscaler selection bits have no effect in this mode of the timer. The Double Update mode provides two additional functions to the user. First, the control loop bandwidth is doubled because the PWM duty cycles can be updated, twice per period. Secondly, asymmetrical center aligned PWM waveforms can be generated, which are useful for minimizing output waveform distortion in certain motor control applications. Note: 15.1.5 Programming a value of 0x0001 in the period register could generate a continuous interrupt pulse, and hence, must be avoided. EQUATION 15-1: TPWM = * a write to the PTMR register * a write to the PTCON register * any device RESET The PTMR register is not cleared when PTCON is written. PWM TIME-BASE POSTSCALER The match output of PTMR can optionally be postscaled through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling) to generate an interrupt. The postscaler counter is cleared when any of the following occurs: * a write to the PTMR register * a write to the PTCON register * any device RESET PWM PERIOD TCY * (PTPER + 1) (PTMR Prescale Value) If the PWM time-base is configured for one of the Up/ Down Count modes, the PWM period will be twice the value provided by Equation 15-1. The maximum resolution (in bits) for a given device oscillator and PWM frequency can be determined from the following formula: EQUATION 15-2: PWM RESOLUTION log (2 * TPWM / TCY) Resolution = PWM TIME-BASE PRESCALER The input clock to PTMR (FOSC/4), has prescaler options of 1:1, 1:4, 1:16, or 1:64, selected by control bits PTCKPS<1:0> in the PTCON SFR. The prescaler counter is cleared when any of the following occurs: 15.1.6 The PWM period can be determined from the following formula: log (2) 15.3 Edge Aligned PWM Edge aligned PWM signals are produced by the module when the PWM time-base is in the Free Running or Single Shot mode. For edge aligned PWM outputs, the output for a given PWM channel has a period specified by the value loaded in PTPER and a duty cycle specified by the appropriate duty cycle register (see Figure 15-3). The PWM output is driven active at the beginning of the period (PTMR = 0) and is driven inactive, when the value in the duty cycle register matches PTMR. If the value in a particular duty cycle register is zero, then the output on the corresponding PWM pin will be inactive for the entire PWM period. In addition, the output on the PWM pin will be active for the entire PWM period if the value in the duty cycle register is greater than the value held in the PTPER register. FIGURE 15-3: EDGE ALIGNED PWM New Duty Cycle Latched The PTMR register is not cleared when PTCON is written. 15.2 PTPER PWM Period PTMR Value PTPER is a 15-bit register and is used to set the counting period for the PWM time-base. PTPER is a double buffered register. The PTPER buffer contents are loaded into the PTPER register at the following instants: * Free Running and Single Shot modes: When the PTMR register is reset to zero after a match with the PTPER register. * Up/Down Counting modes: When the PTMR register is zero. 0 Duty Cycle Period The value held in the PTPER buffer is automatically loaded into the PTPER register, when the PWM time-base is disabled (PTEN = 0). 2002 Microchip Technology Inc. Advance Information DS70082A-page 99 dsPIC30F 15.4 15.5.1 Center Aligned PWM Center aligned PWM signals are produced by the module when the PWM time-base is configured in an Up/Down Counting mode (see Figure 15-4). The PWM compare output is driven to the active state when the value of the duty cycle register matches the value of PTMR and the PWM time-base is counting downwards (PTDIR = 1). The PWM compare output is driven to the inactive state when the PWM time-base is counting upwards (PTDIR = 0) and the value in the PTMR register matches the duty cycle value. If the value in a particular duty cycle register is zero, then the output on the corresponding PWM pin will be inactive for the entire PWM period. In addition, the output on the PWM pin will be active for the entire PWM period if the value in the duty cycle register is equal to the value held in the PTPER register. FIGURE 15-4: CENTER ALIGNED PWM Period/2 PTPER PTMR Value Duty Cycle 0 The four PWM duty cycle registers are double buffered to allow glitchless updates of the PWM outputs. For each duty cycle, there is a duty cycle buffer register that is accessible by the user and a second duty cycle register that holds the actual compare value used in the present PWM period. For edge aligned PWM output, a new duty cycle value will be updated whenever a match with the PTPER register occurs and PTMR is reset. The contents of the duty cycle buffers are automatically loaded into the duty cycle registers when the PWM time-base is disabled (PTEN = 0) and the UDIS bit is cleared in PWMCON2. When the PWM time-base is in the Up/Down Counting mode, new duty cycle values are updated when the value of the PTMR register is zero and the PWM timebase begins to count upwards. The contents of the duty cycle buffers are automatically loaded into the duty cycle registers when the PWM time-base is disabled (PTEN = 0). When the PWM time-base is in the Up/Down Counting mode with double updates, new duty cycle values are updated when the value of the PTMR register is zero, and when the value of the PTMR register matches the value in the PTPER register. The contents of the duty cycle buffers are automatically loaded into the duty cycle registers when the PWM time-base is disabled (PTEN = 0). 15.6 Period 15.5 PWM Duty Cycle Comparison Units There are four 16-bit special function registers used to specify duty cycle values for the PWM module: * * * * PDC1 PDC2 PDC3 PDC4 The value in each duty cycle register determines the amount of time that the PWM output is in the active state. The duty cycle registers are 16-bits wide. The LS bit of a duty cycle register determines whether the PWM edge occurs on Q1 or Q3. Thus, the PWM resolution is effectively doubled. DS70082A-page 100 DUTY CYCLE REGISTER BUFFERS Complementary PWM Operation In the Complementary mode of operation, each pair of PWM outputs is obtained by a complementary PWM signal. A dead-time may be optionally inserted during device switching, when both outputs are inactive for a short period (Refer to Section 15.7). In Complementary mode, the duty cycle comparison units are assigned to the PWM outputs as follows: * * * * PDC1 register controls PWM1H/PWM1L outputs PDC2 register controls PWM2H/PWM2L outputs PDC3 register controls PWM3H/PWM3L outputs PDC4 register controls PWM4H/PWM4L outputs The Complementary mode is selected for each PWM I/O pin pair by clearing the appropriate PMODx bit in the PWMCON1 SFR. The PWM I/O pins are set to Complementary mode by default upon a device RESET. Advance Information 2002 Microchip Technology Inc. dsPIC30F 15.7 15.7.3 Dead-Time Generators Dead-time generation may be provided when any of the PWM I/O pin pairs are operating in the Complementary Output mode. The PWM outputs use PushPull drive circuits. Due to the inability of the power output devices to switch instantaneously, some amount of time must be provided between the turn off event of one PWM output in a complementary pair and the turn on event of the other transistor. The PWM module allows two different dead-times to be programmed. These two dead-times may be used in one of two methods described below to increase user flexibility: * The PWM output signals can be optimized for different turn off times in the high side and low side transistors in a complementary pair of transistors. The first dead-time is inserted between the turn off event of the lower transistor of the complementary pair and the turn on event of the upper transistor. The second dead-time is inserted between the turn off event of the upper transistor and the turn on event of the lower transistor. * The two dead-times can be assigned to individual PWM I/O pin pairs. This Operating mode allows the PWM module to drive different transistor/load combinations with each complementary PWM I/O pin pair. 15.7.1 DEAD-TIME GENERATORS Each complementary output pair for the PWM module has a 6-bit down counter that is used to produce the dead-time insertion. As shown in Figure 15-5, each dead-time unit has a rising and falling edge detector connected to the duty cycle comparison output. 15.7.2 DEAD-TIME RANGES The amount of dead-time provided by each dead-time unit is selected by specifying the input clock prescaler value and a 6-bit unsigned value. The amount of deadtime provided by each unit may be set independently. Four input clock prescaler selections have been provided to allow a suitable range of dead-times, based on the device operating frequency. The clock prescaler option may be selected independently for each of the two dead-time values. The dead-time clock prescaler values are selected using the DTAPS<1:0> and DTBPS<1:0> control bits in the DTCON1 SFR. The following clock prescaler options may be selected for each of the dead-time values: * * * * TCY 2TCY 4TCY 8TCY After the prescaler values are selected, the dead-time for each unit is adjusted by loading two 6-bit unsigned values into the DTCON1 special function register. The dead-time unit prescalers are cleared on the following events: * On a load of the down timer due to a duty cycle comparison edge event. * On a write to the DTCON1 or DTCON2 registers. * On any device RESET. Note: The user should not modify the DTCON1 or DTCON2 values while the PWM module is operating (PTEN = 1). Unexpected results may occur. DEAD-TIME ASSIGNMENT The DTCON2 SFR contains control bits that allow the dead-times to be assigned to each of the complementary outputs. Table 15-2 summarizes the function of each dead-time selection control bit. TABLE 15-2: DEAD-TIME SELECTION BITS Bit Function DTS1A Selects PWM1L/PWM1H active edge dead-time. DTS1I Selects PWM1L/PWM1H inactive edge dead-time. DTS2A Selects PWM2L/PWM2H active edge dead-time. DTS2I Selects PWM2L/PWM2H inactive edge dead-time. DTS3A Selects PWM3L/PWM3H active edge dead-time. DTS3I Selects PWM3L/PWM3H inactive edge dead-time. DTS4A Selects PWM4L/PWM4H active edge dead-time. DTS4I Selects PWM4L/PWM4H inactive edge dead-time. 2002 Microchip Technology Inc. Advance Information DS70082A-page 101 dsPIC30F FIGURE 15-5: DEAD-TIME TIMING DIAGRAM Duty Cycle Generator PWMxH PWMxL Time selected by DTSxA bit (A or B) 15.8 Time selected by DTSxI bit (A or B) Independent PWM Output 15.10 PWM Output Override An independent PWM Output mode is required for driving certain types of loads. A particular PWM output pair is in the Independent Output mode when the corresponding PMOD bit in the PWMCON1 register is set. No dead-time control is implemented between adjacent PWM I/O pins when the module is operating in the Independent mode and both I/O pins are allowed to be active simultaneously. In the Independent mode, each duty cycle generator is connected to both of the PWM I/O pins in an output pair. By using the associated duty cycle register and the appropriate bits in the OVDCON register, the user may select the following signal output options for each PWM I/O pin operating in the Independent mode: * I/O pin outputs PWM signal * I/O pin inactive * I/O pin active 15.9 Single Pulse PWM Operation The PWM module produces single pulse outputs when the PTCON control bits PTMOD<1:0> = 10. Only edge aligned outputs may be produced in the Single Pulse mode. In Single Pulse mode, the PWM I/O pin(s) are driven to the active state when the PTEN bit is set. When a match with a duty cycle register occurs, the PWM I/O pin is driven to the inactive state. When a match with the PTPER register occurs, the PTMR register is cleared, all active PWM I/O pins are driven to the inactive state, the PTEN bit is cleared, and an interrupt is generated. DS70082A-page 102 The PWM output override bits allow the user to manually drive the PWM I/O pins to specified logic states, independent of the duty cycle comparison units. All control bits associated with the PWM output override function are contained in the OVDCON register. The upper half of the OVDCON register contains eight bits, POVDxH<4:1> and POVDxL<4:1>, that determine which PWM I/O pins will be overridden. The lower half of the OVDCON register contains eight bits, POUTxH<4:1> and POUTxL<4:1>, that determine the state of the PWM I/O pins when a particular output is overridden via the POVD bits. 15.10.1 COMPLEMENTARY OUTPUT MODE When a PWMxL pin is driven active via the OVDCON register, the output signal is forced to be the complement of the corresponding PWMxH pin in the pair. Dead-time insertion is still performed when PWM channels are overridden manually. 15.10.2 OVERRIDE SYNCHRONIZATION If the OSYNC bit in the PWMCON2 register is set, all output overrides performed via the OVDCON register are synchronized to the PWM time-base. Synchronous output overrides occur at the following times: * Edge Aligned mode, when PTMR is zero. * Center Aligned modes, when PTMR is zero and when the value of PTMR matches PTPER. Advance Information 2002 Microchip Technology Inc. dsPIC30F 15.11 PWM Output and Polarity Control 15.12.2 There are three device configuration bits associated with the PWM module that provide PWM output pin control. The FLTACON and FLTBCON special function registers have 8 bits each, that determine the state of each PWM I/O pin when it is overridden by a FAULT input. When these bits are cleared, the PWM I/O pin is driven to the inactive state. If the bit is set, the PWM I/O pin will be driven to the active state. The active and inactive states are referenced to the polarity defined for each PWM I/O pin (HPOL and LPOL polarity control bits). * HPOL configuration bit * LPOL configuration bit * PWMPIN configuration bit These three configuration bits in the FPORBOR configuration register (see the System Integration section) work in conjunction with the four PWM enable bits (PWMEN<4:1>), located in the PWMCON1 SFR. The configuration bits and PWM enable bits ensure that the PWM pins are in the correct states after a device RESET occurs. The PWMPIN configuration fuse allows the PWM module outputs to be optionally enabled on a device RESET. If PWMPIN = 0, the PWM outputs will be driven to their inactive states at RESET. If PWMPIN = 1 (default), the PWM outputs will be tristated. The HPOL bit specifies the polarity for the PWMxH outputs, whereas the LPOL bit specifies the polarity for the PWMxL outputs. 15.11.1 The PEN<4:1>H and PEN<4:1>L control bits in the PWMCON1 SFR enable each High PWM output pin and each Low PWM output pin, respectively. If a particular PWM output pin not enabled, it is treated as a general purpose I/O pin. 15.12 PWM FAULT Pins There are two FAULT pins (FLTA and FLTB) associated with the PWM module. When asserted, these pins can optionally drive each of the PWM I/O pins to a defined state. 15.12.1 FAULT PIN ENABLE BITS The FLTACON and FLTBCON Special Function Registers each have 4 control bits that determine whether a particular pair of PWM I/O pins is to be controlled by the FAULT input pin. To enable a specific PWM I/O pin pair for FAULT overrides, the corresponding bit should be set in the FLTACON or FLTBCON register. If all enable bits are cleared in the FLTACON or FLTBCON registers, then the corresponding FAULT input pin has no effect on the PWM module and the pin may be used as a general purpose interrupt pin or I/O. Note: The FAULT pin logic can operate independent of the PWM logic. If all the enable bits in the FLTACON/FLTBCON register are cleared, then the FAULT pin(s) could be used as general purpose interrupt pin(s). Each FAULT pin has an interrupt vector, interrupt flag bit and interrupt priority bits associated with it. 2002 Microchip Technology Inc. A special case exists when a PWM module I/O pair is in the Complementary mode and both pins are programmed to be active on a FAULT condition. The PWMxH pin always has priority in the Complementary mode, so that both I/O pins cannot be driven active simultaneously. 15.12.3 FAULT PIN PRIORITY If both FAULT input pins have been assigned to control a particular PWM I/O pin, the FAULT state programmed for the FAULT A input pin will take priority over the FAULT B input pin. 15.12.4 OUTPUT PIN CONTROL FAULT STATES FAULT INPUT MODES Each of the FAULT input pins has two modes of operation: * Latched Mode: When the FAULT pin is driven low, the PWM outputs will go to the states defined in the FLTACON/FLTBCON register. The PWM outputs will remain in this state until the FAULT pin is driven high and the corresponding interrupt flag has been cleared in software. When both of these actions have occurred, the PWM outputs will return to normal operation at the beginning of the next PWM cycle or half-cycle boundary. If the interrupt flag is cleared before the FAULT condition ends, the PWM module will wait until the FAULT pin is no longer asserted, to restore the outputs. * Cycle-by-Cycle Mode: When the FAULT input pin is driven low, the PWM outputs remain in the defined FAULT states for as long as the FAULT pin is held low. After the FAULT pin is driven high, the PWM outputs return to normal operation at the beginning of the following PWM cycle or half-cycle boundary. The Operating mode for each FAULT input pin is selected using the FLTAM and FLTBM control bits in the FLTACON and FLTBCON Special Function Registers. Each of the FAULT pins can be controlled manually in software. Advance Information DS70082A-page 103 dsPIC30F 15.13 PWM Update Lockout 15.14.1 For a complex PWM application, the user may need to write up to four duty cycle registers and the time-base period register, PTPER, at a given time. In some applications, it is important that all buffer registers be written before the new duty cycle and period values are loaded for use by the module. The PWM special event trigger has a postscaler that allows a 1:1 to 1:16 postscale ratio. The postscaler is configured by writing the SEVOPS<3:0> control bits in the PWMCON2 SFR. The PWM update lockout feature is enabled by setting the UDIS control bit in the PWMCON2 SFR. The UDIS bit affects all duty cycle buffer registers and the PWM time-base period buffer, PTPER. No duty cycle changes or period value changes will have effect while UDIS = 1. 15.14 PWM Special Event Trigger The PWM module has a special event trigger that allows A/D conversions to be synchronized to the PWM time-base. The A/D sampling and conversion time may be programmed to occur at any point within the PWM period. The special event trigger allows the user to minimize the delay between the time when A/D conversion results are acquired and the time when the duty cycle value is updated. The PWM special event trigger has an SFR named SEVTCMP, and five control bits to control its operation. The PTMR value for which a special event trigger should occur is loaded into the SEVTCMP register. When the PWM time-base is in an Up/Down Counting mode, an additional control bit is required to specify the counting phase for the special event trigger. The count phase is selected using the SEVTDIR control bit in the SEVTCMP SFR. If the SEVTDIR bit is cleared, the special event trigger will occur on the upward counting cycle of the PWM time-base. If the SEVTDIR bit is set, the special event trigger will occur on the downward count cycle of the PWM time-base. The SEVTDIR control bit has no effect unless the PWM time-base is configured for an Up/Down Counting mode. DS70082A-page 104 SPECIAL EVENT TRIGGER POSTSCALER The special event output postscaler is cleared on the following events: * Any write to the SEVTCMP register. * Any device RESET. 15.15 PWM Operation During CPU SLEEP Mode The FAULT A and FAULT B input pins have the ability to wake the CPU from SLEEP mode. The PWM module generates an interrupt if either of the FAULT pins is driven low while in SLEEP. 15.16 PWM Operation During CPU IDLE Mode The PTCON SFR contains a PTSIDL control bit. This bit determines if the PWM module will continue to operate or stop when the device enters IDLE mode. If PTSIDL = 0, the module continues to operate. If PTSIDL = 1, the module will stop operation as long as the CPU remains in IDLE mode. Advance Information 2002 Microchip Technology Inc. 01C6 SEVTDIR SEVTCMP 2002 Microchip Technology Inc. 01CE 01D0 01D2 01D4 01D6 01D8 01DA 01DC DTCON2 FLTACON FLTBCON OVDCON PDC1 PDC2 PDC3 PDC4 -- -- -- -- -- -- -- Bit 12 FAOV2H -- PTEN 01C0 01C2 01C4 01C6 SEVTDIR PTMR PTPER Advance Information SEVTCMP -- 01CC 01D0 01D4 01D6 01D8 01DA DTCON1 FLTACON OVDCON PDC1 PDC2 PDC3 Legend: -- PWMCON2 01CA u = uninitialized bit -- -- -- PWMCON1 01C8 -- PTDIR Bit 15 SFR Name Addr. PTCON -- -- -- -- -- -- Bit 14 Bit 13 -- -- -- -- Bit 12 FAOV2H -- -- -- Bit 11 POVD3H POVD3L POVD2H FAOV3H FAOV3L -- -- -- PTSIDL POVD2L FAOV2L -- FLTBM POVD1L -- -- FLTAM PWM Duty Cycle #3 Register PWM Duty Cycle #2 Register -- -- DTAPS<1:0> PWM Duty Cycle #1 Register POVD1H FAOV1L -- -- PEN3H Bit 2 -- PEN3L FBEN4 FAEN4 DTS2A FBEN3 FAEN3 DTS2I Dead-Time A Value -- PEN4L PTCKPS<1:0> Bit 3 Bit 0 FBEN2 FAEN2 DTS1A OSYNC PEN2L FBEN1 FAEN1 DTS1I UDIS PEN1L PTMOD<1:0> Bit 1 RESET State 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1111 1111 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 Bit 5 -- -- PEN2H -- -- PEN1H Bit 4 Bit 2 -- PEN3L -- FAEN3 Dead-Time A Value -- -- PTCKPS<1:0> Bit 3 Bit 0 FAEN2 OSYNC PEN2L FAEN1 UDIS PEN1L PTMOD<1:0> Bit 1 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0111 0111 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 RESET State 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 POUT3H POUT3L POUT2H POUT2L POUT1H POUT1L 0011 1111 0000 0000 PWM Special Event Compare Register -- -- -- DTS3I -- PEN1H Bit 4 POUT3H POUT3L POUT2H POUT2L POUT1H POUT1L 1111 1111 0000 0000 -- -- DTS3A -- PEN2H PTOPS<3:0> Bit 6 PWM Time-Base Period Register FAOV1H -- Bit 7 PWM Timer Count Value -- PTMOD2 PTMOD1 -- Bit 8 PWM Duty Cycle #4 Register PWM Duty Cycle #3 Register PWM Duty Cycle #2 Register Bit 9 -- -- DTS4I POVD1L POUT4H POUT4L FBOV1L FLTAM DTS4A PWM Duty Cycle #1 Register POVD1H FBOV1H FAOV1L -- -- DTAPS<1:0> -- PEN3H PWM Special Event Compare Register PEN4H Bit 5 PTOPS<3:0> Bit 6 PWM Time-Base Period Register FAOV1H -- SEVOPS<3:0> PTMOD3 -- Bit 10 POVD2L 6-OUTPUT PWM REGISTER MAP u = uninitialized bit POVD4H POVD4L POVD3H POVD3L POVD2H FBOV2L FAOV2L -- Bit 7 PWM Timer Count Value -- Bit 8 PTMOD2 PTMOD1 -- Bit 9 SEVOPS<3:0> PTMOD3 -- Bit 10 Dead-Time B Value PTMOD4 -- Bit 11 FBOV4H FBOV4L FBOV3H FBOV3L FBOV2H FAOV4H FAOV4L FAOV3H FAOV3L -- Bit 13 PTSIDL TABLE 15-4: Legend: DTBPS<1:0> 01CC DTCON1 -- -- PWMCON2 01CA -- -- -- -- Bit 14 PWMCON1 01C8 -- 01C4 PTPER PTDIR 01C2 PTMR PTEN Bit 15 01C0 SFR Name Addr. PTCON 8-OUTPUT PWM REGISTER MAP TABLE 15-3: dsPIC30F DS70082A-page 105 dsPIC30F NOTES: DS70082A-page 106 Advance Information 2002 Microchip Technology Inc. dsPIC30F 16.0 SPI MODULE The Serial Peripheral Interface (SPI) module is a synchronous serial interface, useful for communicating with other peripheral devices, such as EEPROMs, shift registers, display drivers and A/D converters, or other microcontrollers. It is compatible with Motorola's SPITM and SIOPTM interfaces. 16.1 Operating Function Description Each SPI module consists of a 16-bit shift register, SPIxSR (where x = 1 or 2), used for shifting data in and out, and a buffer register, SPIxBUF. A control register, SPIxCON, configures the module. Additionally, a status register, SPIxSTAT, indicates various status conditions. In Slave mode, data is transmitted and received as external clock pulses appear on SCK. Again, the interrupt is generated when the last bit is latched in. If SSx control is enabled, then transmission and reception are enabled only when SSx = low. The SDOx output will be disabled in SSx mode with SSx high. The clock provided to the module is (FOSC/4). This clock is then prescaled by the primary (PPRE<1:0>) and the secondary (SPRE<2:0>) prescale factors. The CKE bit determines whether transmit occurs on transition from active clock state to IDLE clock state, or vice versa. The CKP bit selects the IDLE state (high or low) for the clock. 16.1.1 WORD AND BYTE COMMUNICATION The serial interface consists of 4 pins: SDIx (serial data input), SDOx (serial data output), SCKx (shift clock input or output), and SSx (active low slave select). A control bit, MODE16 (SPIxCON<10>), allows the module to communicate in either 16-bit or 8-bit mode. 16-bit operation is identical to 8-bit operation, except that the number of bits transmitted is 16 instead of 8. In Master mode operation, SCK is a clock output, but in Slave mode, it is a clock input. The user software must disable the module prior to changing the MODE16 bit. The SPI module always gets reset to start a new communication when the MODE16 bit is changed by the user. A series of eight (8) or sixteen (16) clock pulses shifts out bits from the SPIxSR to SDOx pin and simultaneously shifts in data from SDIx pin. An interrupt is generated when the transfer is complete and the corresponding interrupt flag bit (SPI1IF or SPI2IF) is set. This interrupt can be disabled through an interrupt enable bit (SPI1IE or SPI2IE). The receive operation is double buffered. When a complete byte is received, it is transferred from SPIxSR to SPIxBUF. If the receive buffer is full when new data is being transferred from SPIxSR to SPIxBUF, the module will set the SPIROV bit, indicating an overflow condition. The transfer of the data from SPIxSR to SPIxBUF will not be completed and the new data will be lost. The module will not respond to SCL transitions while SPIROV is 1, effectively disabling the module until SPIxBUF is read by user software. Transmit writes are also double buffered. The user writes to SPIxBUF. When the master or slave transfer is completed, the SPIxSR is swapped with SPIxBUF. The received data is thus placed in SPIxBUF and the transmit data in SPIxSR is ready for the next transfer. Note: The transmit and receive buffers are mapped to the same register address, SPIxBUF. A basic difference between 8-bit and 16-bit operation is that the data is transmitted out of bit 7 of the SPIxSR for 8-bit operation, and data is transmitted out of bit15 of the SPIxSR for 16-bit operation. In both modes, data is shifted into bit 0 of the SPIxSR. 16.1.2 SDOx DISABLE A control bit, DISSDO, is provided to the SPIxCON register to allow the SDOx output to be disabled. This will allow the SPI module to be connected in an input only configuration. SDO can also be used for general purpose I/O. 16.2 Framed SPI Support The module supports a basic framed SPI protocol in Master or Slave mode. The control bit FRMEN enables framed SPI support and causes the SSx pin to perform the frame synchronization pulse (FSYNC) function. The control bit SPIFSD determines whether the SSx pin is an input or an output, i.e., whether the module receives or generates the frame synchronization pulse. The frame pulse is an active high pulse for a single SPI clock cycle. When frame synchronization is enabled, the data starts transmitting only on the subsequent transmit edge of the SPI clock. In Master mode, the clock is generated by prescaling the system clock. Data is transmitted as soon as SPIBUF is written to. The interrupt is generated at the middle of the transfer of the last bit. 2002 Microchip Technology Inc. Advance Information DS70082A-page 107 dsPIC30F FIGURE 16-1: SPI BLOCK DIAGRAM Internal Data Bus Read Write SPIxBUF SPIxBUF Transmit Receive SPIxSR SDIx bit0 SDOx Shift clock SS & FSYNC Clock Control Control SSx Edge Select Secondary Prescaler 1,2,4,6,8 SCKx Primary Prescaler 1, 4, 16, 64 FOSC Enable Master Clock Note: x = 1 or 2. FIGURE 16-2: SPI MASTER/SLAVE CONNECTION SPI Master SPI Slave SDOx SDIy Serial Input Buffer (SPIxBUF) SDIx Shift Register (SPIxSR) MSb Serial Input Buffer (SPIyBUF) SDOy LSb Shift Register (SPIySR) MSb SCKx Serial Clock LSb SCKy PROCESSOR 1 PROCESSOR 2 Note: x = 1 or 2, y = 1 or 2. DS70082A-page 108 Advance Information 2002 Microchip Technology Inc. dsPIC30F 16.3 Slave Select Synchronization The SSx pin allows a Synchronous Slave mode. The SPI must be configured in SPI Slave mode, with SSx pin control enabled (SSEN = 1). When the SSx pin is low, transmission and reception are enabled, and the SDOx pin is driven. When SSx pin goes high, the SDOx pin is no longer driven. Also, the SPI module is resynchronized, all counters and control circuitry are reset; therefore, when the SSx pin is asserted low again, transmission/reception will begin at the Most Significant bit, even if SSx had been de-asserted in the middle of a transmit/receive. 16.4 16.5 SPI Operation During CPU IDLE Mode When the device enters IDLE mode, all clock sources remain functional. The SPISIDL bit (SPIxSTAT<13>) selects if the SPI module will stop on IDLE or continue on IDLE. If SPISIDL = 0, the module will continue operation when the CPU enters IDLE mode. If SPISIDL = 1, the module will stop when the CPU enters IDLE mode. SPI Operation During CPU SLEEP Mode During SLEEP mode, the SPI module is shut-down. If the CPU enters SLEEP mode while an SPI transaction is in progress, then the transmission and reception is aborted. The transmitter and receiver will stop in SLEEP mode. However, register contents are not affected by entering or exiting SLEEP mode. 2002 Microchip Technology Inc. Advance Information DS70082A-page 109 0220 0222 SPI1STAT SPI1CON -- SPIEN Bit 15 FRMEN DS70082A-page 110 0226 0228 SPI2CON SPIFSD SPISIDL Bit 13 -- -- Bit 12 -- SPIEN Bit 15 FRMEN -- Bit 14 SPIFSD SPISIDL Bit 13 -- -- Bit 12 SPI2 REGISTER MAP SPI2BUF 022A Legend: u = uninitialized bit Addr. SFR Name SPI2STAT TABLE 16-2: -- Bit 14 SPI1 REGISTER MAP SPI1BUF 0224 Legend: u = uninitialized bit Addr. SFR Name TABLE 16-1: -- Bit 10 -- Bit 10 DISSDO MODE16 -- Bit 11 DISSDO MODE16 -- Bit 11 CKE -- Bit 8 SSEN -- Bit 7 CKP SPIROV Bit 6 CKE -- Bit 8 SSEN -- Bit 7 Bit 6 CKP SPIROV Transmit and Receive Buffer SMP -- Bit 9 Transmit and Receive Buffer SMP -- Bit 9 MSTEN -- Bit 5 MSTEN -- Bit 5 SPRE2 -- Bit 4 SPRE2 -- Bit 4 -- Bit 2 SPRE0 -- Bit 2 SPRE1 SPRE0 -- Bit 3 SPRE1 -- Bit 3 PPRE1 SPITBF Bit 1 PPRE1 SPITBF Bit 1 RESET State PPRE0 SPIRBF Bit 0 PPRE0 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 RESET State 0000 0000 0000 0000 0000 0000 0000 0000 SPIRBF 0000 0000 0000 0000 Bit 0 dsPIC30F Advance Information 2002 Microchip Technology Inc. dsPIC30F 17.0 I2C MODULE 17.1 The Inter-Integrated CircuitTM (I2CTM) module provides complete hardware support for both Slave and MultiMaster modes of the I2C serial communication standard, with a 16-bit interface. This module offers the following key features: * Inter-Integrated Circuit (I2C) interface * I2C interface supports both Master and Slave operation. * I2C Slave mode supports 7 and 10-bit address. * I2C Master mode supports 7 and 10-bit address. * I2C port allows bi-directional transfers between master and slaves. * Serial clock synchronization for I2C port can be used as a handshake mechanism to suspend and resume serial transfer (SCLREL control). * I2C supports Multi-Master operation; detects bus collision and will arbitrate accordingly. FIGURE 17-1: Operating Function Description The hardware fully implements all the master and slave functions of the I2C Standard and Fast mode specifications, as well as 7 and 10-bit addressing. Thus, the I2C module can operate either as a slave or a master on an I2C bus. 17.1.1 VARIOUS I2C MODES The following types of I2C operation are supported: * * * I2C Slave operation with 7-bit address I2C Slave operation with 10-bit address I2C Master operation with 7 or 10-bit address See the I2C programmer's model in Figure 17-1. PROGRAMMER'S MODEL I2CRCV (8-bits) bit 7 bit 0 bit 7 bit 0 I2CTRN (8-bits) I2CBRG (9-bits) bit 8 bit 0 I2CCON (16-bits) bit 15 bit 0 bit 15 bit 0 I2CSTAT (16-bits) I2CADD (10-bits) bit 9 17.1.2 PIN CONFIGURATION IN I2C MODE I2C has a 2-pin interface: pin SCL is clock and pin SDA is data. 17.1.3 I2C REGISTERS I2CCON and I2CSTAT are control and status registers, respectively. The I2CCON register is readable and writable. The lower 6 bits of I2CSTAT are read only. The remaining bits of the I2CSTAT are read/write. bit 0 The I2CADD register holds the slave address. A status bit, ADD10, indicates 10-bit Address mode. The I2CBRG acts as the baud rate generator reload value. In receive operations, I2CRSR and I2CRCV together form a double buffered receiver. When I2CRSR receives a complete byte, it is transferred to I2CRCV and the I2CIF interrupt pulse is generated. During transmission, the I2CTRN is not double buffered. Note: I2CRSR is the shift register used for shifting data, whereas I2CRCV is the buffer register to which data bytes are written to or read from. This register is the receive buffer, as shown in Figure 16-1. I2CTRN is the transmit register to which bytes are written during a transmit operation, as shown in Figure 16-2. 2002 Microchip Technology Inc. Advance Information Following a RESTART condition in 10-bit mode, the user only needs to match the first 7-bit address. DS70082A-page 111 dsPIC30F FIGURE 17-2: I2C BLOCK DIAGRAM Internal Data Bus I2CRCV Read SCL Shift Clock I2CRSR LSB SDA Addr_Match Match Detect Write I2CADD Read START and STOP bit Detect I2CSTAT Write Control Logic START, RESTART, STOP bit Generate Write I2CCON Collision Detect Acknowledge Generation Clock Stretching Read Read Write I2CTRN LSB Shift Clock Read Reload Control BRG Down Counter DS70082A-page 112 Write I2CBRG FOSC Advance Information Read 2002 Microchip Technology Inc. dsPIC30F 17.2 I2C Module Addresses The I2CADD register contains the Slave mode addresses. The register is a 10-bit register. If the A10M bit (I2CCON<10>) is 0, the address is assumed to be a 7-bit address. When an address is received, it is compared to the Least Significant 7 bits of the I2CADD register. If the A10M bit is 1, the address is assumed to be a 10-bit address. When an address is received, it will be compared with the binary value `1 1 1 1 0 A9 A8' (where A9, A8 are two Most Significant bits of I2CADD). If that value matches, the next address will be compared with the Least Significant 8-bits of I2CADD, as specified in the 10-bit addressing protocol. 17.3 I2C 7-bit Slave Mode Operation Once enabled (I2CEN = 1), the slave module will wait for a START bit to occur (i.e., the I2C module is `IDLE'). Following the detection of a START bit, 8 bits are shifted into I2CRSR and the address is compared against I2CADD. In 7-bit mode (A10M = 0), bits I2CADD<6:0> are compared against I2CRSR<7:1> and I2CRSR<0> is the R_W bit. All incoming bits are sampled on the rising edge of SCL. If an address match occurs, an Acknowledge will be sent, and on the falling edge of the ninth bit (ACK bit), the I2CIF interrupt pulse is generated. The address match does not affect the contents of the I2CRCV buffer or the RBF bit. 17.3.1 SLAVE TRANSMISSION If the R_W bit received is a '1', then the serial port will go into Transmit mode. It will send ACK on the ninth bit and then hold SCL to '0' until the CPU responds by writing to I2CTRN. SCL is released by setting the SCLREL bit, and 8 bits of data are shifted out. Data bits are shifted out on the falling edge of SCL, such that SDA is valid during SCL high (see timing diagram). The interrupt pulse is sent on the falling edge of the ninth clock pulse, regardless of the status of the ACK received from the master. 17.3.2 If the RBF flag is set, indicating that I2CRCV is still holding data from a previous operation (RBF = 1), then ACK is not sent; however, the interrupt pulse is generated. In the case of an overflow, the contents of the I2CRSR are not loaded into the I2CRCV. Note: 17.4 The I2CRCV will be loaded if the I2COV bit = 1 and the RBF flag = 0. In this case, a read of the I2CRCV was performed, but the user did not clear the state of the I2COV bit before the next receive occurred. The Acknowledge is not sent (ACK = 1) and the I2CRCV is updated. I2C 10-bit Slave Mode Operation In 10-bit mode, the basic receive and transmit operations are the same as in the 7-bit mode. However, the criteria for address match is more complex. The I2C specification dictates that a slave must be addressed for a write operation, with two address bytes following a START bit. The A10M bit is a control bit that signifies that the address in I2CADD is a 10-bit address rather than a 7-bit address. The address detection protocol for the first byte of a message address is identical for 7-bit and 10-bit messages, but the bits being compared are different. I2CADD holds the entire 10-bit address. Upon receiving an address following a START bit, I2CRSR <7:3> is compared against a literal `11110' (the default 10-bit address) and I2CRSR<2:1> are compared against I2CADD<9:8>. If a match occurs and only if R_W = 0, the interrupt pulse is sent. The ADD10 bit will be cleared to indicate a partial address match. If a match fails or R_W = 1, the ADD10 bit is cleared and the module returns to the IDLE state. Then, the low byte of the address is received and compared against I2CADD<7:0>. If an address match occurs, the interrupt pulse is generated and the ADD10 bit is set, indicating a complete 10-bit address match. If an address match did not occur, the ADD10 bit is cleared and the module returns to the IDLE state. 17.4.1 SLAVE RECEPTION If the R_W bit received is a '0' during an address match, then Receive mode is initiated. Incoming bits are sampled on the rising edge of SCL. After 8 bits are received, if I2CRCV is not full or I2COV is not set, I2CRSR is transferred to I2CRCV. ACK is sent on the ninth clock. 10-BIT MODE SLAVE TRANSMISSION Once a slave is addressed in this fashion, with the full 10-bit address (we will refer to this state as "PRIOR_ADDR_MATCH"), the master can begin sending data bytes for a slave reception operation. 17.4.2 10-BIT MODE SLAVE RECEPTION Once addressed, the master can, without generating a STOP bit, generate a Repeated START bit and reset the high byte of the address and R_W = 1, thus initiating a slave transmit operation. 2002 Microchip Technology Inc. Advance Information DS70082A-page 113 dsPIC30F 17.5 Automatic Clock Stretch In the Slave modes, the module can synchronize buffer reads and write to the master device by clock stretching. 17.5.1 TRANSMIT CLOCK STRETCHING Note 1: If the user reads the contents of the I2CRCV, clearing the RBF bit before the falling edge of the ninth clock, the SCLREL bit will not be cleared and clock stretching will not occur. 2: The SCLREL bit can be set in software, regardless of the state of the RBF bit. The user should be careful to clear the RBF bit in the ISR before the next receive sequence in order to prevent an overflow condition. Both 10-bit and 7-bit Transmit modes implement clock stretching by asserting the SCLREL bit after the falling edge of the ninth clock if the TBF bit is cleared, indicating the buffer is empty. This occurs regardless of the state of the STREN bit. In Slave Transmit modes, clock stretching is always performed, irrespective of the STREN bit. Clock synchronization takes place following the ninth clock of the transmit sequence. If the device samples an ACK on the falling edge of the ninth clock, and if the TBF bit is still clear, then the SCLREL bit is automatically cleared. The SCLREL being cleared to `0' will assert the SCL line low. The user's ISR must set the SCLREL bit before transmission is allowed to continue. By holding the SCL line low, the user has time to service the ISR and load the contents of the I2CTRN before the master device can initiate another transmit sequence. Note 1: If the user loads the contents of I2CTRN, setting the TBF bit before the falling edge of the ninth clock, the SCLREL bit will not be cleared and clock stretching will not occur. 2: The SCLREL bit can be set in software, regardless of the state of the TBF bit. 17.5.2 RECEIVE CLOCK STRETCHING The STREN bit in the I2CCON register can be used to enable clock stretching in Slave Receive mode. When the STREN bit is set, the SCL pin will be held low at the end of each data receive sequence. 17.5.3 CLOCK STRETCHING DURING 7-BIT ADDRESSING (STREN = 1) When the STREN bit is set in Slave Receive mode, the SCL line is held low when the buffer register is full. The method for stretching the SCL output is the same for both 7 and 10-bit Addressing modes. Clock stretching takes place following the ninth clock of the receive sequence. On the falling edge of the ninth clock at the end of the ACK sequence, if the RBF bit is set, the SCLREL bit is automatically cleared, forcing the SCL output to be held low. The user's ISR must set the SCLREL bit before reception is allowed to continue. By holding the SCL line low, the user has time to service the ISR and read the contents of the I2CRCV before the master device can initiate another receive sequence. This will prevent buffer overruns from occurring. DS70082A-page 114 17.5.4 CLOCK STRETCHING DURING 10-BIT ADDRESSING (STREN = 1) Clock stretching takes place automatically during the addressing sequence. Because this module has a register for the entire address, it is not necessary for the protocol to wait for the address to be updated. After the address phase is complete, clock stretching will occur on each data receive or transmit sequence as is described earlier. 17.6 Software Controlled Clock Stretching (STREN = 1) When the STREN bit is `1', the SCLREL bit may be cleared by software to allow software to control the clock stretching. The logic will synchronize writes to the SCLREL bit with the SCL clock. Clearing the SCLREL bit will not assert the SCL output until the module detects a falling edge on the SCL output and SCL is sampled low. If the SCLREL bit is cleared by the user while the SCL line is already sampled low, the SCL output will be asserted. The SCL output will remain low until the SCLREL bit is set, and all other devices on the I2C bus have de-asserted SCL. This ensures that a write to the SCLREL bit will not violate the minimum high time requirement for SCL. If the STREN bit is `0', a software write to the SCLREL bit will be disregarded and have no effect on the SCLREL bit. 17.7 Interrupts The I2C module generates two interrupt flags, I2CIF (I2C Transfer Complete Interrupt Flag) and BCLIF (I2C Bus Collision Interrupt Flag). The I2CIF interrupt flag is pulsed high for one TCY on the falling edge of the 9th clock pulse. The BCLIF interrupt flag is pulsed high for one TCY when a bus collision event is detected. Advance Information 2002 Microchip Technology Inc. dsPIC30F 17.8 Slope Control The I2C standard requires slope control on the SDA and SCL signals for Fast Mode (400 kHz). The control bit, DISSLW, enables the user to disable slew rate control, if desired. It is necessary to disable the slew rate control for 1 MHz mode. 17.9 IPMI Support The control bit IPMIEN enables the module to support Intelligent Peripheral Management Interface (IPMI). When this bit is set, the module accepts and acts upon all addresses. 17.10 General Call Address Support The general call address can address all devices. When this address is used, all devices should, in theory, respond with an Acknowledge. The general call address is one of eight addresses reserved for specific purposes by the I2C protocol. It consists of all 0's with R_W = 0. The general call address is recognized when the General Call Enable bit (GCEN) is set (I2CCON<15> = 1). Following a START bit detect, 8 bits are shifted into I2CRSR and the address is compared against I2CADD, and is also compared to the general call address, which is fixed in hardware. If a general call address match occurs, the I2CRSR is transferred to the I2CRCV after the eighth clock, the RBF flag is set, and on the falling edge of the ninth bit (ACK bit), the I2CIF interrupt is set. When the interrupt is serviced, the source for the interrupt can be checked by reading the contents of the I2CRCV to determine if the address was device specific, or a general call address. 17.11 I2C Master Support As a Master device, six operations are supported. * Assert a START condition on SDA and SCL. * Assert a RESTART condition on SDA and SCL. * Write to the I2CTRN register initiating transmission of data/address. * Generate a STOP condition on SDA and SCL. * Configure the I2C port to receive data. * Generate an Acknowledge condition at the end of a received byte of data. 17.12 I2C Master Operation The master device generates all the serial clock pulses and the START and STOP conditions. A transfer is ended with a STOP condition or with a Repeated START condition. Since the Repeated START condition is also the beginning of the next serial transfer, the I2C bus will not be released. 2002 Microchip Technology Inc. In Master Transmitter mode, serial data is output through SDA, while SCL outputs the serial clock. The first byte transmitted contains the slave address of the receiving device (7 bits) and the data direction bit. In this case, the data direction bit (R_W) is logic 0. Serial data is transmitted 8 bits at a time. After each byte is transmitted, an Acknowledge bit is received. START and STOP conditions are output to indicate the beginning and the end of a serial transfer. In Master Receive mode, the first byte transmitted contains the slave address of the transmitting device (7 bits) and the data direction bit. In this case, the data direction bit (R_W) is logic 1. Thus, the first byte transmitted is a 7-bit slave address, followed by a `1' to indicate receive bit. Serial data is received via SDA while SCL outputs the serial clock. Serial data is received 8 bits at a time. After each byte is received, an Acknowledge bit is transmitted. START and STOP conditions indicate the beginning and end of transmission. 17.12.1 I2C MASTER TRANSMISSION Transmission of a data byte, a 7 bit address, or the second half of a 10 bit address is accomplished by simply writing a value to I2CTRN register. The user should only write to I2CTRN when the module is in a WAIT state. This action will set the buffer full flag (TBF) and allow the baud rate generator to begin counting and start the next transmission. Each bit of address/data will be shifted out onto the SDA pin after the falling edge of SCL is asserted. The Transmit Status Flag, TRSTAT (I2CSTAT<14>), indicates that a master transmit is in progress. 17.12.2 I2C MASTER RECEPTION Master mode reception is enabled by programming the receive enable (RCEN) bit (I2CCON<11>). The I2C module must be IDLE before the RCEN bit is set, otherwise the RCEN bit will be disregarded. The baud rate generator begins counting, and on each rollover, the state of the SCL pin changes (high to low/low to high), and data is shifted in to the I2CRSR on the rising edge of each clock. 17.12.3 BAUD RATE GENERATOR In I2C Master mode, the reload value for the BRG is located in the I2CBRG register. When the BRG is loaded with this value, the BRG counts down to 0 and stops until another reload has taken place. If clock arbitration is taking place, for instance, the BRG is reloaded when the SCL pin is sampled high. As per the I2C standard, FSCK may be 100 kHz, 400 kHz. However, the user can specify any baud rate up to 1 MHz. I2CBRG values of 0 or 1 are illegal. EQUATION 17-1: Advance Information SERIAL CLOCK RATE FSCK = FCY / I2CBRG DS70082A-page 115 dsPIC30F 17.12.4 CLOCK ARBITRATION Clock arbitration occurs when the master de-asserts the SCL pin (SCL allowed to float high) during any receive, transmit, or RESTART/STOP condition. When the SCL pin is allowed to float high, the baud rate generator (BRG) is suspended from counting until the SCL pin is actually sampled high. When the SCL pin is sampled high, the baud rate generator is reloaded with the contents of I2CBRG and begins counting. This ensures that the SCL high time will always be at least one BRG rollover count, in the event that the clock is held low by an external device. 17.12.5 MULTI-MASTER COMMUNICATION, BUS COLLISION, AND BUS ARBITRATION Multi-Master operation support is achieved by bus arbitration. When the master outputs address/data bits onto the SDA pin, arbitration takes place when the master outputs a 1 on SDA, by letting SDA float high and another master asserts a 0. When the SCL pin floats high, data should be stable. If the expected data on SDA is a 1 and the data sampled on the SDA pin = 0, then a bus collision has taken place. The master will set the Bus Collision Interrupt (BCLIF) pulse and reset the master portion of the I2C port to its IDLE state. 17.13 I2C Module Operation During CPU SLEEP and IDLE Modes 17.13.1 I2C OPERATION DURING CPU SLEEP MODE When the device enters SLEEP mode, all clock sources to the module are shutdown and stay at logic `0'. If SLEEP occurs in the middle of a transmission, and the state machine is partially into a transmission as the clocks stop, then the transmission is aborted. Similarly, if SLEEP occurs in the middle of a reception, then the reception is aborted. 17.13.2 I2C OPERATION DURING CPU IDLE MODE For the I2C, the I2CSIDL bit selects if the module will stop on IDLE or continue on IDLE. If I2CSIDL = 0, the module will continue operation on assertion of the IDLE mode. If I2CSIDL = 1, the module will stop on IDLE. If a transmit was in progress when the bus collision occurred, the transmission is halted, the TBF flag is cleared, the SDA and SCL lines are de-asserted, and the I2CTRN can now be written to. When the user services the bus collision Interrupt Service Routine, and if the I2C bus is free (i.e., the P bit is set), the user can resume communication by asserting a START condition. If a START, RESTART, STOP, or Acknowledge condition was in progress when the bus collision occurred, the condition is aborted, the SDA and SCL lines are deasserted, and the respective control bits in the I2CCON register are cleared to 0. When the user services the bus collision Interrupt Service Routine, and if the I2C bus is free, the user can resume communication by asserting a START condition. The Master will continue to monitor the SDA and SCL pins, and if a STOP condition occurs, the I2CIF bit will be set. A write to the I2CTRN will start the transmission of data at the first data bit, regardless of where the transmitter left off when bus collision occurred. In a Multi-Master environment, the interrupt generation on the detection of START and STOP conditions allows the determination of when the bus is free. Control of the I2C bus can be taken when the P bit is set in the I2CSTAT register, or the bus is IDLE and the S and P bits are cleared. DS70082A-page 116 Advance Information 2002 Microchip Technology Inc. 0204 0206 0208 I2CBRG I2CCON I2CSTAT -- -- -- -- ACKSTAT -- -- -- -- Bit 13 -- -- -- Bit 12 -- -- -- Bit 11 I2CSIDL SCLREL IPMIEN -- -- -- TRSTAT -- -- -- -- -- -- -- I2CEN Bit 14 Bit 15 I2C REGISTER MAP 020A u = uninitialized bit 0202 I2CTRN I2CADD Legend: 0200 I2CRCV SFR Name Addr. TABLE 17-1: BCL -- A10M -- -- -- Bit 10 GCSTAT DISSLW -- -- -- Bit 9 ADD10 SMEN -- -- Bit 8 IWCOL GCEN Bit 7 I2COV STREN Bit 6 Bit 4 Bit 3 Transmit Register Receive Register P ACKEN Address Register D_A ACKDT S RCEN Baud Rate Generator Bit 5 R_W PEN Bit 2 RBF RSEN Bit 1 TBF SEN Bit 0 RESET State 0000 0000 0000 0000 0000 0000 0000 0000 0001 0000 0000 0000 0000 0000 0000 0000 0000 0000 1111 1111 0000 0000 0000 0000 dsPIC30F 2002 Microchip Technology Inc. Advance Information DS70082A-page 117 dsPIC30F NOTES: DS70082A-page 118 Advance Information 2002 Microchip Technology Inc. dsPIC30F 18.0 UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER (UART) MODULE 18.1 The key features of the UART module are: * * * * This section describes the Universal Asynchronous Receiver/Transmitter Communications module. * * * * * * * FIGURE 18-1: UART Module Overview Full-duplex, 8 or 9-bit data communication Even, Odd or No Parity options (for 8-bit data) One or two STOP bits Fully integrated Baud Rate Generator with 16-bit prescaler Baud rates range from 38 bps to 1.875 Mbps at a 30 MHz instruction rate 4-word deep transmit data buffer 4-word deep receive data buffer Parity, Framing and Buffer Overrun error detection Support for Interrupt only on Address Detect (9th bit = 1) Separate Transmit and Receive Interrupts Loopback mode for diagnostic support UART TRANSMITTER BLOCK DIAGRAM Internal Data Bus Control and Status bits Write UTX8 Write UxTXREG Low Byte Transmit Control - Control TSR - Control Buffer - Generate Flags - Generate Interrupt Load TSR UxTXIF UTXBRK Data UxTX Transmit Shift Register (UxTSR) `0' (START) `1' (STOP) Parity Parity Generator 16 Divider 16X Baud Clock from Baud Rate Generator Control Signals Note: x = 1 or 2. 2002 Microchip Technology Inc. Advance Information DS70082A-page 119 dsPIC30F FIGURE 18-2: UART RECEIVER BLOCK DIAGRAM Internal Data Bus 16 Write Read Read Read UxMODE URX8 Write UxSTA UxRXREG Low Byte Receive Buffer Control - Generate Flags - Generate Interrupt - Shift Data Characters 8-9 LPBACK UxRX 0 * START bit Detect * Parity Check * STOP bit Detect * Shift Clock Generation * Wake Logic Control Signals FERR Load RSR to Buffer Receive Shift Register (UxRSR) 1 PERR From UxTX 16 Divider 16X Baud Clock from Baud Rate Generator UxRXIF DS70082A-page 120 Advance Information 2002 Microchip Technology Inc. dsPIC30F 18.2 18.2.1 Enabling and Setting Up UART ENABLING THE UART Transmitting Data 18.3.1 The UART module is enabled by setting the UARTEN bit in the UxMODE register (where x = 1 or 2). Once enabled, the UxTX and UxRX pins are configured as an output and an input respectively, overriding the TRIS and LATCH register bit settings for the corresponding I/O port pin. The UxTX pin is at logic `1' when no transmission is taking place. 18.2.2 18.3 The following steps must be performed in order to transmit 8-bit data: 1. DISABLING THE UART The UART module is disabled by clearing the UARTEN bit in the UxMODE register. This is the default state after any RESET. If the UART is disabled, all I/O pins operate as port pins, under the control of the latch and TRIS bits of the corresponding port pins. Disabling the UART module resets the buffers to empty states. Any data characters in the buffers are lost, and the baud rate counter is reset. All error and status flags associated with the UART module are reset when the module is disabled. The URXDA, OERR, FERR, PERR, UTXEN, UTXBRK and UTXBF bits are cleared, whereas RIDLE and TRMT are set. Other control bits, including ADDEN, URXISEL<1:0>, UTXISEL, as well as the UxMODE and UxBRG registers, are not affected. Clearing the UARTEN bit while the UART is active will abort all pending transmissions and receptions and reset the module as defined above. Re-enabling the UART will restart the UART in the same configuration. 2. 3. 4. 5. Set up the UART: First, the data length, parity and number of STOP bits must be selected, and then, the Transmit and Receive Interrupt enable and priority bits are setup in the UxMODE and UxSTA registers. Also, the appropriate baud rate value must be written to the UxBRG register. Enable the UART by setting the UARTEN bit (UxMODE<15>). Set the UTXEN bit (UxSTA<10>), thereby enabling a transmission. Write the data byte to be transmitted, to the lower byte of UxTXREG. The value will be transferred to Transmit Shift register (UxTSR) immediately and the serial bit stream will start shifting out during the next rising edge of the baud clock. A Transmit interrupt will be generated depending on the value of the interrupt control bit UTXISEL (UxSTA<15>). Alternatively, the data byte may be written while UTXEN = 0, following which, the user may set UTXEN. This will cause the serial bit stream to begin immediately because the baud clock will start from a cleared state. 18.3.2 18.2.3 ALTERNATE I/O The alternate I/O function is enabled by setting the ALTIO bit (UxMODE<10>). If ALTIO = 1, the UxATX and UxARX pins (alternate transmit and alternate receive pins, respectively) are used by the UART module, instead of the UxTX and UxRX pins. If ALTIO = 0, the UxTX and UxRX pins are used by the UART module. 18.2.4 SETTING UP DATA, PARITY AND STOP BIT SELECTIONS Control bits PDSEL<1:0> in the UxSTA register are used to select the data length and parity used in the transmission. The data length may either be 8-bits with even, odd or no parity, or 9-bits with no parity. The STSEL bit determines whether one or two STOP bits will be used during data transmission. The default (Power-on) setting of the UART is 8 bits, no parity, 1 STOP bit (typically represented as 8, N, 1). 2002 Microchip Technology Inc. TRANSMITTING IN 8-BIT DATA MODE TRANSMITTING IN 9-BIT DATA MODE The sequence of steps involved in the transmission of 9-bit data is similar to 8-bit transmission, except that a 16-bit data word (of which the upper 7 bits are always clear) must be written to the UxTXREG register. 18.3.3 TRANSMIT BUFFER (UXTXB) The transmit buffer is 9-bits wide and 4 characters deep. Including the Transmit Shift Register (UxTSR), the user effectively has a 5-deep FIFO (First In First Out) buffer. The UTXBF status bit (UxSTA<9>) indicates whether the transmit buffer is full. If a user attempts to write to a full buffer, the new data will not be accepted into the FIFO, and no data shift will occur within the buffer. This enables recovery from a buffer overrun condition. The FIFO is reset during any device RESET, but is not affected when the device enters a Power Saving mode, or wakes up from a Power Saving mode. Advance Information DS70082A-page 121 dsPIC30F 18.3.4 TRANSMIT INTERRUPT 18.4.2 The transmit interrupt flag (U1TXIF or U2TXIF) is located in the corresponding interrupt flag register. The transmitter generates an edge to set the UxTXIF bit. The condition of generating the interrupt depends on UTXISEL control bit. a) b) If UTXISEL = 0, an interrupt is generated when a word is transferred from the Transmit buffer to Transmit Shift register (UxTSR). This implies that the transmit buffer has at least one empty word. If UTXISEL = 1, an interrupt is generated when a word is transferred from the Transmit buffer to Transmit Shift register (UxTSR) and the Transmit buffer is empty. Switching between the two interrupt modes during operation is possible and sometimes offers more flexibility. 18.3.5 TRANSMIT BREAK RECEIVE BUFFER (UXRXB) The receive buffer is 4-deep. Including the Receive Shift register (UxRSR), the user effectively has a 5-deep FIFO (First In First Out) buffer. URXDA (UxSTA<0>) = 1 indicates that the receive buffer has data available. URXDA = 0 implies that the buffer is empty. If a user attempts to read an empty buffer, the old values in the buffer will be read, and no data shift will occur within the FIFO. The FIFO is reset during any device RESET. It is not affected when the device enters a Power Saving mode or wakes up from a Power Saving mode. 18.4.3 RECEIVE INTERRUPT The receive interrupt flag (U1RXIF or U2RXIF) can be read from the corresponding interrupt flag register. The interrupt flag is set by an edge generated by the receiver. The condition for setting the receive interrupt flag depends on the settings specified by the URXISEL<1:0> (UxSTA<7:6>) control bits. Setting the UTXBRK bit (UxSTA<11>) will cause the UxTX line to be driven to logic `0'. The UTXBRK bit overrides all transmission activity. Therefore, the user should generally wait for the transmitter to be IDLE before setting UTXBRK. a) To send a break character, the UTXBRK bit must be set by software and must remain set for a minimum of 13 baud clock cycles. The UTXBRK bit is then cleared by software to generate STOP bits. The user must wait for a duration of at least one or two baud clock cycles in order to ensure a valid STOP bit(s), before reloading the UxTXB or starting other transmitter activity. Transmission of a break character does not generate a transmit interrupt. b) 18.4 Switching between the Interrupt modes during operation is possible, though generally not advisable during normal operation. 18.4.1 Receiving Data RECEIVING IN 8-BIT OR 9-BIT DATA MODE The following steps must be performed while receiving 8-bit or 9-bit data: 1. 2. 3. 4. 5. Set up the UART (see Section 18.3.1). Enable the UART (see Section 18.3.1). A receive interrupt will be generated when one or more data bytes have been received, depending on the receive interrupt settings specified by the URXISEL bits (UxSTA<7:6>). Read the OERR bit to determine if an overrun error has occurred. The OERR bit must be reset in software. Read the received data from UxRXREG. The act of reading UxRXREG will move the next word to the top of the receive FIFO, and the PERR and FERR values will be updated. DS70082A-page 122 c) If URXISEL<1:0> = 00 or 01, an interrupt is generated every time a data word is transferred from the Receive Shift Register (UxRSR) to the Receive Buffer. There may be one or more characters in the receive buffer. If URXISEL<1:0> = 10, an interrupt is generated when a word is transferred from the Receive Shift Register (UxRSR) to the Receive Buffer and as a result of the transfer, the Receive Buffer contains 3 characters. If URXISEL<1:0> = 11, an interrupt is set when a word is transferred from the Receive Shift Register (UxRSR) to the Receive Buffer and as a result of the transfer, the Receive Buffer contains 4 characters (i.e., becomes full). 18.5 Reception Error Handling 18.5.1 RECEIVE BUFFER OVERRUN ERROR (OERR BIT) The OERR bit (UxSTA<1>) is set if all of the following conditions occur: a) b) c) The receive buffer is full. The receive shift register is full, but unable to transfer the character to the receive buffer. The STOP bit of the character in the UxRSR is detected, indicating that the UxRSR needs to transfer the character to the buffer. Once OERR is set, no further data is shifted in UxRSR (until the OERR bit is cleared in software or a RESET occurs). The data held in UxRSR and UxRXREG remains valid. Advance Information 2002 Microchip Technology Inc. dsPIC30F 18.5.2 FRAMING ERROR (FERR) 18.6 The FERR bit (UxSTA<2>) is set if a `0' is detected instead of a STOP bit. If two STOP bits are selected, both STOP bits must be `1', otherwise FERR will be set. The read only FERR bit is buffered along with the received data. It is cleared on any RESET. 18.5.3 PARITY ERROR (PERR) The PERR bit (UxSTA<3>) is set if the parity of the received word is incorrect. This error bit is applicable only if a Parity mode (odd or even) is selected. The read only PERR bit is buffered along with the received data bytes. It is cleared on any RESET. 18.5.4 IDLE STATUS When the receiver is active, i.e., between the initial detection of the START bit and the completion of the STOP bit, the RIDLE bit (UxSTA<4>) is `0'. Between the completion of the STOP bit and detection of the next START bit, the RIDLE bit is `1', indicating that the UART is IDLE. 18.5.5 RECEIVE BREAK The receiver will count and expect a certain number of bit times based on the values programmed in the PDSEL (UxMODE<2:1>) and STSEL (UxMODE<0>) bits. If the break is much longer than 13 bit times, the reception is considered complete after the number of bit times specified by PDSEL and STSEL. The URXDA bit is set, FERR is set, zeros are loaded into the receive FIFO, interrupts are generated, if appropriate and the RIDLE bit is set. When the module receives a long break signal and the receiver has detected the START bit, the data bits and the invalid STOP bit (which sets the FERR), the receiver must wait for a valid STOP bit before looking for the next START bit. It cannot assume that the break condition on the line is the next START bit. Break is regarded as a character containing all 0's, with the FERR bit set. The break character is loaded into the buffer. No further reception can occur until a STOP bit is received. Note that RIDLE goes high when the STOP bit has not been received yet. Address Detect Mode Setting the ADDEN bit (UxSTA<5>) enables this special mode, in which a 9th bit (URX8) value of `1' identifies the received word as an address rather than data. This mode is only applicable for 9-bit data communication. The URXISEL control bit does not have any impact on interrupt generation in this mode, since an interrupt (if enabled) will be generated every time the received word has the 9th bit set. 18.7 Loopback Mode Setting the LPBACK bit enables this special mode, in which the UxTX pin is internally connected to the UxRX pin. When configured for the loopback mode, the UxRX pin is disconnected from the internal UART receive logic. However, the UxTX pin still functions as in a normal operation. To select this mode: a) a) b) Configure UART for desired mode of operation. Set LPBACK = 1 to enable Loopback mode. Enable transmission as defined in Section 18.3. 18.8 Baud Rate Generator The UART has a 16-bit baud rate generator to allow maximum flexibility in baud rate generation. The baud rate generator register (UxBRG) is readable and writable. The baud rate is computed as follows: BRG = 16-bit value held in UxBRG register (0 through 65535) FCY = Instruction Clock Rate (1/TCY) The equation for the Baud Rate is given below. EQUATION 18-1: BAUD RATE Baud Rate = FCY / (16*(BRG+1)) Therefore, maximum baud rate possible is = FCY /16 (if BRG = 0), and minimum baud rate possible is = FCY / (16* 65536). With a full 16-bit baud rate generator, at 30 MIPs operation, the minimum baud rate achievable is 28.5 bps. 18.9 Auto Baud Support To allow the system to determine baud rates of received characters, the input can be optionally linked to a selected capture input. To enable this mode, the user must program the input capture module to detect the falling and rising edges of the START bit. 2002 Microchip Technology Inc. Advance Information DS70082A-page 123 dsPIC30F 18.10 UART Operation During CPU SLEEP and IDLE Modes 18.10.1 UART OPERATION DURING CPU SLEEP MODE When the device enters SLEEP mode, all clock sources to the module are shutdown and stay at logic `0'. If entry into SLEEP mode occurs while a transmission is in progress, then the transmission is aborted. The UxTX pin is driven to logic `1'. Similarly, if entry into SLEEP mode occurs while a reception is in progress, then the reception is aborted. The UxSTA, UxMODE, transmit and receive registers and buffers, and the UxBRG register are not affected by SLEEP mode. 18.10.2 UART OPERATION DURING CPU IDLE MODE For the UART, the USIDL bit selects if the module will stop operation when the device enters IDLE mode, or whether the module will continue on IDLE. If USIDL = 0, the module will continue operation during IDLE mode. If USIDL = 1, the module will stop on IDLE. If the WAKE bit (UxSTA<7>) is set before the device enters SLEEP mode, then a falling edge on the UxRX pin will generate a receive interrupt. The Receive Interrupt Select mode bit (URXISEL) has no effect for this function. If the receive interrupt is enabled, then this will wake-up the device from SLEEP. The UARTEN bit must be set in order to generate a wake-up interrupt. DS70082A-page 124 Advance Information 2002 Microchip Technology Inc. 0212 U1RXREG 2002 Microchip Technology Inc. 0216 0218 021A 021C U2MODE U2STA U2TXREG U2RXREG -- -- -- -- Bit 14 Bit 13 -- -- -- USIDL -- -- -- -- Bit 12 -- -- UTXISEL UARTEN Bit 15 -- -- -- -- Bit 14 -- -- -- USIDL Bit 13 -- -- -- -- Bit 12 Bit 10 ALTIO -- Bit 11 -- -- -- Bit 10 -- -- UTXBRK UTXEN -- Bit 11 -- -- -- -- UTXBRK UTXEN UART2 REGISTER MAP 021E u = uninitialized bit Addr. SFR Name TABLE 18-2: U2BRG Legend: -- -- UTXISEL 0214 u = uninitialized bit 0210 U1TXREG U1BRG Legend: 020E U1STA UARTEN Bit 15 020C SFR Name Addr. U1MODE UART1 REGISTER MAP TABLE 18-1: -- -- UTXBF -- Bit 9 -- -- URX8 UTX8 TRMT -- Bit 8 Bit 7 Bit 6 LPBACK LPBACK Bit 6 ABAUD Bit 5 PERR -- Bit 3 RIDLE -- Bit 4 PERR -- Bit 3 Receive Register Transmit Register RIDLE -- Bit 4 Receive Register Transmit Register URXISEL1 URXISEL0 ADDEN WAKE Bit 7 Baud Rate Generator Prescaler URX8 UTX8 TRMT -- Bit 8 Bit 5 ABAUD URXISEL1 URXISEL0 ADDEN WAKE Baud Rate Generator Prescaler UTXBF -- Bit 9 Bit 2 Bit 1 Bit 0 RESET State Bit 1 OERR FERR OERR PDSEL1 PDSEL0 Bit 2 FERR RESET State 0000 0000 0000 0000 0000 0000 0000 0000 0000 000u uuuu uuuu URXDA 0000 0001 0001 0000 STSEL 0000 0000 0000 0000 Bit 0 0000 0000 0000 0000 0000 0000 0000 0000 0000 000u uuuu uuuu URXDA 0000 0001 0001 0000 PDSEL1 PDSEL0 STSEL 0000 0000 0000 0000 dsPIC30F Advance Information DS70082A-page 125 dsPIC30F NOTES: DS70082A-page 126 Advance Information 2002 Microchip Technology Inc. dsPIC30F 19.0 CAN MODULE 19.1 Overview 19.1.1 The Controller Area Network (CAN) module is a serial interface, useful for communicating with other peripherals or microcontroller devices. This interface/protocol was designed to allow communications within noisy environments. The CAN module is a communication controller implementing the CAN 2.0 A/B protocol, as defined in the BOSCH specification. The module will support CAN 1.2, CAN 2.0A, CAN2.0B Passive, and CAN 2.0B Active versions of the protocol. The module implementation is a Full CAN system. The CAN specification is not covered within this data sheet. The reader may refer to the BOSCH CAN specification for further details. The module features are as follows: * Implementation of the CAN protocol CAN1.2, CAN2.0A and CAN2.0B * Standard and extended data frames * 0 - 8 bytes data length * Programmable bit rate up to 1 Mbit/sec * Support for remote frames * Double buffered receiver with two prioritized received message storage buffers (each buffer may contain up to 8 bytes of data) * 6 full (standard/extended identifier) acceptance filters, 2 associated with the high priority receive buffer, and 4 associated with the low priority receive buffer * 2 full acceptance filter masks, one each associated with the high and low priority receive buffers * Three transmit buffers with application specified prioritization and abort capability (each buffer may contain up to 8 bytes of data) * Programmable wake-up functionality with integrated low pass filter * Programmable Loopback mode supports self-test operation * Signaling via interrupt capabilities for all CAN receiver and transmitter error states * Programmable clock source * Programmable link to timer module for timestamping and network synchronization * Low power SLEEP mode 2002 Microchip Technology Inc. OVERVIEW OF THE MODULE The CAN bus module consists of a Protocol Engine and message buffering and control. The CAN protocol engine handles all functions for receiving and transmitting messages on the CAN bus. Messages are transmitted by first loading the appropriate data registers. Status and errors can be checked by reading the appropriate registers. Any message detected on the CAN bus is checked for errors and then matched against filters to see if it should be received and stored in one of the 2 receive registers. The CAN Module supports the following Frame types: * * * * * * Standard Data Frame Extended Data Frame Remote Frame Error Frame Overload Frame Reception Interframe Space 19.1.2 TRANSMIT/RECEIVE BUFFERS The dsPIC30F has three transmit and two receive buffers, two acceptance masks (one for each receive buffer), and a total of six acceptance filters. Figure 19-1 is a block diagram of these buffers and their connection to the protocol engine. Advance Information DS70032D-page 127 dsPIC30F FIGURE 19-1: CAN BUFFERS AND PROTOCOL ENGINE BLOCK DIAGRAM Acceptance Mask RXM1 BUFFERS Acceptance Filter RXF2 Message Queue Control MESSAGE MSGREQ TXABT TXLARB TXERR MTXBUFF TXB2 MESSAGE MSGREQ TXABT TXLARB TXERR MTXBUFF TXB1 MESSAGE MSGREQ TXABT TXLARB TXERR MTXBUFF TXB0 A c c e p t R X B 0 Transmit Byte Sequencer Acceptance Mask RXM0 Acceptance Filter RXF3 Acceptance Filter RXF0 Acceptance Filter RXF4 Acceptance Filter RXF1 Acceptance Filter RXF5 Identifier M A B Data Field Data Field PROTOCOL ENGINE Transmit Error Counter CRC Generator R X B 1 Identifier Receive Error Counter Transmit Shift A c c e p t RERRCNT TERRCNT ErrPas BusOff Receive Shift Protocol Finite State Machine CRC Check Transmit Logic Bit Timing Logic CxTX CxRX Bit Timing Generator Note: x = 1 or 2. DS70032D-page 128 Advance Information 2002 Microchip Technology Inc. 2002 Microchip Technology Inc. 0300 0302 0304 0306 0308 030A 030C 030E 0310 0312 0314 0316 C1RXF0SID C1RXF0EID C1RXF1SID C1RXF1EID C1RXF2SID C1RXF2EID C1RXF3SID C1RXF3EID C1RXF4SID C1RXF4EID C1RXF5SID C1RXF5EID Bit 11 Advance Information Transmit Buffer 2 Byte 3 Transmit Buffer 2 Byte 5 Transmit Buffer 2 Byte 7 Transmit Buffer 1 Byte 1 Transmit Buffer 1 Byte 3 Transmit Buffer 1 Byte 5 Transmit Buffer 1 Byte 7 0328 032A 032C 0330 0332 0334 0336 0338 033A 033C C1TX2B3 C1TX2B4 C1TX1CON C1TX1SID C1TX1EID C1TX1B1 C1TX1B2 C1TX1B3 C1TX1B4 Transmit Buffer 0 Byte 1 Transmit Buffer 0 Byte 3 0344 0346 0348 C1TX0EID C1TX0B1 C1TX0B2 034A C1TX0B3 Legend: u = uninitialized bit Receive Acceptance Mask 0 Extended Identifier Mask DLC<3:0> DLC<3:0> DLC<3:0> Transmit Buffer 0 Byte 5 EXIDE EXIDE Transmit Buffer 0 Byte 4 Transmit Buffer 0 Byte 2 Transmit Buffer 0 Byte 0 -- TXREQ Transmit Buffer 1 Byte 6 Transmit Buffer 1 Byte 4 Transmit Buffer 1 Byte 2 Transmit Buffer 1 Byte 0 -- TXREQ Transmit Buffer 2 Byte 6 Transmit Buffer 2 Byte 4 Transmit Buffer 2 Byte 2 TXABT TXLARB TXERR Transmit Buffer Extended Identifier -- EXIDE TXREQ -- -- EXIDEN EXIDEN EXIDEN EXIDEN EXIDEN EXIDEN Bit 3 Transmit Buffer 2 Byte 0 -- TXABT TXLARB TXERR Transmit Buffer 1 Extended Identifier -- -- -- -- -- -- -- -- -- Bit 4 TXABT TXLARB TXERR Transmit Buffer 2 Extended Identifier -- Receive Acceptance Mask 1 Extended Identifier Mask Transmit Buffer STARTD Identifer 0342 C1TX0SID -- 0340 -- Receive Acceptance Filter 5 Extended Identifier Transmit Buffer12 Standard Identifier -- C1TX0CON TXRTR Receive Acceptance Filter 4 Extended Identifier Transmit Buffer 2 Standard Identifier C1TX2B2 -- Receive Acceptance Filter 3 Extended Identifier Receive Acceptance Mask 1 Standard Identifier Mask Transmit Buffer 2 Byte 1 Bit 5 Receive Acceptance Filter 2 Extended Identifier Receive Acceptance Mask 0 Standard Identifier Mask 0326 Bit 6 Receive Acceptance Filter 1 Extended Identifier Receive Acceptance Filter 5 Standard Identifier Filter -- Bit 7 Receive Acceptance Filter 0 Extended Identifier Receive Acceptance Filter 4 Standard Identifier Filter C1TX2B1 -- Bit 8 Receive Acceptance Filter 3 Standard Identifier Filter 0324 TXRTR Bit 9 Receive Acceptance Filter 2 Standard Identifier Filter C1TX2EID -- Bit 10 Receive Acceptance Filter 1 Standard Identifier Filter 0322 -- Bit 12 Receive Acceptance Filter 0 Standard Identifier Filter Bit 13 C1TX2SID TXRTR Bit 14 0320 -- Bit 15 CAN1 REGISTER MAP C1TX2CON C1RXM1SID 031C C1RXM1EID 031E C1RXM0SID 0318 C1RXM0EID 031A Addr. SFR Name TABLE 19-1: -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 2 EID16 EID16 EID16 EID16 EID16 EID16 EID16 EID16 Bit 0 EID16 EID16 EID17 EID16 TXPRI<1:0> EID17 TXPRI<1:0> EID17 TXPRI<1:0> EID17 EID17 EID17 EID17 EID17 EID17 EDI17 EID17 Bit 1 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuu0 u0uu 0000 0000 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuu0 u0uu 0000 0000 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuu0 u0uu 0000 0000 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu uuu0 00uu uuuu uuuu uuuu uuuu uuuu uuuu uuu0 00uu uuuu uuuu uuuu uuuu uuuu uuuu uuu0 u0uu uuuu uuuu uuuu uuuu uuuu uuuu uuu0 u0uu uuuu uuuu uuuu uuuu uuuu uuuu uuu0 u0uu uuuu uuuu uuuu uuuu uuuu uuuu uuu0 u0uu uuuu uuuu uuuu uuuu uuuu uuuu uuu0 u0uu uuuu uuuu uuuu uuuu uuuu uuuu uuu0 u0uu RESET State dsPIC30F DS70032D-page 129 Receive Buffer 1 Byte 1 Receive Buffer 1 Byte 3 Receive Buffer 1 Byte 5 Receive Buffer 1 Byte 7 Receive Buffer 0 Byte 1 Receive Buffer 0 Byte 3 Receive Buffer 0 Byte 5 Receive Buffer 0 Byte 7 -- -- CANCAP RX0OVR RX1OVR 0354 0356 0358 035A 035C 0360 0362 0364 0366 0368 036A 036C 036E 0370 0372 0374 0376 C1RX1EID C1RX1B1 C1RX1B2 C1RX1B3 C1RX1B4 C1RX0CON C1RX0SID C1RX0EID C1RX0B1 C1RX0B2 C1RX0B3 C1RX0B4 C1CTRL C1CFG1 C1CFG2 C1INTF C1INTE DS70032D-page 130 0378 C1EC Legend: u = uninitialized bit -- -- -- WAKFIL -- -- RXRTR DLC<3:0> Bit 9 Bit 8 DLC<3:0> -- TXEP -- -- ABAT -- SEG2PH<2:0> -- REQOP<2:0> -- -- -- -- -- RXEP TXWAR RXWAR EWARN -- -- -- RXFUL RXM<1:0> IVRIE IVRIF BTLMODE WAKIE WAKIF SAM Bit 4 Bit 3 EXID RXRTRO EXID TX2IE TX1IE TX1IF TX0IE TX0IF BRP<5:0> Receive Error Count Register ERRIE TX2IF SEG1PH<2:0> -- Bit 1 RX1E RX1IF Bit 0 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu u0uu 0000 0000 0000 0000 uuuu uuuu uuuu uuuu RESET State RX0IE RX0IF -- EID16 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 uu00 0uuu uuuu uuuu 0000 0000 0000 0000 0000 0100 1000 0000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu u0uu FILHIT0 0000 0000 0000 0000 EDI16 PRSEG<2:0> EID17 JTOFF EID17 FILHIT<2:0> ICODE<2:0> Receive Buffer 0 Byte 6 Receive Buffer 0 Byte 4 Receive Buffer 0 Byte 2 -- -- Bit 2 RXRTRO DBEN Receive Buffer 0 Byte 0 SRR -- Receive Buffer 1 Byte 6 Receive Buffer 1 Byte 4 Receive Buffer 1 Byte 2 Receive Buffer 1 Byte 0 SRR -- Transmit Buffer 0 Byte 6 ERRIF OPMODE<2:0> SJWS<1:0> Bit 5 RXM<1:0> Bit 6 Receive Buffer 0 Extended Identifer Receive Buffer 0 Standard Identifier RB0 RXFUL Bit 7 Receive Buffer 1 Extended Identifer Receive Buffer 1 Standard Identifier RB0 Bit 10 Transmit Error Count Register -- TXBO -- -- CSIDLE RB1 RB1 Transmit Buffer 0 Byte 7 0352 RXRTR C1RX1SID -- Bit 11 0350 Bit 12 034C Bit 13 C1RX1CON Bit 14 C1TX0B4 Bit 15 CAN1 REGISTER MAP (CONTINUED) Addr. SFR Name TABLE 19-1: dsPIC30F Advance Information 2002 Microchip Technology Inc. 2002 Microchip Technology Inc. Advance Information Transmit Buffer 2 Byte 7 Transmit Buffer 1 Byte 1 Transmit Buffer 1 Byte 3 Transmit Buffer 1 Byte 5 Transmit Buffer 1 Byte 7 03B0 03B2 03B4 03B6 03B8 03BA 03BC 03C0 03C2 03C4 03C6 C2TX2B4 C2TX1CON C2TX1SID C2TX1EID C2TX1B1 C2TX1B2 C2TX1B3 C2TX1B4 C2TX0CON C2TX0SID C2TX0EID C2TX0B1 03C8 C2TX0B2 Legend: u = uninitialized bit -- TXRTR -- -- -- Receive Acceptance Filter 4 Extended Identifier Receive Acceptance Filter 5 Extended Identifier DLC<3:0> TXABT DLC<3:0> TXABT -- TXABT Transmit Buffer Extended Identifier Transmit Buffer STARTD Identifer DLC<3:0> Transmit Buffer 1 Extended Identifier -- Transmit Buffer 2 Extended Identifier -- -- -- -- -- -- -- -- -- Bit 4 EXIDE TXREQ -- -- EXIDEN EXIDEN EXIDEN EXIDEN EXIDEN EXIDEN Bit 3 EXIDE TXREQ EXIDE TXREQ Transmit Buffer 0 Byte 2 Transmit Buffer 0 Byte 0 -- TXLARB TXERR Transmit Buffer 1 Byte 6 Transmit Buffer 1 Byte 4 Transmit Buffer 1 Byte 2 Transmit Buffer 1 Byte 0 -- TXLARB TXERR Transmit Buffer 2 Byte 6 Transmit Buffer 2 Byte 4 Transmit Buffer 2 Byte 2 Transmit Buffer 2 Byte 0 -- TXLARB TXERR Receive Acceptance Mask 1 Extended Identifier Mask Transmit Buffer12 Standard Identifier Transmit Buffer 0 Byte 3 Bit 5 Receive Acceptance Mask 0 Extended Identifier Mask Transmit Buffer 2 Standard Identifier Transmit Buffer 0 Byte 1 -- -- Transmit Buffer 2 Byte 5 03AC C2TX2B3 TXRTR Transmit Buffer 2 Byte 3 03AA C2TX2B2 -- Transmit Buffer 2 Byte 1 03A8 C2TX2B1 -- 03A6 TXRTR Receive Acceptance Filter 3 Extended Identifier Receive Acceptance Mask 1 Standard Identifier Mask 03A4 -- Receive Acceptance Filter 2 Extended Identifier Receive Acceptance Mask 0 Standard Identifier Mask C2TX2EID 0396 C2RXF5EID Bit 6 Receive Acceptance Filter 1 Extended Identifier Receive Acceptance Filter 5 Standard Identifier Filter 03A2 0394 C2RXF5SID C2TX2SID 0392 C2RXF4EID Bit 7 Receive Acceptance Filter 0 Extended Identifier Receive Acceptance Filter 4 Standard Identifier Filter 03A0 0390 C2RXF4SID C2TX2CON 038E C2RXF3EID Bit 8 Receive Acceptance Filter 3 Standard Identifier Filter 039E 038C C2RXF3SID C2RXM1EID 038A C2RXF2EID Bit 9 Receive Acceptance Filter 2 Standard Identifier Filter 039C 0388 C2RXF2SID Bit 10 Receive Acceptance Filter 1 Standard Identifier Filter C2RXM1SID 0386 C2RXF1EID Bit 11 039A 0384 C2RXF1SID Bit 12 Receive Acceptance Filter 0 Standard Identifier Filter Bit 13 C2RXM0EID 0382 C2RXF0EID Bit 14 0398 0380 C2RXF0SID Bit 15 CAN2 REGISTER MAP C2RXM0SID Addr. SFR Name TABLE 19-2: -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 2 EID16 EID16 EID16 EID16 EID16 EID16 EID16 EID16 Bit 0 EID16 EID16 EID17 EID16 TXPRI<1:0> EID17 TXPRI<1:0> EID17 TXPRI<1:0> EID17 EID17 EID17 EID17 EID17 EID17 EDI17 EID17 Bit 1 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuu0 u0uu 0000 0000 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuu0 u0uu 0000 0000 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuu0 u0uu 0000 0000 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu uuu0 00uu uuuu uuuu uuuu uuuu uuuu uuuu uuu0 00uu uuuu uuuu uuuu uuuu uuuu uuuu uuu0 u0uu uuuu uuuu uuuu uuuu uuuu uuuu uuu0 u0uu uuuu uuuu uuuu uuuu uuuu uuuu uuu0 u0uu uuuu uuuu uuuu uuuu uuuu uuuu uuu0 u0uu uuuu uuuu uuuu uuuu uuuu uuuu uuu0 u0uu uuuu uuuu uuuu uuuu uuuu uuuu uuu0 u0uu RESET State dsPIC30F DS70032D-page 131 DS70032D-page 132 Receive Buffer 1 Byte 7 Receive Buffer 0 Byte 1 Receive Buffer 0 Byte 3 Receive Buffer 0 Byte 5 Receive Buffer 0 Byte 7 -- Transmit Error Count Register -- -- 03DA 03DC 03E0 03E2 03E4 03E6 03E8 03EA 03EC 03EE 03F0 03F2 CANCAP WAKFIL 03F4 RX0OVR RX1OVR 03F6 -- -- 03F8 C2RX1B3 C2RX1B4 C2RX0CON C2RX0SID C2RX0EID C2RX0B1 C2RX0B2 C2RX0B3 C2RX0B4 C2CTRL C2CFG1 C2CFG2 C2EC Legend: C2INTE C2INTF Receive Buffer 1 Byte 5 03D8 C2RX1B2 u = uninitialized bit -- -- RXRTR Receive Buffer 1 Byte 3 03D6 C2RX1B1 -- Receive Buffer 1 Byte 1 03D4 TXBO -- -- CSIDLE RB1 ABAT RB0 -- TXEP -- -- DLC<3:0> Bit 9 Bit 8 -- RXEP -- -- -- SEG2PH<2:0> -- REQOP<2:0> -- -- -- TXWAR RXWAR EWARN -- RXFUL RXM<1:0> IVRIE IVRIF BTLMODE WAKIE WAKIF SAM SJWS<1:0> Bit 3 EXID RXRTRO EXID TX2IE TX1IE TX1IF TX0IE TX0IF BRP<5:0> Receive Error Count Register ERRIE TX2IF SEG1PH<2:0> -- Bit 1 EID17 JTOFF EID17 RX1E uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu u0uu 0000 0000 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu RESET State RX0IE RX0IF -- EID16 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 uu00 0uuu uuuu uuuu 0000 0000 0000 0000 0000 0100 1000 0000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu u0uu FILHIT0 0000 0000 0000 0000 PRSEG<2:0> RX1IF Bit 0 EDI16 FILHIT<2:0> ICODE<2:0> Receive Buffer 0 Byte 6 Receive Buffer 0 Byte 4 Receive Buffer 0 Byte 2 -- -- Bit 2 RXRTRO DBEN Receive Buffer 0 Byte 0 -- Receive Buffer 1 Byte 6 Receive Buffer 1 Byte 4 Receive Buffer 1 Byte 2 Receive Buffer 1 Byte 0 SRR --- Transmit Buffer 0 Byte 6 ERRIF OPMODE<2:0> Bit 4 Transmit Buffer 0 Byte 4 Bit 5 RXM<1:0> Bit 6 Receive Buffer 0 Extended Identifer DLC<3:0> -- RXFUL Bit 7 Receive Buffer 1 Extended Identifer Receive Buffer 1 Standard Identifier RB0 C2RX1EID RB1 03D2 RXRTR C2RX1SID -- 03D0 C2RX1CON Bit 10 Transmit Buffer 0 Byte 7 Bit 11 Transmit Buffer 0 Byte 5 Bit 12 03CA Bit 13 03CC Bit 14 C2TX0B4 Bit 15 CAN2 REGISTER MAP (CONTINUED) C2TX0B3 Addr. SFR Name TABLE 19-2: dsPIC30F Advance Information 2002 Microchip Technology Inc. dsPIC30F 20.0 10-BIT HIGH SPEED ANALOGTO-DIGITAL CONVERTER (A/D) MODULE The10-bit high-speed analog-to-digital converter (A/D) allows conversion of an analog input signal to a corresponding 10-bit digital number. This module is based on a Successive Approximation Register (SAR) architecture, and provides a maximum sampling rate of 500 ksps. The A/D module has up to 16 analog inputs, which are multiplexed into four sample and hold amplifiers. The output of the sample and hold is the input into the converter, which generates the result. The analog reference voltages are software selectable to either the device supply voltage (AVDD/AVSS) or the voltage level on the (VREF+/VREF-) pin. The A/D converter has a unique feature of being able to operate while the device is in SLEEP mode. The ADCON1, ADCON2 and ADCON3 registers control the operation of the A/D module. The ADCHS register selects the input channels to be converted. The ADPCFG register configures the port pins as analog inputs or as digital I/O. The ADCSSL register selects inputs for scanning. Note: The SSRC<2:0>, ASAM, SMPI<3:0>, BUFM and ALTS bits, as well as the ADCON3 and ADCSSL registers, must not be written to while ADON = 1. This would lead to indeterminate results. The block diagram of the A/D module is shown in Figure 20-1. The A/D module has six 16-bit registers. * * * * * * A/D Control Register1 (ADCON1) A/D Control Register2 (ADCON2) A/D Control Register3 (ADCON3) A/D Input Select Register (ADCHS) A/D Port Configuration Register (ADPCFG) A/D Input Scan Selection Register (ADCSSL) 2002 Microchip Technology Inc. Advance Information DS70082A-page 133 dsPIC30F FIGURE 20-1: 10-BIT HIGH SPEED A/D FUNCTIONAL BLOCK DIAGRAM AVDD AVSS VREF+ VREF- AN2 + AN6 AN9 - AN1 AN4 + AN7 AN10 - AN2 AN5 + AN8 AN11 - S/H CH1 ADC 10-bit Result S/H CH2 16-word, 10-bit Dual Port RAM S/H CH3 CH1,CH2, CH3,CH0 sample AN3 AN0 AN1 AN2 AN3 AN4 AN4 AN5 AN5 AN6 AN6 AN7 AN7 AN8 AN8 AN9 AN9 AN10 AN10 AN11 AN11 AN12 AN12 AN13 AN13 AN14 AN14 AN15 AN15 + AN1 - DS70082A-page 134 Conversion Logic input switches S/H Sample/Sequence Control Bus Interface AN1 AN0 AN3 Data Format AN0 Input Mux Control CH0 Advance Information 2002 Microchip Technology Inc. dsPIC30F 20.1 A/D Result Buffer The module contains a 16-word dual port RAM, called ADRES<15:0>, to buffer the A/D results. The RAM is 10-bits wide, but is read into different format 16-bit words. Only word writes are allowed to the result buffer. If byte writes are attempted, the results are indeterminate. 20.2 Conversion Operation After the A/D module has been configured as desired, the sampling is started by setting the SAMP bit. Various sources, such as a programmable bit, timer time-outs and external events, will terminate sampling and start a conversion. When the A/D conversion is completed, the result is loaded into ADRES<15:0>, the CONV bit is cleared, and if, at the correct number of samples as specified by the SMPI bit, the A/D interrupt flag ADIF is set. The following steps should be followed for doing an A/D conversion: 1. 2. 3. 4. 5. 6. 7. Configure the A/D module: * Configure analog pins/voltage reference/and digital I/O * Select A/D input channels * Select A/D conversion clock * Select A/D conversion trigger * Turn on A/D module Configure A/D interrupt (if required): * Clear ADIF bit * Select A/D interrupt priority Start sampling. Wait the required sampling time. Trigger sample end, start conversion: * Module sets CONV bit Wait for A/D conversion to complete, by either: * Polling for the CONV bit to be cleared * Waiting for the A/D interrupt Read A/D result buffer, clear ADIF if required. 20.3 Selecting the Conversion Sequence Several groups of control bits select the sequence that the A/D connects inputs to the sample/hold channels, converts channels, writes the buffer memory, and generates interrupts. The sequence is controlled by the sampling clocks. The SIMSAM bit controls the sample/convert sequence for multiple channels. If the SIMSAM bit is 0, the two or four selected channels are sampled and converted sequentially, with two or four sample clocks. If the SIMSAM bit is 1, two or four selected channels are sampled simultaneously, with one sample clock. The channels are then converted sequentially. Obviously, if there is only 1 channel selected, the SIMSAM bit is not applicable. 2002 Microchip Technology Inc. The CHPS bits selects how many channels are sampled. This can vary from 1, 2 or 4 channels. If CHPS selects 1 channel, the CH0 channel will be sampled and at the sample clock, CH0 will be converted. The result is stored in the buffer. If CHPS selects 2 channels, the CH0 and CH1 channels will be sampled and converted. If CHPS selects 4 channels, the CH0, CH1, CH2 and CH3 channels will be sampled and converted. The SMPI bits will select the number of values loaded into the buffer before an interrupt occurs. This can vary from 1 sample per interrupt, to 16 samples per interrupt. The user cannot program a combination of CHPS and SMPI bits that specifies more than 16 conversions per interrupt, or 8 conversions per interrupt, depending on the BUFM bit. The BUFM bit, when set, will split the 16-word results buffer (ADRES) into two 8-word groups. Writing to the 8-word buffers will be alternated on each interrupt event. Use of the BUFM bit will depend on how much time is available for moving data out of the buffers after the interrupt, as determined by the application. If the processor can quickly unload a full buffer within the time it takes to sample and convert one channel, the BUFM bit can be 0 and up to 16 conversions may be done per interrupt. The processor will have one sample and conversion time to move the sixteen conversions. If the processor cannot unload the buffer within the sample and conversion time, the BUFM bit should be 1. For example, if SMPI<3:0> (ADCON2<5:2>) = 0111, then eight conversions will be loaded into 1/2 of the buffer, following which, an interrupt occurs. The next eight conversions will be loaded into the other 1/2 of the buffer. The processor will have the entire time between interrupts to move the eight conversions. The ALTS bit can be used to alternate the inputs selected during the sampling sequence. The input multiplexer has two sets of sample inputs: SAMPLE A and SAMPLE B. If the ALTS bit is 0, only the SAMPLE A inputs are selected for sampling. If the ALTS bit is 1 and SMPI<3:0> = 0000, on the first sample/convert sequence, the SAMPLE A inputs are selected, and on the next sample/convert sequence, the SAMPLE B inputs are selected. The CSCNA bit (ADCON2<10>) will allow the CH0 channel inputs to be alternately scanned across a selected number of analog inputs for the SAMPLE A group. The inputs are selected by the ADCSSL register. If a particular bit in the ADCSSL register is `1', the corresponding input is selected. The inputs are always scanned from lower to higher numbered inputs, starting after each interrupt occurs. If the number of inputs selected is greater than the number of samples taken per interrupt, the higher numbered inputs are unused. Advance Information DS70082A-page 135 dsPIC30F 20.4 Programming the Start of Conversion Trigger If the clearing of the CONV bit coincides with an auto start, the clearing has a higher priority. After the A/D conversion is aborted, a 2 TAD wait is required before the next sampling may be started by setting the SAMP bit. The sample trigger will terminate sampling and start the requested conversions. The SSRC<2:0> bits select the source of the sample trigger. If sequential sampling is specified, the A/D will continue at the next sample pulse which corresponds with the next channel converted. If simultaneous sampling is specified, the A/D will continue with the next multi-channel group conversion sequence. When SSRC<2:0> = 000, the sample trigger is under software control. Clearing the SAMP bit will cause the sample trigger. When SSRC<2:0> = 111 (Auto Start mode), the sample trigger is under A/D clock control. The SAMC bits select the number of A/D clocks between the start of sampling and the start of conversion. This provides the fastest conversion rates on multiple channels. SAMC must always be at least 1 clock cycle. 20.6 Selecting the A/D Conversion Clock The A/D conversion requires 11 TAD. The source of the A/D conversion clock is software selected using a six bit counter. There are 64 possible options for TAD. EQUATION 20-1: Other trigger sources can come from timer modules, Motor Control PWM module, or external interrupts. TAD = TCY * (0.5*(ADCS<5:0> +1)) The SSRC bits provide for up to 5 alternate sources of sample trigger. 20.5 The internal RC oscillator is selected by setting the ADRC bit. Aborting a Conversion For correct A/D conversions, the A/D conversion clock (TAD) must be selected to ensure a minimum TAD time of 150 nsec. Table 20-1 shows the resultant TAD times derived from the device operating frequencies and the A/D clock source selected. Clearing the CONV bit during a conversion will abort the current conversion and stop the sampling sequencing until the next sampling trigger. The ADRES will not be updated with the partially completed A/D conversion sample. That is, the ADRES will continue to contain the value of the last completed conversion (or the last value written to the ADRES register). TABLE 20-1: TYPICAL TAD VS. DEVICE OPERATING FREQUENCIES A/D Clock Source Select A/D ADRC ADCS<5:0> Clock TCY/2 0 000000 A/D Clock Period (TAD Values) Device FCY 30 MHz 25 MHz 12.5 MHz 6.25 MHz 1 MHz 16.67 ns(2) 20 ns(2) 40 ns(2) 500 ns 80 ns(2) 160 ns 80 ns(2) 160 ns 320 ns 2.0 s(3) 320 ns 640 ns(3) 4.0 s(3) 640 ns(3) 1.28 s(3) 8.0 s(3) s(3) s(3) 16.0 s(3) 5.12 s(3) 32.0 s(3) TCY 0 000001 33.33 ns(2) 40 ns(2) 2 TCY 0 000011 66.66 ns(2) 4 TCY 0 000111 8 TCY 0 001111 133.32 ns(2) 266.64 ns 80 ns(2) 160 ns ns(3) 16 TCY 0 011111 533.28 32 TCY 0 111111 1066.56 ns(3) RC 1 Note 1: 2: 3: 4: A/D CONVERSION CLOCK 320 ns 640 ns(3) 1280 ns(3) 1.28 2.56 s(3) 2.56 1.0 s 200 - 400 ns(1,4) 200 - 400 ns(1,4) 200 - 400 ns(1,4) 200 - 400 ns(1,4) 200 - 400 ns(1) The RC source has a typical TAD time of 300 ns for VDD > 3.0V. These values violate the minimum required TAD time. For faster conversion times, the selection of another clock source is recommended. A/D cannot meet full accuracy with RC clock source and FOSC > 20 MHz DS70082A-page 136 xxxxxx Advance Information 2002 Microchip Technology Inc. dsPIC30F 20.7 EQUATION 20-2: A/D Sampling Requirements For the A/D converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The analog input model is shown in Figure 20-2. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), see Figure 20-2. The impedance for analog sources must be small enough to meet accuracy requirements at the given speed. After the analog input channel is selected (changed), this sampling must be done before the conversion can be started. = VI * (1 - e (-TC/CHOLD (RIC+RSS+RS))) 1 - (VO / VI) = e (-TC/CHOLD (RIC+RSS+RS)) VO VI = VIN - VREF- VO = n * LSB - 1/2 LSB VO / VI = (n * LSB - 1/2 LSB) / n * LSB 1 - (VO / VI) = 1 / 2n 1 / 2n = e (-TC/CHOLD (RIC+RSS+RS)) = CHOLD * (RIC+RSS+RS) * -In(1/2 * n) TC TSMP = Amplifier Settling Time + Holding Capacitor Charging Time (TC) + Temperature Coefficient The temperature coefficient is only required for temperatures > 25C. To calculate the minimum sampling time, Equation 20-2 may be used. This equation assumes that the input is stepped some multiple (n) of the LSB step size and the output must be captured to within 1/2 LSb error (2096 steps for 10-bit A/D). TSMP = 0.5 ms + CHOLD * (RIC+RSS+RS) * -In(1/2 * n) + [(Temp - 25C)(0.05 ms/C)] The CHOLD is assumed to be 5 pF for the A/D converter. FIGURE 20-2: A/D SAMPLING TIME EQUATIONS ANALOG INPUT MODEL VDD Rs VT = 0.6V ANx CPIN 5 pF VA VT = 0.6V Sampling Switch RIC 250 SS RSS CHOLD = DAC capacitance = 5 pF I leakage 500 nA VSS Legend: CPIN = input capacitance VT = threshold voltage I leakage = leakage current at the pin due to various junctions RIC SS CHOLD Sampling 3.5 Switch 3.0 (Rss k) 2.5 = interconnect resistance = sampling switch = sample/hold capacitance (from DAC) 2.0 1.5 1.0 0.5 0 2 3 4 5 6 VDD (V) Note: Values shown here are untested typical values, for reference only. Exact electrical specifications are to be determined. 2002 Microchip Technology Inc. Advance Information DS70082A-page 137 dsPIC30F 20.8 Module Power-down Modes The module has 3 internal Power modes. When the ADON bit is 1, the module is in Active mode and is fully powered and functional. When ADON is 0 and ADSTBY is 1, the module is in Standby mode. In Standby mode, the digital portions of the module are active; however, the analog portions are powered down, including the bias generators. The A/D module can operate during SLEEP mode, if the A/D clock source is set to RC (ADRC = 1). When the RC clock source is selected, the A/D module waits for one instruction cycle before starting the conversion. This allows the SLEEP instruction to be executed, which eliminates all digital switching noise from the conversion. When the conversion is completed, the CONV bit will be cleared and the result loaded into the ADRES register. When ADON is 0 and ADSTBY is 0, the module is in Off mode. The digital and analog portions of the circuit are disabled for maximum current savings. If the A/D interrupt is enabled, the device will wake-up from SLEEP. If the A/D interrupt is not enabled, the A/D module will then be turned off, although the ADON bit will remain set. In order to return to the Active mode from Standby or Off mode, the user must wait for the bias generators to stabilize. 20.9.2 20.9 20.9.1 A/D Operation During CPU SLEEP and IDLE Modes A/D OPERATION DURING CPU SLEEP MODE When the device enters SLEEP mode, all clock sources to the module are shutdown and stay at logic `0'. If SLEEP occurs in the middle of a conversion, the conversion is aborted. The converter will not continue with a partially completed conversion on exiting from SLEEP mode. A/D OPERATION DURING CPU IDLE MODE For the A/D, the ADSIDL bit selects if the module will stop on IDLE or continue on IDLE. If ADSIDL = 0, the module will continue operation on assertion of IDLE mode. If ADSIDL = 1, the module will stop on IDLE. 20.10 Effects of a RESET A device RESET forces all registers to their RESET state. This forces the A/D module to be turned off, and any conversion and sampling sequence are aborted. The values that are in the ADRES registers are not modified. The A/D result register will contain unknown data after a Power-on Reset. Register contents are not affected by the device entering or leaving SLEEP mode. DS70082A-page 138 Advance Information 2002 Microchip Technology Inc. dsPIC30F 20.11 Output Formats The A/D result is 10-bits wide. The data buffer RAM is also 10-bits wide. The 10-bit data can be read in one of four different formats. The FORM<1:0> bits select the format. Each of the output formats translates to a 16-bit result on the data bus. Write data will always be in right justified (integer) format. FIGURE 20-3: A/D OUTPUT DATA FORMATS RAM Contents: d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 Read to Bus: Signed Fractional (1.15) d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 0 0 0 0 0 0 Fractional (1.15) d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 0 0 0 0 0 0 Signed Integer Integer d09 d09 d09 d09 d09 d09 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 0 0 0 0 0 0 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 20.12 Configuring Analog Port Pins 20.13 Connection Considerations The use of the ADPCFG and TRIS registers control the operation of the A/D port pins. The port pins that are desired as analog inputs must have their corresponding TRIS bit set (input). If the TRIS bit is cleared (output), the digital output level (VOH or VOL) will be converted. Since the analog inputs employ ESD protection, they have diodes to VDD and VSS. This requires that the analog input must be between VDD and VSS. If the input voltage exceeds this range by greater than 0.3V (either direction), one of the diodes becomes forward biased and it may damage the device if the input current specification is exceeded. The A/D operation is independent of the state of the CH0SA<3:0>/CH0SB<3:0> bits and the TRIS bits. When reading the PORT register, all pins configured as analog input channel will read as cleared (a low level). Pins configured as digital inputs, will not convert an analog input. Analog levels on any pin that is defined as a digital input (including the ANx pins), may cause the input buffer to consume current that exceeds the device specifications. 2002 Microchip Technology Inc. An external RC filter is sometimes added for antialiasing of the input signal. The R component should be selected to ensure that the sampling time requirements are satisfied. Any external components connected (via high impedance) to an analog input pin (capacitor, zener diode, etc.) should have very little leakage current at the pin. Advance Information DS70082A-page 139 DS70082A-page 140 02A6 02A8 PCFG15 PCFG14 02AA CSSL15 CSSL14 u = uninitialized bit ADCHS ADPCFG ADCSSL Legend: -- CH123NB<1:0> -- -- ADSIDL -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 13 CSSL13 PCFG13 CH123SB VCFG<2:0> -- -- -- -- 02A4 ADON -- -- -- ADCON3 -- -- 02A2 -- -- -- ADCON2 0296 ADCBUFB -- -- 02A0 0294 ADCBUFA -- -- ADCON1 0292 ADCBUF9 -- -- 029E 0290 ADCBUF8 -- -- ADCBUFF 028E ADCBUF7 -- -- 029C 028C ADCBUF6 -- -- ADCBUFE 028A ADCBUF5 -- -- 029A 0288 ADCBUF4 -- -- -- ADCBUFD 0286 ADCBUF3 -- -- 0298 0284 ADCBUF2 -- Bit 14 ADCBUFC 0282 ADCBUF1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CSCNA -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 10 Bit 8 CHPS<1:0> FORM<1:0> Bit 9 CH0SB<3:0> SAMC<4:0> Bit 11 CSSL12 CSSL11 CSSL10 CSSL9 CSSL8 PCFG12 PCFG11 PCFG10 PCFG9 PCFG8 CH0NB OFFCAL ADSTBY -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 12 Bit 15 0280 SFR Name Addr. ADCBUF0 ADC REGISTER MAP TABLE 20-2: -- -- CSSL7 PCFG7 CSSL6 PCFG6 Bit 5 Bit 4 ADC Data Buffer 9 ADC Data Buffer 8 ADC Data Buffer 7 ADC Data Buffer 6 ADC Data Buffer 5 ADC Data Buffer 4 ADC Data Buffer 3 ADC Data Buffer 2 ADC Data Buffer 1 ADC Data Buffer 0 CSSL5 PCFG5 CH123SA SIMSAM Bit 3 CSSL4 PCFG4 CH0NA ASAM Bit 2 CSSL3 PCFG3 BUFM SAMP Bit 1 ALTS CONV Bit 0 RESET State 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu CSSL2 CSSL1 CSSL0 0000 0000 0000 0000 PCFG2 PCFG1 PCFG0 0000 0000 0000 0000 CH0SA<3:0> ADCS<5:0> SMPI<3:0> -- ADC Data Buffer 15 ADC Data Buffer 14 ADC Data Buffer 13 ADC Data Buffer 12 ADC Data Buffer 11 ADC Data Buffer 10 SSRC<2:0> Bit 6 CH123NA<1:0> ADRC BUFS Bit 7 dsPIC30F Advance Information 2002 Microchip Technology Inc. dsPIC30F 21.0 SYSTEM INTEGRATION There are several features intended to maximize system reliability, minimize cost through elimination of external components, provide Power Saving Operating modes and offer code protection: * Oscillator Selection * RESET - Power-on Reset (POR) - Power-up Timer (PWRT) - Oscillator Start-up Timer (OST) - Programmable Brown-out Reset (BOR) * Watchdog Timer (WDT) * Power Saving modes (SLEEP and IDLE) * Code Protection * Unit ID Locations * In-Circuit Serial Programming (ICSP) dsPIC30F devices have a Watchdog Timer, which is permanently enabled via the configuration bits, or it can be software controlled. It runs off its own RC oscillator for added reliability. There are two timers that offer necessary delays on power-up. One is the Oscillator Startup Timer (OST), intended to keep the chip in RESET until the crystal oscillator is stable. The other is the Power-up Timer (PWRT), which provides a delay on power-up only, designed to keep the part in RESET while the power supply stabilizes. With these two timers on-chip, most applications need no external RESET circuitry. TABLE 21-1: 21.1 Overview The dsPIC30F oscillator system has the following modules and features: * Various external and internal oscillator options as clock sources * An on-chip PLL to boost internal operating frequency * A clock switching mechanism between various clock sources * Programmable clock postscaler for system power savings * A Fail-Safe Clock Monitor (FSCM) that detects clock failure and takes fail-safe measures * Clock Control Register OSCCON * Configuration bits for main oscillator selection Table 21-1 provides a summary of the dsPIC30F Oscillator Operating modes. A simplified diagram of the oscillator system is shown in Figure 21-1. OSCILLATOR OPERATING MODES Oscillator Mode XTL XT XT w/ PLL 4x XT w/ PLL 8x XT w/ PLL 16x LP HS EC ECIO EC w/ PLL 4x EC w/ PLL 8x EC w/ PLL 16x ERC ERCIO FRC LPRC SLEEP mode is designed to offer a very low current Power-down mode. The user can wake-up from SLEEP through external RESET, Watchdog Timer Wake-up or through an interrupt. Several oscillator options are also made available to allow the part to fit the application. In the IDLE mode, the clock sources are still active, but the CPU is shut-off. The RC oscillator option saves system cost, while the LP crystal option saves power. A set of configuration bits are used to select various options Description 200 kHz - 4 MHz crystal on OSC1:OSC2. 4 MHz - 10 MHz crystal on OSC1:OSC2. 4 MHz - 10 MHz crystal on OSC1:OSC2. 4x PLL enabled. 4 MHz - 10 MHz crystal on OSC1:OSC2. 8x PLL enabled. 4 MHz - 10 MHz crystal on OSC1:OSC2. 16x PLL enabled(1). 32 kHz crystal on SOSC1:SOSC2(2). 10 MHz - 25 MHz crystal. External clock input (0 - 40 MHz). External clock input (0 - 40 MHz). OSC2 pin is I/O. External clock input (0 - 40 MHz). OSC2 pin is I/O. 4x PLL enabled(1). External clock input (0 - 40 MHz). OSC2 pin is I/O. 8x PLL enabled(1). External clock input (0 - 40 MHz). OSC2 pin is I/O. 16x PLL enabled(1). External RC oscillator. OSC2 pin is FOSC/4 output(3). External RC oscillator. OSC2 pin is I/O(3). 8 MHz internal RC Oscillator. 32 kHz internal RC Oscillator. Note 1: dsPIC30F maximum operating frequency of 120 MHz must be met. 2: LP oscillator can be conveniently shared as system clock, as well as real-time clock for Timer1. 3: Requires external R and C. Frequency operation up to 4 MHz. 2002 Microchip Technology Inc. Advance Information DS70082A-page 141 dsPIC30F Configuration bits determine the clock source upon Power-on Reset (POR) and Brown-out Reset (BOR). Thereafter, clock source can be changed between per- FIGURE 21-1: missible clock sources. The OSCCON register controls the clock switching and reflects system clock related status bits. OSCILLATOR SYSTEM BLOCK DIAGRAM Oscillator Configuration bits PWRSAV Instruction Wake-up Request OSC1 OSC2 FPLL Primary Oscillator PLL PLL x4, x8, x16 Lock COSC<1:0> Primary Osc NOSC<1:0> Primary OSWEN Oscillator Stability Detector Oscillator POR Done Start-up Clock Timer Secondary Osc Switching Programmable and Control Clock Divider Block SOSC1 SOSC2 32 kHz LP Oscillator System Clock Secondary 2 Oscillator Stability Detector Internal Fast RC POST<1:0> FRC Oscillator (FRC) Internal Low LPRC Power RC Oscillator (LPRC) Fail-Safe Clock FCKSM<1:0> 2 Monitor (FSCM) CF Oscillator Trap to Timer1 DS70082A-page 142 Advance Information 2002 Microchip Technology Inc. dsPIC30F 21.2 21.2.1 Oscillator Configurations INITIAL CLOCK SOURCE SELECTION While coming out of Power-on Reset or Brown-out Reset, the device selects its clock source based on: a) FOS<1:0> configuration bits that select one of four oscillator groups. AND FPR<3:0> configuration bits that select one of 13 oscillator choices within the primary group. b) The selection is as shown in Table 21-2. TABLE 21-2: CONFIGURATION BIT VALUES FOR CLOCK SELECTION Oscillator Mode Oscillator Source FOS1 FOS0 FPR3 FPR2 FPR1 FPR0 OSC2 Function EC Primary 1 1 1 0 1 1 CLKO ECIO Primary 1 1 1 1 0 0 I/O EC w/ PLL 4x Primary 1 1 1 1 0 1 I/O EC w/ PLL 8x Primary 1 1 1 1 1 0 I/O EC w/ PLL 16x Primary 1 1 1 1 1 1 I/O ERC Primary 1 1 1 0 0 1 CLKO ERCIO Primary 1 1 1 0 0 0 I/O XT Primary 1 1 0 1 0 0 OSC2 XT w/ PLL 4x Primary 1 1 0 1 0 1 OSC2 XT w/ PLL 8x Primary 1 1 0 1 1 0 OSC2 XT w/ PLL 16x Primary 1 1 0 1 1 1 OSC2 XTL Primary 1 1 0 0 0 X OSC2 HS Primary 1 1 0 0 1 X OSC2 LP Secondary 0 0 - - - - (Notes 1, 2) FRC Internal FRC 0 1 - - - - (Notes 1, 2) LPRC Internal LPRC 1 0 - - - - (Notes 1, 2) Note 1: OSC2 pin function is determined by the Primary Oscillator mode selection (FPR<3:0>). 2: Note that OSC1 pin cannot be used as an I/O pin, even if the secondary oscillator or an internal clock source is selected at all times. 2002 Microchip Technology Inc. Advance Information DS70082A-page 143 dsPIC30F 21.2.2 OSCILLATOR START-UP TIMER (OST) In order to ensure that a crystal oscillator (or ceramic resonator) has started and stabilized, an oscillator start-up timer is included. It is a simple 10-bit counter that counts 1024 TOSC cycles before releasing the oscillator clock to the rest of the system. The time-out period is designated as TOST. The TOST time is involved every time the oscillator has to restart, i.e., on POR, BOR and wake-up from SLEEP. The oscillator start-up timer is applied to the LP Oscillator, XT, XTL, and HS modes (upon wake-up from SLEEP, POR and BOR) for the primary oscillator. 21.2.3 LP OSCILLATOR CONTROL Enabling the LP oscillator is controlled by two elements: 1. 2. The current oscillator group bits COSC<1:0>. The LPOSCEN bit (OSCON register). In normal Operating mode, the LP oscillator is ON if: * COSC<1:0> = 00 (LP selected as main oscillator) or * LPOSCEN = 1 In SLEEP mode, the LP oscillator is ON if LPOSCEN = 1. In IDLE mode, the LP oscillator is ON if: * COSC<1:0> = 00 (LP selected as main oscillator) or * LPOSCEN = 1 Keeping the LP oscillator ON at all times allows for a fast switch to the 32 kHz system clock for lower power operation. Returning to the faster main oscillator will still require a start-up time 21.2.4 PHASE LOCKED LOOP (PLL) The PLL multiplies the clock which is generated by the primary oscillator. The PLL is selectable to have either gains of x4, x8, and x16. Input and output frequency ranges are summarized in the table below. TABLE 21-3: 21.2.5 FAST RC OSCILLATOR (FRC) The FRC oscillator is a fast (8 MHz nominal) internal RC oscillator. This oscillator is intended to provide reasonable device operating speeds without the use of an external crystal, ceramic resonator, or RC network. The dsPIC30F operates from the FRC Oscillator whenever the Current Oscillator Selection Control bits in the OSCCON register (OSCCON<13:12>) are set to `01'. 21.2.6 LOW POWER RC OSCILLATOR (LPRC) The LPRC oscillator is a component of the Watchdog Timer (WDT) and oscillates at a nominal frequency of 512 kHz. The LPRC oscillator is the clock source for the Power-up Timer (PWRT) circuit, WDT, and clock monitor circuits. It may also be used to provide a low frequency clock source option for applications where power consumption is critical, and timing accuracy is not required The LPRC oscillator is always enabled at a Power-on Reset, because it is the clock source for the PWRT. After the PWRT expires, the LPRC oscillator will remain ON if one of the following is TRUE: * The Fail-Safe Clock Monitor is enabled * The WDT is enabled * The LPRC oscillator is selected as the system clock via the COSC<1:0> control bits in the OSCCON register If one of the above conditions is not true, the LPRC will shut-off after the PWRT expires. Note 1: OSC2 pin function is determined by the Primary Oscillator mode selection (FPR<3:0>). 2: Note that OSC1 pin cannot be used as an I/O pin, even if the secondary oscillator or an internal clock source is selected at all times. PLL FREQUENCY RANGE FIN PLL Multiplier 4 MHz - 10 MHz 4 MHz - 10 MHz x4 x8 16 MHz - 40 MHz 32 MHz - 80 MHz 4 MHz - 7.5 MHz x16 64 MHz - 160 MHz FOUT The PLL features a lock output, which is asserted when the PLL enters a phase locked state. Should the loop fall out of lock (e.g., due to noise), the lock signal will be rescinded. The state of this signal is reflected in the read only LOCK bit in the OSCCON register. DS70082A-page 144 Advance Information 2002 Microchip Technology Inc. dsPIC30F 21.2.7 FAIL-SAFE CLOCK MONITOR The Fail-Safe Clock Monitor (FSCM) allows the device to continue to operate even in the event of an oscillator failure. The FSCM function is enabled by appropriately programming the FCKSM configuration bits (Clock Switch and Monitor Selection bits) in the FOSC device configuration register. If the FSCM function is enabled, the LPRC Internal oscillator will run at all times (except during SLEEP mode) and will not be subject to control by the SWDTEN bit. In the event of an oscillator failure, the FSCM will generate a Clock Failure Trap event and will switch the system clock over to the FRC oscillator. The user will then have the option to either attempt to restart the oscillator or execute a controlled shutdown. The user may decide to treat the Trap as a warm RESET by simply loading the RESET address into the oscillator fail trap vector. In this event, the CF (Clock Fail) status bit (OSCCON<3>) is also set whenever a clock failure is recognized. In the event of a clock failure, the WDT is unaffected and continues to run on the LPRC clock. If the oscillator has a very slow start-up time coming out of POR, BOR or SLEEP, it is possible that the PWRT timer will expire before the oscillator has started. In such cases, the FSCM will be activated and the FSCM will initiate a Clock Failure Trap, and the COSC<1:0> bits are loaded with FRC oscillator selection. This will effectively shut-off the original oscillator that was trying to start. The user may detect this situation and restart the oscillator in the Clock Fail Trap ISR. Upon a clock failure detection the FSCM module will initiate a clock switch to the FRC Oscillator as follows: 1. 2. 3. The COSC bits (OSCCON<13:12>) are loaded with the FRC Oscillator selection value. CF bit is set (OSCCON<3>). OSWEN control bit (OSCCON<0>) is cleared. The OSCCON register holds the CONTROL and STATUS bits related to clock switching. * COSC<1:0>: Read only status bits always reflect the current oscillator group in effect. * NOSC<1:0>: Control bits which are written to indicate the new oscillator group of choice. - On POR and BOR, COSC<1:0> and NOSC<1:0> are both loaded with the Configuration bit values FOS<1:0>. * LOCK: The LOCK status bit indicates a PLL lock. * CF: Read only status bit indicating if a clock fail detect has occurred. * OSWEN: Control bit changes from a `0' to a `1' when a clock transition sequence is initiated. Clearing the OSWEN control bit will abort a clock transition in progress (used for hang-up situations). If configuration bits FCKSM<1:0> = 1x, then the clock switching function and the fail-safe clock monitor function are disabled. This is the default configuration bit setting. If clock switching is disabled, then the FOS<1:0> and FPR<3:0> bits directly control the oscillator selection and the COSC<1:0> bits do not control the clock selection. However, these bits will reflect the clock source selection. 21.2.8 PROTECTION AGAINST ACCIDENTAL WRITES TO OSCCON A write to the OSCCON register is intentionally made difficult, because it controls clock switching and clock scaling. To write to the OSCCON low byte, the following code sequence must be executed without any other instructions in between: * Byte Write "0x46" to OSCCON low * Byte Write "0x57" to OSCCON low For the purpose of clock switching, the clock sources are sectioned into four groups: Byte Write is allowed for one instruction cycle. Write desired value or use bit manipulation instruction. 1. 2. 3. 4. To write to the OSCCON high byte, the following instructions must be executed without any other instructions in between: Primary Secondary Internal FRC Internal LPRC The user can switch between these functional groups, but cannot switch between options within a group. If the primary group is selected, then the choice within the group is always determined by the FPR<3:0> configuration bits. 2002 Microchip Technology Inc. * Byte Write "0x78" to OSCCON high * Byte Write "0x9A" to OSCCON high Byte Write is allowed for one instruction cycle. Write "Desired Value" or use bit manipulation instruction. Advance Information DS70082A-page 145 dsPIC30F 21.3 RESET The dsPIC30F differentiates between various kinds of RESET: a) b) c) d) e) f) g) h) Power-on Reset (POR) MCLR Reset during normal operation MCLR Reset during SLEEP Watchdog Timer (WDT) Reset (during normal operation) Programmable Brown-out Reset (BOR) RESET Instruction Reset cause by trap lockup (TRAPR) Reset caused by illegal opcode, or by using an uninitialized W register as an address pointer (IOPUWR) FIGURE 21-2: Different registers are affected in different ways by various RESET conditions. Most registers are not affected by a WDT wake-up, since this is viewed as the resumption of normal operation. Status bits from the RCON register are set or cleared differently in different RESET situations, as indicated in Table 21-4. These bits are used in software to determine the nature of the RESET. A block diagram of the on-chip RESET circuit is shown in Figure 21-2. A MCLR noise filter is provided in the MCLR Reset path. The filter detects and ignores small pulses. Internally generated RESETS do not drive MCLR pin low. RESET SYSTEM BLOCK DIAGRAM RESET Instruction Digital Glitch Filter MCLR SLEEP or IDLE WDT Module VDD Rise Detect POR S VDD Brown-out Reset BOR BOREN R Q SYSRST TRAP Conflict Illegal Opcode/ Uninitialized W Register 21.3.1 POR: POWER-ON RESET A power-on event will generate an internal POR pulse when a VDD rise is detected. The Reset pulse will occur at the POR circuit threshold voltage (VPOR), which is nominally 1.85V. The device supply voltage characteristics must meet specified starting voltage and rise rate requirements. For more information, please refer to the Electrical Specifications section (TBD). The POR pulse will reset a POR timer and place the device in the RESET state. The POR also selects the device clock source identified by the oscillator configuration fuses. DS70082A-page 146 The POR circuit inserts a small delay, TPOR, which is nominally 10 s and ensures that the device bias circuits are stable. Furthermore, a user selected powerup time-out (TPWRT) is applied. The TPWRT parameter is based on device configuration bits and can be 0 ms (no delay), 4 ms, 16 ms, or 64 ms. The total delay is at device power-up TPOR + TPWRT. When these delays have expired, SYSRST will be negated on the next leading edge of the Q1 clock, and the PC will jump to the RESET vector. The timing for the SYSRST signal is shown in Figure 21-3 through Figure 21-5. Advance Information 2002 Microchip Technology Inc. dsPIC30F FIGURE 21-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD) VDD MCLR INTERNAL POR TOST OST TIME-OUT TPWRT PWRT TIME-OUT INTERNAL RESET FIGURE 21-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 VDD MCLR INTERNAL POR TOST OST TIME-OUT TPWRT PWRT TIME-OUT INTERNAL RESET FIGURE 21-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 VDD MCLR INTERNAL POR TOST OST TIME-OUT TPWRT PWRT TIME-OUT INTERNAL RESET 2002 Microchip Technology Inc. Advance Information DS70082A-page 147 dsPIC30F 21.3.1.1 POR with Long Crystal Start-up Time (with FSCM Enabled) The oscillator start-up circuitry is not linked to the POR circuitry. Some crystal circuits (especially low frequency crystals) will have a relatively long start-up time. Therefore, one or more of the following conditions is possible after the POR timer and the PWRT have expired: A BOR will generate a RESET pulse which will reset the device. The BOR will select the clock source, based on the device configuration bit values (FOS<1:0> and FPR<3:0>). Furthermore, if an Oscillator mode is selected, the BOR will activate the Oscillator Start-up Timer (OST). The system clock is held until OST expires. If the PLL is used, then the clock will be held until the LOCK bit (OSCCON<5>) is "1". * The oscillator circuit has not begun to oscillate. * The oscillator start-up timer has NOT expired (if a crystal oscillator is used). * The PLL has not achieved a LOCK (if PLL is used). Concurrently, the POR time-out (TPOR) and the PWRT time-out (TPWRT) will be applied before the internal RESET is released. If TPWRT = 0 and a crystal oscillator is being used, then a nominal delay of TFSCM = 100 s is applied. The total delay in this case is (TPOR + TFSCM). If the FSCM is enabled and one of the above conditions is true, then a Clock Failure Trap will occur. The device will automatically switch to the FRC oscillator and the user can switch to the desired crystal oscillator in the trap ISR. The BOR status bit (RCON<1>) will be set to indicate that a BOR has occurred. The BOR circuit, if enabled, will continue to operate while in SLEEP or IDLE modes and will reset the device should VDD fall below the BOR threshold voltage. 21.3.1.2 Operating without FSCM and PWRT FIGURE 21-6: If the FSCM is disabled and the Power-up Timer (PWRT) is also disabled, then on a power-up, the device will exit from RESET rapidly. If the clock source is FRC, LPRC, EXTRC or EC, it will be active immediately. VDD D If the FSCM is disabled and the system clock has not started, the device will be in a frozen state at the RESET vector, until the system clock starts. From the user's perspective, the device will appear to be in RESET until a system clock is available. 21.3.2 BOR: PROGRAMMABLE BROWN-OUT RESET The BOR (Brown-out Reset) module is based on an internal voltage reference circuit. The main purpose of the BOR module is to generate a device RESET when a brown-out condition occurs. Brown-out conditions are generally caused by glitches on the AC mains, i.e., missing waveform portions of the AC cycles due to bad power transmission lines, or voltage sags due to excessive current draw when a large inductive load is turned on. The BOR module allows selection of one of the following voltage trip points: * * * * 2.0V 2.7V 4.2V 4.5V Note: DS70082A-page 148 R R1 C MCLR dsPIC30F Note 1: External Power-on Reset circuit is required only if the VDD power-up slope is too slow. The diode D helps discharge the capacitor quickly when VDD powers down. 2: R should be suitably chosen so as to make sure that the voltage drop across R does not violate the device's electrical specification. 3: R1 should be suitably chosen so as to limit any current flowing into MCLR from external capacitor C, in the event of MCLR/VPP pin breakdown due to Electrostatic Discharge (ESD), or Electrical Overstress (EOS). Note: The BOR voltage trip points indicated here are nominal values provided for design guidance only. Refer to the Electrical Specifications in the specific device data sheet for BOR voltage limit specifications. EXTERNAL POWER-ON RESET CIRCUIT (FOR SLOW VDD POWER-UP) Dedicated supervisory devices, such as the MCP1XX and MCP8XX, may also be used as an external Power-on Reset circuit. Table 21-4 shows the RESET conditions for the RCON Register. Since the control bits within the RCON register are R/W, the information in the table implies that all the bits are negated prior to the action specified in the condition column. Advance Information 2002 Microchip Technology Inc. dsPIC30F TABLE 21-4: INITIALIZATION CONDITION FOR RCON REGISTER CASE 1 Condition Program Counter TRAPR IOPUWR EXTR SWR WDTO IDLE SLEEP POR BOR Power-on Reset 0x000000 0 0 0 0 0 0 0 1 1 Brown-out Reset 0x000000 0 0 0 0 0 0 0 0 1 MCLR Reset during normal operation 0x000000 0 0 1 0 0 0 0 0 0 Software Reset during normal operation 0x000000 0 0 0 1 0 0 0 0 0 MCLR Reset during SLEEP 0x000000 0 0 1 0 0 0 1 0 0 MCLR Reset during IDLE 0x000000 0 0 1 0 0 1 0 0 0 WDT Time-out Reset 0x000000 0 0 0 0 1 0 0 0 0 PC + 2 0 0 0 0 1 0 1 0 0 Interrupt Wake-up from SLEEP (1) PC + 2 0 0 0 0 0 0 1 0 0 Clock Failure Trap 0x000004 0 0 0 0 0 0 0 0 0 Trap Reset 0x000000 1 0 0 0 0 0 0 0 0 Illegal Operation Trap 0x000000 0 1 0 0 0 0 0 0 0 WDT Wake-up Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0' Note 1: When the wake-up is due to an enabled interrupt, the PC is loaded with the corresponding interrupt vector. Table 21-5 shows a second example of the bit conditions for the RCON Register. In this case, it is not assumed the user has set/cleared specific bits prior to action specified in the condition column. TABLE 21-5: INITIALIZATION CONDITION FOR RCON REGISTER CASE 2 Condition Program Counter TRAPR IOPUWR EXTR SWR WDTO IDLE SLEEP POR BOR Power-on Reset 0x000000 0 0 0 0 0 0 0 1 1 Brown-out Reset 0x000000 u u u u u u u 0 1 MCLR Reset during normal operation 0x000000 u u 1 0 0 0 0 u u Software Reset during normal operation 0x000000 u u 0 1 0 0 0 u u MCLR Reset during SLEEP 0x000000 u u 1 u 0 0 1 u u MCLR Reset during IDLE 0x000000 u u 1 u 0 1 0 u u WDT Time-out Reset 0x000000 u u 0 0 1 0 0 u u PC + 2 u u u u 1 u 1 u u Interrupt Wake-up from SLEEP (1) PC + 2 u u u u u u 1 u u Clock Failure Trap 0x000004 u u u u u u u u u Trap Reset 0x000000 1 u u u u u u u u Illegal Operation Reset 0x000000 u 1 u u u u u u u WDT Wake-up Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0' Note 1: When the wake-up is due to an enabled interrupt, the PC is loaded with the corresponding interrupt vector. 2002 Microchip Technology Inc. Advance Information DS70082A-page 149 dsPIC30F 21.4 21.4.1 Watchdog Timer (WDT) The processor wakes up from SLEEP if at least one of the following conditions is true: WATCHDOG TIMER OPERATION The primary function of the Watchdog Timer (WDT) is to reset the processor in the event of a software malfunction. The WDT is a free running timer, which runs off an on-chip RC oscillator, requiring no external component. Therefore, the WDT timer will continue to operate even if the main processor clock (e.g., the crystal oscillator) fails. 21.4.2 ENABLING AND DISABLING THE WDT The Watchdog Timer can be "Enabled" or "Disabled" only through a configuration bit (FWDTEN) in the configuration register FWDT. Setting FWDTEN = 1 enables the Watchdog Timer. The enabling is done when programming the device. By default, after chip-erase, FWDTEN bit = 1. Any device programmer capable of programming dsPIC30F devices allows programming of this and other configuration bits to the desired state. If enabled, the WDT will increment until it overflows or "times out". A WDT time-out will force a device RESET (except during SLEEP). To prevent a WDT time-out, the user must clear the Watchdog Timer using a CLRWDT instruction. If a WDT times out during SLEEP, the device will wakeup. The WDTO bit in the RCON register will be cleared to indicate a wake-up resulting from a WDT time-out. Setting FWDTEN = 0 allows user software to enable/ disable Watchdog Timer via the SWDTEN (RCON<5>) control bit. 21.5 Power Saving Modes There are two power saving states that can be entered through the execution of a special instruction, PWRSAV. These are: SLEEP and IDLE. * on occurrence of any interrupt that is individually enabled and meets the required priority level * on any Reset (POR, BOR and MCLR) * on WDT time-out On waking up from SLEEP mode, the processor will restart the same clock that was active prior to entry into SLEEP mode. When clock switching is enabled, bits COSC<1:0> will determine the oscillator source that will be used on wake-up. If clock switch is disabled, then there is only one system clock. Note: If the clock source is an oscillator, the clock to the device will be held off until OST times out (indicating a stable oscillator). If PLL is used, the system clock is held off until LOCK = 1 (indicating that the PLL is stable). In either case, TPOR, TLOCK and TPWRT delays are applied. If EC, FRC, LPRC or EXTRC oscillators are used, then a delay of TPOR (~ 10 s) is applied. This is the smallest delay possible on wake-up from SLEEP. Moreover, if LP oscillator was active during SLEEP, and LP is the oscillator used on wake-up, then the start-up delay will be equal to TPOR. PWRT delay and OST timer delay are not applied. In order to have the smallest possible start-up delay when waking up from SLEEP, then one of these faster wake-up options should be selected before entering SLEEP. Any interrupt that is individually enabled (using the corresponding IE bit) and meets the prevailing priority level will be able to wake-up the processor. The processor will process the interrupt and branch to the ISR. The SLEEP status bit in RCON register is set upon wake-up. Note: The format of the PWRSAV instruction is as follows: PWRSAV <parameter>, where `parameter' defines IDLE or SLEEP mode. 21.5.1 SLEEP MODE In SLEEP mode, the clock to the CPU and the peripherals is shutdown. If an on-chip oscillator is being used, it is shutdown. The fail-safe clock monitor is not functional during SLEEP, since there is no clock to monitor. However, LPRC clock remains active if WDT is operational during SLEEP. The Brown-out protection circuit and the Low Voltage Detect circuit, if enabled, will remain functional during SLEEP. DS70082A-page 150 If a POR or BOR occurred, the selection of the oscillator is based on the FOS<1:0> and FPR<3:0> configuration bits. In spite of various delays applied (TPOR, TLOCK and TPWRT), the crystal oscillator (and PLL) may not be active at the end of the time-out, e.g., for low frequency crystals. In such cases, if FSCM is enabled, then the device will detect this as a clock failure and process the Clock Failure Trap, the FRC oscillator will be enabled, and the user will have to re-enable the crystal oscillator. If FSCM is not enabled, then the device will simply suspend execution of code until the clock is stable, and will remain in SLEEP until the oscillator clock has started. All RESETS will wake-up the processor from SLEEP mode. Any RESET, other than POR, will set the SLEEP status bit. In a POR, the SLEEP bit is cleared. Advance Information 2002 Microchip Technology Inc. dsPIC30F If Watchdog Timer is enabled, then upon WDT timeout, the processor will wake-up from SLEEP mode. SLEEP and WDTO status bits are both set. 21.5.2 IDLE MODE In IDLE mode, the clock to the CPU is shutdown while peripherals keep running. Unlike SLEEP mode, the clock source remains active. Several peripherals have a control bit in each module, that allows them to operate during IDLE. 21.6 The configuration bits in each device configuration register specify some of the Device modes and are programmed by a device programmer, or by using the InCircuit Serial Programming (ICSP) feature of the device. Each device configuration register is a 24-bit register, but only the lower 16 bits of each register are used to hold configuration data. There are four device configuration registers available to the user: 1. LPRC fail-safe clock remains active if clock failure detect is enabled. 2. The processor wakes up from IDLE if at least one of the following conditions is true: 3. * on any interrupt that is individually enabled (IE bit is `1') and meets the required priority level * on any Reset (POR, BOR, MCLR) * on WDT time-out Upon wake-up from IDLE mode, the clock is re-applied to the CPU and instruction execution begins immediately, starting with the instruction following the PWRSAV instruction. Any interrupt that is individually enabled (using IE bit) and meets the prevailing priority level, will be able to wake-up the processor. The processor will process the interrupt and branch to the ISR. The IDLE status bit in RCON register is set upon wake-up. Any RESET, other than POR, will set the IDLE status bit. On a POR, the IDLE bit is cleared. If Watchdog Timer is enabled, then upon WDT timeout, the processor will wake-up from IDLE mode. IDLE and WDTO status bits are both set. Unlike wake-up from SLEEP, there are no time delays involved in wake-up from IDLE. Device Configuration Registers 4. FOSC (0xF80000): Oscillator Configuration Register FWDT (0xF80002): Watchdog Timer Configuration Register FBORPOR (0xF80004): BOR and POR Configuration Register FGS (0xF8000A): General Code Segment Configuration Register The placement of the configuration bits is automatically handled when you select the device in your device programmer. The desired state of the configuration bits may be specified in the source code (dependent on the language tool used), or through the programming interface. After the device has been programmed, the application software may read the configuration bit values through the table read instructions. For additional information, please refer to the Programming Specifications of the device. 21.7 Peripheral Module Disable (PMD) Registers The peripheral module disable (PMD) registers provide a method to disable a peripheral module by stopping all clock sources supplied to that module. When a peripheral is disabled via the appropriate PMD control bit, the peripheral is in a minimum power consumption state. The control and status registers associated with the peripheral will also be disabled, so writes to those registers will have no effect and read values will be invalid. A peripheral module will only be enabled if both the associated bit in the the PMD register is cleared, and the peripheral is supported by the specific dsPIC variant. If the peripheral is present in the device, it is enabled in the PMD register by default. 2002 Microchip Technology Inc. Advance Information DS70082A-page 151 DS70082A-page 152 0772 IC8MD IC7MD u = uninitialized bit PMD2 Legend: Bit 13 T4MD IC6MD T3MD IC5MD T2MD COSC<1:0> LVDEN Bit 12 IC4MD T1MD -- Bit 11 Bit 9 IC3MD F80002 F80004 F8000A FWDT FBORPOR FGS Addr. F80000 -- -- -- -- Bits 23-16 Bit 14 -- MCLREN FWDTEN -- -- -- FSCKM<1:0> Bit 15 -- -- -- -- Bit 13 Bit 8 IC2MD -- -- -- -- Bit 12 -- -- -- -- Bit 11 IC1MD -- NOSC<1:0> QEIMD PWMMD -- LVDL<3:0> Bit 10 DEVICE CONFIGURATION REGISTER MAP T5MD FOSC File Name TABLE 21-7: 0770 -- PMD1 -- 0742 OSCCON Bit 14 TRAPR IOPUWR BGST Bit 15 0740 Addr. SYSTEM INTEGRATION REGISTER MAP RCON SFR Name TABLE 21-6: SWR Bit 6 U2MD -- PWMPIN -- -- Bit 10 Bit 8 OC6MD U1MD LOCK SWDTEN Bit 5 -- HPOL -- -- LPOL -- FGS<1:0> Bit 9 OC8MD OC7MD I2CMD POST<1:0> EXTR Bit 7 CF SLEEP Bit 3 -- BOREN -- -- Bit 7 OC5MD C2MD -- IDLE Bit 2 -- -- -- -- Bit 6 -- Bit 4 OC2MD C1MD -- BORV<1:0> -- POR Bit 0 Depends on type of RESET. RESET State 0000 0000 0000 0000 -- -- Bit 3 Bit 1 -- -- Bit 0 GCP GWRP FPWRT<1:0> FWPSB<3:0> FG1<3:0> Bit 2 OC1MD 0000 0000 0000 0000 -- LPOSCEN OSWEN Depends on configuration bits. BOR Bit 1 FWPSA<1:0> -- Bit 5 OC4MD OC3MD SPI2MD SPI1MD -- WDTO Bit 4 dsPIC30F Advance Information 2002 Microchip Technology Inc. dsPIC30F 22.0 INSTRUCTION SET SUMMARY The dsPIC30F instruction set adds many enhancements to the previous PICmicro(R) instruction sets, while maintaining an easy migration from PICmicro instruction sets. Most instructions are a single program memory word (24-bits), but there are three instructions that require two program memory locations. Each single-word instruction is a 24-bit word divided into an 8-bit opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. The instruction set is highly orthogonal and is grouped into five basic categories: * * * * * Word or byte-oriented operations Bit-oriented operations Literal operations DSP operations Control operations The literal instructions that involve data movement may use some of the following operands: * A literal value to be loaded into a W register or file register (specified by the value of 'k') * The desired W register or file register to load the literal value into (specified by 'Wb' or 'f') However, literal instructions that involve arithmetic or logical operations use some of the following operands: * The first source operand, which is a register 'Wb' without any address modifier * The second source operand, which is a literal value * The destination of the result (only if not the same as the first source operand), which is typically a register 'Wd' with or without an address modifier The MAC class of DSP instructions may use some of the following operands: Table 22-1 shows the general symbols used in describing the instructions. The dsPIC30F instruction set summary in Table 22-2 lists all the instructions along with the status flags affected by each instruction. Most word or byte-oriented W register instructions (including barrel shift instructions) have three operands: * The first source operand, which is typically a register 'Wb' without any address modifier * The second source operand, which is typically a register 'Ws' with or without an address modifier * The destination of the result, which is typically a register 'Wd' with or without an address modifier However, word or byte-oriented file register instructions have two operands: * The file register specified by the value 'f' * The destination, which could either be the file register 'f' or the W0 register, which is denoted as 'WREG' The destination designator `d' specifies where the result of the operation is to be placed. If 'd' is zero, the result is placed in WREG. If 'd' is one, the result is placed in the file register specified in the instruction. * * * * * The accumulator (A or B) to be used The W registers to be used as the two operands The X and Y address space pre-fetch operations The X and Y address space pre-fetch destinations The accumulator write back destination The other DSP instructions do not involve any multiplication, and may include: * The accumulator to be used * The source or destination operand (designated as Wso or Wdo, respectively) with or without an address modifier * The amount of shift (in the case of accumulator shift instructions), specified by a W register 'Wn' or a literal value The control instructions may use some of the following operands: * A program memory address * The mode of the Table Read and Table Write instructions * No operand required All instructions are a single word, except for certain double-word instructions, which were made doubleword instructions so that all the required information is available in these 48-bits. In the second word, the 8 MSb's are 0's. If this second word is executed as an instruction (by itself), it will execute as a NOP. Most bit oriented instructions (including simple rotate/ shift instructions) have two operands: * The W register (with or without an address modifier) or file register (specified by the value of 'Ws' or 'f') * The bit in the W register or file register (specified by a literal value, or indirectly by the contents of register 'Wb') 2002 Microchip Technology Inc. Advance Information DS70082A-page 153 dsPIC30F Most single word instructions are executed in a single instruction cycle, unless a conditional test is true or the program counter is changed as a result of the instruction. In these cases, the execution takes two instruction cycles with the additional instruction cycle(s) executed as a NOP. Notable exceptions are the BRA (unconditional/computed branch), indirect CALL/GOTO, all Table Reads and Writes and RETURN/RETFIE instructions, which are single word instructions, but take two cycles. Certain instructions that involve skipping over the subsequent instruction, require either two or three cycles if the skip is performed, depending on whether the instruction being skipped is a single word or twoword instruction. Moreover, double-word moves require two cycles. TABLE 22-1: The double-word instructions execute in two instruction cycles. One instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 120 MHz, the normal instruction execution time is 0.033 s. If a conditional test is true or the program counter is changed as a result of an instruction, the instruction execution time is 0.066 s. Note: For more details on the instruction set, refer to the Programmer's Reference Manual. SYMBOLS USED IN ROADRUNNER OPCODE DESCRIPTIONS Field #text (text) .b .d .S .w [text] { } <n:m> Acc AWB bit3 bit4 C, DC, N, OV, Z d Expr f lit1 lit14 lit16 lit23 lit4 lit5 lit8 lit10 None OA, OB, SA, SB PC Slit10 Slit16 Slit5 Wb Wd DS70082A-page 154 Description Means literal defined by "text" Means "content of text" Byte mode selection Double-word mode selection Shadow register select Word mode selection (default) Means "the location addressed by text" Optional field or operation Register bit field One of two accumulators {A, B} Accumulator write back destination address register {W13, [W13]+=2} 3-bit bit selection field (used in byte addressed instructions) {0...7} 4-bit bit selection field (used in word addressed instructions) {0...15} MCU status bits: Carry, Digit Carry, Negative, Overflow, Sticky-Zero File register destination d {WREG, none} Absolute address, label or expression (resolved by the linker) File register address {0x0000...0x1FFF} 1-bit unsigned literal {0,1} 14-bit unsigned literal {0...16384} 16-bit unsigned literal {0...65535} 23-bit unsigned literal {0...8388608}; LSB must be 0 4-bit unsigned literal {0...15} 5-bit unsigned literal {0...31} 8-bit unsigned literal {0...255} 10-bit unsigned literal {0...255} for Byte mode, {0:1023} for Word mode Field does not require an entry, may be blank DSP status bits: AccA Overflow, AccB Overflow, AccA Saturate, AccB Saturate Program Counter 10-bit signed literal {-512...511} 16-bit signed literal {-32768...32767} 5-bit signed literal {-16...15} Base W register {W0..W15} Destination W register { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] } Advance Information 2002 Microchip Technology Inc. dsPIC30F TABLE 22-1: SYMBOLS USED IN ROADRUNNER OPCODE DESCRIPTIONS (CONTINUED) Field Wdo Wm,Wn Wm*Wm Wm*Wn Wn Wnd Wns WREG Ws Wso Wx Wxd Wy Wyd 2002 Microchip Technology Inc. Description Destination W register { Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] } Dividend, Divisor working register pair (direct addressing) Multiplicand and Multiplier working register pair for Square instructions {W4*W4,W5*W5,W6*W6,W7*W7} Multiplicand and Multiplier working register pair for DSP instructions {W4*W5,W4*W6,W4*W7,W5*W6,W5*W7,W6*W7} One of 16 working registers {W0..W15} One of 16 destination working registers {W0..W15} One of 16 source working registers {W0..W15} W0 (working register used in file register instructions) Source W register { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] } Source W register { Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] } X data space pre-fetch address register for DSP instructions {[W8]+=6, [W8]+=4, [W8]+=2, [W8], [W8]-=6, [W8]-=4, [W8]-=2, [W9]+=6, [W9]+=4, [W9]+=2, [W9], [W9]-=6, [W9]-=4, [W9]-=2, [W9+W12],none} X data space pre-fetch destination register for DSP instructions {W4..W7} Y data space pre-fetch address register for DSP instructions {[W10]+=6, [W10]+=4, [W10]+=2, [W10], [W10]-=6, [W10]-=4, [W10]-=2, [W11]+=6, [W11]+=4, [W11]+=2, [W11], [W11]-=6, [W11]-=4, [W11]-=2, [W11+W12], none} Y data space pre-fetch destination register for DSP instructions {W4..W7} Advance Information DS70082A-page 155 dsPIC30F TABLE 22-2: Base Instr # 1 2 3 4 5 6 7 8 9 10 INSTRUCTION SET OVERVIEW Assembly Mnemonic ADD ADDC AND ASR BCLR BRA BSET BSW BTG BTSC Assembly Syntax Description # of # of words cycles Status Flags Affected ADD Acc Add Accumulators 1 1 OA,OB,SA,SB ADD f f = f + WREG 1 1 C,DC,N,OV,Z ADD f,WREG WREG = f + WREG 1 1 C,DC,N,OV,Z ADD #lit10,Wn Wd = lit10 + Wd 1 1 C,DC,N,OV,Z ADD Wb,Ws,Wd Wd = Wb + Ws 1 1 C,DC,N,OV,Z ADD Wb,#lit5,Wd Wd = Wb + lit5 1 1 C,DC,N,OV,Z ADD Wso,#Slit4,Acc 16-bit Signed Add to Accumulator 1 1 OA,OB,SA,SB ADDC f f = f + WREG + (C) 1 1 C,DC,N,OV,Z ADDC f,WREG WREG = f + WREG + (C) 1 1 C,DC,N,OV,Z ADDC #lit10,Wn Wd = lit10 + Wd + (C) 1 1 C,DC,N,OV,Z ADDC Wb,Ws,Wd Wd = Wb + Ws + (C) 1 1 C,DC,N,OV,Z ADDC Wb,#lit5,Wd Wd = Wb + lit5 + (C) 1 1 C,DC,N,OV,Z AND f f = f .AND. WREG 1 1 N,Z AND f,WREG WREG = f .AND. WREG 1 1 N,Z AND #lit10,Wn Wd = lit10 .AND. Wd 1 1 N,Z AND Wb,Ws,Wd Wd = Wb .AND. Ws 1 1 N,Z AND Wb,#lit5,Wd Wd = Wb .AND. lit5 1 1 N,Z ASR f f = Arithmetic Right Shift f 1 1 C,N,OV,Z ASR f,WREG WREG = Arithmetic Right Shift f 1 1 C,N,OV,Z ASR Ws,Wd Wd = Arithmetic Right Shift Ws 1 1 C,N,OV,Z ASR Wb,Wns,Wnd Wnd = Arithmetic Right Shift Wb by Wns 1 1 N,Z ASR Wb,#lit5,Wnd Wnd = Arithmetic Right Shift Wb by lit5 1 1 N,Z BCLR f,#bit4 Bit Clear f 1 1 None BCLR Ws,#bit4 Bit Clear Ws 1 1 None BRA C,Expr Branch if Carry 1 1 (2) None BRA GE,Expr Branch if greater than or equal 1 1 (2) None BRA GEU,Expr Branch if unsigned greater than or equal 1 1 (2) None BRA GT,Expr Branch if greater than 1 1 (2) None BRA GTU,Expr Branch if unsigned greater than 1 1 (2) None BRA LE,Expr Branch if less than or equal 1 1 (2) None BRA LEU,Expr Branch if unsigned less than or equal 1 1 (2) None BRA LT,Expr Branch if less than 1 1 (2) None BRA LTU,Expr Branch if unsigned less than 1 1 (2) None BRA N,Expr Branch if Negative 1 1 (2) None BRA NC,Expr Branch if Not Carry 1 1 (2) None BRA NN,Expr Branch if Not Negative 1 1 (2) None BRA NOV,Expr Branch if Not Overflow 1 1 (2) None BRA NZ,Expr Branch if Not Zero 1 1 (2) None BRA OA,Expr Branch if accumulator A overflow 1 1 (2) None BRA OB,Expr Branch if accumulator B overflow 1 1 (2) None BRA OV,Expr Branch if Overflow 1 1 (2) None BRA SA,Expr Branch if accumulator A saturated 1 1 (2) None BRA SB,Expr Branch if accumulator B saturated 1 1 (2) None BRA Expr Branch Unconditionally 1 2 None BRA Z,Expr Branch if Zero 1 1 (2) None BRA Wn Computed Branch 1 2 None BSET f,#bit4 Bit Set f 1 1 None BSET Ws,#bit4 Bit Set Ws 1 1 None BSW.C Ws,Wb Write C bit to Ws<Wb> 1 1 None BSW.Z Ws,Wb Write Z bit to Ws<Wb> 1 1 None BTG f,#bit4 Bit Toggle f 1 1 None BTG Ws,#bit4 Bit Toggle Ws 1 1 None BTSC f,#bit4 Bit Test f, Skip if Clear 1 1 None (2 or 3) BTSC Ws,#bit4 Bit Test Ws, Skip if Clear 1 1 None (2 or 3) DS70082A-page 156 Advance Information 2002 Microchip Technology Inc. dsPIC30F TABLE 22-2: Base Instr # 11 12 13 14 15 INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic BTSS BTST BTSTS CALL CLR Assembly Syntax Description # of # of words cycles Status Flags Affected BTSS f,#bit4 Bit Test f, Skip if Set 1 1 None (2 or 3) BTSS Ws,#bit4 Bit Test Ws, Skip if Set 1 1 None (2 or 3) BTST f,#bit4 Bit Test f 1 1 Z BTST.C Ws,#bit4 Bit Test Ws to C 1 1 C BTST.Z Ws,#bit4 Bit Test Ws to Z 1 1 Z BTST.C Ws,Wb Bit Test Ws<Wb> to C 1 1 C BTST.Z Ws,Wb Bit Test Ws<Wb> to Z 1 1 Z BTSTS f,#bit4 Bit Test then Set f 1 1 Z BTSTS.C Ws,#bit4 Bit Test Ws to C, then Set 1 1 C BTSTS.Z Ws,#bit4 Bit Test Ws to Z, then Set 1 1 Z CALL lit23 Call subroutine 2 2 None CALL Wn Call indirect subroutine 1 2 None CLR f f = 0x0000 1 1 None CLR WREG WREG = 0x0000 1 1 None CLR Ws Ws = 0x0000 1 1 None CLR Acc,Wx,Wxd,Wy,Wyd,AWB Clear Accumulator 1 1 OA,OB,SA,SB Clear Watchdog Timer 1 1 WDTO,SLEEP 16 CLRWDT CLRWDT 17 COM COM f f=f 1 1 N,Z COM f,WREG WREG = f 1 1 N,Z COM Ws,Wd Wd = Ws 1 1 N,Z CP f Compare f with WREG 1 1 C,DC,N,OV,Z CP Wb,#lit5 Compare Wb with lit5 1 1 C,DC,N,OV,Z CP Wb,Ws Compare Wb with Ws (Wb - Ws) 1 1 C,DC,N,OV,Z CP0 f Compare f with 0x0000 1 1 C,DC,N,OV,Z CP0 Ws Compare Ws with 0x0000 1 1 C,DC,N,OV,Z CP1 f Compare f with 0xFFFF 1 1 C,DC,N,OV,Z CP1 Ws Compare Ws with 0xFFFF 1 1 C,DC,N,OV,Z CPB f Compare f with WREG, with Borrow 1 1 C,DC,N,OV,Z CPB Wb,#lit5 Compare Wb with lit5, with Borrow 1 1 C,DC,N,OV,Z CPB Wb,Ws Compare Wb with Ws, with Borrow (Wb - Ws - C) 1 1 C,DC,N,OV,Z 18 19 20 21 CP CP0 CP1 CPB 22 CPSEQ CPSEQ f Compare f with WREG, skip if = 1 1 None (2 or 3) 23 CPSGT CPSGT f Compare f with WREG, skip if > 1 1 None (2 or 3) 24 CPSLT CPSLT f Compare f with WREG, skip if < 1 1 None (2 or 3) 25 CPSNE CPSNE f Compare f with WREG, skip if 1 1 None (2 or 3) 26 DAW DAW Wn Wn = decimal adjust Wn 1 1 C 27 DEC DEC f f = f -1 1 1 C,DC,N,OV,Z DEC f,WREG WREG = f -1 1 1 C,DC,N,OV,Z DEC Ws,Wd Wd = Ws - 1 1 1 C,DC,N,OV,Z DEC2 f f = f -2 1 1 C,DC,N,OV,Z DEC2 f,WREG WREG = f -2 1 1 C,DC,N,OV,Z DEC2 Ws,Wd Wd = Ws - 2 1 1 C,DC,N,OV,Z DECSNZ f f = f-1, Skip if Not 0 1 1 None (2 or 3) DECSNZ f,WREG WREG = f-1, Skip if Not 0 1 1 None (2 or 3) DECSZ f f = f-1, Skip if 0 1 1 None (2 or 3) DECSZ f,WREG WREG = f-1, Skip if 0 1 1 None (2 or 3) DISI #lit14 Disable Interrupts for k instruction cycles 1 28 29 30 31 DEC2 DECSNZ DECSZ DISI 2002 Microchip Technology Inc. Advance Information 1 None DS70082A-page 157 dsPIC30F TABLE 22-2: Base Instr # 32 INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic DIV Assembly Syntax Description # of # of words cycles Status Flags Affected DIV.S Wm,Wn Signed 16/16-bit Integer Divide 1 18 N,Z,C DIV.SD Wm,Wn Signed 32/16-bit Integer Divide 1 18 N,Z,C DIV.U Wm,Wn Unsigned 16/16-bit Integer Divide 1 18 N,Z,C DIV.UD Wm,Wn Unsigned 32/16-bit Integer Divide 1 18 N,Z,C Signed 16/16-bit Fractional Divide 1 18 N,Z,C 33 DIVF DIVF Wm,Wn 34 DO DO #lit14,Expr Do code to PC+Expr, lit14+1 times 2 2 None DO Wn,Expr Do code to PC+Expr, (Wn)+1 times 2 2 None 35 ED ED Wm*Wm,Acc,Wx,Wy,Wxd Euclidean Distance 1 1 OA,OB,OAB, SA,SB,SAB 36 EDAC EDAC Wm*Wm,Acc,Wx,Wy,Wxd Euclidean Distance Accumulate 1 1 OA,OB,OAB, SA,SB,SAB 37 EXCH EXCH Wns,Wnd Swap Wns with Wnd 1 1 None 38 FBCL FBCL Ws,Wnd Find Bit Change from Left (MSb) Side 1 1 C 39 FF1L FF1L Ws,Wnd Find First One from Left (MSb) Side 1 1 C 40 FF1R FF1R Ws,Wnd Find First One from Right (LSb) Side 1 1 C 41 GOTO GOTO Expr Go to address 2 2 None GOTO Wn Go to indirect 1 2 None INC f f=f+1 1 1 C,DC,N,OV,Z INC f,WREG WREG = f + 1 1 1 C,DC,N,OV,Z INC Ws,Wd Wd = Ws + 1 1 1 C,DC,N,OV,Z INC2 f f=f+2 1 1 C,DC,N,OV,Z INC2 f,WREG WREG = f + 2 1 1 C,DC,N,OV,Z INC2 Ws,Wd Wd = Ws + 2 1 1 C,DC,N,OV,Z INCSNZ f f = f+1, Skip if Not 0 1 1 None (2 or 3) INCSNZ f,WREG WREG = f+1, Skip if Not 0 1 1 None (2 or 3) INCSZ f f = f+1, Skip if 0 1 1 None (2 or 3) INCSZ f,WREG WREG = f+1, Skip if 0 1 1 None (2 or 3) IOR f f = f .IOR. WREG 1 1 N,Z IOR f,WREG WREG = f .IOR. WREG 1 1 N,Z IOR #lit10,Wn Wd = lit10 .IOR. Wd 1 1 N,Z IOR Wb,Ws,Wd Wd = Wb .IOR. Ws 1 1 N,Z IOR Wb,#lit5,Wd Wd = Wb .IOR. lit5 1 1 N,Z 42 43 44 45 46 INC INC2 INCSNZ INCSZ IOR 47 LAC LAC Wso,#Slit4,Acc Load Accumulator 1 1 OA,OB,OAB, SA,SB,SAB 48 LNK LNK #lit14 Link frame pointer 1 1 None 49 LSR LSR f f = Logical Right Shift f 1 1 C,N,OV,Z LSR f,WREG WREG = Logical Right Shift f 1 1 C,N,OV,Z LSR Ws,Wd Wd = Logical Right Shift Ws 1 1 C,N,OV,Z LSR Wb,Wns,Wnd Wnd = Logical Right Shift Wb by Wns 1 1 N,Z LSR Wb,#lit5,Wnd Wnd = Logical Right Shift Wb by lit5 1 1 N,Z MAC Wm*Wn,Acc,Wx,Wxd,Wy,Wyd, AWB Multiply and Accumulate 1 1 OA,OB,OAB, SA,SB,SAB MAC Wm*Wm,Acc,Wx,Wxd,Wy,Wyd Square and Accumulate 1 1 OA,OB,OAB, SA,SB,SAB 50 MAC DS70082A-page 158 Advance Information 2002 Microchip Technology Inc. dsPIC30F TABLE 22-2: Base Instr # 51 INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic MOV Assembly Syntax Description # of # of words cycles Status Flags Affected MOV f,Wn Move f to Wn 1 1 None MOV f Move f to f 1 1 N,Z MOV f,WREG Move f to WREG 1 1 N,Z MOV #lit16,Wn Move 16-bit literal to Wn 1 1 None MOV.b #lit8,Wn Move 8-bit literal to Wn 1 1 None MOV Wn,f Move Wn to f 1 1 None MOV Wso,Wdo Move Ws to Wd 1 1 None MOV WREG,f Move WREG to f 1 1 N,Z MOV.D Wns,Wd Move Double from W(ns):W(ns+1) to Wd 1 2 None MOV.D Ws,Wnd Move Double from Ws to W(nd+1):W(nd) 1 2 None Move Special 1 1 None 52 MOVSAC MOVSAC Acc,Wx,Wxd,Wy,Wyd,AWB 53 MPY MPY Wm*Wn,Acc,Wx,Wxd,Wy,Wyd Multiply Wm by Wn to Accumulator 1 1 OA,OB,OAB, SA,SB,SAB MPY Wm*Wm,Acc,Wx,Wxd,Wy,Wyd Square Wm to Accumulator 1 1 OA,OB,OAB, SA,SB,SAB Wm*Wn,Acc,Wx,Wxd,Wy,Wyd 54 MPY.N MPY.N -(Multiply Wm by Wn) to Accumulator 1 1 None 55 MSC MSC Wm*Wm,Acc,Wx,Wxd,Wy,Wyd, AWB Multiply and Subtract from Accumulator 1 1 OA,OB,OAB, SA,SB,SAB 56 MUL MUL.SS Wb,Ws,Wnd {Wnd+1, Wnd} = signed(Wb) * signed(Ws) 1 1 None MUL.SU Wb,Ws,Wnd {Wnd+1, Wnd} = signed(Wb) * unsigned(Ws) 1 1 None MUL.US Wb,Ws,Wnd {Wnd+1, Wnd} = unsigned(Wb) * signed(Ws) 1 1 None MUL.UU Wb,Ws,Wnd {Wnd+1, Wnd} = unsigned(Wb) * unsigned(Ws) 1 1 None MUL.SU Wb,#lit5,Wnd {Wnd+1, Wnd} = signed(Wb) * unsigned(lit5) 1 1 None MUL.UU Wb,#lit5,Wnd {Wnd+1, Wnd} = unsigned(Wb) * unsigned(lit5) 1 1 None MUL f W3:W2 = f * WREG 1 1 None NEG Acc Negate Accumulator 1 1 OA,OB,OAB, SA,SB,SAB NEG f f=f+1 1 1 C,DC,N,OV,Z NEG f,WREG WREG = f + 1 1 1 C,DC,N,OV,Z NEG Ws,Wd Wd = Ws + 1 1 1 C,DC,N,OV,Z NOP No Operation 1 1 None NOPR No Operation 1 1 None 57 58 59 NEG NOP POP POP f Pop f from top-of-stack (TOS) 1 1 None POP Wdo Pop from top-of-stack (TOS) to Wdo 1 1 None POP.D Wnd Pop from top-of-stack (TOS) to W(nd):W(nd+1) 1 2 None POP.S 60 PUSH Pop Shadow Registers 1 1 All PUSH f Push f to top-of-stack (TOS) 1 1 None PUSH Wso Push Wso to top-of-stack (TOS) 1 1 None PUSH.D Wns Push W(ns):W(ns+1) to top-of-stack (TOS) 1 2 None Push Shadow Registers 1 1 None Go into Standby mode 1 1 WDTO,SLEEP PUSH.S 61 PWRSAV PWRSAV 62 RCALL RCALL Expr Relative Call 1 2 None RCALL Wn Computed Call 1 2 None REPEAT #lit14 Repeat Next Instruction lit14+1 times 1 2 None REPEAT Wn Repeat Next Instruction (Wn)+1 times 1 2 None 63 REPEAT #lit1 64 RESET RESET Software device RESET 1 1 None 65 RETFIE RETFIE Return from interrupt enable 1 3 (2) None 66 RETLW RETLW Return with literal in Wn 1 3 (2) None 67 RETURN RETURN Return from Subroutine 1 3 (2) None 68 RLC RLC f f = Rotate Left through Carry f 1 1 C,N,Z RLC f,WREG WREG = Rotate Left through Carry f 1 1 C,N,Z RLC Ws,Wd Wd = Rotate Left through Carry Ws 1 1 C,N,Z #lit10,Wn 2002 Microchip Technology Inc. Advance Information DS70082A-page 159 dsPIC30F TABLE 22-2: Base Instr # 69 70 71 72 INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic RLNC RRC RRNC SAC Assembly Syntax Description # of # of words cycles Status Flags Affected RLNC f f = Rotate Left (No Carry) f 1 1 N,Z RLNC f,WREG WREG = Rotate Left (No Carry) f 1 1 N,Z RLNC Ws,Wd Wd = Rotate Left (No Carry) Ws 1 1 N,Z RRC f f = Rotate Right through Carry f 1 1 C,N,Z RRC f,WREG WREG = Rotate Right through Carry f 1 1 C,N,Z RRC Ws,Wd Wd = Rotate Right through Carry Ws 1 1 C,N,Z RRNC f f = Rotate Right (No Carry) f 1 1 N,Z RRNC f,WREG WREG = Rotate Right (No Carry) f 1 1 N,Z RRNC Ws,Wd Wd = Rotate Right (No Carry) Ws 1 1 N,Z SAC Acc,#Slit4,Wdo Store Accumulator 1 1 None SAC.R Acc,#Slit4,Wdo Store Rounded Accumulator 1 1 None 73 SE SE Ws,Wnd Wnd = sign extended Ws 1 1 C,N,Z 74 SETM SETM f f = 0xFFFF 1 1 None SETM WREG WREG = 0xFFFF 1 1 None SETM Ws Ws = 0xFFFF 1 1 None SFTAC Acc,Wn Arithmetic Shift Accumulator by (Wn) 1 1 OA,OB,OAB, SA,SB,SAB SFTAC Acc,#Slit5 Arithmetic Shift Accumulator by Slit5 1 1 OA,OB,OAB, SA,SB,SAB SL f f = Left Shift f 1 1 C,N,OV,Z SL f,WREG WREG = Left Shift f 1 1 C,N,OV,Z SL Ws,Wd Wd = Left Shift Ws 1 1 C,N,OV,Z SL Wb,Wns,Wnd Wnd = Left Shift Wb by Wns 1 1 N,Z SL Wb,#lit5,Wnd Wnd = Left Shift Wb by lit5 1 1 N,Z SUB Acc Subtract Accumulators 1 1 OA,OB,OAB, SA,SB,SAB SUB f f = f - WREG 1 1 C,DC,N,OV,Z SUB f,WREG WREG = f - WREG 1 1 C,DC,N,OV,Z SUB #lit10,Wn Wn = Wn - lit10 1 1 C,DC,N,OV,Z SUB Wb,Ws,Wd Wd = Wb - Ws 1 1 C,DC,N,OV,Z SUB Wb,#lit5,Wd Wd = Wb - lit5 1 1 C,DC,N,OV,Z SUBB f f = f - WREG - (C) 1 1 C,DC,N,OV,Z SUBB f,WREG WREG = f - WREG - (C) 1 1 C,DC,N,OV,Z SUBB #lit10,Wn Wn = Wn - lit10 - (C) 1 1 C,DC,N,OV,Z SUBB Wb,Ws,Wd Wd = Wb - Ws - (C) 1 1 C,DC,N,OV,Z SUBB Wb,#lit5,Wd Wd = Wb - lit5 - (C) 1 1 C,DC,N,OV,Z SUBR f f = WREG - f 1 1 C,DC,N,OV,Z SUBR f,WREG WREG = WREG - f 1 1 C,DC,N,OV,Z SUBR Wb,Ws,Wd Wd = Ws - Wb 1 1 C,DC,N,OV,Z SUBR Wb,#lit5,Wd Wd = lit5 - Wb 1 1 C,DC,N,OV,Z SUBBR f f = WREG - f - (C) 1 1 C,DC,N,OV,Z SUBBR f,WREG WREG = WREG -f - (C) 1 1 C,DC,N,OV,Z SUBBR Wb,Ws,Wd Wd = Ws - Wb - (C) 1 1 C,DC,N,OV,Z SUBBR Wb,#lit5,Wd Wd = lit5 - Wb - (C) 1 1 C,DC,N,OV,Z SWAP.b Wn Wn = nibble swap Wn 1 1 None SWAP Wn Wn = byte swap Wn 1 1 None 75 76 77 78 79 80 81 SFTAC SL SUB SUBB SUBR SUBBR SWAP 82 TBLRDH TBLRDH Ws,Wd Read Prog<23:16> to Wd<7:0> 1 2 None 83 TBLRDL TBLRDL Ws,Wd Read Prog<15:0> to Wd 1 2 None 84 TBLWTH TBLWTH Ws,Wd Write Ws<7:0> to Prog<23:16> 1 2 None 85 TBLWTL TBLWTL Ws,Wd Write Ws to Prog<15:0> 1 2 None 86 ULNK ULNK Unlink frame pointer 1 1 None 87 XOR XOR f f = f .XOR. WREG 1 1 N,Z XOR f,WREG WREG = f .XOR. WREG 1 1 N,Z XOR #lit10,Wn Wd = lit10 .XOR. Wd 1 1 N,Z XOR Wb,Ws,Wd Wd = Wb .XOR. Ws 1 1 N,Z XOR Wb,#lit5,Wd Wd = Wb .XOR. lit5 1 1 N,Z ZE Ws,Wnd Wnd = Zero-Extend Ws 1 1 None 88 ZE DS70082A-page 160 Advance Information 2002 Microchip Technology Inc. dsPIC30F 23.0 DEVELOPMENT SUPPORT Microchip offers a comprehensive package of development tools and libraries to support the dsPIC architecture. In addition, the company is partnering with many third party tools manufacturers for additional dsPIC device support. The Microchip tools will include: * MPLAB 6.00 Integrated Development Environment (IDE) * dsPIC Language Suite, including MPLAB C30 C Compiler, Assembler, Linker and Librarian * MPLAB SIM Software Simulator * MPLAB ICE 4000 In-Circuit Emulator * MPLAB ICD 2 In-Circuit Debugger * PRO MATE(R) II Universal Device Programmer * PICSTART(R) Plus Development Programmer 23.1 MPLAB V6.00 Integrated Development Environment Software The MPLAB Integrated Development Environment is available at no cost. The MPLAB IDE gives users the flexibility to edit, compile and emulate, all from a single user interface. Engineers can design and develop code for the dsPIC devices in the same design environment that they have used for PICmicro(R) microcontrollers. The MPLAB IDE is a 32-bit Windows(R) based application. It provides many advanced features for the critical engineer in a modern, easy to use interface. MPLAB IDE integrates: * * * * * * * * * * * Full featured, color coded text editor Easy to use project manager with visual display Source level debugging Enhanced source level debugging for `C' (structures, automatic variables, etc.) Customizable toolbar and key mapping Dynamic status bar displays processor condition at a glance Context sensitive, interactive on-line help Integrated MPLAB SIM instruction simulator User interface for PRO MATE II and PICSTART Plus device programmers (sold separately) User interface for MPLAB ICE 4000 In-Circuit Emulator (sold separately) User interface for MPLAB ICD 2 In-Circuit Debugger The MPLAB IDE allows the engineer to: * Edit your source files in either assembly or `C' * One-touch compile and download to dsPIC program memory on emulator or simulator. Updates all project information. * Debug using: - Source files - Machine code - Mixed mode source and machine code The ability to use the MPLAB IDE with multiple development and debugging targets allows users to easily switch from the cost effective simulator to a fullfeatured emulator with minimal retraining. 23.2 dsPIC Language Suite The Microchip Technology MPLAB C30 C compiler is a fully ANSI compliant product with standard libraries for the dsPIC architecture. It is highly optimizing and takes advantage of many dsPIC architecture specific features to provide efficient software code generation. MPLAB C30 also provides extensions that allow for excellent support of the hardware, such as interrupts and peripherals. It is fully integrated with the MPLAB IDE for high level, source debugging. * 16-bit native data types * Efficient use of register-based, 3-operand instructions * Complex addressing modes * Efficient multi-bit shift operations * Efficient signed/unsigned comparisons MPLAB C30 comes complete with its own assembler, linker and librarian. These allow the user to write Mixed mode C and assembly programs and link the resulting object files into a single executable file. The compiler is sold separately. The assembler, linker and librarian are available for free with MPLAB C30. 23.3 MPLAB SIM Software Simulator The MPLAB SIM software simulator allows code development in a PC-hosted environment, by simulating the dsPIC device on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a file, or user defined key press, to any of the pins. The execution can be performed in Single Step, Execute Until Break, or Trace mode. The MPLAB SIM simulator fully supports symbolic debugging using the MPLAB C30 compiler and assembler. The software simulator offers the flexibility to develop and debug code outside of the laboratory environment, making it an excellent multi-project software development tool. 2002 Microchip Technology Inc. Advance Information DS70082A-page 161 dsPIC30F 23.4 MPLAB ICE 4000 In-Circuit Emulator The MPLAB ICE 4000 In-Circuit Emulator is intended to provide the product development engineer with a complete hardware design tool for the dsPIC devices. Software control of the emulator is provided by MPLAB ICE, allowing editing, building, downloading and source debugging from a single environment. The MPLAB ICE 4000 is a full-featured emulator system with enhanced trace, trigger and data monitoring features. Interchangeable processor modules allow the system to be easily reconfigured for emulation of different processors. The MPLAB ICE 4000 supports the extended, high end PICmicro microcontrollers, the PIC18CXXX and PIC18FXXX devices, as well as the dsPIC30F family of digital signal controllers. The modular architecture of the MPLAB ICE in-circuit emulator allows expansion to support new devices. The MPLAB ICE in-circuit emulator system has been designed as a real-time emulation system, with advanced features that are generally found on more expensive development tools. * Full-speed emulation, up to 50MHz bus speed, or 200MHz external clock speed * Low-voltage emulation down to 1.8 volts * Configured with 2Mb program emulation memory, additional modular memory up to 16Mb * 64K x 136-bit wide Trace Memory * Unlimited software breakpoints * Complex break, trace and trigger logic * Multi-level trigger up to 4 levels * Filter trigger functions to trace specific event * 16-bit Pass counter for triggering on sequential events * 16-bit Delay counter * 48-bit time stamp * Stopwatch feature * Time between events * Statistical performance analysis * Code coverage analysis * USB and parallel printer port PC connection 23.5 MPLAB ICD 2 In-Circuit Debugger Microchip's In-Circuit Debugger, MPLAB ICD, is a powerful, low cost, run-time development tool. This tool is based on the PICmicro and dsPIC30F FLASH devices. The MPLAB ICD utilizes the in-circuit debugging capability built into the various devices. This feature, along with Microchip's In-Circuit Serial ProgrammingTM protocol, offers cost-effective in-circuit debugging from the graphical user interface of MPLAB. This enables a designer to develop and debug source code by watching variables, single-stepping and setting break points. Running at full speed enables testing hardware in real-time. * * * * * * * * * * * Full speed operation to the range of the device Serial or USB PC connector Serial interface externally powered USB powered from PC interface Low-noise power (VPP and VDD) for use with analog and other noise sensitive applications Operation down to 2.0v Can be used as an ICD or in-expensive serial programmer Modular application connector as MPLAB-ICD Limited number of breakpoints "Smart watch" variable windows Some chip resources required (RAM, program memory and 2 pins) 23.6 PRO MATE II Universal Device Programmer The PRO MATE II universal device programmer is a full-featured programmer, capable of operating in stand-alone mode, as well as PC-hosted mode. The PRO MATE II device programmer is CE compliant. The PRO MATE II device programmer has programmable VDD and VPP supplies, which allow it to verify programmed memory at VDDMIN and VDDMAX for maximum reliability when programming requiring this capability. It has an LCD display for instructions and error messages, keys to enter commands. Interchangeable socket modules all package types. In Stand Alone mode, the PRO MATE II device programmer can read, verify, or program PICmicro and dsPIC30F devices. It can also set code protection in this mode. PRO MATE II features include: * * * * * * Runs under MPLAB IDE Field upgradable firmware DOS Command Line interface for production Host, Safe, and "Stand Alone" operation Automatic downloading of object file SQTPSM serialization adds unique serial number to each device programmed * In-Circuit Serial Programming Kit (sold separately) * Interchangeable socket modules supports all package options (sold separately) DS70082A-page 162 Advance Information 2002 Microchip Technology Inc. dsPIC30F 24.0 ELECTRICAL CHARACTERISTICS Electrical characteristics are not available at this time. 2002 Microchip Technology Inc. Advance Information DS70082A-page 163 dsPIC30F NOTES: DS70082A-page 164 Advance Information 2002 Microchip Technology Inc. dsPIC30F 25.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES DC and AC Characteristics Graphs and Tables are not available at this time. 2002 Microchip Technology Inc. Advance Information DS70082A-page 165 dsPIC30F NOTES: DS70082A-page 166 Advance Information 2002 Microchip Technology Inc. dsPIC30F 26.0 PACKAGING INFORMATION 26.1 Package Marking Information 28-Lead PDIP (Skinny DIP) Example XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN 28-Lead SOIC dsPIC30F3010-I/SP 0248017 Example XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN 40-Lead PDIP dsPIC30F4011-I/SO 0248017 Example XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX YYWWNNN Legend: Note: * XX...X Y YY WW NNN dsPIC30F4011-I/P 0248017 Customer specific information* Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. Standard PICmicro device marking consists of Microchip part number, year code, week code, and traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. 2002 Microchip Technology Inc. Advance Information DS70082A-page 167 dsPIC30F 26.2 Package Marking Information (Continued) 44-Lead TQFP Example dsPIC30F 4011-I/PT XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN 0248017 80-Lead TQFP Example XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN DS70082A-page 168 dsPIC30F5013 -I/PT 0236017 Advance Information 2002 Microchip Technology Inc. dsPIC30F 28-Lead Skinny Plastic Dual In-line (SP) - 300 mil (PDIP) E1 D 2 n 1 E A2 A L c B1 A1 eB Units Number of Pins Pitch p B Dimension Limits n p INCHES* MIN NOM MILLIMETERS MAX MIN NOM 28 MAX 28 .100 2.54 Top to Seating Plane A .140 .150 .160 3.56 3.81 4.06 Molded Package Thickness A2 .125 .130 .135 3.18 3.30 3.43 8.26 Base to Seating Plane A1 .015 Shoulder to Shoulder Width E .300 .310 .325 7.62 7.87 Molded Package Width E1 .275 .285 .295 6.99 7.24 7.49 Overall Length D 1.345 1.365 1.385 34.16 34.67 35.18 Tip to Seating Plane L c .125 .130 .135 3.18 3.30 3.43 .008 .012 .015 0.20 0.29 0.38 B1 .040 .053 .065 1.02 1.33 1.65 Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing Mold Draft Angle Top Mold Draft Angle Bottom 0.38 B .016 .019 .022 0.41 0.48 0.56 eB .320 .350 .430 8.13 8.89 10.92 5 10 15 5 10 15 5 10 15 5 10 15 * Controlling Parameter Significant Characteristic Notes: Dimension D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MO-095 Drawing No. C04-070 2002 Microchip Technology Inc. Advance Information DS70082A-page 169 dsPIC30F 28-Lead Plastic Small Outline (SO) - Wide, 300 mil (SOIC) E E1 p D B 2 1 n h 45 c A2 A L Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Top Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic A A2 A1 E E1 D h L c B A1 MIN .093 .088 .004 .394 .288 .695 .010 .016 0 .009 .014 0 0 INCHES* NOM 28 .050 .099 .091 .008 .407 .295 .704 .020 .033 4 .011 .017 12 12 MAX .104 .094 .012 .420 .299 .712 .029 .050 8 .013 .020 15 15 MILLIMETERS NOM 28 1.27 2.36 2.50 2.24 2.31 0.10 0.20 10.01 10.34 7.32 7.49 17.65 17.87 0.25 0.50 0.41 0.84 0 4 0.23 0.28 0.36 0.42 0 12 0 12 MIN MAX 2.64 2.39 0.30 10.67 7.59 18.08 0.74 1.27 8 0.33 0.51 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-013 Drawing No. C04-052 DS70082A-page 170 Advance Information 2002 Microchip Technology Inc. dsPIC30F 40-Lead Plastic Dual In-line (P) - 600 mil (PDIP) E1 D 2 1 n E A2 A L c B1 A1 eB p B Units Dimension Limits n p MIN INCHES* NOM 40 .100 .175 .150 MAX MILLIMETERS NOM 40 2.54 4.06 4.45 3.56 3.81 0.38 15.11 15.24 13.46 13.84 51.94 52.26 3.05 3.30 0.20 0.29 0.76 1.27 0.36 0.46 15.75 16.51 5 10 5 10 MIN Number of Pins Pitch Top to Seating Plane A .160 .190 Molded Package Thickness A2 .140 .160 Base to Seating Plane .015 A1 Shoulder to Shoulder Width E .595 .600 .625 Molded Package Width E1 .530 .545 .560 Overall Length D 2.045 2.058 2.065 Tip to Seating Plane L .120 .130 .135 c Lead Thickness .008 .012 .015 Upper Lead Width B1 .030 .050 .070 Lower Lead Width B .014 .018 .022 Overall Row Spacing eB .620 .650 .680 5 10 15 Mold Draft Angle Top Mold Draft Angle Bottom 5 10 15 * Controlling Parameter Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MO-011 Drawing No. C04-016 2002 Microchip Technology Inc. Advance Information MAX 4.83 4.06 15.88 14.22 52.45 3.43 0.38 1.78 0.56 17.27 15 15 DS70082A-page 171 dsPIC30F 44-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP) E E1 #leads=n1 p D1 D 2 1 B n CH x 45 A c L A1 A2 (F) Units Dimension Limits n p Number of Pins Pitch Pins per Side Overall Height Molded Package Thickness Standoff Foot Length Footprint (Reference) Foot Angle Overall Width Overall Length Molded Package Width Molded Package Length Lead Thickness Lead Width Pin 1 Corner Chamfer Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic n1 A A2 A1 L (F) E D E1 D1 c B CH MIN .039 .037 .002 .018 0 .463 .463 .390 .390 .004 .012 .025 5 5 INCHES NOM 44 .031 11 .043 .039 .004 .024 .039 3.5 .472 .472 .394 .394 .006 .015 .035 10 10 MAX .047 .041 .006 .030 7 .482 .482 .398 .398 .008 .017 .045 15 15 MILLIMETERS* NOM 44 0.80 11 1.00 1.10 0.95 1.00 0.05 0.10 0.45 0.60 1.00 0 3.5 11.75 12.00 11.75 12.00 9.90 10.00 9.90 10.00 0.09 0.15 0.30 0.38 0.64 0.89 5 10 5 10 MIN MAX 1.20 1.05 0.15 0.75 7 12.25 12.25 10.10 10.10 0.20 0.44 1.14 15 15 Notes: Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-026 Drawing No. C04-076 DS70082A-page 172 Advance Information 2002 Microchip Technology Inc. dsPIC30F 80-Lead Plastic Thin Quad Flatpack (PT) 12x12x1 mm Body, 1.0/0.10 mm Lead Form (TQFP) E E1 #leads=n1 p D1 D 2 1 B n CH x 45 A c L A2 A1 (F) Units Dimension Limits n p Number of Pins Pitch Pins per Side Overall Height Molded Package Thickness Standoff Foot Length Footprint (Reference) Foot Angle Overall Width Overall Length Molded Package Width Molded Package Length Lead Thickness Lead Width Pin 1 Corner Chamfer Mold Draft Angle Top Mold Draft Angle Bottom n1 A A2 A1 L (F) MIN .039 .037 .002 .018 E D E1 D1 c B CH 0 .541 .541 .463 .463 .004 .007 .025 5 5 INCHES NOM 80 .020 20 .043 .039 .004 .024 .039 3.5 .551 .551 .472 .472 .006 .009 .035 10 10 MAX .047 .041 .006 .030 7 .561 .561 .482 .482 .008 .011 .045 15 15 MILLIMETERS* NOM 80 0.50 20 1.00 1.10 0.95 1.00 0.05 0.10 0.45 0.60 1.00 0 3.5 13.75 14.00 13.75 14.00 11.75 12.00 11.75 12.00 0.09 0.15 0.17 0.22 0.64 0.89 5 10 5 10 MIN MAX 1.20 1.05 0.15 0.75 7 14.25 14.25 12.25 12.25 0.20 0.27 1.14 15 15 * Controlling Parameter Significant Characteristic Notes: Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-026 Drawing No. C04-092 2002 Microchip Technology Inc. Advance Information DS70082A-page 173 dsPIC30F NOTES: DS70082A-page 174 Advance Information 2002 Microchip Technology Inc. dsPIC30F INDEX A Address Generator Units .................................................... 37 Alternate Vector Table ....................................................... 49 Alternate 16-bit Timer/Counter ........................................... 91 Automatic Clock Stretch ................................................... 114 During 10-bit Addressing (STREN = 1) .................... 114 During 7-bit Addressing (STREN = 1) ...................... 114 Receive Mode .......................................................... 114 Transmit Mode ......................................................... 114 A/D ................................................................................... 133 B Barrel Shifter ...................................................................... 23 Bit-Reversed Addressing ................................................... 43 Example ..................................................................... 43 Implementation .......................................................... 43 Modifier Values (table) ............................................... 44 Sequence Table (16-Entry) ........................................ 44 Block Diagrams CAN Buffers and Protocol Engine ............................ 128 Dedicated Port Structure ............................................ 61 DSP Engine ............................................................... 20 dsPIC30F6010 ........................................................... 10 External Power-on Reset Circuit .............................. 148 Input Capture Mode ................................................... 81 I2C ............................................................................ 112 Oscillator System ..................................................... 142 Output Compare Mode .............................................. 85 Quadrature Encoder Interface ................................... 89 RESET System ........................................................ 146 Shared Port Structure ................................................ 63 SPI ........................................................................... 108 SPI Master/Slave Connection .................................. 108 UART Receiver ........................................................ 120 UART Transmitter .................................................... 119 10-bit High Speed A/D Functional ............................ 134 16-bit Timer1 Module ................................................. 67 16-bit Timer4 .............................................................. 78 16-bit Timer5 .............................................................. 78 32-bit Timer4/5 ........................................................... 77 8-Output PWM Module .............................................. 96 BOR. See Brown-out Reset Brown-out Reset (BOR) ................................................... 141 C CAN Module ..................................................................... 127 CAN1 Register Map ................................................. 129 CAN2 Register Map ................................................. 131 Overview .................................................................. 127 Overview of the Module ........................................... 127 Transmit/Receive Buffers ......................................... 127 Center Aligned PWM ........................................................ 100 Code Examples Data EEPROM Block Erase ....................................... 58 Data EEPROM Block Write ........................................ 60 Data EEPROM Read ................................................. 57 Data EEPROM Word Erase ....................................... 58 Data EEPROM Word Write ........................................ 59 Erasing a Row of Program Memory ........................... 53 Initiating a Programming Sequence ........................... 55 Loading Write Latches ............................................... 54 Program Space Data Read Through Data Space Within a REPEAT Loop .......................... 28 2002 Microchip Technology Inc. Code Protection ............................................................... 141 Complementary PWM Operation ..................................... 100 Configuring Analog Port Pins ............................................. 63 Control Registers ............................................................... 52 NVMADR ................................................................... 52 NVMADRU ................................................................. 52 NVMCON ................................................................... 52 NVMKEY ................................................................... 52 Core Architecture Overview .................................................................... 13 Core Register Map ............................................................. 34 D Data Accumulators and Adder/Subtractor ....................22, 23 Data Address Space .......................................................... 29 Access RAM .............................................................. 31 Alignment ................................................................... 30 Alignment (Figure) ..................................................... 30 Effect of Invalid Memory Accesses ............................ 30 MCU and DSP (MAC Class) Instructions Example ............................................................. 33 Memory Map .............................................................. 30 Memory Map Example ............................................... 32 Spaces ....................................................................... 29 Width ......................................................................... 30 Data EEPROM Memory ..................................................... 57 Erasing ...................................................................... 58 Erasing, Block ............................................................ 58 Erasing, Word ............................................................ 58 Protection Against Spurious Write ............................. 60 Reading ..................................................................... 57 Write Verify ................................................................ 60 Writing ....................................................................... 59 Writing, Block ............................................................. 60 Writing, Word ............................................................. 59 Data Space Organization ................................................... 37 DC and AC Characteristics Graphs and Tables .............. 165 Dead-Time Generators .................................................... 101 Assignment .............................................................. 101 Ranges .................................................................... 101 Selection Bits ........................................................... 101 Device Configuration Register Map ........................................................... 152 Device Configuration Registers ....................................... 151 FBORPOR ............................................................... 151 FGS ......................................................................... 151 FOSC ....................................................................... 151 FWDT ...................................................................... 151 Device Overview .................................................................. 9 Divide Support ................................................................... 18 DSP Engine ....................................................................... 19 Multiplier .................................................................... 21 Dual Output Compare Match Mode ................................... 86 Continuous Pulse Mode ............................................. 86 Single Pulse Mode ..................................................... 86 Advance Information DS70082A-page 175 DSPIC30F E Edge Aligned PWM ............................................................ 99 Electrical Characteristics .................................................. 163 Equations A/D Conversion Clock .............................................. 136 A/D Sampling Time .................................................. 137 Baud Rate ................................................................ 123 PWM Period ............................................................... 99 PWM Resolution ........................................................ 99 Serial Clock Rate ..................................................... 115 Errata ................................................................................... 7 Exception Processing ......................................................... 45 Interrupt Priority .......................................................... 45 Natural Order Priority (table) ...................................... 46 Exception Sequence Trap Sources .............................................................. 47 External Interrupt Requests ............................................... 49 F Fast Context Saving ........................................................... 49 Firmware Instructions ....................................................... 153 FLASH Program Memory ................................................... 51 In-Circuit Serial Programming (ICSP) ........................ 51 Run Time Self-Programming (RTSP) ......................... 51 Table Instruction Operation Summary ....................... 51 I In-Circuit Serial Programming (ICSP) .............................. 141 Independent PWM Output ................................................ 102 Initialization Condition for RCON Register, Case 1 ...................................................................... 149 Initialization Condition for RCON Register, Case 2 ...................................................................... 149 Input Capture Interrupts ..................................................... 82 Register Map .............................................................. 83 Input Capture Module ......................................................... 81 In CPU SLEEP Mode ................................................. 82 Simple Capture Event Mode ...................................... 81 Input Change Notification Module ...................................... 66 Register Map (bit 15-8) .............................................. 66 Register Map (bits 15-8) ............................................. 66 Register Map (bits 7-0) ............................................... 66 Instruction Addressing Modes ............................................ 37 File Register Instructions ............................................ 38 Fundamental Modes Supported ................................. 37 MAC Instructions ........................................................ 38 MCU Instructions ........................................................ 38 Move and Accumulator Instructions ........................... 38 Other Instructions ....................................................... 38 Instruction Flow .................................................................. 16 Pipeline - 1-Word, 1-Cycle (Figure) ............................ 16 Pipeline - 1-Word, 2-Cycle MOV.D Operations (Figure) ............................................ 16 Pipeline - 1-Word, 2-Cycle Table Operations (Figure) ............................................ 17 Pipeline - 1-Word, 2-Cycle with Instruction Stall (Figure) ...................................................... 18 Pipeline - 1-Word, 2-Cycle (Figure) ............................ 16 Pipeline - 2-Word, 2-Cycle DO, DOW (Figure) ............................................. 17 Pipeline - 2-Word, 2-Cycle GOTO, CALL (Figure) .................................................... 17 Instruction Set .................................................................. 153 DS70082A-page 176 Instruction Set Overview .................................................. 156 Instruction Stalls ................................................................ 39 Introduction ................................................................ 39 Raw Dependency Detection ...................................... 39 Inter-Integrated Circuit. See I2C Interrupt Controller Register Map ............................................................. 50 Interrupt Priority Traps .......................................................................... 47 Interrupt Sequence ............................................................ 48 Interrupt Stack Frame ................................................ 48 I2C .................................................................................... 111 I2C Master Mode Baud Rate Generator ............................................... 115 Clock Arbitration ...................................................... 116 Multi-Master Communication, Bus Collision, and Bus Arbitration .......................................... 116 Reception ................................................................. 115 Transmission ........................................................... 115 I2C Module ....................................................................... 111 Addresses ................................................................ 113 General Call Address Support ................................. 115 Interrupts .................................................................. 114 IPMI Support ............................................................ 115 Master Operation ..................................................... 115 Master Support ........................................................ 115 Operating Function Description ............................... 111 Operation During CPU SLEEP and IDLE Modes ..................................................... 116 Pin Configuration ..................................................... 111 Register Map ........................................................... 117 Registers .................................................................. 111 Slope Control ........................................................... 115 Software Controlled Clock Stretching (STREN = 1) .................................................... 114 Various Modes ......................................................... 111 I2C Module Programmer's Model ............................................... 111 I2C 10-bit Slave Mode Operation ..................................... 113 Reception ................................................................. 113 Transmission ........................................................... 113 I2C 7-bit Slave Mode Operation ....................................... 113 I2C 7-bit Slave Mode Operation Reception ................................................................. 113 Transmission ........................................................... 113 I/O Ports ............................................................................. 61 Parallel I/O (PIO) ....................................................... 61 M Memory Organization ......................................................... 25 Modulo Addressing ............................................................ 40 Applicability ................................................................ 42 Decrementing Buffer Operation Example .................. 42 Incrementing Buffer Operation Example .................... 41 Restrictions ................................................................ 43 Start and End Address ............................................... 40 W Address Register Selection ................................... 40 Motor Control PWM Module ............................................... 95 Advance Information 2002 Microchip Technology Inc. dsPIC30F O Oscillator Configurations .................................................. 143 Fail-Safe Clock Monitor ............................................ 145 Fast RC (FRC) ......................................................... 144 Initial Clock Source Selection .................................. 143 Low Power RC (LPRC) ............................................ 144 LP Oscillator Control ................................................ 144 Phase Locked Loop (PLL) ....................................... 144 Start-up Timer (OST) ............................................... 144 Oscillator Operating Modes Table .................................... 141 Oscillator Selection .......................................................... 141 Output Compare Interrupts ................................................ 87 Output Compare Mode Register Map .............................................................. 88 Output Compare Module .................................................... 85 Output Compare Operation During CPU IDLE Mode ........................................................ 87 Output Compare SLEEP Mode Operation ......................... 87 P Packaging Information ..................................................... 167 Marking .................................................................... 167 Peripheral Module Display (PMD) Registers .................... 151 Pinout Descriptions ............................................................ 11 PORTA Register Map .............................................................. 62 PORTB Register Map .............................................................. 64 PORTC Register Map .............................................................. 64 PORTD Register Map .............................................................. 64 PORTE Register Map .............................................................. 64 PORTF Register Map .............................................................. 65 PORTG Register Map .............................................................. 65 POR. See Power-on Reset Position Measurement Mode ............................................. 90 Power Saving Modes ....................................................... 150 IDLE ......................................................................... 151 SLEEP ..................................................................... 150 Power Saving Modes (SLEEP and IDLE) ........................ 141 Power-on Reset (POR) .................................................... 141 Oscillator Start-up Timer (OST) ............................... 141 Power-up Timer (PWRT) ......................................... 141 Product Identification System ........................................... 183 Program Address Space .................................................... 25 Alignment and Data Access Using Table Instructions ............................................... 26 Construction ............................................................... 25 Data Access from, Address Generation ..................... 25 Memory Map .............................................................. 29 Table Instructions TBLRDH ............................................................. 26 TBLRDL ............................................................. 26 TBLWTH ............................................................ 26 TBLWTL ............................................................. 26 Program Counter ................................................................ 14 Program Data Table Access .............................................. 27 Program Space Visibility Window into Program Space Operation ..................... 28 2002 Microchip Technology Inc. Program Space Visibility from Data Space ........................ 27 Data Pre-fetch from Program Space Within a REPEAT Loop ................................................... 27 Programmable ................................................................. 141 Programmable Digital Noise Filters ................................... 91 Programmer's Model ......................................................... 14 Diagram ..................................................................... 15 Programming Operations ................................................... 52 Algorithm for Program FLASH ................................... 53 Erasing a Row of Program Memory ........................... 53 Initiating the Programming Sequence ........................ 55 Loading Write Latches ............................................... 54 Programming, Device Instructions ................................... 153 Protection Against Accidental Writes to OSCCON ............................................................. 145 PWM Duty Cycle Comparison Units ................................ 100 Duty Cycle Register Buffers ..................................... 100 PWM FAULT Pins ............................................................ 103 Enable Bits .............................................................. 103 FAULT States .......................................................... 103 Modes ...................................................................... 103 Cycle-by-Cycle ................................................ 103 Latched ............................................................ 103 Priority ..................................................................... 103 PWM Operation During CPU IDLE Mode ........................ 104 PWM Operation During CPU SLEEP Mode .................... 104 PWM Output and Polarity Control .................................... 103 Output Pin Control ................................................... 103 PWM Output Override ..................................................... 102 Complementary Output Mode .................................. 102 Synchronization ....................................................... 102 PWM Period ....................................................................... 99 PWM Special Event Trigger ............................................. 104 Postscaler ................................................................ 104 PWM Time-Base ................................................................ 98 Continuous Up/Down Counting Modes ...................... 98 Double Update Mode ................................................. 99 Free Running Mode ................................................... 98 Postscaler .................................................................. 99 Prescaler ................................................................... 99 Single Shot Mode ...................................................... 98 PWM Update Lockout ...................................................... 104 Q QEI Module Operation During CPU IDLE Mode ............................ 91 Operation During CPU SLEEP Mode ........................ 91 Register Map ............................................................. 93 Timer Operation During CPU IDLE Mode .................. 92 Timer Operation During CPU SLEEP Mode .............. 91 Quadrature Encoder Interface Interrupts ........................... 92 Quadrature Encoder Interface Logic .................................. 90 Quadrature Encoder Interface (QEI) Module ..................... 89 R RESET ......................................................................141, 146 RESET Sequence .............................................................. 47 RESET Sources ......................................................... 47 RESETS BOR, Programmable ............................................... 148 POR ......................................................................... 146 Operating without FSCM and PWRT ............... 148 POR with Long Crystal Start-up Time ...................... 148 RTSP Operation ................................................................ 52 Advance Information DS70082A-page 177 DSPIC30F S Sales and Support ............................................................ 183 Serial Peripheral Interface. See SPI Simple Capture Event Mode Capture Buffer Operation ........................................... 82 Capture Prescaler ...................................................... 81 Hall Sensor Mode ....................................................... 82 Input Capture in CPU IDLE Mode .............................. 82 Timer2 and Timer3 Selection Mode ........................... 82 Simple Output Compare Match Mode ................................ 86 Simple PWM Mode ............................................................ 86 Input Pin FAULT Protection ....................................... 86 Period ......................................................................... 87 Single Pulse PWM Operation ........................................... 102 Software Stack Pointer, Frame Pointer .............................. 14 CALL Stack Frame ..................................................... 31 SPI ................................................................................... 107 SPI Mode Slave Select Synchronization ................................... 109 SPI1 Register Map ................................................... 110 SPI2 Register Map ................................................... 110 SPI Module ....................................................................... 107 Framed SPI Support ................................................ 107 Operating Function Description ................................ 107 SDOx Disable ........................................................... 107 Word and Byte Communication ............................... 107 SPI Operation During CPU IDLE Mode ........................... 109 SPI Operation During CPU SLEEP Mode ........................ 109 STATUS Register ............................................................... 14 Sticky Z (SZ) Status Bit .............................................. 14 Subtractor ........................................................................... 22 Data Space Write Saturation ...................................... 23 Overflow and Saturation ............................................. 22 Round Logic ............................................................... 23 Write Back .................................................................. 23 Symbols used in Roadrunner Opcode Descriptions ................................................ 154 System Integration ........................................................... 141 Overview .................................................................. 141 Register Map ............................................................ 152 T Timer1 Module ................................................................... 67 Gate Operation ........................................................... 68 Interrupt ...................................................................... 68 Operation During SLEEP Mode ................................. 68 Prescaler .................................................................... 68 Real-Time Clock ......................................................... 68 RTC Interrupts ................................................... 68 RTC Oscillator Operation ................................... 68 Register Map .............................................................. 69 16-bit Asynchronous Counter Mode ........................... 67 16-bit Synchronous Counter Mode ............................ 67 16-bit Timer Mode ...................................................... 67 Timer2 and Timer 3 Selection Mode .................................. 86 Timer2/3 Module ................................................................ 71 ADC Event Trigger ..................................................... 74 Gate Operation ........................................................... 74 Interrupt ...................................................................... 74 Operation During SLEEP Mode ................................. 74 Register Map .............................................................. 75 Timer Prescaler .......................................................... 74 32-bit Synchronous Counter Mode ............................ 71 32-bit Timer Mode ...................................................... 71 DS70082A-page 178 Timer4/5 Module ................................................................ 77 Register Map ............................................................. 79 Timing Diagrams Center Aligned PWM ............................................... 100 Dead-Time ............................................................... 102 Edge Aligned PWM .................................................... 99 PWM Output .............................................................. 87 Time-out Sequence on Power-up (MCLR Not Tied to VDD), Case 1 ........................................ 147 Time-out Sequence on Power-up (MCLR Not Tied to VDD), Case 2 ........................................ 147 Time-out Sequence on Power-up (MCLR Tied to VDD) ..................................................... 147 U UART Address Detect Mode .............................................. 123 Auto Baud Support .................................................. 123 Baud Rate Generator ............................................... 123 Enabling and Setting Up UART ............................... 121 Alternate I/O .................................................... 121 Disabling .......................................................... 121 Enabling ........................................................... 121 Setting Up Data, Parity and STOP Bit Selections ........................................... 121 Loopback Mode ....................................................... 123 Module Overview ..................................................... 119 Operation During CPU SLEEP and IDLE Modes .... 124 Receiving Data ........................................................ 122 In 8-bit or 9-bit Data Mode ............................... 122 Interrupt ........................................................... 122 Receive Buffer (UxRCB) .................................. 122 Reception Error Handling ........................................ 122 Framing Error (FERR) ..................................... 123 IDLE Status ..................................................... 123 Parity Error (PERR) ......................................... 123 Receive Break ................................................. 123 Receive Buffer Overrun Error (OERR Bit) ............................................... 122 Transmitting Data In 8-bit Data Mode ........................................... 121 Transmitting Data .................................................... 121 In 9-bit Data Mode ........................................... 121 Interrupt ........................................................... 122 Transmit Buffer (UxTXB) ................................. 121 UART1 Register Map ............................................... 125 UART2 Register Map ............................................... 125 Unit ID Locations ............................................................. 141 Universal Asynchronous Receiver Transmitter. See UART. W Wake-up from SLEEP ...................................................... 141 Wake-up from SLEEP and IDLE ........................................ 49 Watchdog Timer (WDT) ............................................141, 150 Enabling and Disabling ............................................ 150 Operation ................................................................. 150 WWW, On-Line Support ...................................................... 7 Advance Information 2002 Microchip Technology Inc. dsPIC30F Z 10-bit High Speed Analog-to-Digital Converter. See A/D 10-bit High Speed A/D Aborting a Conversion ............................................. 136 ADCHS .................................................................... 133 ADCON1 .................................................................. 133 ADCON2 .................................................................. 133 ADCON3 .................................................................. 133 ADCSSL ................................................................... 133 ADPCFG .................................................................. 133 Analog Input Model .................................................. 137 Configuring Analog Port Pins ................................... 139 Connection Considerations ...................................... 139 Conversion Operation .............................................. 135 Effects of a RESET .................................................. 138 Operation During CPU IDLE Mode .......................... 138 Operation During CPU SLEEP Mode ...................... 138 Output Formats ........................................................ 139 Power-down Modes ................................................. 138 Programming the Start of Conversion Trigger ......... 136 Register Map ............................................................ 140 Result Buffer ............................................................ 135 Sampling Requirements ........................................... 137 Selecting the Conversion Clock ............................... 136 Selecting the Conversion Sequence ........................ 135 TAD vs. Device Operating Frequencies Table .......... 136 16-bit Integer and Fractional Modes Example ................... 21 16-bit Up/Down Position Counter Mode ............................. 90 Count Direction Status ............................................... 90 Error Checking ........................................................... 90 6-Output PWM Register Map ............................................................ 105 6-Output PWM vs. 8-Output PWM Feature Summary ...................................................... 95 8-Output PWM Register Map ............................................................ 105 2002 Microchip Technology Inc. Advance Information DS70082A-page 179 DSPIC30F NOTES: DS70082A-page 180 Advance Information 2002 Microchip Technology Inc. dsPIC30F ON-LINE SUPPORT Systems Information and Upgrade Hot Line Microchip provides on-line support on the Microchip World Wide Web (WWW) site. The web site is used by Microchip as a means to make files and information easily available to customers. To view the site, the user must have access to the Internet and a web browser, such as Netscape or Microsoft Explorer. Files are also available for FTP download from our FTP site. The Systems Information and Upgrade Line provides system users a listing of the latest versions of all of Microchip's development systems software products. Plus, this line provides information on how customers can receive any currently available upgrade kits.The Hot Line Numbers are: 1-800-755-2345 for U.S. and most of Canada, and 1-480-792-7302 for the rest of the world. Connecting to the Microchip Internet Web Site 013001 The Microchip web site is available by using your favorite Internet browser to attach to: www.microchip.com The file transfer site is available by using an FTP service to connect to: ftp://ftp.microchip.com The web site and file transfer site provide a variety of services. Users may download files for the latest Development Tools, Data Sheets, Application Notes, User's Guides, Articles and Sample Programs. A variety of Microchip specific business information is also available, including listings of Microchip sales offices, distributors and factory representatives. Other data available for consideration is: * Latest Microchip Press Releases * Technical Support Section with Frequently Asked Questions * Design Tips * Device Errata * Job Postings * Microchip Consultant Program Member Listing * Links to other useful web sites related to Microchip Products * Conferences for products, Development Systems, technical information and more * Listing of seminars and events 2002 Microchip Technology Inc. Advance Information DS70082A-page181 dsPIC30F READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this Data Sheet. To: Technical Publications Manager RE: Reader Response Total Pages Sent From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Device: dsPIC30F Y N Literature Number: DS70082A Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this data sheet easy to follow? If not, why? 4. What additions to the data sheet do you think would enhance the structure and subject? 5. What deletions from the data sheet could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? 8. How would you improve our software, systems, and silicon products? DS70082A-page182 Advance Information 2002 Microchip Technology Inc. dsPIC30F PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. d s P I C 3 0 L F 1 0 0 1 AT P - I / P T- 0 0 0 Custom ID Trademark Family PT PT PF SO SP P S W L = Low Voltage Memory Type FLASH = F Memory Size in Bytes 0 = ROMless 1 = 1K to 6K 2 = 7K to 12K 3 = 13K to 24K 4 = 25K to 48K 5 = 49K to 96K 6 = 97K to 192K 7 = 193K to 384K 8 = 385K to 768K 9 = 769K and Up = = = = = = = = Package TQFP 10x10 TQFP 12x12 TQFP 14x14 SOIC SDIP DIP Die (Waffle Pack) Die (Wafers) Temperature I = Industrial -40C to +85C E = Extended High Temp -40C to +125C P = Pilot T = Tape and Reel A,B,C... = Revision Device ID Examples: a) dsPIC30F2011ATP-E/SO = Extended temp., SOIC package, Rev. A. b) dsPIC30F6014ATP-I/PT = Industrial temp., TQFP package, Rev. A. c) dsPIC30F3011ATP-I/P = Industrial temp., PDIP package, Rev. A. * JW Devices are UV erasable and can be programmed to any device configuration. JW Devices meet the electrical requirement of each oscillator type. Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. 2. 3. Your local Microchip sales office The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products. 2002 Microchip Technology Inc. Advance Information DS70082A-page 183 M WORLDWIDE SALES AND SERVICE AMERICAS ASIA/PACIFIC Japan Corporate Office Australia 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: 480-792-7627 Web Address: http://www.microchip.com Microchip Technology Australia Pty Ltd Suite 22, 41 Rawson Street Epping 2121, NSW Australia Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 Microchip Technology Japan K.K. Benex S-1 6F 3-18-20, Shinyokohama Kohoku-Ku, Yokohama-shi Kanagawa, 222-0033, Japan Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Rocky Mountain China - Beijing 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7966 Fax: 480-792-4338 Microchip Technology Consulting (Shanghai) Co., Ltd., Beijing Liaison Office Unit 915 Bei Hai Wan Tai Bldg. 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Le Colleoni 1 20041 Agrate Brianza Milan, Italy Tel: 39-039-65791-1 Fax: 39-039-6899883 United Kingdom Microchip Ltd. 505 Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG41 5TU Tel: 44 118 921 5869 Fax: 44-118 921-5820 05/16/02 DS70082A-page 184 Advance Information 2002 Microchip Technology Inc.