2002 Microchip Technology Inc. Advance Information DS70082A
dsPIC30F Data Sheet
Motor Control and
Power Conversion Family
High Performance
Digital Signal Controllers
M
DS70082A - page ii Advance Information 2002 Microchip Technology Inc.
Information contained in this publication regarding device
applications and the like is intended through sug gestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microc hip Technology Incorporated with respect
to the accuracy or use of such inf orm ation, or inf ringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical com-
ponents in life support systems is not authorized except with
express written approval by Microchip. No licenses are con-
veyed, implicitly or otherwise, under any intellectual property
rights.
Trademarks
The Microchip name and logo, the Microchip logo, FilterLab,
KEELOQ, microID, MPLAB, PIC, PICmicro, PICMASTER,
PICSTART, PRO MATE, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
dsPIC, ECONOMONITOR, FanSense, FlexRO M, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, microPort,
Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM,
MXDEV, MXLAB, PICC, PICDEM, PICDEM.net, rfPIC, Se lect
Mode and Total Endurance are trademarks of Microchip
Technology Incorporated in the U.S.A.
Serialized Quick Turn Programming (SQTP) is a service mark
of Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2002, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999. The
Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code ho pp in g
devices, Serial EEPROMs and microperipheral
products. In addition, Microchips quality
system for the design and manufacture of
development systems is ISO 9001 certified.
Note the following details of the code protection feature on PICmicro® MCUs.
The PICmicro family meets the specifications contained in the Microchip Data Sheet.
Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today,
when used in the intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowl-
edge, require using the PICmicro microcontroller in a manner outside the operating specifications contained in the data sheet.
The person doing so may be engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as unbreakable.
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of
our product.
If you have any further questions about this matter, please contact the local sales office nearest to you.
2002 Microchip Technology Inc. Advance Information DS70082A-page 1
MdsPIC30F
High Performance Modified RISC CPU:
Modified Harvard architecture
C compiler optimized instruction set architecture
88 base instructions
24-bit wide instructions, 16-bit wide data path
Linear pr ogram memory addressing up to 4M
Instruction Words
Linear data memory addre ssing up to 64 Kbytes
Up to 144 Kbytes on-chip FLASH program space
- Up to 48K Instr uction Words
Up to 8 Kbytes of on-chip data RAM
Up to 4 Kbytes of non-volatile data EEPROM
16 x 16-bit working register array
Three Address Generation Units that enable:
- Dual data fetch
- Accumulator write back for DSP operations
Flexible Addressing modes supporting:
- Indirect, Modulo and Bit-Reversed modes
Two, 40-bit wide accumulators with optional
saturati on log ic
17-bit x 17-bit single cycle hardware fractional/
integer multiplier
Single cycle Multiply-Accumulate (MAC) operation
40-stage Barrel Shifter
Up to 30 MIPs operation:
- DC to 40 MHz external clock input
- 4 MHz - 10 MHz oscillator input with
PLL active (4x, 8x, 16x)
Up to 42 interrupt sources
- 8 user selectable priority levels
Vector table with up to 62 vectors
- 54 interrupt vectors
- 8 processor exceptions and software traps
Peripheral Feat ures:
High current sink /source I/O pi ns: 25 mA/25 mA
Up to 5 external interrupt sources
Timer module with programmable prescaler:
- Up to five 16-bit timers/counters; optionally
pair up 16-bit timers into 32-bit timer modules
16-bit Capture input functions
16-bit Compare /PWM output functions
- Dua l Co mpare mode availabl e
3-wire SPITM modules (supports 4 Frame modes)
I2CTM module suppo r t s Mu lti-Master /Sla ve mo de
and 7-bit/10-bit addressing
Peripheral Feat ures (Continued):
Addressable UART modules supporting:
- Interrupt on address bit
- Wake-up on START bit
- 4 characters deep TX and RX FIFO buffers
CAN bus modules
Motor Control PWM Module Features:
Up to 8 PWM output channels
- Complement ary or Indepe ndent Outpu t modes
- Edge and Center Aligned modes
4 duty cycle generators
Dedicated time-base with 4 modes
Programmable output polarity
Dead-time control for Complementary mode
Manual output control
Trigger for A/D conversions
Quadrature Encoder Interface Module
Features:
Phase A, Phase B and Index Pulse input
16-bit up/down position counter
Count di rection s tatus
Position Measurement (x2 and x4) mode
Programmable digital noise filters on inputs
Alternate 16-bit Timer/Counter mode
Interrupt on position counter rollover/underflow
Input Capture Module Features:
Captures 16- bit t imer value
- Capture every 1st, 4th or 16th rising edge
- Capture every falling edge
- Capture every rising and falling edge
Resolution of 33 ns at 30 MIPs
Timer2 or Timer3 time-base selection
Input Capt ure duri ng ID LE
Interrupt on input capture event
Analog Features:
10-bit Analog-to-Digital Converter (A/D) with:
- 500 Ksps (for 10-bit A/D) co nversion rate
- Up to 16 input channels
- Conversion available during SLEEP and IDLE
Programmable Low Voltage Detection (PLVD)
Programmable Brown-out Detection and Reset
generation
dsPIC30F Enhan ced FLASH 16-bit Digital Signal Contr ollers
Motor Contr ol and Power Conversion Family
2002 Microchip Technology Inc. Advance Information DS70082A-page 2
dsPIC30F
Special Microcontroller Features:
Enhanced FLASH program memory
- 10,000 erase/write cycle (typical) for
industrial temperature range
Data EEPROM memory
- 100,000 erase/write cycle (typical)
industrial temperature range
Self-reprogrammable under software control
Power-on Reset (POR), Power-up Timer (PWRT)
and Oscillator Start-up Timer (OST)
Flexible Watchdog Timer (WDT) with on-chip low
power RC oscillator for reliable operation
Fail-Safe clock monitor operation
- Det ec t s clo ck failu re and sw it ch es to on-c hip
low power RC oscillator
Programmable code protection
In-Circuit Serial Programming (ICSP) via 3
pins and power/ground
Selectable Power Management modes
- SLEEP, IDLE and Alternate Clock modes
CMOS Technology:
Low power, high speed FLASH technology
Wide operating voltage range (2.5V to 5.5V)
Industrial and Extended temperature ranges
Low power consumption
2002 Microchip Technology Inc. Advance Information DS70082A-page 3
dsPIC30F
dsPIC30F Motor Control and Powe r Conversion Family
Pin Diagrams
Device Pins Program
Mem. Bytes/
Instructions
SRAM
Bytes EEPROM
Bytes Timer
16-bit Input
Cap
Output
Comp/Std
PWM
Motor
Control
PWM
A/D 10-bit
500 Ksps Quad
Enc
UART
SPITM
I2CTM
CAN
dsPIC30F2010 28 12K/4K 512 1024 3 4 2 6 ch 6 ch Yes 1 1 1 -
dsPIC30F3010 28 24K/8K 1024 1024 5 4 2 6 ch 6 ch Yes 1 1 1 -
dsPIC30F4012 28 48K/16K 2048 1024 5 4 2 6 ch 6 ch Yes 1 1 1 1
dsPIC30F3011 40/44 24K/8K 1024 1024 5 4 4 6 ch 9 ch Yes 2 1 1 -
dsPIC30F4011 40/44 48K/16K 2048 1024 5 4 4 6 ch 9 ch Yes 2 1 1 1
dsPIC30F5015* 64 66K/22K 2048 1024 5 4 4 8 ch 16 ch Yes 1 2 1 1
dsPIC30F6010 80 144K/48K 8192 4096 5 8 8 8 ch 16 ch Yes 2 2 1 2
* Pinout for dsPIC30F5015 will be provided at a later date.
MCLR
PWM1L/RE0
PWM1H/RE1
PWM2L/RE2
PWM2H/RE3
PWM3L/RE4
PWM3H/RE5VSS
VDD
PGD/EMUD/AN0/VREF+/CN2/RB0
PGC/EMUC/AN1/VREF-/CN3/RB1
AVDD
AVSS
AN2/SS1/LVDIN/CN4/RB2
EMUD2/OC2/IC2/INT2/RD1 EMUC2/OC1/IC1/INT1/RD0
EMUC1/SOSC1/T1CK/U1ARX/CN0/RC14
EMUD1/SOSC2/T2CK/U1ATX/CN1/RC13 VSS
OSC2/CLKO/RC15
OSC1/CLKI VDD
EMUC3/FLTA/INT0/SCK1/OCFA/RE8
U1RX/SDI1/SDA/C1RX/RF2
EMUD3/U1TX/SDO1/SCL/C1TX/RF3
AN5/QEB/IC8/CN7/RB5
AN4/QEA/IC7/CN6/RB4
AN3/INDX/CN5/RB3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
28-Pin SDIP
Note: Pinout subject to change.
dsPIC30F2010
AN7/RB7
AN6/OCFA/RB6
C1RX/RF0
C1TX/RF1
OC3/RD2
EMUC2/OC1/IC1/INT1/RD0
AN8/RB8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
dsPIC30F3011
MCLR
VDD
VSS
PGD/EMUD/AN0/VREF+/CN2/RB0
PGC/EMUC/AN1/VREF-/CN3/RB1
AN2/SS1/LVDIN/CN4/RB2
EMUD2/OC2/IC2/INT2/RD1
EMUC1/SOSC1/T1CK/U1ARX/CN0/RC14
EMUD1/SOSC2/T2CK/U1ATX/CN1/RC13
OSC2/CLKO/RC15
OSC1/CLKI
AN5/QEB/IC8/CN7/RB5
AN4/QEA/IC7/CN6/RB4
AN3/INDX/CN5/RB3
PWM1L/RE0
PWM1H/RE1
PWM2L/RE2
PWM2H/RE3
PWM3H/RE5
AVDD
AVSS
OC4/RD3
VSS
VDD
EMUC3/SCK1/RF6
U1RX/SDI1/SDA/RF2
EMUD3/U1TX/SDO1/SCK/RF3
PWM3L/RE4
VSS VDD
U2RX/RF4
U2TX/RF5
FLTA/INT0/RE8
40-Pin PDIP
Note: Pinout subject to change.
dsPIC30F3010
dsPIC30F4012
dsPIC30F4011
2002 Microchip Technology Inc. Advance Information DS70082A-page 4
dsPIC30F
Pin Diagrams (Continued)
10
11
2
3
4
5
6
1
18
19
20
21
22
12
13
14
15
38
8
7
44
43
42
41
40
39
16
17
29
30
31
32
33
23
24
25
26
27
28
36
34
35
9
37
EMUD3/U1TX/SDO1/SCL/RF3
EMUC3/SCK1/TC1/RF6
EMUC2/OC1/IC1/INT1/RD0
OC3/RD2
VDD
EMUC1/SOSC1/T1CK/U1ARX/CN0/RC14
NC
VSS
OC4/RD3
EMUD2/OC2/IC2/INT2/RD1
FLTA/INT0/RE8
AN3/INDX/CN5/RB3
AN2/SS1/LVDIN/CN4/RB2
PGC/EMUC/AN1/VREF-/CN3/RB1
PGD/EMUD/AN0/VREF+/CN2/RB0
MCLR
NC
AVDD
AVSS
PWM1L/RE0
PWM1H/RE1
PWM2L/RE2
PWM2H/RE3
PWM3L/RE4
PWM3H/RE5
VDD
VSS
NC
C1RX/RF0
C1TX/RF1
U2RXRF4
U2TX/RF5
U1RX/SDI1/SDA/RF2
AN4/QEA/IC7/CN6/RB4
AN5/QEB/IC8/CN7/RB5
AN6/OCFA/RB6
AN7/RB7
AN8/RB8
NC
VDD
VSS
OSC1/CLKI
OSC2/CLKO/RC15
EMUD1/SOSC2/T2CK/U1ATX/CN1/RC13
dsPIC30F3011
44-Pin TQFP
Note: Pinout subject to change.
dsPIC30F4011
2002 Microchip Technology Inc. Advance Information DS70082A-page 5
dsPIC30F
Pin Diagrams (Continued)
72
74
73
71
70
69
68
67
66
65
64
63
62
61
20
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
50
49
48
47
46
45
44
21
41
40
39
38
37
36
35
34
23
24
25
26
27
28
29
30
31
32
33
dsPIC30F6010
17
18
19
75
1
57
56
55
54
53
52
51
60
59
58
43
42
76
78
77
79
22
80
IC5/RD12
OC4/RD3
OC3/RD2
EMUD2/OC2/RD1
PWM2L/RE2
PWM1H/RE1
PWM1L/RE0
C2RX/RG0
C2TX/RG1
C1TX/RF1
C1RX/RF0
PWM3L/RE4
PWM2H/RE3
OC8/CN16/UPDN/RD7
OC6/CN14/RD5
EMUC2/OC1/RD0
IC4/RD11
IC2/RD9
IC1/RD8
INT4/RA15
IC3/RD10
INT3/RA14
VSS
OSC1/CLKI
VDD
SCL/RG2
U1RX/RF2
U1TX/RF3
EMUC1/SOSC1/
EMUD1/SOSC2/CN1/RC13
VREF+/RA10
VREF-/RA9
AVDD
AVSS
AN8/RB8
AN9/RB9
AN10/RB10
AN11/RB11
VDD
U2RX/CN17/RF4
IC8/CN21/RD15
U2TX/CN18/RF5
AN6/OCFA/RB6
AN7/RB7
PWM4H/RE7
T2CK/RC1
T4CK/RC3
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
SS2/CN11/RG9
AN4/QEA/CN6/RB4
AN3/INDX/CN5/RB3
AN2/SS1/LVDIN/CN4/RB2
PGC/EMUC/AN1/CN3/RB1
PGD/EMUD/AN0/CN2/RB0
VSS
VDD
PWM3H/RE5
PWM4L/RE6
FLTB/INT2/RE9
FLTA/INT1/RE8
AN12/RB12
AN13/RB13
AN14/RB14
AN15/OCFB/CN12/RB15
VDD
VSS
OC5/CN13/RD4
IC6/CN19/RD13
SDA/RG3
SDI1/RF7
EMUD3/SDO1/RF8
AN5/QEB/CN7/RB5
VSS
OSC2/CLKO/RC15
OC7/CN15/RD6
EMUC3/SCK1/INT0/RF6
IC7/CN 20/ RD 14
80-Pin TQFP
Note: Pinout subject to change.
T1CK/CN0/RC14
2002 Microchip Technology Inc. Advance Information DS70082A-page 6
dsPIC30F
Table of Contents
1.0 Device Ov e rv i e w.............................................................. ............................................ ............................................................ 9
2.0 Core Architecture Overview ................................................................................................................................................... 13
3.0 Memory Organization................................................ ............. .... ...... ........... .... ...... ........... ...................................................... 25
4.0 Ad dress G enerator U nits........................................................................................................................................................ 37
5.0 Exception Processing.... .................................................................................. ....................................................................... 45
6.0 FLASH Prog ram Memory............................................ ........................................................................................................... 51
7.0 Data EEPROM Memory.. ................... .................................................................................................................................... 57
8.0 I/O Ports................................................................................................................... .............................................................. 61
9.0 Timer1 Module....................................................................................................................................................................... 67
10.0 Timer2/3 Module ............................ .. .... .. ....... .... .. .... .. ....... .... .. .... .. .... ....... .. .... .. .... .. ....... .. ........................................................ 71
11.0 Timer4/5 Module ............................ .. .... .. ....... .... .. .... .. ....... .... .. .... .. .... ....... .. .... .. .... .. ....... .. ........................................................ 77
12.0 Input Capture Module............................................................................................................................................................. 81
13.0 Output Compare Module........................................................................................................................................................ 85
14.0 Quadrature Encoder Interface (QEI) Module ......................................................................................................................... 89
15.0 Motor Control PWM Module................................................................................................................................................... 95
16.0 SPI Module........................................................................................................................................................................... 107
17.0 I2C Module............ .... .. .. .. .. ..... .. .. .. .. .. .. .. .. ..... .. .... .. .. .. .. .. ..... .. .. .. .. .. .. .. .. ..... .... .. .. .. .. .. .. ..... .......................................................... 111
18.0 Universal Asynchronous Receiv er Transmitter (UAR T) Module.......................................................................................... 119
19.0 CAN Module................ .. .. .. ....... .. .. .. .. .. .. .. ..... .... .. .. .. .. .. .. ..... .... .. .. .. .. .. .. ..... .. .... .. .. .. .. .. ..... .. ........................................................ 127
20.0 10-bit High speed Analog-to-Digital Converter (A/D) Module .............................................................................................. 133
21.0 System Integration............................................................................................................................................................... 141
22.0 Instruction Set Summary...................................................................................................................................................... 153
23.0 Development Support ...................... .. .. .. ....... .. .. .... .. .. .. ....... .. .... .. .. .. ....... .. .. .... .. .. .... ..... .. .... .. .................................................. 161
24.0 Electrical Characteristics...................................................................................................................................................... 163
25.0 DC and AC Characteristics Graphs and Tables................................................................................................................... 165
26.0 Packaging Information ......................................................................................................................................................... 167
Index .................................................................................................................................................................................................. 175
On-Line Support.................... .... .. .... ....... .... .... .. .... ......... .. .... .... .. ......... .. .... .... .. ......... .... .. .... ................................................................. 181
Reader Response.............................................................................................................................................................................. 182
Product Identification System ............................................................................................................................................................ 183
2002 Microchip Technology Inc. Advance Information DS70082A-page 7
dsPIC30F
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improv e our publications to better suit your needs. Our publications will be refined and
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If you have any questions o r co mm ents regarding this publication, please c ontact the M arketing Communications Department via
E-mail at docerrors@mail.microchip.com or fax the R eader Response Form in the back of th is data sheet to (480) 792-4150.
We welcome your feedback.
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To determine if an errata sheet exists for a particular device, please check with one of the following:
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2002 Microchip Technology Inc. Advance Information DS70082A-page 8
dsPIC30F
NOTES:
2002 Microchip Technology Inc. Advance Information DS70082A-page 9
dsPIC30F
1.0 DEVICE OVERVIEW
This document contains device family specific
information for the dsPIC30F family of Digital Signal
Controller (DSC) devices. The dsPIC30F devices
contain extensive Digital Signal Processor (DSP)
functionality within a high performance 16-bit
Microcontroller (MCU) architecture.
Figure 1-1 shows a sample device block diagram.
Note: The device(s) depicted in this block
diagram are representative of the
corresponding device family. Other
devices of the same family may vary in
terms of number of pins and multiplexing of
pin functions. Typically, smaller devices in
the family contain a subset of the
periphera ls pres ent in the dev ice(s ) shown
in this diagram.
dsPIC30F
DS70082A-page 10 Advance Information 2002 Microchip Technology Inc.
FIGURE 1-1: dsPIC30F6010 BLOCK DIAGRAM
AN8/RB8
AN9/RB9
AN10/RB10
AN11/RB11
Power-up
Timer
Oscillator
Start-up Timer
POR/BOR
Reset
Watchdog
Timer
Instruction
Decode &
Control
OSC1/CLKI
MCLR
VDD, VSS
AN4/QEA/CN6/RB4
AN12/RB12
AN13/RB13
AN14/RB14
AN15/OCFB/CN12/RB15
Low Vo l tage
Detect
UART1,
SPI1, Motor Control
PWM
INT4/RA15
INT3/RA14
VREF+/RA10
VREF-/RA9
CAN2
Timing
Generation
CAN1,
AN5/QEB/CN7/RB5
16
PCH PCL
16
Program Counter
ALU<16>
16
Address Latch
Prog ram Memory
(144 Kbytes)
Data Latch
24
24
24
24
X Data Bus
IR
I2C
QEI
AN6/OCFA/RB6
AN7/RB7
PCU
PWM1L/RE0
PWM1H/RE1
PWM2L/RE2
PWM2H/RE3
PWM3L/RE4
10-bit ADC
Timers
PWM3H/RE5
PWM4L/RE6
PWM4H/RE7
FLTA/INT1/RE8
FLTB/INT2/RE9
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
SS2/CN11/RG9
U2TX/CN18/RF5
EMUC3/SCK1/INT0/RF6
SDI1/RF7
EMUD3/SDO1/RF8
Input
Capture
Module
Output
Compare
Module
EMUC1/SOSC1/T1CK/CN0/RC14
EMUD1/SOSC2/CN1/RC13
T4CK/RC3
T2CK/RC1
PORTB
C1RX/RF0
C1TX/RF1
U1RX/RF2
U1TX/RF3
C2RX/RG0
C2TX/RG1
SCL/RG2
SDA/RG3
PORTG PORTF
PORTD
16
16 16
16 x 16
W Reg Array
Divide
Unit
Engine
DSP
Decode
ROM Latch
16
Y Data Bus
Effective Address
X RAGU
X WAGU
Y AGU
PGD/EMUD/AN0/CN2/RB0
PGC/EMUC/AN1/CN3/RB1
AN2/SS1/LVDIN/CN4/RB2
AN3/INDX/CN5/RB3
OSC2/CLKO/RC15
U2RX/CN17/RF4
AVDD, A VSS
UART2
SPI2
16
16
16
16
16
PORTA
PORTC
PORTE
16
16
16
16
8
Interrupt
Controller
PSV & Table
Data Access
Control Bl ock
Stack
Control
Logic
Loop
Control
Logic
Data LatchData Latch
Y Data
(4 Kbytes)
RAM X Data
(4 Kbytes)
RAM
Address
Latch
Address
Latch
Control Signals
to Variou s Blocks
EMUC2/OC1/RD0
EMUD2/OC2/RD1
OC3/RD2
OC4/RD3
OC5/CN13/RD4
OC6/CN14/RD5
OC7/CN15/RD6
OC8/CN16/UPDN/RD7
IC1/RD8
IC2/RD9
IC3/RD10
IC4/RD11
IC5/RD12
IC6/CN19/RD13
IC7/CN20/RD14
IC8/CN21/RD15
16
Data EEP ROM
(4 Kbyt es)
2002 Microchip Technology Inc. Advance Information DS70082A-page 11
dsPIC30F
Table 1-1 provides a brief description of device I/O
pinouts and the functions that may be multiplexed to a
port pin. Multiple functions may exist on one port pin.
When multiplexing occurs, the peripheral modules
functional requirements may force an override of the
data dire ction of the port pin.
TABLE 1-1: PINOUT I/O DESCRIPTIONS
Pin Name Pin
Type Buffer
Type Description
AN0 - AN 15 IAnalog Analog input channels.
AN0 and AN1 are also used for device progr amming data and clock inputs, respect ively.
AVDD P P Positive supply for analog module.
AVSS P P Ground referenc e f or anal og module .
CLKI
CLKO I
OST/CMOS
External cl ock source inpu t. Al ways assoc i at ed wi t h O SC 1 pin function.
Oscillator crystal output. Connects to crystal or resonator in Crystal
Oscillator mode. Optionally functions as CLKO in RC and EC modes. Always
associ at ed with OSC2 pin func tion.
CN0 - CN23 IST Input change notification inputs.
Can be s of twa re programm ed for internal w eak pull-ups on al l in puts.
COFS
CSCK
CSDI
CSDO
I/O
I/O
I
O
ST
ST
ST
Data Co nverter Int er fa ce fr am e synchroni zation pin.
Dat a C onverter Interface serial cl ock inpu t /output pi n.
Data Co nv erter Interfa ce serial dat a in put pin.
Data Converter Interface serial data output pin.
C1RX
C1TX
C2RX
C2TX
I
O
I
O
ST
ST
CAN1 bus receive pi n.
CAN1 bus transm i t pin.
CAN2 bus receive pi n.
CAN2 bus transm i t pin.
EMUD
EMUC
EMUD1
EMUC1
EMUD2
EMUC2
EMUD3
EMUC3
I/O
I
I/O
I
I/O
I
I/O
I
ST
ST
ST
ST
ST
ST
ST
ST
ICD Primary Comm unication Channel dat a i nput/output pin.
ICD Primary Comm unication Channel cl ock input pin.
ICD Sec on dary Com m uni cation Channel dat a in pu t/output pin.
ICD Sec ondary Co m munication Channel clock input pin.
ICD Te rti ary C om m unication Channel dat a input/out put pin.
ICD Te rti ary C om m unication Chan nel clock input pin.
ICD Quaternar y Com munication Channel data inp ut / output pin.
ICD Quaternar y C om m unication Channel cl ock input p in .
IC1 - IC8 IST Capture inputs 1 through 8.
INDX
QEA
QEB
UPDN
I
I
I
O
ST
ST
ST
CMOS
Quadrature Encoder Index Pulse input.
Quadrat ur e Encoder Phase A input in QEI m ode.
Auxiliary Timer External Clock/Gate input in Timer mode.
Quadrat ur e Encoder Phase A input in QEI m ode.
Auxiliary Timer External Clock/Gate input in Timer mode.
Positio n Up/ D own Count er Dir ec tion State.
INT0
INT1
INT2
INT3
INT4
I
I
I
I
I
ST
ST
ST
ST
ST
Ex tern a l interr u pt 0.
Ex tern a l interr u pt 1.
Ex tern a l interr u pt 2.
Ex tern a l interr u pt 3.
Ex tern a l interr u pt 4.
LVDIN IAnalog Low Voltage Detect Reference Voltage input pin.
FLTA
FLTB
PWM1L
PWM1H
PWM2L
PWM2H
PWM3L
PWM3H
PWM4L
PWM4H
I
I
O
O
O
O
O
O
O
O
ST
ST
PWM Fa ult A inpu t .
PWM Fa ult B inpu t .
PWM 1 Lo w output.
PWM 1 High output.
PWM 2 Lo w output.
PWM 2 High output.
PWM 3 Lo w output.
PWM 3 High output.
PWM 4 Lo w output.
PWM 4 High output.
Legend: CMOS = CMOS compatible input or output Analog = Analog input
ST = Schmitt Tr ig ger input with CMOS levels O = Output
I = Input P = Power
dsPIC30F
DS70082A-page 12 Advance Information 2002 Microchip Technology Inc.
MCLR I/P ST Mast er Clea r ( R es et ) input or prog ra m m in g voltage input. This pin is an act i ve low
RESET t o th e device.
OCFA
OCFB
OC1 - OC8
I
I
O
ST
ST
Compare Fault A input (fo r Compare cha nnels 1, 2, 3 and 4).
Compare Fault B input (fo r Compare cha nnels 5, 6, 7 and 8).
Compare output s 1 t hr ough 8.
OSC1
OSC2 I
I/O ST/CMOS
Oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise.
Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode.
Option al ly fu nctions as CLKO i n R C and EC modes.
PGD
PGC I/O
IST
ST In-Circ uit Se rial Pr ogr am ming data i nput/outpu t pin.
In-Circ uit Se rial Pr ogr am m i ng cl ock input pin.
RA9 - RA10
RA14 - RA15 I/O
I/O ST
ST PORTA is a bi-directional I/O port.
RB0 - RB15 I/O ST PORTB is a bi-directional I/O port.
RC1
RC3
RC13 - R C15
I/O
I/O
I/O
ST
ST
ST
PORTC is a bi-directional I/O port.
RD0 - RD15 I/O ST PORTD is a bi-directional I/O port.
RE0 - RE9 I/O ST PORTE is a bi-directional I/O port.
RF0 - RF8 I/O ST PORTF is a bi-direc tion al I/O port.
RG0 - RG3
RG6 - RG9 I/O
I/O ST
ST PORTG is a bi-directional I/O port.
SCK1
SDI1
SDO1
SS1
SCK2
SDI2
SDO2
SS2
I/O
I
O
I
I/O
I
O
I
ST
ST
ST
ST
ST
ST
Synchronous serial clock input/output for SPI1.
SPI1 Data In.
SPI1 Data Out.
SPI1 Slave Synchronization.
Synchronous serial clock input/output for SPI2.
SPI2 Data In.
SPI2 Data Out.
SPI2 Slave Synchronization.
SCL
SDA I/O
I/O ST
ST Synchronous serial clock input/output for I2C.
Synchronous serial data input/output for I2C.
SOSC1
SOSC2 I
OST/CMOS
32 kHz low power oscillator crystal input; CMOS otherwise.
32 kHz low power osc i llat or crysta l ou t put .
T1CK
T2CK
T3CK
T4CK
T5CK
I
I
I
I
I
ST
ST
ST
ST
ST
Timer1 external clock input.
Timer2 external clock input.
Timer3 external clock input.
Timer4 external clock input.
Timer5 external clock input.
U1RX
U1TX
U1ARX
U1ATX
U2RX
U2TX
I
O
I
O
I
O
ST
ST
ST
UART1 Receive.
UART1 Transmit.
UART1 Alte r nate Re ceive.
UART1 Alte r nate Transm it.
UART2 Receive.
UART2 Transmit.
VDD PPositive supply for logic and I/O pins.
VSS PGround reference for logic and I/O pins.
VREF+ I Analog Analog Voltage Reference (High) input.
VREF- I Analog Analog Voltage Reference (Low) input.
TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name Pin
Type Buffer
Type Description
Legend: CMOS = CMOS compatible input or output Analog = Analog input
ST = Schmitt Tr ig ger input with CMOS levels O = Output
I = Input P = Power
2002 Microchip Technology Inc. Advance Information DS70082A-page 13
dsPIC30F
2.0 CORE ARCHITECTURE
OVERVIEW
2.1 Core Overview
The core has a 24-bit instruction word. The Program
Counter (PC) is 23-bits wide with the Least Significant
(LS) bit always clear (see Section 3.1), and the Most
Significant (MS) bit is ignored during normal program
execution, except for certain specialized instructions.
Thus, the PC can address up to 4M instruction words
of user pro gram space. An inst ruc tion pr e- fetc h mech -
anism is used to help maintain throughput. Uncondi-
tional overhead free program loop constructs are
supported using the DO and REPEAT instr uct i ons, bot h
of which are int errup tib le at any point.
The work ing re giste r array c onsist s o f 16 x 16 -bit re gis-
ters, each of which can act as data, address or offset
registers. One working register (W15) operates as a
software stack pointer for interrupts and calls.
The data space is 64 Kbytes (32K words), and is split
into two blocks, referred to as X and Y data memory.
Each block has its own independent Address Genera-
tion Unit (AGU). Most instructions operate solely
through the X memory AGU, which provides the
appearance of a single unified data space. The
Multiply-Accumulate (MAC) class of dual source DSP
instructions operate through both the X and Y AGUs,
splitting the data address space into two parts (see
Section 3.2). The X and Y data space boundary is
device specific and cannot be altered by the user . Each
data word consists of 2 bytes, and most instructions
can address data either as words or bytes.
There are two methods of accessing data stored in
program memory:
The upper 32 Kbytes of data space memory can
optionally be mapped into the lower half (user
space) of program space at any 16K program
word boundary, defined by the 8-bit Program
Spac e Visibility Page (PSVP AG) register . This let s
any ins truction a ccess p rogram sp ace as if it were
data space, with the sole limitation that the access
requires an additional cycle. Moreover, only the
lower 16 bits of each instruction word can be
accessed using this method.
Linear indirect access of 32K word pages within
progra m spac e is also possibl e using any w orking
register, via table read and write instructions.
Table read and write instructions can be used to
access all 24 bits of an instruction word.
Overhead-free circular buf fers (modulo addressing) are
supported in both X and Y address spaces. This is pri-
marily intended to remove the loop overhead for DSP
algorithms.
The X AGU also supports bit-reversed addressing on
destination ef fective addresses, to g reatly simplify input
or output data reordering for radix-2 FFT algorithms.
Refer to Section 4.0 for details on modulo and
bit-reversed addressing.
The core s up ports Inherent (no opera nd), Relative, Lit-
eral, Memory Direct, Register Direct, Register Indirect,
Register Offset and Literal Offset Addressing modes.
Instruct ions ar e associat ed with p redefined Addressin g
modes, depending upon their functional requirements.
For m os t i ns tru c ti o ns , the c or e i s c apa bl e of e xe c ut i ng
a data (or program data) memory read, a working reg-
ister (data) read, a data memory write and a program
(instruction) memory read per instruction cycle. As a
result, 3-operand instructions are supported, allowing
C = A+B operations to be executed in a single cycle.
A DSP engine has been included to significantly
enhance the core arithmetic capab ility and t hroughput.
It features a high speed 17-bit by 17-bit multiplier, a
40-bit ALU, two 40-bit saturating accumulators and a
40-bit bi-directional barrel shifter. Data in the accumu-
lator or any worki ng register can be shi fted up to 15 bit s
right or 16 bits left in a single cycle. The DSP instruc-
tions ope rate sea mles sly with all other in struct ions an d
have be en desi gned for o ptimal re al-time p erforma nce.
The MAC class of instructions can concurrently fetch
two data operands from memory, while multiplying two
W registers. To enable this concurrent fetching of data
operands, the data space is split for these instructions
and linear for all others. This is achieved in a transpar-
ent and flexible manner, through dedicating certain
working registers to each address space for the MAC
class of instructions.
The core does not support a multi-stage instruction
pipeline. However, a single stage instruction pre-fetch
mechanism is used, which accesses and partially
pre-decodes instructions a cycle ahead to maximize
availa ble executio n time. Mos t instructions execute in a
single cycle, with certain exceptions as outlined in
Section 2.3.
The core features a vectored exception processing
structure for traps and interrupts, with 62 independent
vectors. The exceptions consist of up to 8 traps (of
which 4 are res erv ed ) an d 54 interrupts . Eac h in terru pt
is prio ritized based o n a use r assigned priori ty betwee n
1 and 7 (1 being the lowest priority and 7 being the
highest) in conjunction with a predetermined natural
order. T raps hav e fixed prio rities, rangi ng from 8 to 15.
dsPIC30F
DS70082A-page 14 Advance Information 2002 Microchip Technology Inc.
2.2 Programmers Model
The programmers model is shown in Figure 2-1 and
consists of 16 x 16-bit working registers (W0 through
W15), 2 x 40-bit accumulators (AccA and AccB),
STATUS register (SR), Data Table Page register
(TBLPAG), Program Space Visibility Page register
(PSVPAG), DO and REPEAT registers (DOSTART,
DOEND, DCOUNT and RCOUNT), and Program
Counter (PC). The working registers can act as data,
address or offset registers. All registers are memory
mapped. W0 acts as the W register for file register
addressing.
Most o f these registers h ave a shadow regi ste r a ss oc i-
ated with each of them, as shown in Figure 2-1. The
shadow register is used as a temporary holding register
and can tr ansfer its con ten t s t o or fro m i t s hos t reg is ter
upon some the occurrence of an event. None of the
shadow registers are accessible directly. The following
rules apply for transfer of registers into and out of
shadows.
PUSH.S and POP.S
W0...W14, TBLPAG, PSVPAG, SR (DC, N, OV, Z
and C bits only) transferred
DO instruction
DOSTART, DOEND, DCOUNT shadows push ed
on loop start, popped on loop end
When a byte operation is performed on a working reg-
ister, only th e L eas t S ign ifi can t By te of t he target regi s-
ter is affected. However, a benefit of memory mapped
working registers is that both the Least and Most Sig-
nificant Bytes can be manipulated through byte wide
data m emory space accesses .
2.2.1 SOFTWARE STACK POINTER/
FRAME POINTER
The dsPICTM de vice s contain a softw are sta ck. W1 5 is
the dedicated software stack pointer (SP), and will be
automatically modified by exception processing and
subrouti ne call s and returns. H owever, W15 can b e ref-
erenced by any instruction in the same manner as all
other W registers. This simplifies the reading, writing
and manipulation of the stack pointer (e.g., creating
stac k fram es ).
W15 is initialized to 0x0800 during a RESET. The user
may reprogram the SP during initialization to any
location within data space.
W14 has been dedicated as a stack frame pointer as
defined by the LNK and ULNK instructions. However,
W14 can be referenced by any instruction in the same
manner as all other W registers.
2.2.2 STATUS REGISTER
The dsPIC core has a 16-bit status register (SR), the
LS Byte of which is referred to as the SR Low Byte
(SRL) and the MS Byte as the SR High Byte (SRH).
See Figure 2-1 for SR layout.
SRL contains all the MCU ALU operation status flags
(includ ing the Z bit ), as well as the CPU Inter rupt Prior-
ity Level status bits, IPL<2:0>, and the REPEAT active
status bit, RA. During exception processing, SRL is
concatenated with the MS Byte of the PC to form a
complete word value which is then stacked.
The upper byte of the STATUS register contains the
DSP Adder/Subtractor status bits, the DO Loop Active
bit (DA) and the Digit Carry (DC) status bit.
Most SR bits are read/write. Exceptions are:
1. The DA bit: DA is read and clear only, because
accidentally setting it could cause erroneous
operation.
2. The RA bit: RA is a read only bit, because acci-
dentally setting it could cause erroneous opera-
tion. RA is only set on entry into a repeat loop,
and cannot be directly cleared by software.
3. The OV, OA, OB and OAB bits: These bits are
read only and can only be set by the DSP engine
overflow logic.
4. The SA, SB and SAB bits: These are read and
clear only and can only be set by the DSP
engine saturation logic. Once set, these flags
remain s et until c leared by the user, irrespective
of the results from any subsequent DSP
operations.
2.2.2.1 Z Status Bit
Instructions that use a carry/borrow input (ADDC,
CPB, SUBB and SUBBR) will only be able to clear Z
(for a non-zero result) and can never set it. A multi-
precision sequence of instructions (starting with an
instruction with no carry/borrow input) will thus, auto-
matically logically AND the successive results of the
zero test. All results must be zero for the Z flag to
remain set by the end of the sequence.
All other instructions can set as well as clear the Z bit.
2.2.3 PROGRAM COU NTER
The Program Counter is 23-bits wide. Bit 0 is always
clear. Therefore, the PC can address up to 4M
instruction words.
Note: In o rder to pr otect against misalign ed stac k
accesses, W15<0> is always clear.
Note 1: Clearing the SAB bit will also clear both
the SA and SB bits.
2: When the memory mapped status regis-
ter (S R) i s th e de stina tio n add res s fo r an
operatio n which affects an y of the SR bits,
data writes are disabled to all bits.
2002 Microchip Technology Inc. Advance Information DS70082A-page 15
dsPIC30F
FIGURE 2-1: PROGRAMME RS MODEL
TABPAG
PC22 PC0
7 0
D0D15
Program Counter
Data Table Page Address
Status Register
Working Registers
DSP Operand
Registers
W1
W2
W3
W4
W5
W6
W7
W8
W9
W10
W11
W12/DSP Offset
W13/DSP Write Back
W14/Frame Pointer
W15/Stack Pointer
DSP Address
Registers
AD39 AD0AD31
DSP
Accumulators AccA
AccB
PSVPAG
7 0 Program Space Visibility Page Address
Z
0
OA OB SA SB
RCOUNT
15 0REPEAT Loop Counter
DCOUNT
15 0DO Loop Counter
DOSTART
22 0DO Loop Start Address
IPL2 IPL1
SPLIM Stack Pointer Limit Register
AD15
SRL
PUSH.S Shadow
DO Shadow
OAB SAB
15 0 Core Configuration Register
Legend
CORCON
DA DC RA N
TBLPAG
PSVPAG
IPL0 OV
W0/WREG
SRH
DO Loop End Address
DOEND
22
C
dsPIC30F
DS70082A-page 16 Advance Information 2002 Microchip Technology Inc.
2.3 Instruction Flow
There are 8 types of instruction flows:
1. Norma l one-word, one -cycle in struction s. These
instructions take one effective cycle to execute,
as sh own i n Figure 2-2.
FIGURE 2-2: INSTRUCTION PIPELINE FLOW: 1-WORD, 1-CYCLE
2. One-word, two-cycle (or three-cycle) instruc-
tions. These instructions include the relative
branches, relative call, skips and returns. When
an instruction changes the PC (other than to
increment it), the pipelined fetch is discarded.
This causes the instruction to take two effective
cycles to execute as shown in Figure 2-3. Some
program flow change instructions, such as skip
instructions that skip over 2-word instructions,
and the RETURN, RETFIE and RETLW instruc-
tions that are used to return from a subroutine call
or Interrupt Service Routine, require 3 cycles.
FIGURE 2-3: INSTRUCTION PIPELINE FLOW: 1-WORD, 2-CYCLE
3. One-word, two-cycle instructions that are not
flow co ntrol instru ctions. The only instructi ons of this type are the MOV.D (load and store double
word) instructions, as shown in Figure 2-4.
FIGURE 2-4: INSTRUCTION PIPELINE FLOW: 1-WORD, 2-CYCLE MOV.D OPERATIONS
TCY0TCY1TCY2TCY3TCY4TCY5
1. MOV.b #0x55,W0 Fetch 1 Execute 1
2. MOV.b #0x35,W1 Fetch 2 Execute 2
3. ADD.b W0,W1,W2 Fetch 3 Execute 3
TCY0TCY1TCY2TCY3TCY4TCY5
1. MOV #0x55,W0 Fetch 1 Execute 1
2. BTSC W1,#3 Fetch 2 Execute 2
Skip Taken
3. ADD W0,W1,W2 Fetch 3 Flush
4. BRA SUB_1 Fetch 4 Execute 4
5. SUB W0,W1,W3 Fetch 5 Flush
6. Instruction @ address SUB_1 Fetch SUB_1
TCY0TCY1TCY2TCY3TCY4TCY5
1. MOV W0,0x1234 Fetch 1 Execute 1
2. MOV.D [W0++],W1 Fetch 2 Execute 2
R/W Cycle 1
3. MOV W1,0x00AA Fetch 3 Execute 2
R/W Cycle2
3a. Stall Stall Execute 3
4. MOV 0x0CC, W0 Fetch 4 E xecute 4
2002 Microchip Technology Inc. Advance Information DS70082A-page 17
dsPIC30F
4. Table read/write in str uct ion s. Th es e in stru ctions
will suspe nd the fetching to insert a read or write
cycle to the program memory. The instruction
fetched while executing the table operation is
saved for 1 cycle and executed in the cycle
immediately after the table operation, as shown
in Figure 2-5.
FIGURE 2-5: INSTRUCTION PIPELINE FLOW: 1-WORD, 2-CYCLE TABLE OPERATIONS
5. Two-word instructions for CALL and GOTO. In
these instructions, the fetch after the instruction
provides the remainder of the jump or call desti-
nation address. These instructions require 2
cycles to execute , 1 for fetch ing the 2 i nstruction
words (enabled by a high speed path on the sec-
ond fetch), and 1 for the subsequent pipeline
flush, as shown in Figure 2 -6.
FIGURE 2-6: INSTRUCTION PIPELINE FLOW: 2-WORD, 2-CYCLE GOTO, CALL
6. Two-word instructions for DO. In these instruc-
tions, the fetch after the instruction contains an
address offset. This address offset is added to
the first instruction address to generate the last
loop instruction address. Therefore, these
instructions require two cycles, as shown in
Figure 2-7.
FIGURE 2-7: INSTRUCTION PIPELINE FLOW: 2-WORD, 2-CYCLE DO, DOW
TCY0TCY1TCY2TCY3TCY4TCY5
1. MOV #0x1234,W0 Fetch 1 Execute 1
2. TBLRDL [W0++],W1 Fetch 2 Execute 2
3. MOV #0x00AA,W1 Fetch 3 Execute 2
Read Cycle
3a. Table Operation Bus Read Execute 3
4. MOV #0x0CC,W0 Fetch 4 E xecute 4
TCY0TCY1TCY2TCY3TCY4TCY5
1. MOV #0x1234,W0 Fetch 1 Execute 1
2. GOTO LABEL Fetch 2L Update PC
2a. Second Word Fetch 2H NOP
3. Instruction @ address LABEL Fetch
LABEL Execute
LABEL
4. BSET W1, #BIT3 Fetch 4 E xecute 4
TCY0TCY1TCY2TCY3TCY4
1. PUSH DOEND Fetch 1 Execute 1
2. DO LABEL,#COUNT Fetch 2L NOP
2a. Second Word Fetch 2H Execute 2
3. 1st Instruction of Loop Fetch 3 Execute 3
dsPIC30F
DS70082A-page 18 Advance Information 2002 Microchip Technology Inc.
7. Instr uction s that are subjected to a st all due to a
data dependency between the X RAGU and X
W AGU. An a dditional cy cle is in serted to resolve
the resource conflict, as shown in Figure 2-7.
Instruction stalls caused by data dependencies
are further discussed in Section 4.0.
FIGURE 2-8: INSTRUCTION PIPELINE FLOW: 1-WORD, 2-CYCLE WITH INSTRUCTION ST ALL
8. Interrupt recognition execution. Refer to
Section 5.0 for details on interrupts.
2.4 Divide Support
The ds PIC device s feature a 16 /16-bit s igned fra ctional
divide operation, as well as 32/16-bit and 16/16-bit
signed and unsigned integer divide operations, in the
form of single instruction iterati ve divides. The followin g
instructions and data sizes are supported:
1. DIVF 16/16 signed fractional divide
2. DIV.sd 32/16 signed divide
3. DIV.ud 32/16 unsigned divide
4. DIV.sw 16/16 signed divide
5. DIV.uw 16/16 unsigned divide
The 16/16 divides are simila r to the 32/16 (same number
of iterations), but the dividend is eithe r zero-extended or
sign-extended during the first iteration.
The quotient for all divide instructions ends up in W0,
and the remainder in W1. DIV and DIVF can specify any
W register for both the 16-bit dividend and divisor. All
other divides can specify any W register for the 16-bit
divisor, but the 32-bit dividend must be in an aligned W
register pair, such as W1:W0, W3:W2, etc.
The non-restoring divide algorithm requires one cycle
for an in itial div idend sh ift (for integer divides only), one
cycle per divisor bit, and a remainder/quotient correc-
tion cycle. The correction cycle is the last cycle of the
iteration loop, but must be performed (even if the
remainder is not required) because it may also adjust
the quotient. A consequence of this is that DIVF will
also pro duce a val id rem ain der (though it is of little use
in fractional arithmetic).
The divide instructions must be executed within a
REPEAT loop. Any other form of execution (e.g. a
series of discrete divide instructions) will not function
correctly because the instruction flow depends on
RCOUNT. The divide ins truction does not automatically
set up the RCOUNT value, and it must, therefore, be
explic itly and correctl y specifi ed in the REPEAT instruc-
tion, as shown in Table 2-1 (REPEAT will execute the
target instruction {operand value+1} times). The
REPEAT loop count must be set up for 18 iterations of
the DIV/DIVF instruction. Thus, a complete divide
operation requires 19 cycles.
TABLE 2-1: DIVIDE INSTRUCTIONS
TCY0TCY1TCY2TCY3TCY4TCY5
1. MOV.b W0,[W1] Fetch 1 Execute 1
2. MOV.b [W1],PORTB Fetch 2 NOP
2a. Stall (NOP) Stall Execute 2
3. MOV.b W0,PORTB Fetch 3 Execute 3
Note: The Divide flow is interruptible. However,
the user needs to save the context as
appropriate.
Instruction Function
DIVF Signed fractional divide: Wm/Wn W0; Rem W1
DIV.sd Signed divide: (Wm+1:Wm)/Wn W0; Rem W1
DIV.sw Signed divide: Wm/Wn W0; Rem W1
DIV.ud Unsigned divide: (Wm+1:Wm)/Wn W0; Rem W1
DIV.uw Unsigned divide: Wm/Wn W0; Rem W1
2002 Microchip Technology Inc. Advance Information DS70082A-page 19
dsPIC30F
2.5 DSP Engine
Concurrent operation of the DSP engine with MCU
instruction flow is not possible, though both the MCU
ALU and DSP engine resources may be used concur-
rently by the same instruction (e.g., ED and EDAC
instructions).
The DSP engine consists of a high speed 17-bit x
17-bit multiplier, a barrel shifter and a 40-bit adder/
subtractor with two target accumulators, round and
saturati on log ic .
Dat a input t o the DSP engine i s derived f rom one o f the
following:
1. Directly from the W array (registers W4, W5, W6
or W7 ) via the X and Y da ta buses f or the MAC
class of instructions (MAC, MSC, MPY,
MPY.N, ED, EDAC, CLR and MOVSAC).
2. From the X bus for al l other DSP instructions.
3. From the X bus for all MCU instructions which
use the barrel shifter.
Data output from the DSP engine is written to o ne of the
following:
1. The target accumulator, as defined by the DSP
instruction being executed.
2. The X bus for MAC, MSC, CLR and MOVSAC
accumulator writes, where the EA is derived
from W13 on ly. (MPY, MPY.N, ED and EDAC
do not offer an accumulator write option.)
3. The X bus for all MCU instructions which use the
barrel shifter.
The DSP engine also has the capability to perform inher-
ent accumulator-to-accumulator operations, which
require no additional data. These instructions are ADD,
SUB and NEG.
The DSP engine has various options selected through
various bits in the CPU Core Configuration Register
(CORCON), as listed below:
1. Fractional or integer multiply (IF).
2. Conventional or convergent rounding (RND).
3. Automatic saturation on/off for AccA (SATA).
4. Automatic saturation on/off for AccB (SATB).
5. Automatic saturation on/off for writes to data
memory (SATDW).
6. Accumulator Saturation mode selection
(ACCSAT).
A block diagram of the DSP engine is shown in
Figure 2-9.
Note: For CORCON layout, see Table 4-3.
dsPIC30F
DS70082A-page 20 Advance Information 2002 Microchip Technology Inc.
FIGURE 2-9: DSP ENGINE BLOCK DIAGRAM
Zero Backfill
Sign-Extend
Barrel
Shifter
40-bit Accumula tor A
40-bit Accumula tor B Round
Logic
X Data Bus
To/From W Array
Adder
Saturate
Negate
32
32
33
16
16 16
16
40 40
40 40
S
a
t
u
r
a
t
e
Y Data Bus
40
Carry/Borrow Out
Carry/Borrow In
16
40
Multiplier/Scaler
17-bit
2002 Microchip Technology Inc. Advance Information DS70082A-page 21
dsPIC30F
2.5.1 MULTIPLIER
The 17x17-bit multiplier is capable of signed or unsigned
operation and can multiplex its output using a scaler to
support either 1.31 fractional (Q31), or 32-bit integer
results. Unsigned operands are zero-extended into the
17th bit of the multiplier input value. Signed operands
are sign-extended into the 17th bit of the multiplier input
value. The output of the 17x17-bit multiplier/scaler is a
33-bit value, which is sign-extended to 40 bits. The
respective number representation formats are shown in
Figure 2-10. Integer data is inherently represented as a
signed twos complement value, where the MSB is
defined as a sign bit. Generally speaking, the range of
an N-bit twos complement integer is -2N-1 to 2N-1 1.
For a 16-bit integer, the data range is -32768 (0x8000)
to 32767 (0x7FFF), including 0 (see Figure 2-10). For a
32-bit integer, the data range is -2,147,483,648
(0x8000 0000) to 2,147,483,645 (0x7FFF FFFF).
When the multip lier is configured for Frac tional m ultipli-
cation, the data is represented as a twos complement
fraction , where the MS B is define d as a sig n bit and th e
radix po int is im plied to l ie just after the sign b it (QX for-
mat) . Th e rang e of an N -bit twos complement fraction
with this implied radix point is -1.0 to (1-21-N). For a
16-bit fraction, the Q15 data range is -1.0 (0x8000) to
0.999969482 (0x7 FFF), including 0 and has a precision
of 3.01518x10-5. In Fractional mode, a 16x16 multiply
operation generates a 1.31 product, which has a
preci si on of 4.65 661 x1 0-10.
FIGURE 2-10: 16-BIT INTEGER AND FRACTIONAL MODES
Certain multiply operations always operate on signed
data. These include the MAC/MSC, MPY[.N] and
ED[AC] instructions. The 40-bit adder/subtractor may
also optionally negate one of its operand inputs to
change the result sign (without changing the oper-
ands). This is used to create a multiply and subtract
(MSC) or multiply and negate (MPY.N) operation.
In the special case when both input operands are 1.15
fractions and equal to 0x8000 (-110), the result of the
multipl icati on is corrected to 0x7FFF FFFF (as th e clo s-
est approx imation to +1) by hardware, be fore it is used.
It sh ou l d be n ot e d th at w i th t h e ex ce pt ion o f DS P mul-
tiplies, the dsPIC30F ALU operates identically on inte-
ger and fractional data. Namely, an addition of two
integers will yield the same result (binary number) as
the ad dit ion of tw o fra cti onal num ber s. The onl y diffe r-
ence is how the result is interpreted by the user. How-
ever, multiplies performed by DSP operations are
different. In these instructions, data format selection is
made by the IF bit (CORCON<0>), and it must be set
accordingly (0 for Fractional mode, 1 for Integer
mode). This is required because of the implied radix
point used by dsPIC30F fractions. In Integer mode,
multiplying two 1 6-bit integers produ ces a 32-bit integer
result. H o wev er, multiplying tw o 1.1 5 v al ues ge ne rates
a 2.30 res ult. Sinc e th e ds PIC 30 F us es 1.3 1 format for
the accumulators, a DSP multiply in Fractional mode
also includes a left shift by one bit to keep the radix
point properly aligned. This feature reduces the resolu-
tion of the DSP multiplier to 2-30, but has no other ef fect
on the computation.
The same multiplier is used to support the MCU multi-
ply instructions, which include integer 16-bit signed,
unsigned and mixed sign multiplies. Additional data
paths are provided to allow these instructions to write
the result bac k into the W array and X dat a bus (via the
W array). These paths are placed prior to the data
scaler. The IF bit in the CORCON register, therefore,
only affects the result of the MAC and MPY instructions.
All other mul tiply op eration s are ass umed to be integ er
operations. If the user executes a MAC or MPY inst ruc-
tion on fractional data, without clearing the IF bit, the
result m ust be ex plicitly s hifted le ft by the use r program
after mul tiplicati on, in orde r to obt ain the co rrect resul t.
The MUL instruction may be directed to use byte or
word si zed op erands. By te opera nds wil l direc t a 16-b it
result, and word operands will direct a 32-bit result to
the specified register(s) in the W array.
Different Representations of 0x4001
Integer:
214 213 212 211 . . . . 20
0x4001 = 214 + 20 = 16385
1.15 Fractional:
2-15
0x4001 = 2-1 + 2-15 = 0.500030518
0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1
2-1 2-2 2-3 . . .
-20
0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1
20
dsPIC30F
DS70082A-page 22 Advance Information 2002 Microchip Technology Inc.
2.5.2 DATA ACCUMULATORS AND
ADDER/SUBTRACTOR
The data accumulator consists of a 40-bit adder/
subractor with automatic sign extension logic. It can
select one of two accumulators (A or B) as its pre-
accumulation source and post-accumulation destina-
tion. For the ADD and LAC instructions, the data to be
accum ulated or l oaded ca n be optio nally sca led via th e
barrel shifter, prior to accumulation.
2.5.2.1 Adder/Subtractor, Overflow and
Saturation
The adder/subtractor is a 40-bit adder with an optional
zero inpu t into on e side and eith er true, or c omple ment
data into the other input. In the case of addition, the
carry/borrow input is active high and the other input is
true data (not complemented), whereas in the case of
subtrac tion, the carry/borrow inp ut is active low and the
other input is complemented. The adder/subtractor
generates overflow status bits SA/SB and OA/OB,
which are latched and reflected in the status register:
Overflow from bit 39: th is is a catastrophic
overflow in which the sign of the accumulator is
destroyed.
Overflow into guard bits 32 through 39: this is a
recoverable overflow. This bit is set whenever al l
the guard bits bits are not identical to each other.
The adder has an additional saturation block which
controls accumulator data saturation, if selected. It
uses the result of the adder, the overflow status bits
described above, and the SATA/B (CORCON<7:6>)
and ACCSAT (CORCON<4>) mode control bits to
determine when to saturate and to what value to
saturate.
Six status register bits have been provided to support
saturation and overflow; they are:
1. OA:
AccA overflo w ed int o guard bit s
2. OB:
AccB overflo w ed int o guard bit s
3. SA:
AccA saturat ed (bit 31 overflow and satu rati on)
or
AccA overflowed into guard bits and saturated
(bit 39 overflow and saturation)
4. SB:
AccB saturat ed (bit 31 overflow and satu rati on)
or
AccB overflowed into guard bits and saturated
(bit 39 overflow and saturation)
5. OAB:
Logical OR of OA and OB
6. SAB:
Logical OR of SA and SB
The OA and OB bits are modified each time data
passes through the adder/subtractor. When set, they
indicate that the most recent operation has overflowed
into the accumulator guard bits (bits 32 through 39).
The OA and OB bits can also optionally generate an
arithmetic warning trap when set and the correspond-
ing ove rflow trap flag enable bit (O V A T EN, OVBTEN) in
the INTCON1 re gis ter (refe r to Sec ti on 5.0) is set. Thi s
allows the user to take immediate action, for example,
to correct system gain.
The SA and SB bit s are m odified each tim e data pass es
through the adder/subtractor, but can only be cleared by
the user. When set, they indicate that the accumulator
has overflowed it s max imum range (bit 31 for 32-bi t sat-
uration, or bit 39 for 40-bit saturation) and will be satu-
rated (if saturation is enabled). When saturation is not
enabled, the SA and SB default to bit 39 overflow and
thus, indicate that a catastrop hic overflow has occurred.
If the COVTE bit in the INTCON1 register is set, SA and
SB bits will generate an arithmetic warning trap when
saturation is dis abled.
The overflow and saturation status bits can optionally
be view ed in the S tat us Register (SR) as the logic al OR
of OA and OB (in bit OAB) and the logical OR of SA and
SB (in bit SAB). This all ows programmers to chec k one
bit in the St atus Regist er to determin e if either accum u-
lator has overflowed, or one bit to determine if either
accumulator has saturated. This would be useful for
complex number arithmetic which typically uses both
the accumulators.
The device supports three Saturation and Overflow
modes.
1. Bit 39 Overflow and Saturation:
When bit 39 overflow and saturation occurs, the
saturate logic loads the maximally positive 9.31
(0x7FFFFFFFFF) or maximally negative 9.31
value (0x8000000000) into the target accumula-
tor. The SA or SB bit is set and remains set until
cleared by the user. This is referred to as super
saturation and provides protection against erro-
neous data, or unexpected algorithm problems
(e.g., gain calculations).
2. Bit 31 Overflow and Saturation:
When bit 31 overflow and saturation occurs, the
saturate logic then loads the maximally positive
1.31 value (0x007FFFFFFF) or maximally nega-
tive 1.31 value (0x0080000000) into the target
accumulator. The SA or SB bit is set and remains
set until cleared by the user. When this Saturation
mode is in effect, the guard bits are not used (so
the OA, OB or OAB bit s are never se t).
3. Bit 39 Catastrophic Overflow
The bit 39 overflow status bit from the adder is
used to set the SA or SB bit, which remain set
until cleared by the user . No saturation operation
is performed and the accumulator is allowed to
overflow (d estroying its sign). If the COVTE bit in
the INTCON1 register is set, a catastrophic
overflow can initiate a trap exception.
2002 Microchip Technology Inc. Advance Information DS70082A-page 23
dsPIC30F
2.5.2.2 Accumulator Write Back
The MAC class of instructions (with the exception of
MPY, MPY.N, ED and EDAC) can optionally write a
roun ded ver sion of t he hig h word ( bits 31 t hrough 16)
of the accumulator, that is not targeted by the instruc-
tion into data space memory. The write is performed
across the X bus into combined X and Y address
spa ce. The following Addressing modes are supported.
1. W13, Regi ste r Direct:
The rounded contents of the non-target accumula-
tor are written into W13 as a 1.15 fraction.
2. [W13]+=2, Register Indirect with Post-Increment:
The round ed contents of the non-target a ccumu-
lator are written into the address pointed to by
W13 as a 1.15 fraction. W13 is then
incremented by 2 (for a word write).
2.5.2.3 Round Logic
The round logic is a combinational block, which per-
forms a conventional (biased) or convergent (unbiased)
round function during an accumulator write (store). The
Round mode is det ermined by the state of the R ND bit
in the CORCON register. It generates a 16-bit, 1.15 data
value which is passed to the data space write saturation
logic. If rounding is not indicated by the instruction, a
truncated 1.1 5 da ta value i s sto red and the LS Word is
simply discarded.
The two Rounding modes are shown in Figure 7-7.
Conve nti ona l ro unding t ak es bit 15 o f the ac cumulator,
zero-ex tend s it and ad ds it to th e AC CxH w ord (b it s 16
through 31 of the accumulator). If the AC CxL word (bits
0 through 15 of the accumulator) is between 0x8000
and 0xFFFF (0x8000 included), ACCxH is incre-
mented. If ACCxL is between 0x0000 and 0x7FFF,
ACCxH is left unchanged. A consequence of this algo-
rithm is that over a succession of random rounding
operations, the value will tend to be biased slightly
positive.
Convergent (or unbiased) rounding operates in the
same manner as conventional rounding, except when
ACCxL equ als 0x8000. If thi s is the case, the LS bit (bit
16 of the ac cumu lator) of ACCxH is examine d. If it is 1,
ACCxH is incremented. If it is 0, ACCxH is not modi-
fied. Assuming that bit 16 is effectively random in
natur e, th is sc hem e wi ll re move any rou nding bias th at
may accumulate .
The SAC and SAC.R instructions store either a trun-
cated (SAC) or rounded (SAC.R) version of the content s
of the t arget accumul ator to data mem ory , via the X bu s
(subject to data saturation, see Section 2.5.2.4). Note
that for the MAC class of instructions, the accumulator
write back operation will function in the same manner,
addressing combined MCU (X and Y) data space
though the X bus. For this class of instructions, the data
is always subje ct to round ing .
2.5.2.4 Data Space Wri te Saturation
In addition to adder/subtractor saturation, writes to data
space may al so be satu rate d, bu t wit hou t affect ing t he
contents of the source accumulator. The data space
write saturation logic block accepts a 16-bit, 1.15 frac-
tional value from the round logic block as its input,
together with overflow status from the original source
(accumulator) and the 16-bit round adder. These are
combin ed and used t o sele ct the a ppropri ate 1.15 frac-
tional value as output to write to data space memory.
If the SATDW bit in the CORCON register is set, data
(after roundi ng or trun ca tio n) is tes ted for overflo w and
adjusted accordingly, For input data greater than
0x007FF F, data writte n to memory i s forced to the m ax-
imum positive 1.15 value, 0x7FFF. For input data less
than 0xF F80 00, dat a w ritten to me mor y is forc ed to th e
maximum negative 1.15 value, 0x8000. The MS bit of
the source (bit 39) is used to determine the sign of the
operand bei ng t es ted.
If the SATDW bit in the CORCON regis ter is not set , the
input data is always passed through unmodified under
all conditions.
2.5.3 BARREL SHIFTER
The barrel shifter is capable of performing up to 15-bit
arithmetic or logic right shifts, or up to 16-bit left shifts
in a single cycle. The source can be either of the two
DSP accumulators, or the X bus (to support multi-bit
shifts of register or memory data).
The sh ifter requires a s ign ed bi nary v al ue to de term in e
both the m agnitude (number of bits) and direct ion of the
shift operation. A positive value will shift the operand
right. A negative value will shift the operand left. A
value of 0 will not modify the operand.
The barrel shifter is 40 bits wide, thereby obtaining a
40-bit res ult for DSP shift ope rations an d a 16-bit resu lt
for MCU shift operations. Data from the X bus is pre-
sented to the barrel shifter between bit positions 16 to
31 for right shift s, and bit positi ons 0 to 15 for l eft shifts .
dsPIC30F
DS70082A-page 24 Advance Information 2002 Microchip Technology Inc.
NOTES:
2002 Microchip Technology Inc. Advance Information DS70082A-page 25
dsPIC30F
3.0 MEMORY ORGANIZATION
3.1 Program Address Space
The program address space is 4M instruction words. It
is addressable by a 24-bit value from either the PC,
table instruction EA, or data space EA, when program
space is mapped into data space, as defined by
Table 3-1. Note that the program space address is
incremented by two between successive program
words, in orde r to pro vide c omp atibi lity w ith d ata sp ace
addressing.
User program space access is restricted to the lower
4M instruction word address range (0x000000 to
0x7FFFFE), for all access es other than TBLRD/TBLWT,
which use TBLPAG<7> to determin e user or conf igura-
tion space access. In Table 3-1, Read/Write instruc-
tions, b it 23 allo ws access to the Dev ice ID, the Use r ID
and the configuration bits. Otherwise, bit 23 is always
clear.
TABLE 3-1: PROGRAM SPACE ADDRESS CONSTRUCTION
FIGURE 3-1: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION
Note: The address map shown in Figure 3-5 is
concep tual, and the actu al memory co nfig-
uratio n ma y v ary acro ss ind ivi dual devices
depending on available memory.
Access Type Access
Space Program Spac e Addre ss
<23> <22:16> <15> <14:1> <0>
Instruction Access User 0PC<22:1> 0
TBLRD/TBLWT User
(TBLPAG<7> = 0) TBLPAG<7:0> Data EA <15:0>
TBLRD/TBLWT Configuration
(TBLPAG<7> = 1) TBLPAG<7:0> Data EA <15:0>
Program Space Visibility User 0PSVPAG<7:0> Data EA <14:0>
0Program Counter
24-bits
1
PSVPAG Reg
8-bits
EA
15-bits
Program
Using
Select
TBLPAG Reg
8-bits
EA
16-bits
Using
Byte
24-bit EA
0
0
1/0
Select
User/
Configuration
Table
Instruction
Program
Space
Counter
Using
Space
Select
Note: Program Space Visibility cannot be used to access bits <23:16> of a word in program mem ory.
Visibility
dsPIC30F
DS70082A-page 26 Advance Information 2002 Mic rochip Technology Inc.
3.1.1 PROGRAM SPACE ALIGNMENT
AND DATA ACCESS USING TABLE
INSTRUCTIONS
This arc hit ec ture f etc hes 24 -bi t w ide pro gram memo ry.
Consequently, instructions are always aligned. How-
ever, as the architecture is modified Harvard, data can
also be presen t in program space.
There are two methods by which program space can
be accessed: via special table instructions, or through
the rema ppi ng of a 16K word prog ram space page in to
the upper half of data space (see Section 3.1.2). The
TBLRDL and TBLWTL instruc tions of fer a direc t method
of readin g or wri ting the LS W ord o f any ad dress w ithin
progra m spa ce, witho ut g oing thro ugh dat a sp ac e. The
TBLRDH and TBLWTH instructions are the only method
whereb y th e u ppe r 8 bi ts of a program space word can
be accessed as data.
The PC is incremented by two for each successive
24-bit program word. This allows program memory
addresses to directly map to data space addresses.
Program memory can thus be regarded as two 16-bit
word wide address sp ac es , res id ing si de by si de, eac h
with the same address range. TBLRDL and TBLWTL
access the space which contains the LS Data Word,
and TBLRDH and TBLWTH access the space which con-
tains the MS Data Byte.
Figure 3-1 shows h ow th e EA is cre ate d fo r t a ble oper-
ations and data space accesses (PSV = 1). Here,
P<23:0> refers to a program space word, whereas
D<15:0> refers to a data space word.
A set of Table Instruct ions are provided to mo ve byte or
word siz ed data to and from program space.
1. TBLRDL: Table Re ad Low
Word: Read the LS Word of the program
address;
P<15:0> maps to D<15:0>.
Byte: Read one of the LS Bytes of the program
address;
P<7:0> maps to the destination byte when byte
select = 0;
P<15:8> m aps to the d estination byte when byte
select = 1.
2. TBLWTL: Table Write Low (refer to Section 6.0
for details on FLASH Programming).
3. TBLRDH: Table Re ad High
Word: Read the MS Word of the program
address;
P<23:16> maps to D<7:0>; D<15:8> always
be = 0.
Byte: Read one of the MS By tes of the pro gram
address;
P<23:16> maps to the destination byte when
byte select = 0;
The destination byte will always be = 0 when
byte select = 1.
4. TBLWTH: Tabl e Writ e Hi gh (r efe r to S ecti on 6.0
for details on FLASH Programming).
FIGURE 3-2: PROGRAM DATA TABLE ACCESS (LS WORD)
0
8
16
PC Address
0x000000
0x000002
0x000004
0x000006
23
00000000
00000000
00000000
00000000
Program Memory
Phantom Byte
(Read as 0).
TBLRDL.W
TBLRDL.B (Wn<0> = 1)
TBLRDL.B (Wn<0> = 0)
2002 Microchip Technology Inc. Advance Information DS70082A-page 27
dsPIC30F
FIGURE 3-3: PROGRAM DATA TABLE ACCESS (MS BYTE)
3.1. 2 PROGR AM SPACE VISIBILI TY
FROM DATA SPACE
The upper 32 Kbytes of data space may optionally be
mapped into any 16K word program space page. This
provides transparent access of stored constant data
from X data space, without the need to use special
instructions (i.e., TBLRDL/H, TBLWTL/H instructions).
Program space access through the data space occurs
if th e MS bit of the data space EA i s set and program
space visibility is enabled, by setting the PSV bit in the
Core Control register (CORCON). The functions of
CORCON are discussed in Section 6.0, DSP Engine.
Data accesses to this area add an additional cycle to
the instruction being executed, since two program
memory fetch es are requ ire d.
Note that the upper half of addressable data space is
always part of the X data space. Therefore, when a
DSP ope ration uses p rogram sp ace mapp ing to acces s
this m em ory regi on , Y d ata space s ho uld ty pic al ly co n-
tain state (variable) data for DSP operations, whereas
X data space should typically contain coefficient
(constant) da ta.
Although each dat a sp ace address, 0x8000 and higher ,
maps directly into a corresponding program memory
address (see Figure 3-4), only the lower 16-bits of the
24-bit program word are used to contain the data. The
upper 8 bits shoul d be progra mmed to forc e an illeg al
instruction to maintain machine robustness. Refer to
the Programmers Reference Manual (DS70030) for
details on instruction encoding.
Note that by incrementing the PC by 2 for each pro-
gram memory word, the LS 15 bits (16 bits for the
TBLRDL/H, TBLWTL/H instructions) of data space
addresses directly map to the LS 15 bits in the corre-
sponding program space addresses. The remaining
bits are provided by the Program Space Visibility Page
register, PSVPAG<7:0>, as shown in Figure 3-4.
3.1.2.1 Data Pre-Fetch from Program Space
Within a REPEAT Loop
Consider the special case of any instruction executed
within the REPEAT loop. When pre-fetching data resi-
dent in prog ram spac e, via the dat a space w indow from
within a REPEAT loop, all iterations of the repeated
instruction will reload the instruction from the Instruc-
tion Latch without re-fetching it, thereby releasing the
program bus for a data pre-fetch. In this example, the
initial 2 data words for the first iteration of the instruction
to be repeated (MAC) are fetched by a prior instruction
(e.g., CLR instruction). The subsequent MAC instruc-
tions, th ere fore , only need to fet ch tw o more data pairs
to comp lete the loop. Th e initial fetch of the MAC instruc-
tion is performed by the REPEAT instruction. As a
result, only the last iteration of the REPEAT loop
requires 2 cycles to execute. Each of the other itera-
tions executes in 1 cycle.
0
8
16
PC Address
0x000000
0x000002
0x000004
0x000006
23
00000000
00000000
00000000
00000000
Program Memory
Phantom Byte
(Read as 0)
TBLRDH.W
TBLRDH.B (Wn<0> = 1)
TBLRDH.B (Wn<0> = 0)
Note: PSV access is temporarily disabled during
Table Reads/Writes.
dsPIC30F
DS70082A-page 28 Advance Information 2002 Mic rochip Technology Inc.
EXAMPLE 3-1: PROGRAM SPACE DATA READ THROUGH DATA SPACE WITHIN A
REPEAT LOOP
FIGURE 3-4: DATA SPACE WINDOW INTO PROGRAM SPACE OPERATION
; In this example, data for MAC operations is stored in Program Space.
CLR A, [W8]+=2, W4, [W10]+=2, W5 ; Acc. A cleared, data prefetched (2 cycles)
REPEAT #99 ; Repeat the MAC operation 100 times (1 cycle)
MAC W4*W5, A, [W8]+=2, W4, [W10]+=2, W5
; MAC operation within REPEAT loop (2 cycles for 1st and 100th iterations, 1 cycle for 2nd - 99th
iterations)
23 15 0
PSVPAG(1)
15
15
EA<15> = 0
EA<15> = 1
16
Data
Space
EA
Data Space
Program Space
8
15 23
0x0000
0x8000
0xFFFF
0x21
0x108000
0x10FFFF
Data Read
Upper Half of Data
Space is Mapped
into Program Space
Note: PSVPAG is an 8-bit register, containing bits <22:15> of the program space address
(i.e., it defines the page in program space to which the upper half of data space is being mapped).
0x108200
Address
Concatenation
BSET CORCON,#2 ; PSV bit set
MOV #0x21, W0 ; Set PSVPAG register
MOV W0, PSVPAG
MOV 0x8200, W0 ; Access program memory location
; using a data space access
2002 Microchip Technology Inc. Advance Information DS70082A-page 29
dsPIC30F
FIGURE 3-5: SAMPLE PROGRAM
SPACE MEMORY MAP 3.2 Data Address Space
The core ha s two data spa ces. The dat a spaces can be
considered either separate (for some DSP instruc-
tions), or as o ne u nifi ed lin ear a ddre ss rang e (fo r MC U
instructions). The data spaces are accessed using two
Address Generation Units (AGUs) and separate data
paths.
3.2.1 DATA SPACE S
The X data space is used by all instructions and sup-
ports all Addressing modes. There are separate read
and write data buse s. The X read data bus is the return
data path for all instructions that view data space as
combined X and Y address space. It is also the X
address space data path for the dual operand read
instructions (MAC class). The X write data bus is the
only write path to data space for all instructions.
The X data space also supports Modulo Addressing for
all instructions, subject to Addressing mode restric-
tions. Bit-Reversed Addressing is only supported for
writes to X data space.
The Y data space is used in concert with the X data
space by the MAC class of instructions (CLR, ED,
EDAC, MAC, MOVSAC, MPY, MPY.N and MSC) to
provide two concurrent data read paths. No writes
occur ac ros s th e Y bu s. T his cl as s of ins truc tio ns ded i-
cates two W regi ster pointers, W10 and W11, to always
address Y data space, independent of X data space,
whereas W8 and W9 always address X data space.
Note that during accumulator write back, the data
address sp a ce is c onsidered a co mbination of X and Y
data spaces, so the write oc curs across the X bus. Con-
sequently, it can be to any address in the entire data
space.
The Y data space can only be used for the data pre-
fetch operation associated with the MAC class of
instructions. It also supports Modulo Addressing for
automat ed c irc ula r buffers. Of course, a ll o the r ins truc -
tions can access the Y dat a address sp ace through the
X data path, as part of the composite li near space.
The boundary between the X and Y data spaces is
defined as shown in Figure 3-8 and is not user pro-
grammab le. Sh ould a n EA po int to dat a out side its own
assign ed a ddre ss sp a ce , or to a l ocation outside p hys -
ical memory, an all-zero word/ byte will be returne d. For
example, although Y address space is visible by all
non-MAC instructions using any Addressing mode, an
attempt by a MAC instruction to fetch data from that
space, using W8 or W9 (X space pointers), will return
0x0000.
RESET - Target Address
User Memory
Space
000000
00007E
000002
000080
Device Configuration
User FLASH
Program Memory
018000
017FFE
Configuration Memory
Space
Data FLASH
(48K instructions)
(4 Kbytes)
800000
F80000
Registers F8000E
F80010
DEVID (2) FEFFFE
FF0000
FFFFFE
Reserved F7FFFE
Reserved
7FF000
7FEFFE
(Read 0s)
8005FE
800600
UNITID (32 instr.)
Vector Tables
8005BE
8005C0
RESET - GOTO Instruction
000004
Reserved
7FFFFE
Reserved
000100
0000FE
000084
Alternate Vector Table
Reserved
Interrupt Vector Table
Note: These address boundaries may vary from one device
to another.
dsPIC30F
DS70082A-page 30 Advance Information 2002 Mic rochip Technology Inc.
All effective addresses are 16-bits wide and point to
bytes within the data space. Therefore, the data space
address range is 64 Kbytes or 32K words.
3.2.2 DATA SPACE WIDTH
The core data wid th is 16-b it s . All in tern al reg is ters are
organ ized as 16-bit wide words. Dat a sp ac e mem ory is
organized in byte addressable, 16-bit wide blocks.
3.2.3 DATA ALIGNMENT
To help maintain backward compatibility with
PICmicro® devices and improve data space memory
usage ef ficiency, the dsPIC30F ins truction set sup ports
both word and byte operations. Data is aligned in data
memory a nd regist ers as wo rds, but all dat a sp ace EAs
resolve to bytes. Data byte reads will read the complete
word, which contains the byte, using the LS bit of any
EA to determine which byte to select. The selected byte
is placed onto the LS Byte of the X data path (no byte
acces ses are possible fro m the Y data pa th as the MAC
clas s of inst ruct ion can only fetch words). That is, data
memory and registers are organized as two parallel
byte wide entities with shared (word) address decode,
but sepa rate wri te lines . Data byte w rites o nly write to
the corresponding side of the array or register which
matches the byte address.
As a cons equence of this byte access ibility, all effec tive
address c alc ul ati ons (i ncl ud ing tho se ge nerated by th e
DSP operations, which are restricted to word sized
data ) are internal ly scale d to step th rough word ali gned
memory. For example, the core would recognize that
Post-Modified Register Indirect Addressing mode
[Ws++], will result in a value of Ws+1 for byte opera-
tions and Ws+2 for word operations.
All wo rd accesses must be aligned to an eve n address .
Misaligned word data fetches are not supported, so
care must be taken when mixing byte and word opera-
tions, or translating from 8-bi t MCU code. Should a mis-
aligned read or write be attempted, an Address Error
trap wil l be ge ner ated . I f th e er ror oc curre d o n a read ,
the instruction underway is completed, whereas if it
occurred on a write, the instruction will be inhibited and
the PC will not be incremented. In either case, a trap
will then be executed, allowing the system and/or user
to exa mi ne th e mac hin e stat e pr ior t o ex ecu tio n of the
address fault.
FIGURE 3-6: DATA ALIGNMENT
All byte loads into a ny W register are loaded into the LS
Byte. The MSB is not modified.
A sign-extend (SE) instruction is provided to allow
users to tran slate 8- bit s igned dat a to 16-b it si gned val-
ues. Alternatively, for 16-bit unsigned data, users can
clear the MSB of any W register, by executing a
zero-extend (ZE) instruction on the appropriate
address.
Although m os t i ns truc tio ns are capable of opera t ing o n
word or byte data sizes, it should be noted that some
instructions, including the DSP instructions, operate
only on words.
3.2.4 DATA SPA CE MEMORY MAP
The data space memory is split into two blocks, X and
Y data space. A key element of th is archi tec ture is th at
Y space is a subset of X space, and is fully contained
within X space. In order to provide an apparent linear
addressing space, X and Y spaces have contiguous
addresses.
When executing any instruction other than one of the
MAC class of instructions, the X block consists of the
entire 64 Kbyte data address space (including all Y
addresses). When executing one of the MAC class of
instruc tions, the X block consi st s of the ent ire 64 Kby te
data address space excluding the Y address block (for
data reads only). In other words, all other instructions
regard the entire data memory as one composite
address space. The MAC class instructions extract the
Y address space from data space and addresses it
using EAs sou rce d from W10 and W11. The remai nin g
X data space is addressed using W8 and W9. Both
address spaces are concurrently accessed only by the
MAC class instructions.
An example data space memory map is shown in
Figure 3-8.
TABLE 3-2: EFFECT OF INVALID
MEMORY ACCESSES
Attempted Operation Data Returned
EA = an unimplemented address 0x0000
W8 or W9 used to access Y data
spa ce in a MAC instru ction 0x0000
W10 or W11 used to access X
data space in a MAC instruction 0x0000
15 8 7 0
0001
0003
0005
0000
0002
0004
Byte 1 Byte 0
Byte 3 Byte 2
Byte 5 Byte 4
LS ByteMS Byte
2002 Microchip Technology Inc. Advance Information DS70082A-page 31
dsPIC30F
3.2.5 NEAR DATA SPACE
An 8 Kbyte near data space is reserved in X address
memory space between 0x0000 and 0x1FFF, which is
directly add res sab le via a 13-bit absolute address fiel d
within all memory direct instructions. The remaining X
address space and all of the Y address space is
address able indirec tly. Addi tionally, the whole o f X data
space is addressable using MOV instructions, which
support memory direct addressing with a 16-bit
address field.
The stack pointer always points to the first available
free word and grows from lower addresses towards
higher addresses. It pre-decrements for stack pops
(reads) and post-increments for stack pushes (writes),
as show n i n Fi gu re 3-7. Note that for a PC push durin g
any CALL instruction, the MSB of the PC is zero-
extended before the push, ensuring that the MSB is
always clear.
3.2.6 SOFTWARE STACK
The dsPIC contains a software stack. W15 is used as
the Stack Pointer.
There is a S tack Limit reg ister (SPLI M) assoc iated wi th
the stack pointer. SPLIM is uninitialized at RESET. As
is the case for the stac k point er, SPLIM<0> is forced to
0, because all stack operations must be word aligned.
Wheneve r an effective address (EA) is generate d using
W15 as a source or destination pointer, the address
thus gene rated is compa red with the value in SPLIM. If
the EA is found to be greater than the contents of
SPLIM, then a Stack Pointer Overflow (Stack Error)
trap is generated.
Similarly, a Stack Pointer Underflow (Stack Error) trap
is generated when the stack pointer address is found to
be less than 0x0800, thus preventing the stack from
interfering with the Special Function Register (SFR)
space.
FIGURE 3-7: CALL STACK FRAME
Note: A PC push during exception processing
will concatenate the SRL register to the
MSB of the PC prior to the push.
<Free Word>
PC<15:0>
000000000 PC<22:16>
015
W15 (before CALL)
W15 (after CALL)
Stack Grows Towa rd s
Higher Addres s
PUSH : [W15++]
POP : [--W15]
0x0000
dsPIC30F
DS70082A-page 32 Advance Information 2002 Mic rochip Technology Inc.
FIGURE 3-8: SAMPLE DATA SPACE MEMORY MAP
0x0000
0x07FE
SFR Space
0x17FE
0xFFFE
X Data RAM (X)
LS Byte
Address
16-bits
LSBMSB
MS Byte
Address
0x0001
0x07FF
0x17FF
0xFFFF
X Data
0x8001 0x8000
Optionally
Mapped
into Program
Memory
Unimplemented (X)
0x27FF 0x27FE
0x28000x2801
0x0801 0x0800
0x1801
0x1800
Near
Data
0x1FFE 0x1FFF
Y Data RAM (Y)
2 Kbyte
SFR Space
8 Kbyt e
SRAM Space
8 Kbyt e
SRAM boundary
Note: The address map shown in Figure 3-8 is conceptual, and may vary across individual devices
depending on available memory.
Space
2002 Microchip Technology Inc. Advance Information DS70082A-page 33
dsPIC30F
FIGURE 3-9: DATA SPACE FOR MCU AND DSP (MAC CLASS) INSTRUCTIONS EXAMPLE
SFR SPACE
(Y SPACE)
X SPACE
SFR SPACE
UNUSED
X SPACE
X SPACE
Y SPACE
UNUSED
UNUSED
Non-MAC Class Ops (Read) MAC Class Ops (Read)
Indirect EA from any W Indirect EA from W8, W9 Indirect EA from W10, W11
dsPIC30F
DS70082A-page 34 Advance Information
2002 Microchip Technology Inc.
TABLE 3-3: CORE REGISTER MAP
SFR Name Address
(Home) Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RESET State
W0 0000 W0 / WREG 0000 0000 0000 0000
W1 0002 W1 0000 0000 0000 0000
W2 0004 W2 0000 0000 0000 0000
W3 0006 W3 0000 0000 0000 0000
W4 0008 W4 0000 0000 0000 0000
W5 000A W5 0000 0000 0000 0000
W6 000C W6 0000 0000 0000 0000
W7 000E W7 0000 0000 0000 0000
W8 0010 W8 0000 0000 0000 0000
W9 0012 W9 0000 0000 0000 0000
W10 0014 W10 0000 0000 0000 0000
W11 0016 W11 0000 0000 0000 0000
W12 0018 W12 0000 0000 0000 0000
W13 001A W13 0000 0000 0000 0000
W14 001C W14 0000 0000 0000 0000
W15 001E W15 0000 1000 0000 0000
SPLIM 0020 SPLIM 0000 0000 0000 0000
ACCAL 0022 ACCAL 0000 0000 0000 0000
ACCAH 0024 ACCAH 0000 0000 0000 0000
ACCAU 0026 Sign-Extension (ACCA<39>) ACCAU 0000 0000 0000 0000
ACCBL 0028 ACCBL 0000 0000 0000 0000
ACCBH 002A ACCBH 0000 0000 0000 0000
ACCBU 002C Sign-Extension (ACCB<39>) ACCBU 0000 0000 0000 0000
PCL 002E PCL 0000 0000 0000 0000
PCH 0030 PCH 0000 0000 0000 0000
TBLPAG 0032 TBLPAG 0000 0000 0000 0000
PSVPAG 0034 PSVPAG 0000 0000 0000 0000
RCOUNT 0036 RCOUNT uuuu uuuu uuuu uuuu
DCOUNT 0038 DCOUNT uuuu uuuu uuuu uuuu
DOSTARTL 003A DOSTARTL 0uuuu uuuu uuuu uuu0
DOSTARTH 003C DOSTARTH 0000 0000 0uuu uuuu
DOENDL 003E DOENDL 0uuuu uuuu uuuu uuu0
DOENDH 0040 DOENDH 0000 0000 0uuu uuuu
SR 0042 OA OB SA SB OAB SAB DA DC IPL2 IPL1 IPL0 RA NOV Z C 0000 0000 0000 0000
CORCON 0044 EDT DL2 DL1 DL0 SATA SATB SATDW ACCSAT IPL3 PSV RND IF 0000 0000 0000 0000
Legend: u = uninitialized bit
2002 Microchip Technology Inc.
Advance Inf ormat ion
DS70082A-page 35
dsPIC30F
MODCON 0046 XMODEN YMODEN BWM<3:0> YWM<3:0> XWM<3:0> 0000 0000 0000 0000
XMODSRT 0048 XS<15:1> 0uuuu uuuu uuuu uuu0
XMODEND 004A XE<15:1> 1uuuu uuuu uuuu uuu1
YMODSRT 004C YS<15:1> 0uuuu uuuu uuuu uuu0
YMODEND 004E YE<15:1> 1uuuu uuuu uuuu uuu1
XBREV 0050 BREN XB<14:0> uuuu uuuu uuuu uuuu
DISICNT 0052 DISICNT<13:0> 0000 0000 0000 0000
TABLE 3-3: CORE REGISTER MAP (CONTINUED)
SFR Name Address
(Home) Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RESET State
Legend: u = uninitialized bit
dsPIC30F
DS70082A-page 36 Advance Information 2002 Mic rochip Technology Inc.
NOTES:
2002 Microchip Technology Inc. Advance Information DS70082A-page 37
dsPIC30F
4.0 ADDRESS GENERATOR UNITS
The dsPIC core contains two independent address
generat or units: the X AGU and Y AGU. Fu rther, the X
AGU has two parts: X RAGU (Read AGU) and X
WAGU (Write AGU). The X RAGU and X WAGU sup-
port byte and word sized data space reads and writes,
respectively, for both MCU and DSP instructions. The
Y AGU supports word sized data reads for the DSP
MAC class of instructions only. They are each capable
of supporting two types of data addressing:
Linear Addressing
Modulo (Circular) Addressing
In addition, the X WAGU can support:
Bit-Reversed Addre ss ing
Linear and Modulo Data Addressing modes can be
applied to data space or program space. Bit-Reversed
address ing is only applic able t o dat a s pa ce add resses .
4.1 Data Space Organizati on
Although the data sp ace memory is organized as 16-b it
words, all effective addresses (EAs) are byte
addresses. Instructions can thus access individual
bytes as well as properly aligned words. Word
addresses must be aligned at even boundaries. Mis-
aligned word accesses are not supported, and if
attempted, will initiate an address error trap.
When executing instructions which require just one
source operand to be fetched from data space, the X
RAGU a nd X WAGU are used to ca lcula te the ef fectiv e
address . The X RAGU and X W AGU can genera te any
address in the 64 Kbyte data space. They support all
MCU Addressing modes and Modulo Addressing for
low overhead circular buffers. The X WAGU also sup-
ports Bit-Reversed Addressing to facilitate FFT data
reorganization.
When executing instructions which require two source
operands to be concurre ntly fetche d (i.e., the MAC class
of DSP instru ct io ns ), bo th t h e X RA GU an d Y AGU are
used simultaneously and the data space is split into 2
independent address spaces, X and Y. The Y AGU sup-
ports Register Indirect Post-Modified and Modulo
Addressing only. Note that the data write phase of the
MAC class of i ns truc tio n do es not s pl it X a nd Y a dd res s
space. The write EA is calculated using the X WAGU
and the data space is configured for full 64 Kbyte
access.
In the Split Data Space mode, some W register address
pointers are dedicated to X RAGU, and others to Y
AGU. The EAs of each operand must, therefore, be
restricted to be within different address spaces. If they
are not, one of the EAs will be outside the address
space of the corresponding data space (and will fetch
the bus default value, 0x0000).
4.2 Instruction Addressing Modes
The Addressing modes in Table 4-1 form the basis of
the Addressing modes optimized to s upport the specific
features of individual instructions. The Addressing
modes provided in the MAC class of instructions are
somewhat different from those in the other instruction
types.
Some Addressing mode combinations may lead to a
one-cycle stall during instruction execution, or are not
allow ed, as dis c uss ed in Sectio n 4.3.
TABLE 4-1: FUNDAMENTAL ADDRESSING MODES SUPPORTED
Addressing Mode Description
File Register Direct The address of the file register is specified explicitly.
Register Direct The contents of a register are accessed directly.
Register Indir ect The contents of Wn forms the EA.
Register Indirect Post-modified The contents of Wn forms the EA. Wn is post-modified (incremented or
decremented) by a constant value.
Register Indirect Pre-modified Wn is pre-modi fied (increm ente d or dec rem en ted) by a sign ed co ns t an t value
to form the EA.
Register Indirect with Register Offset The sum of Wn and Wb forms the EA.
Register Indirect with Literal Offset The sum of Wn and a literal forms the EA.
dsPIC30F
DS70082A-page 38 Advance Information 2002 Microchip Technology Inc.
4.2.1 FILE REGISTER INSTRUCTIONS
Most fil e re gis ter i ns truc tio ns us e a 1 3-bi t ad dres s fiel d
(f) to directly address data present in the first 8192
bytes of data memory. These memory locations are
known as File Registers. Most file register instructions
employ a working register W0, which is denoted as
WREG in these instructions. The destin ation is typically
either th e same fil e re gi ste r, or WREG (with the ex ce p-
tion of the MUL instruction), which writes the result to a
register or register pair. The MOV instruction can use a
16-bit address field.
4.2.2 MCU INSTRUCTIONS
The three-operand MCU instructions are of the form:
Operand 3 = Operand 1 <function> Operand 2
where Ope r and 1 is alwa ys a w orking register (i. e., th e
Addressing mode can only be register direct), which is
referred to as Wb. Operand 2 can be W register,
fetched from data memory, or 5-bit literal. In two-
operand i ns truc tions, the res ult loc ati on is the same as
that of one of the operands. Certain MCU instructions
are one -op eran d ope rati ons . The foll ow in g Add res sin g
modes are s uppor ted by MCU instructions:
Register Di rec t
Regist er Indi rect
Register Indi rec t Post-m od ifi ed
Regis ter Indi rec t Pre-mo dif ied
5-bit or 10-bit Literal
4.2.3 MOVE AND ACCUMULATOR
INSTRUCTIONS
Move instructions and the DSP accumulator class of
instructions provide a greater degree of addressing
flexibility than other instructions. In addition to the
Addressing modes supported by most MCU instruc-
tions, Move and Accumulator instructions also support
Register Indirect with Register Offset Addressing
mode, also referred to as Register Indexed mode.
In summary, the following Addressing modes are
supported by Move and Accumulator instructions:
Register Direct
Register Indirect
Register Indirect Post-modified
Register Indirect Pre-modified
Register Indirect with Register Offset (Indexed)
Register Indirect with Literal Offset
8-bit Literal
16-bit Literal
4.2.4 MAC INSTRUCTIONS
The dual so urce op erand D SP instructio ns (CLR, ED,
EDAC, MAC, MPY, MPY.N, MOVSAC and MSC), also
referred to a s MAC instruction s, utilize a si mplified set of
Addressing modes to allow the user to effectively
manipulate the data pointers through register indirect
tables.
The 2 source operand pre-fetch registers must be a
member of the set {W8, W9, W10, W11}. For data
reads, W8 and W9 will always be directed to the X
RAGU and W10 and W11 will alway s be directe d to the
Y AGU. The effective addresses generated (before and
after modification) must, therefore, be valid addresses
within X data space for W8 and W9, and Y data space
for W10 and W11.
In summary, the following Addressing modes are
supported by the MAC class of instructions:
Register Indirect
Register Indirect Post-modified by 2
Register Indirect Post-modified by 4
Register Indirect Post-modified by 6
Register Indirect with Register Offset (Indexed)
4.2.5 OTHER INSTRUCTIONS
Besides the various Ad dressing mo des outlined above,
some i nstructio ns use li teral con sta nts of various sizes.
For example, BRA (branch) instructions use 16-bit
signed l iterals to spe cify the branch de stination dire ctly ,
whereas the DISI instruction uses a 14-bit unsigned
literal field. In some instructions, such as ADD Acc, the
source of an operand or result is implied by the opc ode
it self. Cert ain opera tions, such as NOP, do not have any
operands.
Note: Not all instruct ions support all the Addres s-
ing modes given above. Individual instruc-
tions may support different subsets of
these Addressing modes.
Note: For the MOV instructions, the Addressing
mode specifi ed in the instruction can differ
for the source and destination EA. How-
ever, the 4-bit Wb (Register Offset) field is
shared between both source and
destination (but typically only used by
one).
Note: Not all instructi ons support all the Address-
ing modes given above. Individual instruc-
tions may support different subsets of
these Addressing modes.
Note: Register Indirect with Register Offset
Addressing is only available for W9 (in X
spac e) and W11 (in Y spac e).
2002 Microchip Technology Inc. Advance Information DS70082A-page 39
dsPIC30F
4.3 Instruction Stalls
4.3.1 INTRODUCTION
In order to maximize data space, EA calculation and
operand fetch time, the X data space read and write
accesses are partially pipelined. The latter half of the
read phase overlaps the first half of the write phase of
an instruction, as show n in Section 2.
Address register data dependencies, also known as
Read Afte r Write (RA W) dependen cies, may therefore
arise between successive read and write operations
using common registers. They occur across instruction
boundaries and are detected by the hardware.
An exam pl e of a RAW depende nc y is a w rite operation
(in the current instruction) that modifies W5, followed
by a read operation (in the next instruction) that uses
W5 as a source addre ss pointer . W 5 will not be v alid for
the read operation until the earlier write completes.
This p robl em is re solv ed by st allin g t he ins tructi on ex e-
cution for one instruction cycle, thereby allowing the
write to complete before the next read is started.
4.3.2 RAW DEPENDENCY DETECTION
During the inst ruction pre -de code, t he core determi nes
if any address register d epe nde nc y i s i mm in ent ac ros s
an instruction boundary. The stall detection logic com-
pares the W regi ster (if any ) used for t he destination EA
of the instruction currently being executed, with the W
register to be us ed by the so urce EA (if an y) of th e pre-
fetched instruction. As t he W registers are also memor y
mapped, the stall detection logic also derives an SFR
address from the W regis ter being us ed by the destin a-
tion EA, and determines whether this address is being
issued during the write phase of the instruction cur-
rently being executed.
When it o bserves a match be tween the de stinat ion and
source registers, a set of rules are applied to decide
whether or not to stall the instruction by one cycle.
Table 4-2 lists out the various RAW conditions which
cause an instruction execution stall.
TABLE 4-2: RAW DEPENDENCY RULES (DETECTION BY HARDWARE)
Destination
Addressing M ode
Using Wn
Source Addressing
Mode Using Wn Status Examples
(Wn = W2)
Direct Direct No Stall ADD.w W0, W1, W2
MOV.w W2, W3
Direct Indirect Stall ADD.w W0, W1, W2
MOV.w [W2], W3
Direct Indirect with Pre- or
Post-Modification Stall ADD.w W0, W1, W2
MOV.w [W2++], W3
Indirect Direct No Stall ADD.w W0, W1, [W2]
MOV.w W2, W3
Indirect Indirect No Stall ADD.w W0, W1, [W2]
MOV.w [W2], W3
Indirect Indirect Stall ADD.w W0, W1, [W2] ; W2=0x0004 (mapped W2)
MOV.w [W2], W3 ; (i.e., if W2 = addr. of W2)
Indirect Indirect with Pre- or
Post-Modification No Stall ADD.w W0, W1, [W2]
MOV.w [W2++], W3
Indirect Indirect with Pre- or
Post-Modification Stall ADD.w W0, W1, [W2] ; W2=0x0004 (mapped W2)
MOV.w [W2++], W3 ; (i.e., if W2 = addr. of W2)
Indirect wi th Pre- or
Post-Modification Direct No Stall ADD.w W0, W1, [W2++]
MOV.w W2, W3
Indirect wi th Pre- or
Post-Modification Indirect Stall ADD.w W0, W1, [W2++]
MOV.w [W2], W3
Indirect wi th Pre- or
Post-Modification Indirect with Pre- or
Post-Modification Stall ADD.w W0, W1, [W2++]
MOV.w [W2++], W3
dsPIC30F
DS70082A-page 40 Advance Information 2002 Microchip Technology Inc.
4.4 Modulo Addressing
Modulo addressing is a method of providing an auto-
mated means to support circular data buffers using
hardwa re. The ob jectiv e is to remo ve t he need for soft-
ware to perform data address boundary checks when
executing tightly looped code, as is typical in many
DSP algorithms.
Modulo Addressing can operate in either data or pro-
gram space (since the dat a pointer mechanism is essen-
tially the same for both). One circular buffer can be
supported in each of the X (which also provides the
pointers into Program space) and Y data spaces. Mod-
ulo Addressing can operate on any W register pointer.
However, it is not advisable to use W14 or W15 fo r Mod-
ulo Addressing, since these two registers are used as
the S tack Frame Pointer and S tack Pointer , respectively .
In general, any particular circular buffer can only be
configu red to operate in one direct ion, as ther e are c er-
tain restrictions on the buffer start address (for incre-
menting buffers) or end address (for decrementing
buffe rs), based upon the direction of the buffer.
The only exception to the usage restrictions is for buff-
ers which have a power-of-2 length. As these buffers
satisfy the start and end address criteria, they may
operate in a Bi-Directional mode, i.e., address bound-
ary checks will be performed on both the lower and
upper address boundaries.
4.4.1 START AND END ADDRESS
The Modulo Addressing scheme requires that a start-
ing and an end address be specified and loaded into
the 16-bi t mod ulo bu f fer ad dress registe rs: XMO DSR T,
XMODEND, YMODSRT, YMODEND (see Table 3-3).
If the length of an inc rementin g buffer is gre ater than M
= 2N-1, but not greater than M = 2N bytes, then the last
N bits of the data buffer start address must be zeros.
There are no such res trictions on the end addres s of an
incrementing buffer. For example, if the buffer size
(modulu s value) is cho sen to be 100 bytes (0x6 4), then
the buf fer st art addres s for an in crementing b uffer m ust
cont ain 7 Le ast Significan t ze ros. Valid sta rt addres ses
may, therefore, be 0xXX00 and 0xXX80, where X is
any hexa decimal value. Adding the buff er length to this
value and subtracting 1 will give the end address to be
written into X/YMODEND.
For example, if the start address was chosen to be
0x2000, then the X/YMODEND would be set to
(0x2000 + 0x0064 1) = 0x2063.
In the case of a decrementing buffer, the last N bits of
the data buffer end address must be ones. There are
no such restrictions on the start address of a decre-
menting buffer . For exam ple, if the buf fer size (modu lus
value) i s chose n to be 10 0 bytes (0x64), the n the buf fer
end address for a decrementing buffer must contain 7
Least Significant ones. Valid end addresses may,
therefore, be 0xXXFF and 0xXX7F, where X is any
hexadecimal value. Subtracting the buffer length from
this val ue and a dding 1 wi ll g ive the sta rt addres s to be
written into X/YMODSRT. For example, if the end
address was chosen to be 0x207F, then the start
address would be (0x207F 0x0064+1) = 0x201C,
which is the first physical address of the buffer.
The leng th of a ci rcular buf fer is not di rectly spec ified. It
is determined by the difference between the corre-
spondin g st art and end addres ses. The maxi mu m pos-
sible length of the circular buffer is 32K words
(64 Kbytes).
4.4.2 W ADDRESS R EGI S TER
SELECTION
The M od u lo an d B i t-R e ve rs ed A dd r es si ng c o ntr o l reg -
ister MODCON<15:0> contains enable flags plus W
register field to specify the W address registers. The
XWM and YWM fields select which registers will oper-
ate with Modulo Add ressing. If XWM = 15, X RAGU and
X WAGU Modulo Addressing are disabled. Similarly, if
YWM = 15, Y AGU Modulo Addressing is disabled.
The X address space pointer W register (XWM) to
which Modulo Addressing is to be applied, is stored in
MODCON<3 :0> (see Table 3-3). Modul o Addres sing i s
enabled for X data sp ace when XWM is set to any value
other than 15 and the XMODEN bit is set at
MODCON<15>.
The Y address space pointer W register (YWM) to
which Modulo Addressing is to be applied, is stored in
MODCON<7:4>. Modulo addressing is enabled for Y
data space when YWM is set to any value other than 15
and the YM ODEN bit is set at MODCON<14>.
Note: The start and end addresses are the first
and last byte addresses of the buffer (irre-
spective of whether it is a word or byte
buffer, or an increasing or decreasing
buffer). Moreover, the start address must
be even and the end address must be odd
(for both word and byte buffers).
Note: Start address refers to the smallest
address boundary of the circular buffer.
The first access of th e buffer m ay be at any
address within the modulus range (see
Section 4.4.4).
Note: Y-space Modulo Addressing EA calcula-
tions assume word sized data (LS bit of
every EA is always clear).
Note: The XMO DSR T an d XMO DEND registers ,
and the XWM register selection, are
shared between X RAGU and X WAGU.
2002 Microchip Technology Inc. Advance Information DS70082A-page 41
dsPIC30F
FIGURE 4-1: INCREMENTING BUFFER MODULO ADDRESSING OPERATION EXAMPLE
0x1100
0x1163
Start Addr = 0x1100
End Addr = 0x1163
Length = 0x0032 words
MOV #0x1100,W0
MOV W0,XMODSRT ;set modulo start address
MOV #0x1163,W0
MOV W0,MODEND ;set modulo end address
MOV #0x8001,W0
MOV W0,MODCON ;enable W1, X AGU for modulo
MOV #0x0000,W0 ;W0 holds buffer fill value
MOV #0x1110,W1 ;point W1 to buffer
DO AGAIN,#0x31 ;fill the 50 buffer locations
MOV W0,[W1++] ;fill the next location
AGAIN: INC W0,W0 ;increment the fill value
Byte
Address
dsPIC30F
DS70082A-page 42 Advance Information 2002 Microchip Technology Inc.
FIGURE 4-2: DECREMENTING BUFFER MODULO ADDRESSING OPERATION EXAMPLE
4.4.3 MODULO ADDRESSING
APPLICABILITY
Modulo Addressing can be applied to the effective
address (EA) calculation associated with any W regis-
ter. It is important to realize that the address bound-
aries c he ck fo r ad dre sses le ss th an or greater tha n th e
upper (for incrementing buffers), and lower (for decre-
menting buffers) boundary addresses (not just equal
to). A ddress change s may, therefore, j ump over b ound-
arie s and stil l be adjust ed correc tly (see S ection 4.4. 4
for restrictions)
.
0x11D0
0x11FF
Start Addr = 0x11 D0
End Addr = 0x11FF
Length = 0x0018 words
MOV #0x11D0,W0
MOV #0,XMODSRT ;set modulo start address
MOV 0x11FF,W0
MOV W0,XMODEND ;set modulo end address
MOV #0x8001,W0
MOV W0,MODCON ;enable W1, X AGU for modulo
MOV #0x000F,W0 ;W0 holds buffer fill value
MOV #0x11E0,W1 ;point W1 to buffer
DO AGAIN,#0x17 ;fill the 24 buffer locations
MOV W0,[W1--] ;fill the next location
AGAIN: DEC W0,W0 ; decrement the fill value
Byte
Address
Note: The modulo corrected effective address is
written back to the register only when Pre-
Modify or Post-Modify Addressing mo de i s
used to compute the Effective Address.
When an address offset (e.g., [W7+W2] ) is
used, modulo address correction is per-
formed, but the contents of the register
remains unchanged.
2002 Microchip Technology Inc. Advance Information DS70082A-page 43
dsPIC30F
4.4.4 MODULO ADDRESSING
RESTRICTIONS
As stated in Section 4.4.1, for an incrementing buffer,
the circular buffer start address (lower boundary) is
arbitrary, but must be at a zero power-of-two bound-
ary. For a decrementing buffer, the circular buffer end
address is arbitrary, but must be at a ones boundary.
There are no restrictions regarding how much an EA
calculation can exceed the address boundary being
checked, and still be successfully corrected.
Once configured, the direction of successive
addresses into a buffer should not be changed.
Although all EAs will co ntinue to be gen erated c orrectly
irrespective of offset sign, only one address boundary
is checked for each type of buffer . Thus, if a buf fer is set
up to be an incrementing buffer by choosing an appro-
priate starting address, then correction of the effective
address will be performed by the AGU at the upper
address b oun dary, but no address c orrec ti on will occur
if the EA crosses the lower address boundary. Similarly ,
for a decrementing boundary, address correction will
be performed by the AGU at the lower address bound-
ary, but no address correction will take place if the EA
crosses the upper address boundary. The circular
buf f er poin ter ma y be free ly modified in both directions
without a possibility of out-of-range address access
only when the start address satisfies the condition for
an inc rement ing b uff er (las t N bit s are zeroe s) and the
end address satisfies the condition for a decrementing
buffer (last N bits are ones). Thus, the Modulo
Addressing capability is truly bi-directional only for
modulo-2 length buffers.
4.5 Bit-Reversed Addressing
Bit-Reversed Addressing is intended to simplify data
re-ordering for radix-2 FFT algorithms. It is supported
by the X WAGU only, i.e., for data writes only.
The modifier , which may be a constant value or register
contents, is regarded as having its bit order reversed.
The addres s sourc e and dest inat ion are ke pt in norma l
order. Thus, the only operand requiring reversal is the
modifier.
4.5.1 BIT-REVERSED ADDRESSING
IMPLEMENTATION
Bit-Reversed Addressing is enabled when:
1. BWM (W register selection) in the MODCON
register is any value other than 15 (the stac k can
not be accessed using Bit-Reversed Address-
ing) and
2. the BREN bit is set in the XBREV register and
3. the Addressing mode used is Register Indirect
with Pre-Increment or Post-Increment.
XB<14:0> is the Bit-Reversed Address modifier or
pivot po in t w hic h is typ ic all y a c ons t a nt. In the case of
an FFT computation, its value is equal to half of the FFT
dat a buffer size.
When enabled, Bit-Reversed Addressing will only be
executed with register indirect with Pre-Increment or
Post-Incre ment Addressing and word sized data writes.
It will no t functio n for any ot her Addres sing m ode or for
byte-sized data, and normal addresses will be gener-
ated instea d. When Bit-R eversed Addr essin g is active,
the W address pointer will always be added to the
address modifier (XB) and the offset associated with
the register Indirect Addressing mode will be ignored.
In addition, as word sized data is a requirement, the LS
bit of the EA is ignored (and a lways clear).
FIGURE 4-3: BIT-REVERSED ADDRESS EXAMPLE
Note: All Bit-Reversed EA calculations assume
word sized data (LS bit of every EA is
always clear). The XB value is scaled
accordingly to generate compatible (byte)
addresses.
Note: Modulo Addressing and Bit-Reversed
Addressing should not be enabled together .
In the event that the user attempts to do
this, bit reversed addressing will assume
priority when active for the X WAGU, and X
W AGU Mo dulo Addressing will be dis abled.
However, Modulo Addressing will continue
to function in the X RAGU.
b3 b2 b1 0
b2 b3 b4 0
Bit Locations Swapped Left-to-Right
Around Center of Binary Value
Bit-Reversed Address
XB = 0x0008 for a 16-word Bit-Reversed Buffer
b7 b6 b5 b1
b7 b6 b5 b4b11 b10 b9 b8
b11 b10 b9 b8
b15 b14 b13 b12
b15 b14 b13 b12
Sequenti al Addre ss
Pivot Point
dsPIC30F
DS70082A-page 44 Advance Information 2002 Microchip Technology Inc.
TABLE 4-3: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY)
TABLE 4-4: BIT-REVERSED ADDRESS MODIFIER VALUES
Normal
Address Bit-Reversed
Address
A3 A2 A1 A0 Decimal A3 A2 A1 A0 Decimal
0 0 0 0 0 0 0 0 0 0
0 0 0 1 1 1 0 0 0 8
0 0 1 0 2 0 1 0 0 4
0 0 1 1 3 1 1 0 0 12
0 1 0 0 4 0 0 1 0 2
0 1 0 1 5 1 0 1 0 10
0 1 1 0 6 0 1 1 0 6
0 1 1 1 7 1 1 1 0 14
1 0 0 0 8 0 0 0 1 1
1 0 0 1 9 1 0 0 1 9
1 0 1 0 10 0 1 0 1 5
1 0 1 1 11 1 1 0 1 13
1 1 0 0 12 0 0 1 1 3
1 1 0 1 13 1 0 1 1 11
1 1 1 0 14 0 1 1 1 7
1 1 1 1 15 1 1 1 1 15
Buffer Size (Words) XB<14:0> Bit-Reversed Address Modifier Value
32768 0x4000
16384 0x2000
8192 0x1000
4096 0x0800
2048 0x0400
1024 0x0200
512 0x0100
256 0x0080
128 0x0040
64 0x0020
32 0x0010
16 0x0008
80x0004
40x0002
20x0001
2002 Microchip Technology Inc. Advance Information DS70082A-page 45
dsPIC30F
5.0 EXCEPTION PROCESSING
The dsPIC30F Motor Control and Power Conversion
Family has up to 44 interrupt sources and 4 processor
exceptions (traps), which must be arbitrated based on
a priority scheme.
The processor core is responsible for reading the
Interrupt Vector Table (IVT) and transferring the
address contained in the interrupt vector to the pro-
gram counter. The interrupt vector is transferred from
the program data bus into the program counter, via a
24-bit wide multiplexer on the input of the program
counter.
The Interrupt Vector Table (IVT) and Alternate Inter-
rupt Vector Tabl e (AIVT) are pl aced ne ar the begin ning
of program memory (0x000004). The IVT and AIVT
are shown in Table 5-2.
The interrupt controller is responsible for pre-
processing the interrupts and processor exceptions,
prior to their being presented to the processor core.
The peripheral interrupts and traps are enabled, priori-
tized, and controlled using centralized special function
registers:
IFS0<15:0>, IFS1<15:0>, IFS2<15:0>
All interrupt request flags are maintained in these
three registers. The flags are set by their respec-
tive peripherals or external signals, and they are
cleared via software.
IEC0<15:0>, IEC1<15:0>, IEC2<15:0>
All interrupt enable control bits are maintained in
these three registers. These control bits are used
to individually enable interrupts from the
peripherals or external signals.
IPC0<15:0> ... IPC11<7:0>
The user assignable priority level associated with
each of these 44 interrupts is held centrally in
these twelve registers.
IPL<3:0> The current CPU priority level is explic-
itly stored in the IPL bits. IPL<3> is present in the
CORCON reg ister , whereas IPL<2:0 > are present
in the status register (SR) in the processor core.
INTCON1< 15:0>, INTCON2<1 5:0>
Global interru pt co ntrol fu nctio ns are deriv ed from
these two registers. INTCON1 contains the con-
trol and status flags for the processor exceptions.
The INTCON2 register controls the external inter-
rupt request signal behavior and the use of the
alternate vector table.
All interrupt sources can be user assigned to one of 7
priority levels, 1 through 7, via the IPCx registers.
Each interrupt source is associated with an interrupt
vector, as shown in Table 5-2. Levels 7 and 1 repre-
sent the highest and lowest maskable priorities,
respe ct ive ly.
If the NSTDIS bit (INTCON1<15>) is set, nesting of
interrupts is prev en ted . Th us , i f a n i nte rrupt is c urrentl y
being serviced, processing of a new interrupt is pre-
vented, even if the new interrupt is of higher priority
than the one currently being serviced.
Certain interrupts have specialized control bits for fea-
tures like edge or level triggered interrupts, interrupt-
on-change, etc. Control of these features remains
within the peripheral module which generates the
interrupt.
The DISI instruction can be used to disable the pro-
cessing of interrupts of priorities 6 and lower for a cer-
tain number of instructions, during which the DISI bit
(INTCON2<14>) remains set.
When an interrupt is serviced, the PC is loaded with the
address stor ed in the vecto r locati on in Program mem-
ory that cor respond s to the interrupt. There are 63 dif-
feren t vectors within the IVT (refer to Table 5-2). These
vectors are contained in locations 0x000004 through
0x0000FE of program memory (refer to Table 5-2).
These locations contain 24-bit addresses, and in order
to preserve robustness, an address error trap will take
place should the PC attempt to fetch any of these
words during normal execution. This prevents execu-
tion of random dat a through acc ide nt a lly decrementin g
a PC into vector space, accidentally mapping a data
spac e addr ess in to vec tor sp ace , or the PC roll ing over
to 0x000000 after reaching the end of implemented
program memory space. Execution of a GOTO instruc-
tion to this vector space will also generate an address
error trap.
5.1 Interrupt Priority
The user a ssig nab le In terru pt Pri ori ty (I P<2:0 >) bi t s for
each individual interrupt source are located in the LS
3-bits of each nibble, within the IPCx register(s). Bit 3
of each nibble is not used and is read as a 0. These
bits define the priority level assigned to a particular
interrupt by the user.
Since more than one interrupt request source may be
assigned to a specific user specified priority level, a
means i s provided to assign priority within a given level.
This method is called Natural Order Priority.
Note: Interru pt fla g bit s get set when an in terru pt
conditi on oc curs, rega rdle ss of the state of
its c orresponding enable bit. User s oftware
should ensure the appropriate interrupt
flag bits are clear prior to enabling an
interrupt.
Note: Assigning a priority level of 0 to an interrupt
source is equivalent to disabling that
interrupt.
Note: The u ser sele cta ble priority levels s tart at 0
as the lowest priority and level 7, as the
highest priority.
dsPIC30F
DS70082A-page 46 Advance Information 2002 Microchip Technology Inc.
Table 5-1 lists the interrupt numbers and interrupt
sources for the dsPIC devices, and their associated
vector numbers.
The ability for the user to assign every interrupt to one
of sev en priority lev els i mp lie s that the u ser c an as sig n
a very high overall priority level to an interrupt with a
low natural order priority. For example, the PLVD (Low
Voltage Detect) can be given a priority of 7. The INT0
(external interrupt 0) may be assigned to priority level
1, thus giving it a very low effective priority.
TABLE 5-1: NATURAL ORDER PRIORITY
Note 1: The natural order priority scheme has 0
as the highest priority and 53 as the
lowest priority.
2: The natural order priority number is the
same as the INT number.
INT
Number Vector
Number Interrupt Source
Highest Natural Order Priority
0 8 INT0 - External Interrupt 0
1 9 IC1 - Input Capture 1
210 OC1 - Output Compare 1
311 T1 - Timer 1
412 IC2 - Input Capture 2
513 OC2 - Output Compare 2
614 T2 - Timer 2
715 T3 - Timer 3
816 SPI1
917 U1RX - UART1 Receiver
10 18 U1TX - UART1 Transmitter
11 19 ADC - ADC Convert Done
12 20 NVM - NVM Write Complete
13 21 I2C - I2C Transfer Complete
14 22 BCL - I2C Bus Collision
15 23 Input Change Interrupt
16 24 INT1 - External Interrupt 1
17 25 IC7 - Input Capture 7
18 26 IC8 - Input Capture 8
19 27 OC3 - Output Compare 3
20 28 OC4 - Output Compare 4
21 29 T4 - Timer 4
22 30 T5 - Timer 5
23 31 INT2 - External Interrupt 2
24 32 U2RX - UART2 Receiver
25 33 U2TX - UART2 Transmitter
26 34 SPI2
27 35 C1 - Combin ed IRQ for CAN1
28 36 IC3 - Input Capture 3
29 37 IC4 - Input Capture 4
30 38 IC5 - Input Capture 5
31 39 IC6 - Input Capture 6
32 40 OC5 - Output Compare 5
33 41 OC6 - Output Compare 6
34 42 OC7 - Output Compare 7
35 43 OC8 - Output Compare 8
36 44 INT3 - External Interrupt 3
37 45 INT4 - External Interrupt 4
38 46 C2 - Combin ed IRQ for CAN2
39 47 PWM - PWM Period Match
40 48 Q EI - QEI Interrupt
41 49 Reserved
42 50 LVD - Low Voltage Detect
43 51 FLTA - PWM Fault A
44 52 FLTB - PWM Fault B
45 - 53 53 - 61 Reserved
Lowest Natural Order Priority
2002 Microchip Technology Inc. Advance Information DS70082A-page 47
dsPIC30F
5.2 RESET Sequence
A RESET is n ot a tr ue exc eption, b ecaus e the interru pt
controller is not involved in the RESET process. The
processor initializes its registers in response to a
RESET, which forces the PC to zero. The processor
then begi ns program execution at location 0x000000. A
GOTO instruction is stored in the first program memory
locatio n, immediately followed by the add ress target for
the GOTO instruction. The processor executes the GOTO
to the specified address and then begins operation at
the specified target (start) address.
5.2.1 RESET SOURCES
In addition to external, Power-on Resets (POR) and
software Reset, there are four sources of error
conditions which trap to the RESET vector.
Watchdog Time-out:
The watchdog has timed out, indicating that the
process or is no longer ex ecu tin g the corre ct flo w
of code.
Uninitialized W Register Trap:
An attempt to use an uninitialized W register as
an address pointer will cause a RESET.
Illegal Instruction Trap:
Attempted execution of any unused opcodes will
result in an illegal instruction trap. Note that a
fetch of an illegal instruction does not result in an
illegal instruction trap if that instruction is flushed
prior to execution due to a flow change.
Brown-out Reset (BOR):
A momentary dip in the power supply to the
device has been detected, which may result in
malfunction.
5.3 Traps
Traps can be considered as non-maskable, non-stable
interrupts, which adhere to a predefined priority as
shown in Table 5-2. They are intended to provide the
user a means to correct erroneous operation during
debug and when operating within the application.
Note that many of these trap conditions can only be
detecte d when th ey occur. Consequentl y, the ques tion-
able instruction is allowed to complete prior to trap
exception processing. If the user chooses to recover
from the error, the result of the erroneous action that
caused the trap may have to be corrected.
There are 8 fixed priority levels for traps: Level 8
through Le ve l 15, whic h impl ies tha t the IPL3 i s alw ays
set during processing of a trap.
If the us er is n ot cur rentl y execu ting a trap, a nd he s et s
the IP L<3:0> bit s to a value of 0111 (Level 7), t hen al l
interr upts are disabled, b ut traps c an still b e processed.
5.3.1 TRAP SOURCES
The following traps are provided with increasing prior-
ity. However, since all traps can be nested, priority has
little effect.
Math Error Trap:
The Math Error trap executes under the following
three ci rcu ms t ances.
1. Should an attempt be made to divide by
zero, the div ide operation wil l be aborted on
a cycle boundary and the trap taken.
2. If enabled, a Math Error trap will be taken
when an arithmetic operation on either
accumulator A or B, causes an overflow
from bit 31 and the accumulator guard bits
are not utilized.
3. If enabled, a Math Error trap will be taken
when an arithmetic operation on either
accumulator A or B causes a catastrophic
overflow from bit 39 and all saturation is
disabled.
Address Error Trap:
This trap is initiated when any of the following
circumstances occurs:
1. A misaligned data word fetch is attempted.
2. A data fetch from unused data address
spac e is atte mpted.
3. A program fetch from unimplemented user
program address space is attempted.
4. A program fe tch from vec tor addr ess sp ac e
is attempted.
Stack Error T ra p
This trap is initiated under the following
conditions:
1. The stack pointer is loaded with a value
which is greater than the (user program-
mable) limit value written into the SPLIM
register (st a ck overf low ).
2. The stack pointer is loaded with a value
which is less than 0x0800 (simple stack
underflow).
Oscillator Fail Trap:
This trap is initiated if the external oscillator fails
and operation becomes reliant on an internal RC
backup.
Note: If the user does not intend to take correc-
tive action in the event of a trap error con-
dition, these vectors must be loaded with
the RESET vect or address. If, on the oth er
hand, one of the vectors containing an
invalid address is called, an address error
trap is generated.
Note: The IPL3 bit is read only , which implies that
the user can not man ually set th e IPL<3:0>
bits to a value greater than 7.
dsPIC30F
DS70082A-page 48 Advance Information 2002 Microchip Technology Inc.
5.3.2 HARD AND SOFT TRAPS
It is possible that multiple traps can become active
within the same cycle (e.g., a misaligned word stack
write to an overflowed address). In such a case, the
fixed priority shown in Figure 5-2 is implemented,
whic h may requir e the user t o check if oth er traps are
pending, in order to completely correct the fault.
Soft trap s include ex ceptions of p riority level 8 through
level 11, inclusive. The arithmetic error trap (level 11)
falls into this cat egory of traps. Soft traps can be tr eated
like non-maskable sources of interrupt that adhere to
the priority assigned by their position in the IVT. Soft
traps are pr oce ssed li ke in terrupt s an d requ ire 2 c ycle s
to be sampled and Acknowledged prior to exception
processing. Therefore, additional instructions may be
executed before a soft trap is Acknowledged.
Hard traps include exceptions of priority level 12
through level 15, inclusive. The address error (level
12), st ack error (leve l 13), and osc illator error (level 14)
traps fall into this category.
Like soft traps, hard traps can also be viewed as non-
maska ble so urc es of i nter r upt . The difference betw ee n
hard traps and soft traps is that hard traps force the
CPU t o s t op c od e ex ec ut i on af te r th e i n st ruc t io n caus -
ing t he t rap h as complet ed. Norm al program ex ec ution
flow will not resume until after the trap has been
acknowl edged and process ed.
If a higher priority trap occurs while any lower priority
trap is in progress, processing of the lower priority trap
will be suspended and the higher priority trap will be
acknowledged and processed. The lower priority trap
will remain pending until processing of the higher
priority trap completes.
Each hard trap that occurs must be acknowledged
before code execution of any type may continue. If a
lower priority hard trap occurs while a higher priority
trap is pending, acknowledged, or is being processed,
a hard trap conflict will occur. The conflict occurs
because the lower priority trap cannot be Acknowl-
edged until processing for the higher priority trap
completes.
The device is automatically RESET in a hard trap con-
flict condition. The TRAPR status bit (RCON<15> ) is
set when th e RESET oc cu rs, s o th at the c ond iti on ma y
be detected in software.
5.4 Interrupt Sequence
All interr upt event flags are sampled in the be ginning of
each instruction cycle by the IFSx registers. A pending
interrupt re quest (I RQ) is in dicate d by the flag bit b eing
equal to a 1 i n an IFS x regis ter. The IRQ will c ause an
interrupt to occur if the corresp onding bit in the interrupt
enable (IECx) register is set. For the remainder of the
instruction cycle, the priorities of all pending interrupt
requests are evaluated.
If there is a pending IRQ with a priority level greater
than the current processor priority level in the IPL bits,
the processor will be interrupted.
The proce ssor then stac ks the current program counter
and the low byte of the pro cessor status register (SRL),
as show n in Figu re 5-1. The low b yte of the status reg-
ister contains the processor priority level at the time,
prior to the beginning of the interrupt cycle. The proces-
sor then load s the priority level for this interrup t into the
status register. This action will disable all lower priority
interrupts until the completion of the Interrupt Service
Routine.
FIGURE 5-1: INTERRUPT STACK
FRAME
The RETFIE (Return from Interrupt) instruction will
unstack the program counter and status registers to
return the processor to its state prior to the interrupt
sequence.
Note 1: The user can always lower the priority
level by writing a new value into SR. The
Interrupt Service Routine must clear the
interrupt flag bits in the IFSx register
before lowering the processor interrupt
priority, in order to avoid recursive
interrupts.
2: The IPL3 bit (CORCON<3>) is always
clear when interrupts are being pro-
cessed. It is set only during execution of
traps.
<Free Wo rd>
015
W15 (bef ore CALL)
W15 (after CALL)
Stack Grows Towards
Higher Address
PUSH : [W15++]
POP : [--W15]
0x0000
PC<15:0>
SRL IPL3 PC<22:16>
2002 Microchip Technology Inc. Advance Information DS70082A-page 49
dsPIC30F
TABLE 5-2: EXCEPTION VECTORS
5.5 Alternate Vector Table
In Program Memory, the Interrupt Vector Table (IVT) is
follow ed b y the A ltern ate I nte rrupt Vector Table (AIVT),
as show n in Table 5- 2. Acce ss to the Al ternate Ve ctor
Table is provided by the ALTIVT bit in the INTCON2
register. If the ALTIVT bit is set, a ll in terrupt a nd exce p-
tion processes will use the alternate vectors instead of
the defa ult vectors. The alternate vectors are organized
in the same manner as the default vectors. The AIVT
supports emulation and debugging efforts by providing
a means to switch between an application and a sup-
port environment, without requiring the interrupt vec-
tors to be reprogrammed. This feature also enables
switching between applications for evaluation of
different software algorithms at run time.
If the AIVT is not required, the program memory allo-
cated to the AIVT may be used for other purposes.
AIVT is not a protected section and may be freely
programmed by the user.
5.6 Fast Context Saving
A context saving option is available using shadow reg-
isters. Shadow registers are provided for the DC, N,
OV, Z and C bits in SR, the TBLPAG and PSVPAG reg-
isters, and the registers W0 through W14. The shad-
ows are only on e level deep. Th e shado w regi sters a re
accessible using the PUSH.S and POP.S instructions
only.
When the processor vectors to an interrupt, the
PUSH.S instruction can be used to store the current
value of the aforementioned registers into their
respective shadow registers.
If an ISR of a certain priority uses the PUSH.S and
POP.S instructions for fast context saving, then a
higher priority ISR shou ld no t inc lude the s ame instruc-
tions. Users must save the key registers in software
during a lower priorit y interrupt, if t he higher prio rity ISR
uses fast context saving.
5.7 External Interrupt Requests
The interrupt controller supports up to five external
interrupt re quest signa ls, INT0 - INT4. Th ese input s are
edge se nsitive, i.e., the y require a low-to-high or a high-
to-low transition to generate an interrupt request. The
INTCON2 regis ter ha s fi ve bi t s , INT0EP - INT4EP, that
select the polarity of the edge detection circuitry.
5.8 Wake-up from SLEEP and IDLE
The interrupt controller may be used to wake up the
processor f rom either SLEEP o r IDLE modes, if SLEEP
or IDLE mode is active whe n the inte rrupt is g enerated.
If an enabled interrupt request of sufficient priority is
received by the interrupt controller, then the standard
interrupt request is presented to the processor. At the
same time, the processor will wake-up from SLEEP or
IDLE and begin execution of the Interrupt Service
Routin e (ISR), nee ded to p rocess t he interru pt request.
Address Error Trap Vector
Oscillator Fail Trap Vector
Stack Error Trap Vector
Reserved Vector
Math Error Trap Vector
Reserved
Oscillator Fail Trap Vector
Address Error Trap Vector
Reserved Vector
Reserved Vector
Interrupt 0 Vector
Interrupt 1 Vector
Interrupt 52 Vector
Interrupt 53 Vector
Math Error Trap Vector
Decreasing
Priority
0x000000
0x000014
Reserved
Stack Error Trap Vector
Reser ved Vector
Reser ved Vector
Interrupt 0 Vector
Interrupt 1 Vector
Interrupt 52 Vector
Interrupt 53 Vecto r
IVT
AIVT
0x000080
0x00007E
0x0000FE
Reserved
0x000094
RESET - GOTO Instruction
RESET - GOTO Addr ess 0x000002
Reserved 0x000082
0x000084
0x000004
Reser ved Vector
dsPIC30F
DS70082A-page 50 Advance Information
2002 Microchip Technology Inc.
TABLE 5-3: INTERRUPT CONTROLLER REGISTER MAP
SFR
Name ADR Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RESET State
INTCON1 0080 NSTDIS OVATE OVBTE COVTE MATHERR ADDRERR STKERR OSCFAIL 0000 0000 0000 0000
INTCON2 0082 ALTIVT INT4EP INT3EP INT2EP INT1EP INT0EP 0000 0000 0000 0000
IFS0 0084 CNIF BCLIF I2CIF NVMIF ADIF U1TXIF U1RXIF SPI1IF T3IF T2IF OC2IF IC2IF T1IF OC1IF IC1IF INT0 0000 0000 0000 0000
IFS1 0086 IC6IF IC5IF IC4IF IC3IF C1IF SPI2IF U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF IC8IF IC7IF INT1IF 0000 0000 0000 0000
IFS2 0088 FLTBIF FLTAIF LVDIF QEIIF PWMIF C2IF INT4IF INT3IF OC8IF OC7IF OC6IF OC5IF 0000 0000 0000 0000
IEC0 008C CNIE BCLIE I2CIE NVMIE ADIE U1TXIE U1RXIE SPI1IE T3IE T2IE OC2IE IC2IE T1IE OC1IE IC1IE INT0IE 0000 0000 0000 0000
IEC1 008E IC6IE IC5IE IC4IE IC3IE C1IE SPI2IE U2TXIE U2RXIE INT2IE T5IE T4IE OC4IE OC3IE IC8IE IC7IE INT1IE 0000 0000 0000 0000
IEC2 0090 FLTBIE FLTAIE LVDIE QEIIE PWMIE C2IE INT4IE INT3IE OC8IE OC7IE OC6IE OC5IE 0000 0000 0000 0000
IPC0 0094 T1IP<2:0> OC1IP<2:0> IC1IP<2:0> INT0IP<2:0> 0100 0100 0100 0100
IPC1 0096 T31P<2:0> T2IP<2:0> OC2IP<2:0> IC2IP<2:0> 0100 0100 0100 0100
IPC2 0098 ADIP<2:0> U1TXIP<2:0> U1RXIP<2:0> SPI1IP<2:0> 0100 0100 0100 0100
IPC3 009A CNIP<2:0> BCLIP<2:0> I2CIP<2:0> NVMIP<2:0> 0100 0100 0100 0100
IPC4 009C OC3IP<2:0> IC8IP<2:0> IC7IP<2:0> INT1IP<2:0> 0100 0100 0100 0100
IPC5 009E INT2IP<2:0> T5IP<2:0> T4IP<2:0> OC4IP<2:0> 0100 0100 0100 0100
IPC6 00A0 C1IP<2:0> SPI2IP<2:0> U2TXIP<2:0> U2RXIP<2:0> 0100 0100 0100 0100
IPC7 00A2 IC6IP<2:0> IC5IP<2:0> IC4IP<2:0> IC3IP<2:0> 0100 0100 0100 0100
IPC8 00A4 OC8IP<2:0> OC7IP<2:0> OC6IP<2:0> OC5IP<2:0> 0100 0100 0100 0100
IPC9 00A6 PWMIP<2:0> C2IP<2:0> INT41IP<2:0> INT3IP<2:0> 0100 0100 0100 0100
IPC10 00A8 FLTAIP<2:0> LVDIP<2:0> QEIIP<2:0> 0100 0100 0000 0100
IPC11 00AA FLTBIP<2:0> 0000 0000 0000 0100
Legend: u = uninitialized bit
2002 Microchip Technology Inc. Advance Information DS70032D-page 51
dsPIC30F
6.0 FLASH PROGRAM MEMORY
The dsPIC30F family of devices contains internal pro-
gram FLASH memory for executing user code. There
are two methods by which the user can program this
memory:
1. Run Time Self-Programming (RTSP)
2. In-Circuit Serial Pr ogrammi ngTM (ICSPTM)
6.1 In-Circui t Serial Programming
(ICSP)
The details of ICSP will be provided at a later date.
6.2 Run Time Self-Programming
(RTSP)
RTSP is accomplished using TBLRD (table read) and
TBLWT (table write) instructions, and the following
control regi sters:
NVMCON: Non-Vo latile Memory Control Register
NVMKEY: Non-Volatile Memory Key Register
NVMADR: Non-Volatile Memory Address
Register
With RTSP, the user may erase program memory, 32
instruc tions (96 bytes ) at a tim e an d c an wr it e pro gram
memory data, 4 instructions (12 bytes) at a time.
6.3 Table Instruction Operation Summary
The TBLRDL and the TBLWTL instructions are used to
read or write to bits <15:0> of program memory.
TBLRDL and TBLWTL can access program memory in
Word or Byte mode.
The TBLRDH and TBLWTH instruc tions are us ed to read
or write to bits<23:16> of program memory. TBLRDH
and TBLWTH can access program memory in Word or
Byte mode.
A 24-bit program memory address is formed using
bits<7:0> of the TBLPAG register and the effective
address (EA) from a W register specified in the table
instruction, as sh own i n Figure 6-1.
FIGURE 6-1: ADDRESSING FOR TABLE AND NVM REGISTERS
0Program Counter
24-bits
TBLPAG Reg
8-bits 16-bits
Program
Using
TBLPA G Reg
8-bits
Working Reg EA
16-bits
Using
Byte
24-b it EA
1/0
0
1/0
Select
Table
Instruction
NVMADR
Addressing
Counter
Using
NVMADR Re g EA
User/Configuration
Space S elect
dsPIC30F
DS70032D-page 52 Advance Information 2002 Mic rochip Technology Inc.
6.4 RTSP Operation
The dsPIC30F FLASH program memory is organized
into rows and panels. Each row consists of 32 instruc-
tions, or 96 bytes. Each panel consists of 128 rows, or
4K x 24 instructions. Run Time Self Programming
(RTSP) allows the user to erase one row (32 instruc-
tions) at a time and to program four instructions at one
time. RTSP may be used to program multiple program
memory p a ne ls, bu t th e table p oin ter must be change d
at each panel boundary.
Each panel of program memory contains write latches
that hold four instructi ons of program ming data. Prio r to
the actual programming operation, the write data must
be loaded into the panel write latches. The data to be
programmed into the panel is loaded in sequential
order into the write latches: instruction 0, instruction 1,
etc. T he i ns truc tio n words loaded m us t a lw ay s be from
a group of four boundary (e.g., loading of instructions 3,
4, 5, 6 is not allowed).
The basi c sequence for R TSP programming is to set up
a table point er, then do a se ries o f TBLWT instructions
to load th e wri te latc hes. Program ming is perfo rmed by
setting the special bits in the NVMCON register. Four
TBLWTL and four TBLWTH instructions are required to
load the four instructions. To fully program a row of
program memory , eight cycles of four TBLWTL and four
TBLWTH are req uired. If multipl e pane l prog rammi ng
is required, the table pointer needs to be changed and
the next set of multiple write latches written.
All of the table write operations are single word writes
(2 instruction cycles), because only the table latches
are writt en. A total of 8 programming p asses, ea ch writ-
ing 4 inst ruction words, are required per row . A 12 8 row
panel requires 1024 programming cycles.
The FLASH Program Memory is readable, writable,
and erasable during normal operation, over the entire
VDD range.
6.5 Control Registers
The three SFRs used to read and write the program
FLASH memory are:
NVMCON
NVMADR
NVMADRU
NVMKEY
6.5.1 NVMCON REGISTER
The NVMCON register controls which blocks are to be
erased, which memory type is to be programmed, and
start of the programming cycle.
6.5.2 NVMADR REGISTER
The NVMADR register is used to hold the lower two
bytes of the effective address. The NVMADR register
captures the EA<15 :0> of the last table instru ct ion that
has been executed and selects the row to write.
6.5.3 NVMADRU REGISTER
The NVMADRU register is used to hold the upper byte
of the effective address. The NVMADRU register cap-
tures the EA<23:16> of the last table instruction that
has been exec uted.
6.5. 4 NVMKEY REGISTER
NVMKEY is a write only register that is used for write
protection. To start a programming or an erase
sequence, the user must consecutively write 0x55 and
0xAA, to th e NVMKEY register. Refer t o Section 6.6 f or
further details.
6.6 Programming Operations
A complete programming sequence is necessary for
programming or erasing the internal FLASH in RTSP
mode. A progra mming operati on is nominally 2 ms ec in
duration and the processor stalls (waits) until the oper-
ation is finished. Setting the WR bit (NVMCON<15>)
starts the operation, and the WR bit is automatically
cleared when the operation is finished.
2002 Microchip Technology Inc. Advance Information DS70032D-page 53
dsPIC30F
6.6.1 PROGRAMMING ALGORITHM FOR
PROGRAM FLASH
The user can erase one row of program FLASH mem-
ory at a time. The user can program one block (4
instruction words) of FLASH memory at a time. The
general proc es s is:
1. Read one row of pr ogram FLAS H (32 instruct ion
words) and store into data RAM as a data image.
2. Update the data image with the desired new data.
3. Erase program FLASH row.
a. Setup NVMCON register for multi-word,
program FLASH, eras e, and set WREN bit.
b. Write address of row to be erased into
NVMADR.
c. Write 55 to NVMKEY.
d. Write AA to NVMKEY.
e. Set the WR bit. This will begin erase cycle.
f. CPU will stall for the duration of the erase cycle.
g. The WR bit is cleared when erase cycle ends.
4. Write four instruction words of data from data
RAM into the program FLASH write latches.
5. Program 4 instruction words into program
FLASH.
a. Setup NVMCON register for multi-word,
program FLASH, program, and set WREN bit.
b. Write 55 to NVMKEY.
c. Write AA to NVMKEY.
d. Set the WR bit. This will begin program cycle.
e. CPU will stall for duration of the program cycle.
f. The WR bit is cleared by the hardware when
program cycle ends.
6. Re peat ste ps (4 - 5) seven mor e times to fi nish
programming FLASH row.
7. Repeat steps 1 throu gh 6 as needed to pro gram
desired amount of program FLASH memory.
6.6.2 ERASING A ROW OF PROGRAM
MEMORY
The following is a code sequence that can be used to
erase a row (32 instructions) of program memory.
EXAMPLE 6-1: ERASING A ROW OF PROGRAM MEMORY
; Setup NVMCON for erase operation, multi word write
; program memory selected, and writes enabled
MOV #0x4041,W0 ;
MOV W0,NVMCON ; Init NVMCON SFR
; Init pointer to row to be ERASED
MOV #tblpage(PROG_ADDR),W0 ;
MOV W0,TBLPAG ; Initialize PM Page Boundary SFR
MOV #tbloffset(PROG_ADDR),W0 ; Intialize in-page EA[15:0] pointer
MOV W0, NVMADR ; Intialize NVMADR SFR
MOV #0x55,W0 ;
MOV #0xAA,W1 ;
MOV W0,NVMKEY ; Write the 0x55 key
MOV W1,NVMKEY ; Write the 0xAA key
NOP ;
BSET NVMCON,#WR ; Start the erase sequence
NOP ; Insert two NOPs after the erase
NOP ; command is asserted
dsPIC30F
DS70032D-page 54 Advance Information 2002 Mic rochip Technology Inc.
6.6.3 LOADING WRITE LATCHES
The following is a sequence of instructions that can be
used to load the 96 bits of write latches. Four TBLWTL
and four TBLWTH instructions are needed to load the
write latches selected by the table pointer.
EXAMP L E 6-2: L OA D ING WRIT E LA TCHES
; Set up a pointer to the first program memory location to be written
; program memory selected, and writes enabled
MOV #0x0000,W0 ;
MOV W0,TBLPAG ; Initialize PM Page Boundary SFR
MOV #0x6000,W0 ; An example program memory address
; Perform the TBLWT instructions to write the latches
; 0th_program_word
MOV #LOW_WORD_0,W2 ;
MOV #HIGH_BYTE_0,W3 ;
TBLWTL W2,[W0] ; Write PM low word into program latch
TBLWTH W3,[W0++] ; Write PM high byte into program latch
; 1st_program_word
MOV #LOW_WORD_1,W2 ;
MOV #HIGH_BYTE_1,W3 ;
TBLWTL W2,[W0] ; Write PM low word into program latch
TBLWTH W3,[W0++] ; Write PM high byte into program latch
; 2nd_program_word
MOV #LOW_WORD_2,W2 ;
MOV #HIGH_BYTE_2,W3 ;
TBLWTL W2, [W0] ; Write PM low word into program latch
TBLWTH W3, [W0++] ; Write PM high byte into program latch
; 3rd_program_word
MOV #LOW_WORD_3,W2 ;
MOV #HIGH_BYTE_3,W3 ;
TBLWTL W2, [W0] ; Write PM low word into program latch
TBLWTH W3, [W0++] ; Write PM high byte into program latch
Note: In Example 6-2, the contents of the upper byte of W3 has no effect.
2002 Microchip Technology Inc. Advance Information DS70032D-page 55
dsPIC30F
6.6.4 INITIATING THE PROGRAMMING
SEQUENCE
For protec tion, the w rite i nitiate sequenc e for N VMKEY
must be used to allow any erase or program operation
to procee d. After the prog ramming comm and has bee n
executed, the user must wait for the programming time
until programming is co mplete. The two instructions fol-
lowing the start of the programming sequence should
be NOPs.
EXAMPLE 6-3: INITIATING A PROGRAMMING SEQUENCE
MOV #0x55,W0 ;
MOV #0xAA,W1 ;
MOV W0,NVMKEY ; Write the 0x55 key
MOV W1,NVMKEY ; Write the 0xAA key
NOP ;
BSET NVMCON,#WR ; Start the erase sequence
NOP ; Insert two NOPs after the erase
NOP ; command is asserted
DSPIC30F
DS70032D-page 56 A dva nce Information
2002 Microchip Technology Inc.
TABLE 6-1: NVM REGISTER MAP
File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All RESETS
NVMCON 0760 WR WREN WRERR PROGOP<6:0> 0000 0000 0000 0000
NVMADR 0762 NVMADR<15:0> uuuu uuuu uuuu uuuu
NVMADRU 0764 NVMADR<23:16> 0000 0000 uuuu uuuu
NVMKEY 0766 KEY<7:0> 0000 0000 0000 0000
Legend: u = uninitialized bit
2002 Microchip Technology Inc. Advance Information DS70082A-page 57
dsPIC30F
7.0 DATA EEPROM MEMORY
The Data EEPROM Memory is readable and writable
during no rmal operatio n over the enti re VDD range. The
data EEPROM memory is directly mapped in the
program memory address space.
The four SFRs used to read and write the program
FLASH memory are used to access data EEPROM
memory, as well. As described in Section 4.0, these
registers are:
NVMCON
NVMADR
NVMADRU
NVMKEY
The EEPROM data memory allows read and write of
single words and 16-word blocks. When interfacing to
data memory, NVMADR in conjunction with the
TBLPAG register, are used to address the EEPROM
locatio n bei ng ac cess ed. TBLRDL and TBLWTL instruc-
tions are used to read and write data EEPROM. The
dsPIC30F devices have up to 8 Kbytes (4K words) of
data EEPROM, with an address range from 0x7FF000
to 0x7FFFFE.
A word wri te operatio n should be prec eded by an e rase
of the corresponding memory location(s). The write typ-
ically requires 2 ms to complete. However, the write
time varies with voltage and temperature.
A program or erase operation on the data EEPROM
does n ot sto p the ins truc tion fl ow. The user is re spon-
sible for waiting for the appropriate duration of time
before initiating another data EEPROM write/erase
operatio n. Attem pting t o read t he dat a EEPROM, while
a programming or erase operation is in progress,
results in unspecified data.
Control bi t WR in itia tes w rite ope rati ons , s im ila r to p ro-
gram FLASH writes. This bit cannot be cleared, only
set, in software. This bit is cleared in hardware at the
completion of the write operation. The inability to clear
the WR bit in software prevents the accidental or
premature termination of a write operation.
The WREN bit, when set, will allow a write operation.
On powe r-up, the WR EN bit is clear. The WRERR bit i s
set when a write operation is interrupted by a MCLR
Reset, or a WDT Time-out Reset, during normal oper-
ation . In these situa tio ns, foll owing Rese t, the us er can
check the WRERR bit and rewrite the location. The
address register NVMADR remains unchanged.
7.1 Reading the Data EEPROM
A TBLRD instruction reads a word at the current pro-
gram word address. This example uses W0 as a
pointer to data EEPROM. The result is placed in
register W4, as shown in Example 7-1.
EXAMPLE 7-1: DATA EEPROM READ
Note: Interru pt flag bit NVMI F in the IFS0 regis ter
is set when write is complete. It must be
cleared in software.
MOV #LOW_ADDR_WORD,W0 ; Init Pointer
MOV #HIGH_ADDR_WORD,W1
MOV W1,TBLPAG
TBLRDL [ W0 ], W4 ; read data Flash
dsPIC30F
DS70082A-page 58 Advance Information 2002 Microchip Technology Inc.
7.2 Erasing Data EEPROM
7.2.1 ERASI NG A BLOCK OF DATA
EEPROM
In order to erase a block of data EEPRO M, the TBLP AG
and NVMADR registers must initially point to the block
of memory to be erased. Configure NVMCON for eras-
ing a block of data EEPROM, and set the ERASE and
WREN bits in NVMCON register. Setting the WR bit
initiates the erase, as shown in Exampl e 7-2.
EXAMPLE 7-2: DATA EEPROM BLOCK ERASE
7.2.2 ERASING A WORD OF DATA
EEPROM
The TBLPA G and NVMADR registers must point to the
block. Select erase a block of data FLASH, and set the
ERASE and WREN bits in NVMCON register. Setting
the WR bit initiates the erase, as shown in Example 7-3.
EXAMPLE 7-3: DATA EEPROM WORD ERASE
; Select data EEPROM block, ERASE, WREN bits
MOV #4045,W0
MOV W0,NVMCON ; Initialize NVMCON SFR
; Start erase cycle by setting WR after writing key sequence
MOV #0x55,W0 ;
MOV #0xAA,W1 ;
MOV W0,NVMKEY ; Write the 0x55 key
MOV W1,NVMKEY ; Write the 0xAA key
NOP ;
BSET NVMCON,#WR ; Initiate erase sequence
; Erase cycle will complete in 2mS. CPU is not stalled for the Data Erase Cycle
; User can poll WR bit, use NVMIF or Timer IRQ to determine erasure complete
; Select data EEPROM word, ERASE, WREN bits
MOV #4044,W0
MOV W0,NVMCON
; Start erase cycle by setting WR after writing key sequence
MOV #0x55,W0 ;
MOV #0xAA,W1 ;
MOV W0,NVMKEY ; Write the 0x55 key
MOV W1,NVMKEY ; Write the 0xAA key
NOP ;
BSET NVMCON,#WR ; Initiate erase sequence
; Erase cycle will complete in 2mS. CPU is not stalled for the Data Erase Cycle
; User can poll WR bit, use NVMIF or Timer IRQ to determine erasure complete
2002 Microchip Technology Inc. Advance Information DS70082A-page 59
dsPIC30F
7.3 Writing to the Data EEPROM
To write an EEPROM data location, the following
sequen ce must be followed:
1. Erase data EEPROM word.
a. Select word, data EEPROM, erase, and set
WREN bit in NVMCO N regis ter.
b. Write address of word to be erased into
NVMADR.
c. Optionally, enable NVM interrupt.
d. Write 55 to NVMKEY.
e. Write AA to NVMKEY.
f. Set the WR bit. This will begin erase cycle.
g. Either poll NVMIF bit or wait for NVMIF interrupt.
h. The WR bit is cleared when the erase cycle
ends.
2. Write data word into data EEPROM write
latches.
3. Program 1 data word into data EEPROM.
a. Select word, data EEPROM, program, and set
WREN bit in NVMCO N regis ter.
b. Optionally, enable NVM write done interrupt.
c. Write 55 to NVMKEY.
d. Write AA to NVMKEY.
e. Set The WR bit. This will begin program cycle.
f. Either poll NVMIF bit or wait for NVM interrup t.
g. The WR bit is cleared when the write cycle
ends.
The write will not initiate if the above sequence is not
exactly followed (write 0x55 to NVMKEY, write 0xAA to
NVMCON, then set WR bit) for each word. It is strongly
recommended that interrupts be disabled during this
code segment.
Additionally, the WREN bit in NVMCON must be set to
enable writes. This mechanism prevents accidental
writes to data EEPROM, due to unexpected code exe-
cution. The WR EN b it sho ul d be k ept clear at a ll tim es ,
except when updating the EEPROM. The WREN bit is
not cleared by hardware.
After a write sequence has been initiated, clearing the
WREN bit wil l not affect the current write cycle. The WR
bit will be inhibited from being set unless the WREN bit
is set. The WREN bit must be set o n a previous instruc -
tion. Both WR a nd WREN c an not be se t with th e s am e
instruction.
At the completion of the write cycle, the WR bit is
cleared in hardware and the Non-Volatile Memory
Write Complete Interrupt Flag bit (NVMIF) is set. The
user may either enable this interrupt, or poll this bit.
NVMIF must be cleared by software.
7.3.1 WRITING A WORD OF DATA
EEPROM
Assuming the user has erased the word to be pro-
grammed, then, use a table write instruction to write
one write latch, as shown in Example 7-4.
EXAMPLE 7-4: DATA EEPROM WORD WRITE
; Point to data memory
MOV #LOW_ADDR_WORD,W0 ; Init pointer
MOV #HIGH_ADDR_WORD,W1
MOV W1,TBLPAG
MOV #LOW(WORD),W2 ; Get data
TBLWTL W2,[ W0] ; Write data
; The NVMADR captures last table access address
; Select data EEPROM for 1 word op
MOV #0x4004,W0
MOV W0,NVMCON
; Operate key to allow write operation
MOV #0x55,W0
MOV #0xAA,W1
MOV W0,NVMKEY ; Write the 0x55 key
MOV W1,NVMKEY ; Write the 0xAA key
NOP
BSET NVMCON,#WR ; Initiate program sequence
; Write cycle will complete in 2mS. CPU is not stalled for the Data Write Cycle
; User can poll WR bit, use NVMIF or Timer IRQ to determine write complete
dsPIC30F
DS70082A-page 60 Advance Information 2002 Microchip Technology Inc.
7.3.2 WRITING A BLOCK OF DATA
EEPROM
To write a block of data EEPROM, write to all sixteen
latches first, then set the NVMCON register and
progra m the block .
EXAMPLE 7-5: DATA EEPROM BLOCK WRITE
7.4 Write V e rify
Depending on the application, good programming
practice may dictate that the value written to the mem-
ory should be verified against the original value. This
should be used in applications where excessive writes
can stress bits near the specification limit.
7.5 Protection Against Spurious Write
There are conditions when the device may not want to
write to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been built-in. On power-up, the WREN bit is cleared;
also, the Power-up Timer prevents EEPROM write.
The wri te initiate sequenc e and the W REN bit toge ther ,
help prevent an accidental write during brown-out,
power glitch, or software malfunction.
MOV #LOW_ADDR_WORD,W0 ; Init pointer
MOV #HIGH_ADDR_WORD,W1
MOV W1,TBLPAG
MOV #data1,W2 ; Get 1st data
TBLWTL W2,[ W0]++ ; write data
MOV #data2,W2 ; Get 2nd data
TBLWTL W2,[ W0]++ ; write data
MOV #data3,W2 ; Get 3rd data
TBLWTL W2,[ W0]++ ; write data
MOV #data4,W2 ; Get 4th data
TBLWTL W2,[ W0]++ ; write data
MOV #data5,W2 ; Get 5th data
TBLWTL W2,[ W0]++ ; write data
MOV #data6,W2 ; Get 6th data
TBLWTL W2,[ W0]++ ; write data
MOV #data7,W2 ; Get 7th data
TBLWTL W2,[ W0]++ ; write data
MOV #data8,W2 ; Get 8th data
TBLWTL W2,[ W0]++ ; write data
MOV #data9,W2 ; Get 9th data
TBLWTL W2,[ W0]++ ; write data
MOV #data10,W2 ; Get 10th data
TBLWTL W2,[ W0]++ ; write data
MOV #data11,W2 ; Get 11th data
TBLWTL W2,[ W0]++ ; write data
MOV #data12,W2 ; Get 12th data
TBLWTL W2,[ W0]++ ; write data
MOV #data13,W2 ; Get 13th data
TBLWTL W2,[ W0]++ ; write data
MOV #data14,W2 ; Get 14th data
TBLWTL W2,[ W0]++ ; write data
MOV #data15,W2 ; Get 15th data
TBLWTL W2,[ W0]++ ; write data
MOV #data16,W2 ; Get 16th data
TBLWTL W2,[ W0]++ ; write data. The NVMADR captures last table access address.
MOV #0x400A,W0 ; Select data EEPROM for multi word op
MOV W0,NVMCON ; Operate Key to allow program operation
MOV #0x55,W0
MOV #0xAA,W1
MOV W0,NVMKEY ; Write the 0x55 key
MOV W1,NVMKEY ; Write the 0xAA key
BSET NVMCON,#WR ; Start write cycle
2002 Microchip Technology Inc. Advance Information DS70082A-page 61
dsPIC30F
8.0 I/O PORTS
All of the device pins (except VDD, VSS, MCLR, and
OSC1/CL KIN) are shared bet ween the pe ripherals an d
the parallel I/O ports.
All I/O input ports feature Schmitt Trigger inputs for
improved noise immunity.
8.1 Parallel I/O (P I O ) P o rts
When a peripheral is enabled, the use of any associ-
ated pin as a general purpose output pin is disabled.
The I/O pin may be read, but the output driver for the
parallel port bit will be disabled. If a peripheral is
enabled , bu t the peri phe ral i s n ot ac ti vel y d riv ing a pi n,
that pin may be dri ven by a port.
All port pins have three registers directly associated
with the operation of the port pin. The data direction
register (TRISx ) determ ines whe ther the pin is an inp ut
or an output. If the Data Direction bit is a 1, then the
pin is an input. All port pins are defined as inputs after
a RESET. Reads from the latch (LATx), read the latch.
Writes to the latch, write the latch (LATx). Reads from
the port (PORTx), read the port pins, and writes to the
port pins, write the latch (LATx).
Any bit and its associated data and control registers
that is not valid for a particular device will be disabled.
That means the corresponding LATx and TRISx
registers and the port pin will read as zeros.
When a pin is shared with another peripheral or func-
tion that is defined as an input only, it is nevertheless
regarded as a dedicated port because there is no
other competing source of outputs. An example is the
INT4 pin.
The format of the registers for PORTA are shown in
Table 8-1.
The TRISA (Data Direction Control) register controls
the direction of the RA<7:0> pins, as well as the INTx
pins and the VREF pins. The LATA register supplies
data to the outputs, and is readable/writable. Reading
the PORTA register yields the state of the input pins,
while writing the PORTA register modifies the contents
of the LATA register.
FIGURE 8-1: BLOCK DIAGRAM OF A DEDICATED PORT STRUCTURE
QD
CK
WR LAT +
TRIS Latch
I/O Pad
WR Port
Data Bus
QD
CK
Data Latch
Read LAT
Read Port
Read TRIS
WR TRIS
I/O Cell
Dedicated Port Module
dsPIC30F
DS70082A-page 62 Advance Information
2002 Microchip Technology Inc.
TABLE 8-1: PORTA REGISTER MAP
SFR
Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 1 1 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RESET State
TRISA 02C0 TRISA15 TRISA14 ———TRISA10 TRISA9 1100 0110 0000 0000
PORTA 02C2 RA15 RA14 ———RA10 RA9 0000 0000 0000 0000
LATA 02C4 LATA15 LATA14 ———LATA10 LATA9 0000 0000 0000 0000
Legend: u = uninitialized bit
2002 Microchip Technology Inc. Advance Information DS70082A-page 63
dsPIC30F
A parallel I/O (PIO) port that shares a pin with a
peripheral is, in general, subservient to the peripheral.
The peripherals output buffer data and control signals
are provi ded to a pair of mult iplexer s . The mult iplexers
select whether the peripheral or the associated port
has ow nershi p of the outp ut dat a and c ontrol sign als of
the I/O pad cell. Figure 8-2 shows how ports are
shared with other peripherals, and the associated I/O
cell (pad) to which they are connected. Table 8-2
through Table 8-7 show the formats of the registers for
the shared ports, PORTB through PORTG.
FIGURE 8-2: BLOCK DIAGRAM OF A SHARED PORT STRUCTURE
8.2 Configuring Analog Port Pins
The use of the ADPC FG and TRIS registers control the
operation of the A/D port pins. The port pins that are
desired as analog inputs must have their correspond-
ing TRIS bit set (input). If the TRIS bit is cleared (out-
put), the digital output level (VOH or VOL) will be
converted.
When read ing the POR T register, all pins confi gured as
analog in put channel w ill read as cleare d (a low lev el).
Pins configured as digital inputs, will not convert an
analog i nput. Analog leve ls on any pin that is defined as
a digital input (including the ANx pins), may cause the
input buffer to consume current that exceeds the
device specifications.
Note: The actual bits in use vary between
devices.
QD
CK
WR LAT +
TRIS Latch
I/O Pad
WR Port
Data Bus
QD
CK
Data Latch
Read LA T
Read Port
Read TRIS
1
0
1
0
WR TRIS
Peripheral Output Data Output Enable
Peripheral Input Data
I/O Cell
Peripheral Module
Peripheral Output Enable
PIO Module
Out put Mult iplexers
Output Data
Input Data
Peripheral Module Enable
dsPIC30F
DS70082A-page 64 Advance Information
2002 Microchip Technology Inc.
TABLE 8-2: PORTB REGISTER MAP
TABLE 8-3: PORTC REGISTER MAP
TABLE 8-4: PORTD REGISTER MAP
TABLE 8-5: PORTE REGISTER MAP
SFR
Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RESET St ate
TRISB 02C6 TRISB15 TRISB14 TRISB13 TRISB12 TRISB11 TRISB10 TRISB9 TRISB8 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111
PORTB 02C8 RB15 RB14 RB13 RB12 RB11 RB10 RB9 RB8 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 0000 0000 0000 0000
LATB 02CB LATB15 LATB14 LATB13 LATB12 LATB11 LATB10 LATB9 LATB8 LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 0000 0000 0000 0000
Legend: u = uninitialized bit
SFR
Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RESET State
TRISC 02CC TRISC15 TRISC14 TRISC13 ———————— TRISC3 TRISC1 1110 0000 0000 1010
PORTC 02CE RC15 RC14 RC13 ———————— RC3 RC1 0000 0000 0000 0000
LATC 02D0 LATC15 LATC14 LATC13 ———————— LATC3 LATC1 0000 0000 0000 0000
Legend: u = uninitialized bit
SFR
Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RESET State
TRISD 02D2 TRISD15 TRISD14 TRISD13 TRISD12 TRISD11 TRISD10 TRISD9 TRISD8 TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 1111 1111 1111 1111
PORTD 02D4 RD15 RD14 RD13 RD12 RD11 RD10 RD9 RD8 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 0000 0000 0000 0000
LATD 02D6 LATD15 LATD14 LATD13 LATD12 LATD11 LATD10 LATD9 LATD8 LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 0000 0000 0000 0000
Legend: u = uninitialized bit
SFR
Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RESET State
TRISE 02D8 TRISE9 TRISE8 TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 0000 0011 1111 1111
PORTE 02DB RE9 RE8 RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0 0000 0000 0000 0000
LATE 02DC LATE9 LATE8 LATE7 LATE6 LATE5 LATE4 LATE3 LATE2 LATE1 LATE0 0000 0000 0000 0000
Legend: u = uninitialized bit
2002 Microchip Technology Inc.
Advance Inf ormat ion
DS70082A-page 65
dsPIC30F
TABLE 8-6: PORTF REGISTER MAP
TABLE 8-7: PORTG REGISTER MAP
SFR
Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RESET State
TRISF 02EE TRISF8 TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 0000 0001 1111 1111
PORTF 02E0 RF8 RF7 RF6 RF5 RF4 RF3 RF2 RF1 RF0 0000 0000 0000 0000
LATF 02E2 LATF8 LATF7 LATF6 LATF5 LATF4 LATF3 LATF2 LATF1 LATF0 0000 0000 0000 0000
Legend: u = uninitialized bit
SFR
Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RESET State
TRISG 02E4 TRISG9 TRISG8 TRISG7 TRISG6 TRISG3 TRISG2 TRISG1 TRISG0 0000 0011 1100 1111
PORTG 02E6 RG9 RG8 RG7 RG6 ——RG3 RG2 RG1 RG0 0000 0000 0000 0000
LATG 02E8 LATG9 LATG8 LATG7 LATG6 LATG3 LATG2 LATG1 LATG0 0000 0000 0000 0000
Legend: u = uninitialized bit
dsPIC30F
DS70082A-page 66 Advance Information 2002 Microchip Technology Inc.
8.3 Input Change Notifi cation Module
The Input Change Notification module provides the
dsPIC30F devices the ability to generate interrupt
requests to the processor in response to a change of
state on selected input pins. This module is capable of
detecti ng inp ut ch ang e of s t a tes ev en i n SL EEP m od e,
when the cl ocks are disabled. The re are up to 22 exter-
nal signals (CN0 through CN21) that may be selected
(enabled) for generating an interrupt request on a
change of state.
TABLE 8-8: INPUT CHANGE NOTIFICATION REGISTER MAP (BITS 15-8)
TABLE 8-9: INPUT CHANGE NOTIFICATION REGISTER MAP (BITS 7-0)
SFR
Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 RESET State
CNEN1 00C0 CN15IE CN14IE CN13IE CN12IE CN11IE CN10IE CN9IE CN8IE 0000 0000 0000 0000
CNEN2 00C2 0000 0000 0000 0000
CNPU1 00C4 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE CN9PUE CN8PUE 0000 0000 0000 0000
CNPU2 00C6 0000 0000 0000 0000
Legend: u = uninitialized bit
SFR
Name Addr. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RESET State
CNEN1 00C0 CN7IE CN6IE CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE 0000 0000 0000 0000
CNEN2 00C2 CN21IE CN20IE CN19IE CN18IE CN17IE CN16IE 0000 0000 0000 0000
CNPU1 00C4 CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE 0000 0000 0000 0000
CNPU2 00C6 CN21PUE CN20PUE CN19PUE CN18PUE CN17PUE CN16PUE 0000 0000 0000 0000
Legend: u = uninitialized bit
2002 Microchip Technology Inc. Advance Information DS70082A-page 67
dsPIC30F
9.0 TIMER1 MODULE
This section describes the 16-bit General Purpose
(GP) Timer1 module and associated Operational
modes. Figure 9-1 depic ts the simpli fied blo ck dia gram
of the 16-bit Timer1 Module.
The following sections provide a detailed description,
includ ing s etup an d con trol reg isters al ong w ith a ssoci-
ated block diagrams for the Operational modes of the
timers.
The T imer1 mo dule is a 16-bit timer which can serv e as
the time count er for the rea l-time clo ck, o r operate as a
free runnin g interva l timer/c ounter . The 16-bit tim er has
the following modes:
16-bit Timer
16-bit Synchronous Counter
16-bit Asynchronous Counter
Further, the following operational characteristics are
supported:
Timer gate operation
Selectable prescaler settings
Timer operation during CPU IDLE and SLEEP
modes
Interrupt on 16-bit period register match or falling
edge of external gate signal
These Operat ing modes are determined by set ting the
appropriate bit(s) in the 16-bit SFR, T1CON. Figure 9-1
presents a block diagram of the 16-bit timer module.
16-bit T imer Mode: In t he 16-bi t T imer m ode, the timer
increments on every instruction cycle up to a match
value, preloaded into the period register PR1, then
resets to 0 and continues to count.
When the CPU goes into the IDLE mode, the timer will
stop incrementing, unless the TSIDL (T1CON<13>)
bit = 0. If TS IDL = 1, the tim er module l ogic w ill resum e
the incrementing sequence upon termination of the
CPU IDLE mode.
16-bit Synchronous Counter Mode: In the 16-bit
Synchronous Counter mode, the timer increments on
the rising edge of the applied external clock signal,
which is synchronized with the internal phase clocks.
The timer counts up to a match value preloaded in PR1,
then resets to 0 and continues.
When the CPU goes into the IDLE mode, the timer will
stop incre menting, unl ess the respectiv e TSIDL bit = 0.
If TSIDL = 1, the timer module logic will resume the
incrementing sequence upon termination of the CPU
IDLE mode.
16-bit Asynchronous Counter Mode: In the 16-bit
Asynchronous Counter mode, the timer increments on
every rising edge of the applied external clock signal.
The timer counts up to a match value preloaded in PR1,
then resets to 0 and continues.
When the timer is co nfigured for the Asynchronous mode
of operation and the CPU goes into the IDLE mode, the
timer w ill s to p incr ementing if TSIDL = 1 .
FIGURE 9-1: 16-BIT TIMER1 MODULE BLOCK DIAGRAM
TON
Sync
SOSC2
SOSC1/
PR1
T1IF
Equal Comparator x 16
TMR1
RESET
LPOSCEN
Event Flag
1
0
TSYNC
Q
QD
CK
TGATE
TCKPS<1:0>
Prescaler
1, 8, 64, 256
2
TGATE
TCY
1
0
T1CK
TCS
1 X
0 1
TGATE
0 0
(3)
Gate
Sync
dsPIC30F
DS70082A-page 68 Advance Information 2002 Microchip Technology Inc.
9.1 Timer Gate Operation
The 16-bi t timer can be pl aced in the Ga ted Ti me Accu-
mulation mode. This mode allows the internal TCY to
increm ent the respec tive timer when the gate input si g-
nal (T1CK pin) is asserted high. Control bit TGATE
(T1CON<6>) must be set to enable this mode. The
timer must be enabled (TON = 1) and the timer clock
source se t to interna l (TCS = 0).
When the CPU goe s int o the ID LE mo de, the time r will
stop incrementing, unless TSIDL = 0. If TSIDL = 1, the
timer will resume the incrementing sequence upon
termination of the CPU IDLE mode.
9.2 Timer Prescaler
The input clock (FOSC/4 or external clock) to the 16-bit
Timer, has a prescale option of 1:1, 1:8, 1:64, and
1:256 selected by control bits TCKPS<1:0>
(T1CON< 5:4 >). T he pres ca le r counter is c le are d whe n
any of the following occurs:
a wri te to the TMR1 register
a write to the T1CON register
device RESET such as POR and BOR
However, if the timer is disabled (TON = 0), then the
timer prescaler cannot be reset since the prescaler
clock is halted.
TMR1 is not cleared when T1CON is written. It is
cleared by writin g to the TMR1 register.
9.3 Timer Operation During SLEEP
Mode
During CPU SLEEP mode, the timer will operate if:
The timer module is enabled (TON = 1) and
The timer clock source is selected as external
(TCS = 0) and
The TSYNC bit (T1CON<2>) is asse rted to a logic
0, which defines the external clock source as
asynchronous.
When all three conditions are true, the timer will con-
tinue to count up to the period register and be reset to
0x0000.
When a match bet ween the timer and the peri od re gis-
ter occurs, an interrupt can be generated, if the
respective timer interrupt enable bit is asserted.
9.4 Timer Interrupt
The 16-bit tim er ha s the ab ili ty to ge nerate an interrupt
on period match. When the timer count matches the
period reg ister , th e T1IF bit is asserted and an interrupt
will be generated, if enabled. The T1IF bit must be
cleared in software. The timer interrupt flag T1IF is
located in the IFS0 control register in the Interrupt
Controller.
When the Gated Time Accumulation mode is enabled,
an interru pt will also be generated o n the falling edge of
the gate signal (at the end of the accumulation cycle).
Enabling an interrupt is accomplished via the respec-
tive timer interrupt enable bit, T1IE. The timer interrupt
enable bit is located in the IEC0 control register in the
Interrupt Controller.
9.5 Real-Time Clock
Timer1, when operating in Real-Time Clock (RTC)
mode, provides time-of-day and event time stamping
capabilities. Key operational features of the RTC are:
Operation from 32 KHz LP oscillator
8-bit presc ale r
Low power
Real-Time Clock Interrupts
These Operating modes are determined by
setting the appropriate bit(s) in the T1CON
Control register
9.5.1 RTC OSCILLATOR OPERATION
When the TON = 1, TCS = 1 and TGATE = 0, t he t im er
increme nt s on the risin g e dge of the 32 k Hz LP os c ill a-
tor output signal, up to the value specified in the period
register, and is then reset to 0.
The TSYNC bit must be asserted to a logic 0
(Asynchronous mode) for correct operation.
Enabling LPOSCEN (OSCCON<1>) will disable the
normal Timer and Counter modes and enable a timer
carry-out wake-up event.
When the CPU en ters SLEEP o r IDLE m ode , the timer
will continue to increment, provided the external clock
is active and the control bits have not been changed.
The TSIDL bit is excluded from the control of the timer
module for this mode.
9.5.2 RTC INTERRUPTS
When an interrupt event occurs, the respective inter-
rupt flag, T1 IF, is asserted an d an inte rrupt wi ll be ge n-
erated, if enabled. The T1IF bit must be cleared in
software. The respective Timer interrupt flag, T1IF, is
located in the IFS0 status register in the Interrupt
Controller.
Enabling an interrupt is accomplished via the respec-
tive time r interrupt ena ble bit, T1IE. Th e T imer interrupt
enable bit is located in the IEC0 control register in the
Interrupt Controller.
2002 Microchip Technology Inc.
Advance Inf ormat ion
DS70082A-page 69
dsPIC30F
TABLE 9-1: TIMER1 REGISTER MAP
SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RESET State
TMR1 0100 Tim er 1 Regi ste r uuuu uuuu uuuu uuuu
PR1 0102 Period Regis ter 1 1111 1111 1111 1111
T1CON 0104 TON TSIDL TGATE TCKPS1 TCKPS0 TSYNC TCS 0000 0000 0000 0000
Legend: u = uninitialized bit
dsPIC30F
DS70082A-page 70 Advance Information 2002 Microchip Technology Inc.
NOTES:
2002 Microchip Technology Inc. Advance Information DS70082A-page 71
dsPIC30F
10.0 TIMER2/3 MODULE
This section describes the 32-bit General Purpose
(GP) Timer module (Timer2/3) and associated Opera-
tional modes. Figure 10-1 depicts the simplified block
diagram of the 32-bit Timer2/3 Module. Figure 10-2
and Figure 10-3 show Timer2/3 configured as two
independent 16-bit timers, Timer2 and Timer3,
respectively.
The Timer2/3 module is a 32-bit timer (which can be
configu red as two 1 6-bit ti mers) wi th sel ect able o per at-
ing modes. These timers are utilized by other
peripheral modules such as:
Input Capture
Output Compare/Simple PWM
The following sections provide a detailed description,
including setup and control registers, along with asso-
ciated bloc k dia grams for t he O peratio nal m odes of th e
timers.
The 32-bit timer has the following modes:
Two independent 16-bit timers (Timer2 and
Timer3) with all 16-bit Operating modes (except
Asynchronous Counter mode)
Single 32-bit Timer operation
Single 32-bit Synchronous Counter
Further, the following operational characteristics are
supported:
ADC Event Trigger
Timer Gate Operation
Selectable Prescaler Settings
Timer Operation during IDLE and SLEEP modes
Interrupt on a 32-bit Period Register Match
These Operating modes are determined by setting the
appropriate bit(s) in the 16-bit T2CON and T3CON
SFRs.
For 32-bit timer/counter operation, Timer2 is the LS
Word and Timer3 is the MS Word of the 32-bit timer.
16-bit Mode: In the 16-bit mode, Timer2 and Timer3
can be configured as two independent 16-bit timers.
Each time r can be set up in either 16-b it T imer mod e or
16-bit Synchronous Counter mode. See the Timer1
section for details on these two Operating modes.
The only functional difference between Timer2 and
Timer3 is that Timer2 provides synchronization of the
clock prescal er output. This is usefu l for high frequenc y
external clock inputs.
32-bit T imer Mode: In t he 32-bi t T imer m ode, the timer
increments on every instruction cycle up to a match
value, pre loade d into the combi ned 32-bi t period regis-
ter PR3/PR2, then resets to 0 and continues to count.
For synchronous 32-bit reads of the Timer2/Timer3
pair, reading the LS word (TMR2 register) will cause
the MS word to be read and latched into a 16-bit
holding register, termed TMR3HLD.
For synchronous 32-bit writes, the holding register
(TMR3HLD) must first be written to. When followed by
a write to the TMR2 re gister, the contents of TMR3H LD
will be transferred and latched into the MSB of the
32-bit timer (TMR3).
32-bit Synchronous Counter Mode: In the 32-bit
Synchronous Counter mode, the timer increments on
the rising edge of the applied external clock signal,
which is synchronized with the internal phase clocks.
The timer counts up to a match value preloaded in the
combined 32-bit period register PR3/PR2, then resets
to 0 and continues.
When the timer is configured for the Synchronous
Counter mode of operation and the CPU goes into the
IDLE mode, the timer will s top incrementing, un less the
TSIDL (T2CON<13>) bit = 0. If TSIDL = 1, the timer
module logic will resume the incrementing sequence
upon termination of the CPU IDLE mode.
Note: For 32-bit timer operation, T3CON control
bits are ignored. Only T2CON control bits
are used for setup and control. Timer 2
clock and gate inputs are utilized for the
32-bit timer module, but an interrupt is gen-
erated with the Timer3 interrupt flag (T3IF)
and the interrupt is enabled with the
Timer3 interrupt enable bit (T3IE).
dsPIC30F
DS70082A-page 72 Advance Information 2002 Microchip Technology Inc.
FIGURE 10-1: 32-BIT TIMER 2/3 BLOCK DIAGRAM
TMR3 TMR2
T3IF
Equal Comparator x 32
PR3 PR2
RESET
LSB
MSB
Event Flag
Note 1: Timer c onfiguration bit T32, T2CON(<3>) m ust be set to 1 for a 32-bit timer/counter operation. All control
bits are respective to the T2CON register.
Data Bus<15:0>
TMR3HLD
Read TMR2
Write TMR2 16
16
16
Q
QD
CK
TGATE(T2CON<6>)
(T2CON<6>)
TGATE
0
1
TON TCKPS<1:0>
Prescaler
1, 8, 64, 256
2
TCY
TCS
1 X
0 1
TGATE
0 0
Gate
T2CK
Sync
ADC Event Trigger
Sync
2002 Microchip Technology Inc. Advance Information DS70082A-page 73
dsPIC30F
FIGURE 10-2: 16-BIT TIMER 2 BLOCK DIAGRAM
FIGURE 10-3: 16-BIT TIMER 3 BLOCK DIAGRAM
TON
Sync
PR2
T2IF
Equal Comparator x 16
TMR2
RESET
Event Flag
Q
QD
CK
TGATE
TCKPS<1:0>
Prescaler
1, 8, 64, 256
2
TGATE
TCY
1
0
TCS
1 X
0 1
TGATE
0 0
Gate
T2CK
Sync
TON
PR3
T3IF
Equal Comparator x 16
TMR3
RESET
Event Fl ag
Q
QD
CK
TGATE
TCKPS<1:0>
Prescaler
1, 8, 64, 256
2
TGATE
TCY
1
0
TCS
1 X
0 1
TGATE
0 0
T3CK
ADC Event Trigger
Sync
dsPIC30F
DS70082A-page 74 Advance Information 2002 Microchip Technology Inc.
10.1 Timer Gate Operation
The 32-bi t timer can be pl aced in the Ga ted Ti me Accu-
mulation mode. This mode allows the internal TCY to
increm ent the respec tive timer when the gate input si g-
nal (T2CK pin) is asserted high. Control bit TGATE
(T2CO N<6>) mus t be set to en able this mode . When in
this mode, Timer2 is the originating clock source. The
TGATE setting is ign ored for T imer3. The tim er must be
enabled (TON = 1) and the timer clock source set to
internal (TCS = 0).
The falling edge of the external signal terminates the
count ope rati on, bu t does not res et the time r. The user
must reset the timer in order to start counting from zero.
10.2 ADC Event Trigger
When a matc h occurs betwe en the 32-bit timer (TM R3/
TMR2) and the 32-bit combined period register (PR3/
PR2), a special ADC trigger event signal is generated
by Timer3.
10.3 Timer Prescaler
The in put cloc k (FOSC/4 or external clock) to the timer
has a prescale option of 1:1, 1:8, 1:64, and 1:256
selected by control bits TCKPS<1:0> (T2CON<5:4>
and T3CON<5:4>). For the 32-bit timer operation, the
origina ting clock so urce is Timer2. The prescaler oper-
ation for Timer3 is not applicable in this mode. The
prescaler counter is cleared when any of the following
occurs:
a write to the TMR2/TMR3 register
a write to the T2CON/T3CON register
device RESET such as POR and BOR
However, if the timer is disabled (TON = 0), then the
Timer 2 prescaler cannot be reset, since the prescaler
clock is halted.
TMR2/TMR3 is not cleared when T2CON/T3CON is
written.
10.4 Timer Operation During SLEEP
Mode
During CPU SLEEP mode, the timer will not operate,
because the internal clocks are disabled.
10.5 Timer Interrupt
The 32-bit timer module can generate an interrupt on
period ma tch, or on the fa lling edge of the externa l gate
signal. When the 32-bit timer count matches the
respective 32-bit period register, or the falling edge of
the external gate signal is detected, the T3IF bit
(IFS0<7>) is asserted and an interrupt will be gener-
ated if enabled. In this mode, the T3IF interrupt flag is
used as the source of the interrupt. The T3IF bit must
be cleared in sof tw are.
Enabling an interrupt is accomplished via the
respective timer interrupt enable bit, T3IE (IEC0<7>).
2002 Microchip Technology Inc.
Advance Inf ormat ion
DS70082A-page 75
dsPIC30F
TABLE 10-1: T IMER2/3 REGISTER MAP
SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RESET State
TMR2 0106 Timer2 Regist er uuuu uuuu uuuu uuuu
TMR3HLD 0108 Timer3 Holding Register (For 32-bit timer operations only) uuuu uuuu uuuu uuuu
TMR3 010A Timer3 Regist er uuuu uuuu uuuu uuuu
PR2 010C Period Register 2 1111 1111 1111 1111
PR3 010E Period Register 3 1111 1111 1111 1111
T2CON 0110 TON TSIDL TGATE TCKPS1 TCKPS0 T32 TCS 0000 0000 0000 0000
T3CON 0112 TON TSIDL TGATE TCKPS1 TCKPS0 TCS 0000 0000 0000 0000
Legend: u = uninitialized bit
dsPIC30F
DS70082A-page 76 Advance Information 2002 Microchip Technology Inc.
NOTES:
2002 Microchip Technology Inc. Advance Information DS70082A-page 77
dsPIC30F
11.0 TIMER4/5 MODULE
This section describes the second 32-bit General Pur-
pose (GP) Timer module (Timer4/5) and associated
Operational modes. Figure 11-1 depicts the simplified
block diagram of the 32-bit Timer4/5 Module.
Figure 11-2 and Figure 11-3 show Timer4/5 confi gure d
as two independent 16-bit timers, Timer4 and Timer5,
respectively.
The Timer4/5 module is similar in operation to the
Timer 2/3 module. However, there are some differ-
ences, which are listed below:
The Timer4/5 module does not support the ADC
Event Trigger feature
Timer4/5 can not be utilized by other peripheral
modules such as Input Capture and Output
Compare
The Operating modes of the Timer4/5 module are
determined by setting the appropriate bit(s) in the
16-bit T4CON and T5CON SFRs.
For 32-bit timer/counter operation, Timer4 is the LS
Word and Timer5 is the MS Word of the 32-bit timer.
FIGURE 11-1: 32-BIT TIMER4/5 BLOC K DIAGRAM
Note: For 32-bit timer operation, T5CON control
bits are ignored. Only T4CON control bits
are used for setup and control. Timer4
clock and gate inputs are utilized for the
32-bit timer module, but an interrupt is gen-
erated with t he Timer5 interrup t flag (T5IF)
and the interrupt is enabled with the
Timer5 interrupt enable bit (T5IE).
TMR5 TMR4
T5IF
Equal Comparator x 32
PR5 PR4
RESET
LSB
MSB
Event Flag
Note 1: Timer con figuration bit T32, T4CON(<3>) must be s et to 1 for a 32 -bit timer/counter operation. Al l control
bits are respective to the T4CON register.
Data Bus<15:0>
TMR5HLD
Read TMR4
Write TMR4 16
16
16
Q
QD
CK
TGATE(T4CON<6>)
(T4CON<6>)
TGATE
0
1
TON TCKPS<1:0>
Prescaler
1, 8, 64, 256
2
TCY
TCS
1 X
0 1
TGATE
0 0
Gate
T4CK
Sync
Sync
dsPIC30F
DS70082A-page 78 Advance Information 2002 Microchip Technology Inc.
FIGURE 11-2: 16-BIT TIMER4 BLOCK DIAGRAM
FIGURE 11-3: 16-BIT TIMER5 BLOCK DIAGRAM
TON
Sync
PR4
T4IF
Equal Comparator x 16
TMR4
RESET
Event Flag
Q
QD
CK
TGATE
TCKPS<1:0>
Prescaler
1, 8, 64, 256
2
TGATE
TCY
1
0
TCS
1 X
0 1
TGATE
0 0
Gate
T4CK
Sync
TON
PR5
T5IF
Equal Comparator x 16
TMR5
RESET
Event Flag
Q
QD
CK
TGATE
TCKPS<1:0>
Prescaler
1, 8, 64, 256
2
TGATE
TCY
1
0
TCS
1 X
0 1
TGATE
0 0
T5CK
ADC Event Trigger
Sync
2002 Microchip Technology Inc.
Advance Inf ormat ion
DS70082A-page 79
dsPIC30F
TABLE 11-1: TIMER4/5 REGISTER MAP
SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RESET State
TMR4 0114 Timer 4 Register uuuu uuuu uuuu uuuu
TMR5HLD 0116 Timer 5 Holding Register (For 32-bit operations only) uuuu uuuu uuuu uuuu
TMR5 0118 Timer 5 Register uuuu uuuu uuuu uuuu
PR4 011A Period Regis ter 4 1111 1111 1111 1111
PR5 011C Period Register 5 1111 1111 1111 1111
T4CON 011E TON TSIDL TGATE TCKPS1 TCKPS0 T45 TCS 0000 0000 0000 0000
T5CON 0120 TON TSIDL TGATE TCKPS1 TCKPS0 TCS 0000 0000 0000 0000
Legend: u = uninitialized bit
dsPIC30F
DS70082A-page 80 Advance Information 2002 Microchip Technology Inc.
NOTES:
2002 Microchip Technology Inc. Advance Information DS70082A-page 81
dsPIC30F
12.0 INPUT CAPTURE MODULE
This section describes the Input Capture module and
associated Operational modes. The features provided
by this module are useful in applications requiring Fre-
quency (Period) and Pulse measurement. Figure 12-1
depicts a block diagram of the Input Capture Module.
Input capture is useful for such modes as:
Frequency/Period/Pulse Measurements
Additional sources of External Interrupts
The key operational features of the Input Capture
module are:
Simple Capture Event mode
Timer2 and Timer3 mode selection
Interrupt on input capture event
These operating modes are determined by setting the
appropriate bits in the ICxCON register (where x =
1,2,...,N). The dsPIC devices contain up to 8 capture
channels, i.e., the maximum value of N is 8.
FIGURE 12-1: INPUT CAPTURE MODE BLOCK DIAGRAM
12.1 Simple Capture Event Mode
The simple capture events in the dsPIC30F product
family are:
Capture every falling edge
Capture every rising edge
Capture every 4th rising edge
Capture every 16th rising edge
Capture every rising and falling edge
These simple Input Capture modes are configured by
setting the appropriate bits ICM<2:0> (ICxCON<2:0>).
12.1.1 CAPTURE PRESCALER
There are four input capture prescaler settings, speci-
fied by bits ICM<2:0> (ICxCON<2:0>). Whenever the
capture c hanne l is turn ed of f, the pre scaler co unter w ill
be cleared. In addition, any RESET will clear the
prescaler counter.
ICxBUF
Prescaler
ICx
ICM<2:0>
Mode Select
3
Note 1: Where x is shown, reference is made to the registers or bits associated to the respective input capture
channels 1 through N.
10
Set Flag
Pin
ICxIF
ICTMR
T2_CNT T3_CNT
Edge
Detection
Logic
Clock
Synchronizer
1, 4, 16
From GP Timer Module
16 16
FIFO
R/W
Logic
ICI<1:0>
ICBNE, ICOV
ICxCON Interrupt
Logic
Set Flag
ICxIF
Data Bus
dsPIC30F
DS70082A-page 82 Advance Information 2002 Microchip Technology Inc.
12.1.2 CAPTURE BUFFER OPERATION
Each capture channel has an associated FIFO buffer,
which is four 16-bit words deep. There are two status
flags, which provide status on the FIFO buffer:
ICBFNE - Input Capture Buffer Not Empty
ICOV - Input Capture Overflow
The ICBFNE will be set on the fir st input ca ptu r e event
and remain set until all capture events have been read
from the FIF O. As each word is read fro m the FIFO, th e
remaining words are advanced by one position within
the buffer.
In the event that the FIFO is full with four capture
events and a fifth capture event occurs prior to a read
of the FIFO, an overflow condition will occur and the
ICOV bit will be set to a logic 1. The fifth ca ptu re eve nt
is lost and is not stored in the FIFO. No additional
events will be captured till all four events have been
read from the buffer.
If a FIFO read is performed after the last read and no
new capture event has been received, the read will
yield indeterminate results.
12.1.3 TIMER2 AND TIMER3 SELECTION
MODE
The inp ut capture mod ule cons ist s of up to 8 input cap-
ture chann els. Each channel can select between one of
two timers for the time-base, Timer2 or Timer3.
Selection of the timer resource is accomplished
through SFR bit ICTMR (ICxCON<7>). Timer3 is the
default timer resource available for the input capture
module.
12.1.4 HALL SENSOR MODE
When the input capture module is set for capture on
every ed ge, rising a nd falli ng, ICM <2:0> = 001, the fol-
lowing operations are performed by the input capture
logic:
The input capture interrupt flag is set on every
edge, rising and falling.
The interrupt on Capture mode setting bits,
ICI<1:0>, is ignored, sin c e every capture
generates an interrupt.
A capture overflow condition is not generated in
this mode.
12.2 Input Capture Operation During
SLEEP and IDLE Modes
An input capture event will generate a device wake-up
or interrupt, if enabled, if the device is in CPU IDLE or
SLEEP mode.
Independent of the timer being enabled, the input
capture module will wake-up from the CPU SLEEP
or IDLE mode when a capture event occurs, if
ICM<2:0> = 111 and the interrupt enable bit is
asserted. The same wake-up can generate an inter-
rupt, if the conditions for processing the interrupt have
been satisfied. The wake-up feature is useful as a
method of adding extra external pin interrupts.
12.2.1 INPUT CAPTURE IN CPU SLEEP
MODE
CPU SLEEP mode allows input capture module oper-
ation with reduced functionality. In the CPU SLEEP
mode, the ICI<1:0> bits are not applicable, and the
input capture module can only function as an external
interr upt so urce .
The capture module must be configured for interrupt
only on the rising edge (ICM<2:0> = 111), in order for
the input capture module to be used while the device
is in SLEEP mode. The pres cale settin gs of 4 :1 or 16 :1
are not applicable in this mode.
12.2.2 INPUT CAPTURE IN CPU IDLE
MODE
CPU IDLE mode allows input capture module operation
with full functionality. In the CPU IDLE mode, the inter-
rupt mode selected by the ICI<1:0> bits are applicable,
as well as the 4:1 and 16:1 capture prescale settings,
which are defined by control bits ICM<2:0>. This mode
requires the selected timer to be enabled. Moreover, the
ICSIDL bit must be asserted to a logic 0.
If the input capture module is defined as
ICM<2: 0> = 111 in CPU IDLE mode, the input capture
pin will serve only as an external interrupt pin.
12.3 Input Capture Interrupts
The inpu t captur e channe ls have the a bility to generate
an interrupt, based upon the selected number of cap-
ture even t s . The selecti on num be r is se t b y c ont rol bit s
ICI<1:0> (ICxCON<6:5>).
Each chan nel provide s an interrupt flag (ICxI F) bit. The
respective capture channel interrupt flag is located in
the corresponding IFSx Status register.
Enabling an interrupt is accomplished via the respec-
tive capture channel interrupt enable (ICxIE) bit. The
capture interrupt enable bit is located in the
corresponding IEC Control register.
2002 Microchip Technology Inc.
Advance Inf ormat ion
DS70082A-page 83
dsPIC30F
TABLE 12-1: INPUT CAPTURE REGISTER MAP
SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RESET State
IC1BUF 0140 Input 1 Capture Register uuuu uuuu uuuu uuuu
IC1CON 0142 ICSIDL ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000
IC2BUF 0144 Input 2 Capture Register uuuu uuuu uuuu uuuu
IC2CON 0146 ICSIDL ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000
IC3BUF 0148 Input 3 Capture Register uuuu uuuu uuuu uuuu
IC3CON 014A ICSIDL ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000
IC4BUF 014C Input 4 Capture Register uuuu uuuu uuuu uuuu
IC4CON 014E ICSIDL ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000
IC5BUF 0150 Input 5 Capture Register uuuu uuuu uuuu uuuu
IC5CON 0152 ICSIDL ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000
IC6BUF 0154 Input 6 Capture Register uuuu uuuu uuuu uuuu
IC6CON 0156 ICSIDL ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000
IC7BUF 0158 Input 7 Capture Register uuuu uuuu uuuu uuuu
IC7CON 015A ICSIDL ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000
IC8BUF 015C Input 8 Capture Register uuuu uuuu uuuu uuuu
IC8CON 015E ICSIDL ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000
Legend: u = uninitialized bit
dsPIC30F
DS70082A-page 84 Advance Information 2002 Microchip Technology Inc.
NOTES:
2002 Microchip Technology Inc. Advance Information DS70082A-page 85
dsPIC30F
13.0 OUTPUT COMPARE MODULE
This section describes the Output Compare module
and associated Operational modes. The features pro-
vided by this module are useful in applications requiring
Oper ati ona l mod es such as:
Generation of Variable Width Output Pulses
Power Factor Correction
Figure 13-1 depicts a block diagram of the Output
Compare module.
The key operational features of the Output Compare
module include:
Timer2 and Timer3 Selection mode
Simple Output Compare Match mode
Dual Output Compare Match mode
Simple PWM mode
Output Compare during SLEEP and IDLE modes
Interrupt on Output Compare/PWM Event
These operating modes are determined by setting the
appropria te b its in the 1 6-b it O CxC ON SFR (w he re x =
1,2,3,...,N). The dsPIC devices contain up to 8
compare channels, i.e., the maximum value of N is 8.
OCxRS and OCxR in the figure represent the dual
compare registers. In the Dual Compare mode, the
OCxR register is used for the f irst comp are and O CxRS
is used for the second compare.
FIGURE 13-1: OUTPUT COMPARE MODE BLOCK DIAGRAM
OCxR
Comparator
Output
Logic QS
R
OCM<2:0>
Output Enable
OCx
Set Flag bi t
OCxIF
OCxRS
Mode Select
3
Note: Where x is shown, reference is made to the registers associated with the respective output compare channels 1
through N.
OCFA
OCTSEL 01
T2P2_MATCH
TMR2<15:0 TMR3<15:0> T3P3_MATCH
From GP Timer Module
(for x = 1, 2, 3 or 4)
or OCFB
(for x = 5, 6, 7 or 8)
01
dsPIC30F
DS70082A-page 86 Advance Information 2002 Microchip Technology Inc.
13.1 T imer2 and T imer3 Selection Mode
Each output compare channel can select between one
of two 16-bit timers, Timer2 or Timer3.
The selection of t he timers is controlled by the OCTSEL
bit (OCxCON<3> ). T im er2 is the de fault ti mer reso urce
for the Output Compare module.
13.2 Simple Output Compare Match
Mode
When control bits OCM<2:0> (OCxCON<2:0>) = 001,
010 or 011, the selected output compare channel is
configured for one of three simple Output Compare
Match modes:
Compare forces I/O pin low
Compare forces I/O pin high
Compare toggles I/O pin
The OCxR reg is ter i s us ed in th es e m ode s. Th e O C xR
register is loaded with a value and is compared to the
selected incrementing timer count. When a compare
occurs, o ne of these Compare Match modes occurs. If
the counter resets to zero before reaching the value in
OCxR, the state of the OCx pin remains unchanged.
13.3 Dual Output Compare Match Mode
When control bits OCM<2:0> (OCxCON<2:0>) = 100
or 101, the selec ted outp ut compare channel is co nfig-
ured for one of two Dual Output Compare modes,
which ar e:
Single Output Pulse mode
Continuous Output Pulse mode
13.3.1 SINGLE PULSE MODE
For the use r to confi gure the modul e for the ge ner ation
of a single output pulse, the following steps are
required (assuming timer is off):
Determine instruction cycle time TCY.
Calcu la te d es ired pulse widt h v al ue bas ed on TCY.
Calcu late ti me to s tart pulse from ti mer st a rt valu e
of 0x0000.
Write pulse width start and stop times into OCxR
and OCxRS compare registers (x denotes
channel 1, 2, ...,N).
Set timer period register to value equal to, or
greater than, value in OCxRS compare register.
Set OCM<2:0> = 100.
Enable timer, TON (TxCON<15>) = 1.
To initiate another single pulse, issue another write to
set OCM<2:0> = 100.
13.3.2 CONTINUOUS PULSE MODE
For the use r to confi gure the modul e for the ge neratio n
of a continuous stream of output pulses, the following
steps are required:
Determine instruction cycle time TCY.
Calculate desired pulse value based on TCY.
Calculat e timer to st art pulse wid th from tim er start
value of 0x0000.
Write pulse width start and stop times into OCxR
and OCxRS (x denotes channel 1, 2, ...,N)
compare registers, respectively.
Set timer period register to value equal to, or
greater than, value in OCxRS compare register.
Set OCM<2:0> = 101.
Enable timer, TON (TxCON<15>) = 1.
13.4 Simple PWM Mode
When control bits OCM<2:0> (OCxCON<2:0>) = 110
or 111, the selec ted outp ut compare channel is co nfig-
ured for th e PWM mode of opera tion. When co nfigured
for the PWM mode of operation, OCxR is the Main latch
(read only) and OCxRS is the Secondary latch. This
enables glitchless PWM transitions.
The user must perform the following steps in order to
configure the output compare module for PWM
operation:
1. Set the PWM period by writing to the appropria te
period register.
2. Set the PWM duty c ycle by wr iting to t he OCxRS
register.
3. Configure the output compare module for PWM
operation.
4. Set the TMRx prescale value and enable the
Timer, TON (TxCON<15>) = 1.
13.4.1 INPUT PIN FAULT PROTECTION
FOR PWM
When control bits OCM<2:0> (OCxCON<2:0>) = 111,
the selected output compare channel is again config-
ured for the PWM mode of operation, with the addi-
tional feature of input fault protection. While in this
mode, if a logic 0 is detected on the OCFA/B pin, the
respective PWM output pin is placed in the high imped-
ance input state. The OCFLT bit (OCxCON<4>) indi-
cates whether a FAULT condition has occurred. This
state will be maintained until:
The external FAULT condition has been removed
and
The PWM mode is re-enabled by writing to the
appropriate control bits.
2002 Microchip Technology Inc. Advance Information DS70082A-page 87
dsPIC30F
13.4.2 PWM PERIOD
The PWM peri od is spe cified by writing to the PRx reg-
ister. The PWM period can be calculated using the
following formula.
EQUATION 13-1:
PWM frequency is defined as 1 / [PWM period].
When the selected TMRx is equal to its respective
period reg ister, PRx, th e followi ng four e vent s occ ur on
the next i ncrement cycle:
TMRx is cleare d.
The OCx pin is set.
- Exception 1: If PWM duty cycle is 0x0000,
the OCx pin will r emain low.
- Exception 2: If d uty cycle is great er than PRx,
the pin will remain high.
The PWM duty cycle is latched from OCxRS into
OCxR.
The corresponding timer interrupt flag is set.
See Figure 13-2 for key PWM period comparisons.
Timer3 is referred to in the figure for clarity.
FIGURE 13-2: PWM OUTPUT TIMING
13.5 Output Comp are Operation During
CPU SLEEP Mode
When the CPU enters the SLEEP mode, all internal
clocks are stopped. Therefore, when the CPU enters
the SLEEP state, the output compare channel will
drive the pin to the active s t ate that was o bs erv ed pri or
to entering the CP U SLEEP stat e.
For example, if the pin was high when the CPU
entered the SLEEP state, the pin will remain high.
Likewis e, if the pin wa s low when the CPU entered the
SLEEP state, the pin will remain low. In either case,
the output compare module will resume operation
when the device wakes up.
13.6 Output Comp are Operation During
CPU IDLE Mode
When the CPU enters the IDLE mode, the output
compare module can operate with full functionality.
The output compare channel will operate during the
CPU IDLE mode if the OCSIDL bit (OCxCON<13>) is
at logic 0 and the selected time-base (Timer2 or
Timer3) is enabled and the TSIDL bit of the selected
timer is set to logic 0.
The selected time-base for the output compare can be
configu r ed for:
Internal Ins truc tio n Cycl e
External Syn chr ono us
13.7 Outp u t Compare Interrupts
The outpu t comp are channels have the abil ity to gener-
ate an interrupt on a compare match, for whichever
Match mode has been selected.
For all m odes exc ept the PWM mode, when a comp are
event oc curs, the respec tive interrup t flag (OCxIF) bit i s
asserte d an d an int errup t wil l be ge nera ted, if enable d.
The OCxIF bit is located in the corresponding IFS
Status register, and must be cleared in software. The
interrupt is enabled via the respective compare inter-
rupt enable (OCxIE) bit, located in the corresponding
IEC Control register.
For the PWM mode, when a n event occurs, the respec-
tive timer interrupt flag (T2IF or T3IF) is asserted and
an interrupt will be generated, if enabled. The IF bit is
located in the IFS0 S tatus register, and must be cleared
in software. The interrupt is enabled via the respective
timer interrupt enable bit (T2IE or T3IE), located in the
IEC0 Control register. The output compare interrupt
flag is never set during the PWM mode of operation.
PWM period = [(PRx) + 1] • 4 • TOSC
(TMRx prescale value)
Period
Duty Cycle
TMR3 = Duty Cycle (OCxR) TMR3 = Duty Cycle (OCxR)
TMR3 = PR3
T3IF = 1
(Interrupt Flag)
OCxR = OCxRS
TMR3 = PR3
(Interrupt Flag)
OCxR = OCxRS
T3IF = 1
dsPIC30F
DS70082A-page 88 Advance Information
2002 Microchip Technology Inc.
TABLE 13-1: OUTPUT COMPARE REGISTER MAP
SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RESET State
OC1RS 0180 Output Compare 1 Secondary Register 0000 0000 0000 0000
OC1R 0182 Output Compare 1 Main Register 0000 0000 0000 0000
OC1CON 0184 OCSIDL OCFLT OCTSEL OCM<2:0> 0000 0000 0000 0000
OC2RS 0186 Output Compare 2 Secondary Register 0000 0000 0000 0000
OC2R 0188 Output Compare 2 Main Register 0000 0000 0000 0000
OC2CON 018A OCSIDL OCFLT OCTSE OCM<2:0> 0000 0000 0000 0000
OC3RS 018C Output Compare 3 Secondary Register 0000 0000 0000 0000
OC3R 018E Output Compare 3 Main Register 0000 0000 0000 0000
OC3CON 0190 OCSIDL OCFLT OCTSEL OCM<2:0> 0000 0000 0000 0000
OC4RS 0192 Output Compare 4 Secondary Register 0000 0000 0000 0000
OC4R 0194 Output Compare 4 Main Register 0000 0000 0000 0000
OC4CON 0196 OCSIDL OCFLT OCTSEL OCM<2:0> 0000 0000 0000 0000
OC5RS 0198 Output Compare 5 Secondary Register 0000 0000 0000 0000
OC5R 019A Output Compare 5 Main Register 0000 0000 0000 0000
OC5CON 019C OCSIDL OCFLT OCTSEL OCM<2:0> 0000 0000 0000 0000
OC6RS 019E Output Compare 6 Secondary Register 0000 0000 0000 0000
OC6R 01A0 Output Compare 6 Main Register 0000 0000 0000 0000
OC6CON 01A2 OCSIDL OCFLT OCTSEL OCM<2:0> 0000 0000 0000 0000
OC7RS 01A4 Output Compare 7 Secondary Register 0000 0000 0000 0000
OC7R 01A6 Output Compare 7 Main Register 0000 0000 0000 0000
OC7CON 01A8 OCSIDL OCFLT OCTSEL OCM<2:0> 0000 0000 0000 0000
OC8RS 01AA Output Compare 8 Secondary Register 0000 0000 0000 0000
OC8R 01AC Output Compare 8 Main Register 0000 0000 0000 0000
OC8CON 01AE OCSIDL OCFLT OCTSEL OCM<2:0> 0000 0000 0000 0000
Legend: u = uninitialized bit
2002 Microchip Technology Inc. Advance Information DS70082A-page 89
dsPIC30F
14.0 QUADRATURE ENCODER
INTERFACE (QEI) MODULE
This section describes the Quadrature Encoder Inter-
face (Q EI) m od ule and assoc iat ed Op erational modes.
The QEI module provides the interface to incremental
encoders for obtaining motor positioning data. Incre-
mental encoders are very useful in motor control
applications.
The Quadrature Encoder Interface (QEI) is a key fea-
ture require ment for several motor control applic ations,
such as Switched Reluctance (SR) and AC Induction
Motor (ACIM). The operatio nal features of the QEI are,
but not limited to:
Three input channels for two phase signals and
index pulse
16-bit up/down position counter
Count di rection s tatus
Position Measurement (x2 and x4) mode
Programmable digital noise filters on inputs
Alternate 16-bit Timer/Counter mode
Quadrature Encoder Interface interrupts
These Operating modes are determined by setting the
appropriate bits QEIM<2:0> (QEICON<10:8>).
Figure 14-1 depicts the Quadrature Encoder Interface
block dia gram .
FIGURE 14-1: QUADRATURE ENCODER INTERFACE BLOCK DIAGRAM
16-bit Up/Down Counter
Comparator/
Max Count Register
Quadrature
Programmable
Digital Filter
QEA
Programmable
Digital Filter
INDX
0
1Up/Down
Existing Pin Logic
UPDN
3
Encoder
Programmable
Digital Filter
QEB
Interface Logic
QEIM<2:0>
Mode Select
3
(POSCNT)
(MAXCNT)
PCDOUT
QEIIF
Event
Flag
RESET
Equal
2
TCY
1
0
TQCS TQCKPS<1:0>
2
1, 8, 64, 256
Prescaler
Q
Q
D
CK
TQGATE
QEIM<2:0>
Synchronize
Det
1
0
SLEEP Input
0
1
UPDN_CNT
QEICON<11> Zero Detect
dsPIC30F
DS70082A-page 90 Advance Information 2002 Microchip Technology Inc.
14.1 Quadrature Encoder Interface
Logic
A typica l in cre me nt a l (a.k .a . optical) enc ode r has thre e
outputs: Phase A, Phase B, and an index pulse. These
signals are useful and often required in position and
speed control of ACIM and SR motors.
The two chann els, Phase A (QEA) and Phase B (QEB),
have a unique relationship. If Phase A leads Phase B,
then the direction (of the motor) is deemed positive or
forward. If Phase A lags Phase B, then the direction (of
the motor) is deemed negative or reverse.
A third channel, termed index pulse, occurs once per
revolution and is used as a reference to establish an
absolute position. The index pulse coincides with
Phase A and Phase B, both low.
14.2 16-bi t Up /Down Posit ion Counter
Mode
The 16-bit Up/Down Counter counts up or down on
ever y count pulse, w hich is generat ed by t he dif ference
of the Phase A and Phase B input signals. The counter
acts as an integrato r , wh ose cou nt value is proporti onal
to position. The direction of the count is determined by
the UPDN signal, which is generated by the
Quadrat ure Enc ode r Interfac e Log ic.
14.2.1 POSITION COUNTER ERROR
CHECKING
Position c oun t e rror checking in the Q EI i s p rov ide d for
and indic ated by the CNTERR bit (QEICO N<15>). The
error checking only applies when the position counter
is configured for RESET on the Index Pulse modes
(QEIM<2: 0> = 110 or 100). In these mo des, the con-
tents of t he POSCNT re giste r is comp ar ed wit h the va l-
ues (0xFFFF or MAXCNT depending on direction). If
these values are detected, an error condition is gener-
ated by setting the CNTERR bit and a QEI count error
interrupt is generated. The position counter continues
to count encoder edges after an error has been
detecte d. The POS CNT reg ister contin ues to coun t up/
down until a natural rollover/underflow. No interrupt is
generate d fo r th e natural roll ov er/u nde rflo w ev en t. Th e
CNTERR bit is a read/write bi t and reset in software by
the user.
14.2.2 POSITION COUNTER RESET
The position counter RESET enable bit, POSRES
(QEI<2>) c ontrols wheth er the position coun ter is reset
when the index pulse is detected. This bit is only
applicable when QEIM<2:0> = 100 or 110.
If the PO SRES bit is set to 1, then the positi on counter
is reset when the index pulse is detected. If the
POSRES bit is set to 0, then the position coun ter is not
reset when the index pulse is detected. The position
counter will continue counting up or down, and will be
reset on the rollover or underflow condition.
The interrupt is still generated on the detection of the
index pulse and not on the position counter overflow/
underflow.
14.2.3 COUNT DIRECTION STATUS
As mentioned in the previous section, the QEI logic
generates an UPDN signal, based upon the relation-
ship between Phase A and Phase B. In addition to the
output pin, the state of this int ernal UPDN sign al is sup-
plied to a SFR bit U PDN (QEICON< 11>) as a re ad only
bit. To place the state of this signal on an I/O pin, the
SFR bit PCDOUT (QEICON<6>) must be 1.
14.3 Position Measurement Mode
There are two Measurement modes which are sup-
ported and are termed x2 and x4. These modes are
selected by the Q E IM <2: 0> mo de select bits located i n
SFR QEICON<10:8>.
When control bits QEIM<2:0> = 100 or 101, the x2
Measurement mode is selected and the QEI logic only
looks at the Phase A input for the position counter
increment rate. Every rising and falling edge of the
Phase A s ignal ca uses the positio n counter to b e incre-
mented o r decr ement ed. The Ph ase B sig nal is still ut i-
lized for the determ in ati on of the cou nter di rec tio n, jus t
as in the x4 mode.
Within the x2 Measurement mode, there are two
variations of how the position counter is reset:
1. Position counter reset by detection of index
pulse, QEIM<2:0> = 100.
2. Position counter reset by match with MAXCNT,
QEIM<2:0> = 101.
When control bits QEIM<2:0> = 110 or 111, the x4
Measurement mode is selected and the QEI logic looks
at both edges of the Phase A and Phase B input sig-
nals. Every edge of both signals causes the position
counter to inc rem ent or decr em ent.
Within the x4 Measurement mode, there are two
variations of how the position counter is reset:
1. Position counter reset by detection of index
pulse, QEIM<2:0> = 110.
2. Position counter reset by match with MAXCNT,
QEIM<2:0> = 111.
The x4 Measurement mode provides for finer resolu-
tion data (more position counts) for determining motor
position.
2002 Microchip Technology Inc. Advance Information DS70082A-page 91
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14.4 Programmable Digital Noise
Filters
The digital noise filter section is responsible for reject-
ing noise on the incoming capture or quadrature sig-
nals. Schmitt Trigger inputs and a three-clock cycle
delay filter combine to reject low level noise and large,
short duration nois e s pik es tha t ty pic al ly occ ur i n n ois e
prone applications, such as a motor system.
The filter ensures that the filtered output signal is not
permitted to change until a stable value has been reg-
istered for three consecutive clock cycles.
QEA and QEB is programmed by bits QECK<2:0>
(DFLTCON<6:4> ) and is d erived fro m the base instruc-
tion cycle TCY. For the index channel the clock divide
frequency for the digital filter is programmed by bits
INDCK<2:0> (DFLTCON<2:0>), and is also derived
from the base instruction cycle TCY.
To enable the filter output for channels QEA and QEB,
the QEO UT bit must be 1. To enable th e filter out put for
the index channel, the IND OUT bit must be 1. The filter
network for all channels is disabled on POR and BOR
Reset.
14.5 Alter nate 16-bit Ti mer/Counter
When the QEI module is not configured for the QEI
mode QEIM<2:0> = 001, the module can be configured
for a sim ple 16-bit timer/c ounte r. The setup and co ntrol
for the auxiliary timer is accomplished through the
QEICON SFR register. This timer functions identical to
Timer1. The QEA pin is used as the timer clock input.
When configured as a timer, the POSCNT register
serves as the Timer Count Register and the MAXCNT
register serves as the Period Register. When a timer/
period register match occur, the QEI interrupt flag will
be asserted.
The only exception between the general purpose tim-
ers and this timer is the added feature of external
up_dow n inp ut se le ct. Wh en the UPDN pin is asserte d
high, the timer will increment up. When the UPDN pin
is asserted low, the timer will be decremented.
The UPDN control/status bit (QEICON<11>) can be
used to select the count direction state of the Timer reg-
ister. When UPDN = 1, the timer will count up. When
UPDN = 0, the timer will count down.
In addition, control bit UPDN_CNT (QEICON<0>)
determines whether the timer count direction state is
based o n the l ogi c st ate, writte n into the UP DN co ntrol/
status bit (QEICON<11>), or the QEB pin state. When
UPDN_CNT = 1, the timer count direction is controlled
from the QEB pin. Likewise, when UPDN_CNT = 0, the
timer count direction is controlled by the UPDN bit.
14.6 QEI Module Operation During CPU
SLEEP Mode
14.6.1 QEI OPERATION DURING CPU
SLEE P MOD E
The QEI module will be halted during the CPU SLEEP
mode.
14.6.2 TIMER OPERATION DURING CPU
SLEE P MOD E
During CPU SLEEP mode, the timer will not operate,
because the internal clocks are disabled.
14.7 QEI Module Operation During CPU
IDLE Mode
Since the QEI module can function as a quadrature
encoder interface, or as a 16-bit timer, the following
section describes operation of the module in both
modes.
14.7.1 QEI OPERATION DURING CPU IDLE
MODE
When the CPU is placed in the IDLE mode, the QEI
module will operate if the QEISIDL bit (QEICON<13>)
= 0. This bit defaults to a logic 0 upon executing POR
and BOR. For halting the QEI module during the CPU
IDLE mode, QEISIDL should be set to 1.
Note: Changing the Operational mode, i.e., from
QEI to T imer or vice versa, will not affect the
Timer/Position Count Register contents.
Note: This Timer does not support the External
Asynchronous Counter mode of operation.
If using an ex tern al c lo ck s ourc e, the cl oc k
will automatically be synchronized to the
internal instruction cycle.
dsPIC30F
DS70082A-page 92 Advance Information 2002 Microchip Technology Inc.
14.7.2 TIMER OPERATION DURING CPU
IDLE MODE
When the CPU is placed in the IDLE mode and the
QEI modu le is c onfig ured in t he 16-bi t T im er mod e, the
16-bit timer will operate if the QEISIDL bit
(QEICON<13 >) = 0. This bi t d efau lt s to a logic 0 upo n
execut ing POR a nd BO R. F or halting the ti mer module
during the CPU IDLE mode, QEISIDL should be set
to 1.
If the QEISIDL bit is cleared, the timer will function
normally, as if the CPU IDLE mode had not been
entered.
14.8 Quadrature Encoder Interface
Interrupts
The quadrature encoder interface has the ability to
generate an interrupt on occurrence of the following
events:
Interrupt on 16-bit up/down posit ion counter
rollover/underflow
Detection of qualified index pulse, or if CNTERR
bit is set
Timer period match event (overflow/underflow)
Gate accumulation event
The QEI interrupt flag bit, QEIIF, is asserted upon
occurrence of any of the above events. The QEIIF bit
must be cleared in software. QEIIF is located in the
IFS2 Status register.
Enabling an interrupt is accomplished via the respec-
tive enable bit, QEIIE. The QEIIE bit is located in the
IEC2 Control register.
2002 Microchip Technology Inc.
Advance Inf ormat ion
DS70082A-page 93
dsPIC30F
TABLE 14-1: QEI REGISTER MAP
SFR
Name Addr. Bit 15 Bit
14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RESET State
QEICON 0122 CNTERR QEISIDL INDX UPDN QEIM2 QEIM1 QEIM0 SWPAB PCDOUT TQGATE TQCKPS1 TQCKPS0 POSRES TQCS UPDN_CNT 0000 0000 0000 0000
DFLTCON 0124 QEOUT QECK2 QECK1 QECK0 INDOUT INDCK2 INDCK1 INDCK0 0000 0000 0000 0000
POSCNT 0126 Position Counter<15:0> 0000 0000 0000 0000
MAXCNT 0128 Maximun Count<15:0> 1111 1111 1111 1111
Legend: u = uninitialized bit
dsPIC30F
DS70082A-page 94 Advance Information 2002 Microchip Technology Inc.
NOTES:
2002 Microchip Technology Inc. Advance Information DS70082A-page 95
dsPIC30F
15.0 MOTOR CONTROL PWM
MODULE
This module simplifies the task of generating multiple,
synchronized Pulse Width Modulated (PWM) outputs.
In particular, the following power and motion control
applications are supported by the PWM module:
Three Phase AC I nduction Motor
Switched Reluctance (SR) Motor
Brushless DC (BLDC) Motor
Uninterruptible Power Supply (UPS)
The PWM module has the following features:
8 PWM I/O pins with 4 duty cycle generators
Up to 16-bit resolution
•‘On-the-Fly PWM frequency changes
Edge and Center Aligned Output modes
Single Pulse Generati on mode
Interrupt support for asymmetrical updates in
Center Alig ned mode
Output ove rrid e cont rol for Electric al ly
Commutative Motor (ECM) operation
•‘Special Event comparator for scheduling other
peripheral events
FAULT pins to optionally drive each of the PWM I/
O pins to a defined state
This module contains 4 duty cycle generators, num-
bered 1 through 4. The modul e has 8 PW M output p ins,
numbere d PWM1 H/PWM 1L throu gh PWM 4H/PWM4 L.
The eight I/O pins are grouped into High/Low num-
bered pairs, denoted by the suffix H or L, respectively.
For complementary loads, the low PWM pins are
always the complement of the corresponding High I/O
pin.
There are tw o v ers io ns of th e PWM module de pen din g
on the particular dsPIC30F device selected. There is
an 8-output module in some devices and a 6-output
PWM module in others.
Simplified block diagrams of the 8-output and 6-output
Motor Contro l PWM mod ules are sho wn in Figure 15-1
and Figure 15-2 , respectively.
TABLE 15-1: FEATURE SUMMARY: 6-OUTPUT PWM VS. 8-OUTPUT PWM
Feature 6-Output PWM Module 8-Output PWM Module
I/O Pins 6 8
PWM Generators 3 4
FAULT Input Pins 1 2
Dead-Time Generators 1 2
dsPIC30F
DS70082A-page 96 Advance Information 2002 Microchip Technology Inc.
FIGURE 15-1: 8-OUTPUT PWM MODULE BLOCK DIAGRAM
PDC4
PDC4 Buffer
PWMCON1
PTPER Buffer
PWMCON2
PTPER
PTMR
Comparator
Comparator
Channel 4 Dead-Time
Generator and
PTCON
SEVTCMP
Comparator Special Event Trigger
FLTBCON
OVDCON
PWM Enable and Mode SFRs
PWM Ma nua l
Control SFR
Channel 3 Dead-Time
Generator and
Channel 2 Dead-Time
Generator and
PWM Generator
#3
PWM Generator
#2
PWM Ge nera t or #4
SEVTDIR
PTDIR
DTCON1 Dead-Time Control SFRs
Special Event
Postscaler
PWM1L
PWM1H
PWM2L
PWM2H
PWM3L
PWM3H
PWM Generator
#1 Channel 1 De ad- Tim e
Generator and
Note: Details of PWM Gener ator #1, #2, and #3 not shown for clarity.
16-bit Data Bus
PWM4L
PWM4H
DTCON2
FLTACON FAULT Pin Control SFRs
PWM Time-Base
Output
Driver
Block
FLTB
FLTA
Overr ide Log i c
Overr ide Log i c
Overr ide Log i c
Override Logic
2002 Microchip Technology Inc. Advance Information DS70082A-page 97
dsPIC30F
FIGURE 15-2: 6-OUTPUT PWM BLOCK DIAGRAM
PDC3
PDC3 Buffer
PWMCON1
PT PE R Bu f f e r
PWMCON2
PTPER
PTMR
Comparator
Comparator
Channel 3 Dead-Time
Generator and
PTCON
SEVTCMP
Comparator Special Event Trigger
FLTACON
OVDCON
PWM Enable and Mode SFRs
FAULT Pin Control SFR
PWM Manual
Channel 2 Dead-Time
Generator and
Channel 1 Dead-Time
Generator and
PWM Generator
#2
PWM Generator
#1
PWM Generator #3
SEVTDIR
PTDIR
DTCON1 Dead-Time Control SFR
Special Event
Postscaler
FLTA
PWM1L
PWM1H
PWM2L
PWM2H
PWM3L
PWM3H
16-bit Data Bus
Override Logi c
Override Logic
Override Logic
Control SFR
PWM Time-Base
Output
Driver
Block
Note: Details of PWM Generator #1 and #2 not shown for clarity.
dsPIC30F
DS70082A-page 98 Advance Information 2002 Microchip Technology Inc.
The PWM module allows several modes of operation,
which are beneficial for specific power control applica-
tions. Each mode of operation is described
subsequently.
15.1 PWM Time-Bas e
The PWM time-base is provided by a 15-bit timer with
a prescaler and postscaler. The time-base is accessi-
ble via the PTMR SFR. PTMR<15> is a read only sta-
tus bit, PTDIR, that indicates the present count
direction of the PWM time-base. If PTDIR is cleared,
PTMR is counting upwards, whereas PTDIR set, indi-
cates that PTMR is counting downwards. The PWM
time-ba se is configured vi a the PTCON SFR . The time-
base is enabled/disabled by setting/clearing the PTEN
bit in the PTCON SFR. PTMR is not cleared when the
PTEN bit is cleared in software.
The PTPER SFR sets the counting period for PTMR.
The user must write a 15-bit value to PTPER<14:0>.
When the value in PTMR<14:0> matches the value in
PTPER<14:0>, the time-base will either reset to 0, or
reverse the count direction on the next occurring clock
cycle. The action taken depends on the Operating
mode of the time-base.
The PWM time-base can be configured for four
different modes of operation:
Free Running mode
Single Shot mode
Continuous Up/Down Count mode
Continuous Up/Down Count mode with interrupts
for double updates
These four modes are selected by the PTMOD<1:0>
bits in the PT CON SFR. The Up/Down Counting modes
support center aligned PWM generation. The Single
Shot mode allows the PWM module to support pulse
control of certain Electronically Commutative Motors
(ECMs).
The inte rrupt s ignals gene rated b y the PWM time- base
depend on the mode sele ction bit s (P TMOD<1:0>) and
the post sca ler bit s (P T OPS <3:0>) in the PT CON SFR.
15.1.1 FREE RUNNING MODE
In the Free Runn ing m od e, the PWM time-bas e co unts
upward s until the val ue in the time-base period regist er
(PTPER) is matched. The PTMR register is reset on the
following input clock edge and the time-base will con-
tinue to count upwards as long as the PTEN bit remains
set.
When the PWM time-base is in the Free Run ning mode
(PTMOD<1:0> = 00), an interrupt event is generated
each tim e a m atch wi th the P TPER reg ister o ccurs an d
the PTMR register is reset to zero. The postscaler
selection bits may be used in this mode of the timer to
reduce the frequency of the interrupt events.
15.1.2 SI NGLE SHO T MODE
In the Single Shot Countin g mod e, the PWM time-bas e
begins counting upwards when the PTEN bit is set.
When the value in the PTMR register matches the
P TPER reg is ter, the PTMR register w il l be res et o n th e
following input clock edge and the PTEN bit will be
cleared by the hardware to halt the time-base.
When the PWM time-base is in the Single Shot mode
(PTMOD<1:0> = 01), an interrupt event is generated
when a match with the PTPER register occurs, the
PTMR register is reset to zero on the following input
clock edge, and the P TEN bit is cleared. The postscaler
selection bits have no effect in this mode of the timer.
15.1.3 CONTINUOUS UP/DOWN
COUNTING MODES
In the Continuous Up/Down Counting modes, the PWM
time-bas e counts upwards u ntil the value i n the PTPER
register is matched. The timer will begin counting
downwards on the following input clock edge. The
PTDIR bit in the P TCON SFR is read only and indicates
the counting direction The PTDIR bit is set when the
timer counts downwards.
In the Up/Down Counting mode (PTMOD<1:0> = 10),
an interrupt event is generated each time the value of
the PTMR register becomes zero and the PWM time-
base begins to count upwards. The postscaler selec-
tion bit s may be used in this mode of the timer to reduce
the frequency of the interrupt events.
Note: If the period register is set to 0x0000, the
timer will stop counting, and the interrupt
and the special event trigger will not be
generated, even if the special event value
is also 0x0 000. The modul e will not upda te
the period register, if it is already at
0x0000; therefore, the user must disable
the module in order to update the period
register.
2002 Microchip Technology Inc. Advance Information DS70082A-page 99
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15.1.4 DOUBLE UPDATE MODE
In the Double Update mode (PTMOD<1:0> = 11), an
inter rupt event is ge nerated each time the P TM R regis-
ter is eq ual to zero, as well as ea ch time a pe riod match
occurs. The postscaler selection bits have no effect in
this mode of the timer.
The Do uble Update mo de provid es two addition al func-
tions to the user. First, the control loop bandwidth is
doubled because the PWM duty cycles can be
updated, twice per period. Secondly, asymmetrical
center aligned PWM waveforms can be generated,
which are useful for minimizing ou tput wavefor m distor-
tion in certain motor control applications.
15.1.5 PWM TIME-BASE PRE SCALE R
The input clock to PTMR (FOSC/4), has prescaler
options of 1:1, 1:4, 1:16, or 1:64, selected by control
bits PTCKPS<1:0> in the PTCON SFR. The prescaler
counter is cleared when any of the following occurs:
a write to the PTMR re gister
a write to the PTCON register
any device RESET
The PTMR register is not cleared when PTCON is
written.
15.1.6 PW M TIME-BAS E PO STS CAL ER
The match output of PTMR can optionally be post-
scaled through a 4-bit postscaler (which gives a 1:1 to
1:16 scaling) to generate an interrupt.
The postscaler counter is cleared when any of the
following occurs:
a write to the PTMR re gister
a write to the PTCON register
any device RESET
The PTMR register is not cleared when PTCON is written.
15.2 PWM Period
PTPER is a 15-bit register and is used to set the count-
ing period f or the PWM time-b ase. PTPER is a doubl e
buffered register. The PTPER buffer contents are
loaded into the PTPER register at the following instants:
Free Running and Single Shot modes: Whe n the
PTMR register is reset to zero after a match with
the PTPER register.
Up/Down Counting modes: When the PTMR
register is zero.
The value held in the PTPER buffer is automatically
loaded into the PTPER register, when the PWM
time-base is disabled (PTEN = 0).
The PWM pe rio d c an b e d etermined from the followin g
formula:
EQUATION 15-1: PWM PERIOD
If the PWM time-base is configured for one of the Up/
Down Count modes, the PWM period will be twice the
value provided by Equation 15-1.
The maximum resolution (in bits) for a given device
oscill ato r and PWM freque nc y c an be d ete rmined from
the following formula:
EQUATION 15-2: PWM RESOLUTION
15.3 Edge Aligned PWM
Edge aligned PWM signals are produced by the module
when the PWM time-base is in the Free Running or Sin-
gle Shot mode. For edge aligned PWM outputs, the out-
put for a given PWM channel has a period specified by
the value l oaded in PTPER and a d uty cycle specified
by the appropriate duty cycle register (see Figure 15-3).
The PWM output is driven active at the beginning of the
period (PTMR = 0) and is driven inactive, when the
value in the duty cycle register matches PTMR.
If the value in a particular duty cycle register is zero,
then the output on the corresponding PWM pin will be
inactiv e for the entire PWM period. In additi on, the out-
put on the PWM pin will be active for the entire PWM
period if the value in the duty cycle register is greater
than the value held in the PTPER register.
FIGURE 15-3: EDGE ALIGNED PWM
Note: Programming a value of 0x0001 in the
period register could gen erate a contin uous
interrupt pulse, and hence, must be
avoided.
TPWM = TCY (PTPER + 1)
(PTMR Prescale Value)
Resolution = log (2 TPWM / TCY)
log (2)
Period
Duty Cycle
0
PTPER
PTMR
Value
New Duty Cycle Latched
dsPIC30F
DS70082A-page 100 Advance Information 2002 Microchip Technology Inc.
15.4 Center Ali gned PWM
Center aligned PWM signal s are produc ed by the mod-
ule when the PWM time-base is configured in an
Up/Down Counting mode (see Figure 15-4).
The PWM compare output is driven to the active state
when the value of the duty cycle register matches the
value of PTMR and the PWM time-base is counting
downwards (PTDIR = 1). The PWM compare output is
driven to th e inactive state w hen the PWM time-ba se is
counting upwards (PTDIR = 0) and the value in the
PTMR register matches the duty cycle value.
If the value in a particular duty cycle register is zero,
then the output on the corresponding PWM pin will be
inactiv e for the en tire PWM p erio d. In add iti on, the out-
put on the PWM pin will be active for the entire PWM
peri od i f t h e val ue i n th e du t y cy cle r e gi ste r is eq u al t o
the value held in the PTPER register.
FIGURE 15-4: CENTER ALIGNED PWM
15.5 PWM Duty Cycle Comparison
Units
There are four 16-bit special function registers used to
specify duty cycle values for the PWM module:
PDC1
PDC2
PDC3
PDC4
The value in each duty cycle register determines the
amount of time that the PWM output is in the active
stat e. The duty c ycle reg isters are 1 6-bits wide. The LS
bit of a duty cycle register determines whether the
PWM edge occurs on Q1 or Q3. Thus, the PWM
resolution is effectively doubled.
15.5.1 DUTY CYCLE REGISTER BUFFERS
The four PWM duty cy cle regis ters are double buf fered
to allow glitchless updates of the PWM outputs. For
each dut y cycle, there is a duty cycle buffer register that
is accessible by the user and a second duty cycle reg-
ister that holds the actual compare value used in the
prese nt PWM peri od .
For edge aligned PWM output, a new duty cycle value
will be up dated whenever a match with the PTPER reg-
ister occurs and PTMR is reset. The contents of the
duty cycle buffers are automatically loaded into the
duty cycle registers when the PWM time-base is dis-
abled (PTEN = 0) and the UDIS bit is cleared in
PWMCON2.
When the PWM time-base is in the Up/Down Counting
mode, new duty cycle values are updated when the
value of the PTMR register is zero and the PWM time-
base b egins to c ount upwar ds. The co ntents o f the duty
cycle buffers are automatically loaded into the duty
cycle registers when the PWM time-base is disabled
(PTEN = 0).
When the PWM time-base is in the Up/Down Counting
mode with double updates, new duty cycle values are
updated when the value of the PTMR register is zero,
and when the value of the PTMR register matches the
value in the PTPER register. The contents of the duty
cycle buffers are automatically loaded into the duty
cycle registers when the PWM time-base is disabled
(PTEN = 0).
15.6 Complementary PWM Operation
In the Complementary mode of operation, each pair of
PWM outputs is obtained by a complementary PWM
signal. A dead-time may be optionally inserted during
device switching, when both outputs are inactive for a
short period (Refer to Section 15.7).
In Complementary mode, the duty cycle comparison
units are assigned to the PWM outputs as follows:
PDC1 register controls PWM1H/PWM1L outputs
PDC2 register controls PWM2H/PWM2L outputs
PDC3 register controls PWM3H/PWM3L outputs
PDC4 register controls PWM4H/PWM4L outputs
The Complementary mode is selected for each PWM
I/O pin pair by clearing the appropriate PMODx bit in the
PWMCON1 SFR. The PWM I/O pins are set to
Complementary mode by default upon a device RESET .
0
PTPER PTMR
Value
Period
Period/2
Duty
Cycle
2002 Microchip Technology Inc. Advance Information DS70082A-page 101
dsPIC30F
15.7 Dead-Time Generators
Dead-time generation may be provided when any of
the PWM I/O pin pairs are operating in the Comple-
mentary Output mode. The PWM outputs use Push-
Pull drive circuits. Due to the inability of the power out-
put devic es to sw it ch instantane ous ly, some amoun t of
time must be provided between the turn off event of one
PWM output in a complementary pair and the turn on
event of the other transistor.
The PWM module al lows two dif ferent d ead-times to b e
programmed. These two dead-times may be used in
one of two methods described below to increase user
flexibility:
The PWM output signals can be optimized for dif-
ferent turn off times in the high side and low side
transistors in a complementary pair of transistors.
The first dead-time is inserted between the turn
off e vent of th e low er trans istor of t he comple men-
tary pair and the turn on event of the upper tran-
sistor. The second dead-time is inserted between
the turn off event of the upper transistor and the
turn on ev ent of the lower transistor.
The two dea d-time s can be as signe d to indiv idual
PWM I/O pin pairs. This Operating mode all ows
the PWM module to drive different transistor/load
combin ati ons w it h ea ch complemen tary PWM I/O
pin pair.
15.7.1 DEAD-TIME GENERATORS
Each complementary output pair for the PWM module
has a 6-bit down counter that is used to produce the
dead-time insertion. As shown in Figure 15-5, each
dead-time unit has a rising and falling edge detector
connected to the duty cycle comparison output.
15.7.2 DEAD-TIME ASSIGNMENT
The DTCON2 SFR contains control bits that allow the
dead-times to be assigned to each of the complemen-
tary outputs. Table 15-2 summarizes the function of
each dead-time selection control bit.
TABLE 15-2: DEAD-TIME SELECTION BITS
15.7.3 DEAD-TIME RANGES
The amount of dead-time provided by each dead-time
unit is selected by specifying the input clock prescaler
value an d a 6- bit unsign ed val ue. T he amount o f dea d-
time provided by each unit may be set independently.
Four input clock prescaler selections have been pro-
vided to al low a suita ble range of dead-ti mes, based on
the device operating frequency. The clock prescaler
option may be selected independently for each of the
two dead-time values. The dead-time clock prescaler
values are selected using the DTAPS<1:0> and
DTBPS<1:0> co ntrol bits i n the DTCON1 SFR. The fol-
lowing clock prescaler options may be selected for
each of the dead-time values:
TCY
2TCY
4TCY
8TCY
After the prescaler values are selected, the dead-time
for each unit is adjusted by loading two 6-bit unsigned
values into the DTCON1 special function register.
The dead-time unit prescalers are cleared on the fol-
lowing events:
On a load of the down timer due to a duty cycle
comparison edge event.
On a write to the DTCON1 or DTCON2 registers.
On any device RESET.
Bit Function
DTS1A Selects PWM1L/PWM1H active edge dead-time.
DTS1I Selects PWM1L/PWM1H inactive edge
dead-time.
DTS2A Selects PWM2L/PWM2H active edge dead-time.
DTS2I Selects PWM2L/PWM2H inactive edge
dead-time.
DTS3A Selects PWM3L/PWM3H active edge dead-time.
DTS3I Selects PWM3L/PWM3H inactive edge
dead-time.
DTS4A Selects PWM4L/PWM4H active edge dead-time.
DTS4I Selects PWM4L/PWM4H inactive edge
dead-time.
Note: The user should not modify the DTCON1
or DTC ON2 val ues while the PWM modul e
is operating (PTEN = 1). Unexpected
results may occur.
dsPIC30F
DS70082A-page 102 Advance Information 2002 Microchip Technology Inc.
FIGURE 15-5: DEA D-TIME TIMING DIAGRAM
15.8 Independent PWM Output
An indepen dent PWM Output mode is required for dri v-
ing certain types of loads. A particular PWM output pair
is in the Independent Output mode when the corre-
sponding PMOD bit in the PWMCON1 register is set.
No dead-time control is implemented between adjacent
PWM I/O pins when the module is operating in the
Indepen dent mode and both I/O pin s a re al low e d to b e
active simultaneously.
In the Ind ependent mod e, e ach du ty c yc le gen era tor is
connected to both of the PWM I/O pins in an output
pair. By using the associated duty cycle register and
the appropriate bits in the OVDCON register, the user
may select the following signal output options for each
PWM I/O pin operating in the Independent mode:
I/O pin outputs PWM signal
I/O pin inactive
I/O pin active
15.9 Single Pulse PWM Operation
The PWM m odule p rodu ce s single pulse output s when
the PTCON control bi t s PTMOD<1:0> = 10. Only edge
aligned outputs may be produced in the Single Pulse
mode. In Single Pulse mode, the PWM I/O pin(s) are
driven to the active state when the PTEN bit is set.
When a match with a duty cycle register occurs, the
PWM I/O pin is driven to the inactive state. When a
match with the PTPER register occurs, the PTMR reg-
ister is cleared, all active PWM I/O pins are driven to
the inactive state, the PTEN bit is cleared, and an
interrupt is generated.
15.10 PWM Output Override
The PWM output override bits allow the user to manu-
ally drive the PWM I/O pins to specified logic states,
independent of the duty cycle comparison units.
All control bits associated with the PWM output over-
ride function are contained in the OVDCON register.
The upper half of the OVDCON register contains eight
bits , POVDxH<4:1> and POVDxL<4 :1>, that de termine
which PWM I/O pins will be overridden. The lower half
of the OVDCON register contains eight bits,
POUTxH<4:1> and POUTxL<4:1>, that determine the
state of the PWM I/O pins when a particular output is
overridden via the POVD bits.
15.10.1 COMPLEMENTARY OUTPUT MODE
When a PWMxL pin is driven active via the OVDCON
register, the output signal is forced to be the comple-
ment of the corresponding PWMxH pin in the pair.
Dead-time insertion is still performed when PWM
channel s are overridden manually.
15.10.2 OVERRIDE SYNCHRONIZATION
If the OSYNC bit in the PWMCON2 register is set, all
output overrides performed via the OVDCON register
are sync hroniz ed to th e PWM time-b ase. Sy nchron ous
output overrides occur at the following times:
Edge Aligned mode, when PTMR is zero.
Center Aligned modes, when PTMR is zero and
when the value of PTMR matches PTPER.
Duty Cycle Generator
PWMxH
PWMxL
Time selected by DTSxA bit (A or B) Time selected by DTSxI bit (A or B)
2002 Microchip Technology Inc. Advance Information DS70082A-page 103
dsPIC30F
15.11 PWM Output and Polarity Control
There are three device configuration bits associated
with the PWM module that provide PWM output pin
control.
HPOL configuration bit
LPOL configuration bit
PWMPIN configuration bit
These th ree configurati on bits in the FPORBOR co nfig-
uration register (see the System Integration section)
work in conjunction with the four PWM enable bits
(PWMEN<4:1>), located in the PWMCON1 SFR. The
configu ration bit s and PWM enable bit s ensure that the
PWM pins are in the correct states after a device
RESET occurs. The PWMPIN configuration fuse
allows the PWM module outputs to be optionally
enabled on a devic e RES ET. If PW MPIN = 0, th e PWM
output s will be dri ven to the ir in ac tive s t ates at RESET.
If PWMPIN = 1 (default), the PWM outputs will be tri-
stated. The HPOL bit specifies the polarity for the
PWMxH outputs, whereas the LPOL bit specifies the
polarity for the PWMxL outputs.
15.11.1 OUTPUT PIN CONTROL
The PEN<4:1>H and PEN<4:1>L control bits in the
PWMCON1 SFR enable each High PWM output pin
and eac h Low PWM o utput pin, resp ectively. If a p artic-
ular PWM output pin not enabled, it is treated as a
general purpose I/O pin.
15.12 PWM FAULT Pins
There are two F AULT pins (FLT A and FL T B) associated
with the PWM module. When asserted, these pins can
optionally drive each of the PWM I/O pins to a defined
state.
15.12.1 FAULT PIN ENABLE BITS
The FLTACON and FLTBCON Specia l Funct ion Regi s-
ters each have 4 control bits that determine whether a
particular pair of PWM I/O pins is to be controlled by the
FAULT in put pin. To enable a spe cific PWM I/ O pin pa ir
for FAULT overrides, the corresponding bit should be
set in the FLTACON or FLTBCON re gister.
If all enable bits are cleared in the FLTACON or
FLTBCON registers, then the corresponding FAULT
input pi n has no effect on the PWM modu le and the pi n
may be used as a general purpose interrupt pin or I/O.
15.12.2 FAULT STATES
The FLTACON and FLTBCON special function regis-
ters have 8 bits each, that determine the state of each
PWM I/O pin when it is overridden by a FAULT input.
When the se bi ts are c leared , the PW M I/O pin is drive n
to the inactive state. If the bit is set, the PWM I/O pin
will be driven to the active state. The active and inactive
states are referenced to the polarity defined for each
PWM I/O pin (HPOL and LPOL polarity control bits).
A special case exists when a PWM module I/O pair is
in the Complementary mode and both pins are pro-
grammed to be active on a FAULT condition. The
PWMxH pin always has priority in the Complementary
mode, so that both I/O pins cannot be driven active
simultaneously.
15.12.3 FAULT PIN PRIORITY
If bot h FAULT input pins h ave be en as signe d to co ntrol
a particular PWM I/O pin, the F AUL T state programmed
for the FAULT A input pin will take priority over the
FAULT B input pin.
15.12.4 FAULT INPUT MODES
Each of the FAULT input pins has two modes of
operation:
Latched Mode: When the FAULT pin is driven
low, the PWM out put s wil l go to the sta tes define d
in the FLTACON/FLTBCON register. The PWM
outputs will remain in this state until the FAULT
pin is driven high and the corresponding interrupt
flag has been cleared in software. When both of
these actions have occurred, the PWM outputs
will return to normal operation at the beginning of
the next PWM cycle or half-cycle boundary. If the
interrupt flag is cleared before the FAULT condi-
tion ends, the PWM modul e wi ll wait unti l the
FAULT pin is no longer asserted, to restore the
outputs.
Cycle-by-Cycle Mode: When the FAULT input
pin is driven low, the PWM outputs remain in the
defined FAULT states for as long as the FAULT
pin is held lo w. After the FAULT pin is driven high,
the PWM ou tputs retur n to normal ope ration at the
beginning of the following PWM cycle or
half-cycle boundary.
The Operating mode for each FAULT input pin is
selected using the FLTAM and FLTBM control bits in
the FLTACON and FLTBCON Special Function
Registers.
Each of the FA ULT pins can be c ontro lled ma nually in
software.
Note: The FAULT pin logic can operate indepen-
dent of t he PWM lo gic. If all th e enab le bit s
in the FLTACON/FLTBCON register are
cleared, then the FAULT pin(s) could be
used as general purpose interrupt pin(s).
Each FAULT pin has an interrupt vector,
interrupt flag bit and interrupt priority bits
associat ed with it.
dsPIC30F
DS70082A-page 104 Advance Information 2002 Microchip Technology Inc.
15.13 PWM Update Lockout
For a comple x PWM appl ica tion, the user may nee d to
write up to four duty cycle registers and the time-base
period reg is ter, PTPER, at a give n tim e. In some appl i-
cations , it is importan t that all buf fer registers be wr itten
befor e the new duty cycle and p eriod values are loaded
for use by the module.
The PWM update lockout feature is enabled by setting
the UDIS c ontro l bi t in the PW MC ON 2 SFR. The UDIS
bit affects all duty cycle buffer registers and the PWM
time-base period buffer, PTPER. No duty cycle
change s or period va lu e ch ang es wi ll h av e effect while
UDIS = 1.
15.14 PWM Special Event Trigger
The PWM module has a special event trigger that
allows A/D conversions to be synchr onized to the PWM
time-ba se. The A/ D sampling and conve rsion time may
be programmed to occur at any point within the PWM
period. The special even t trigger allows the user to min-
imize th e delay betwee n the time whe n A/D conversio n
results are acquired and the time when the duty cycle
value is updated.
The PWM special event trigger has an SFR named
SEVTCMP, and five control b its to control it s opera tion.
The PTMR value for which a special event trigger
should occur is loaded into the SEVTCMP register.
When the PWM time-base is in an Up/Down Counting
mode, an addi tional c ontrol b it is r equired t o sp ecify th e
counting phase for the special event trigger. The count
phase is selected using the SEVTDIR control bit in the
SEVTCMP SFR. If the SEVTDIR bit is cleared, the spe-
cial event trigger will occur on the upward counting
cycle of the PWM time-base. If the SEVTDIR bit is set,
the special event trigger will occur on the downward
count cycle of the PWM time-base. The SEVTDIR
control bit has no effect unless the PWM time-base is
configured for an Up/Down Counting mode.
15.14.1 SPECIAL EVENT TRIGGER
POSTSCALER
The PWM special event trigger has a postscaler that
allows a 1:1 to 1:16 postscale ratio. The postscaler is
configured by writing the SEVOPS<3:0> control bits in
the PWMCON2 SFR.
The special event output postscaler is cleared on the
following events :
Any write to the SEVTCMP register.
Any device RESET.
15.15 PWM Operation During CPU
SLEEP Mode
The FAULT A and FAULT B input pins have the ability
to wake the CPU from SLEEP mode. The PWM mod-
ule gene rate s a n i nte rrupt if either of the FAULT pins is
driven low while in SLEEP.
15.16 PWM Operation During CPU IDLE
Mode
The PTCON SFR contains a PTSIDL control bit. This
bit determines if the PWM module will continue to
operate or stop when the device enters IDLE mode. If
PTSIDL = 0, the module continues to operate. If
PTSIDL = 1, the module will stop operation as long as
the CPU remains in IDLE mode.
2002 Microchip Technology Inc.
Advance Inf ormat ion
DS70082A-page 105
dsPIC30F
TABLE 15-3: 8-OUTPUT PWM REGISTER MAP
TABLE 15-4: 6-OUTPUT PWM REGISTER MAP
SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RESET State
PTCON 01C0 PTEN PTSIDL PTOPS<3:0> PTCKPS<1:0> PTMOD<1:0> 0000 0000 0000 0000
PTMR 01C2 PTDIR PWM Timer Coun t Value 0000 0000 0000 0000
PTPER 01C4 PWM Time-Base Period Regis ter 0000 0000 0000 0000
SEVTCMP 01C6 SEVTDIR PWM Special Event Compare Register 0000 0000 0000 0000
PWMCON1 01C8 PTMOD4 PTMOD3 PTMOD2 PTMOD1 PEN4H PEN3H PEN2H PEN1H PEN4L PEN3L PEN2L PEN1L 0000 0000 1111 1111
PWMCON2 01CA SEVOPS<3:0> OSYNC UDIS 0000 0000 0000 0000
DTCON1 01CC DTBPS<1:0> Dead-Ti me B Value DTAPS<1:0> Dead-Time A Value 0000 0000 0000 0000
DTCON2 01CE DTS4A DTS4I DTS3A DTS3I DTS2A DTS2I DTS1A DTS1I 0000 0000 0000 0000
FLTACON 01D0 FAOV4H FAOV4L FAOV3H FAOV3L FAOV2H FAOV2L FAOV1H FAOV1L FLTAM FAEN4 FAEN3 FAEN2 FAEN1 0000 0000 0000 0000
FLTBCON 01D2 FBOV4H FBOV4L FBOV3H FBOV3L FBOV2H FBOV2L FBOV1H FBOV1L FLTBM FBEN4 FBEN3 FBEN2 FBEN1 0000 0000 0000 0000
OVDCON 01D4 POVD4H POVD4L POVD3H POVD3L POVD2H POVD2L POVD1H POVD1L POUT4H POUT4L POUT3H POUT3L POUT2H POUT2L POUT1H POUT1L 1111 1111 0000 0000
PDC1 01D6 PWM Duty Cycle #1 Register 0000 0000 0000 0000
PDC2 01D8 PWM Duty Cycle #2 Register 0000 0000 0000 0000
PDC3 01DA PWM Duty Cycle #3 Register 0000 0000 0000 0000
PDC4 01DC PWM Duty Cycle #4 Regi ster 0000 0000 0000 0000
Legend: u = uninitialized bit
SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RESET State
PTCON 01C0 PTEN PTSIDL PTOPS<3:0> PTCKPS<1:0> PTMOD<1:0> 0000 0000 0000 0000
PTMR 01C2 PTDIR PWM Timer Coun t Value 0000 0000 0000 0000
PTPER 01C4 PWM Time-Base Period Regis ter 0000 0000 0000 0000
SEVTCMP 01C6 SEVTDIR PWM Special Event Compare Register 0000 0000 0000 0000
PWMCON1 01C8 PTMOD3 PTMOD2 PTMOD1 PEN3H PEN2H PEN1H PEN3L PEN2L PEN1L 0000 0000 0111 0111
PWMCON2 01CA SEVOPS<3:0> OSYNC UDIS 0000 0000 0000 0000
DTCON1 01CC DTAPS<1:0> Dead-Time A Value 0000 0000 0000 0000
FLTACON 01D0 FAOV3H FAOV3L FAOV2H FAOV2L FAOV1H FAOV1L FLTAM FAEN3 FAEN2 FAEN1 0000 0000 0000 0000
OVDCON 01D4 POVD3H POVD3L POVD2H POVD2L POVD1H POVD1L POUT3H POUT3L POUT2H POUT2L POUT1H POUT1L 0011 1111 0000 0000
PDC1 01D6 PWM Duty Cycle #1 Register 0000 0000 0000 0000
PDC2 01D8 PWM Duty Cycle #2 Register 0000 0000 0000 0000
PDC3 01DA PWM Duty Cycle #3 Register 0000 0000 0000 0000
Legend: u = uninitialized bit
dsPIC30F
DS70082A-page 106 Advance Information 2002 Microchip Technology Inc.
NOTES:
2002 Microchip Technology Inc. Advance Information DS70082A-page 107
dsPIC30F
16.0 SPI MODULE
The Serial Peripheral Interface (SPI) module is a syn-
chronous serial interface, useful for communicating
with othe r periphera l devices, such as EEPROMs, shift
registers, display drivers and A/D converters, or other
microcontrollers. It is compatible with Motorolas SPITM
and SIOPTM interfaces.
16.1 Operating Function Description
Each SPI module consists of a 16-bit shift register,
SPIxSR (where x = 1 or 2), used for shifting data in
and out, and a buffer register, SPIxBUF. A control reg-
ister, SPIxCON, configures the module. Additionally, a
status register, SPIxSTAT, indicates various status
conditions.
The serial interface consists of 4 pins: SDIx (serial
data input), SDOx (serial data output), SCKx (shift
clock input or output), and SSx (active low slave
select).
In Master mode operation, SCK is a clock output, but
in Slave mode, it is a clock input.
A series of eight (8) or sixteen (16) clock pulses shifts
out bits from the SPIxSR to SDOx pin and simulta-
neously shifts in data from SDIx pin. An interrupt is
generated when the transfer is complete and the cor-
responding interrupt flag bit (SPI1IF or SPI2IF) is set.
This interrupt can be disabled through an interrupt
enable bit (SPI1IE or SPI2IE).
The receive operation is double buffered. When a
complete byte is received, it is transferred from
SPIxSR to SPIxBUF.
If the receive buffer is full when new data is being
transferred from SPIxSR to SPIxBUF, the module will
set the SPIROV bit, indicating an overflow condition.
The transfer of the data from SPIxSR to SPIxBUF will
not be completed and the new data will be lost. The
module will not respond to SCL transitions while
SPIROV is 1, effectively disabling the module until
SPIxBUF is read by user software.
Transmit writes are also double buffered. The user
write s to SPIxBU F. When the master or slave t ransfer
is completed, the SPIxSR is swapped with SPIxBUF.
The received data is thus placed in SPIxBUF and the
transmit data in SPIxSR is ready for the next transfer.
In Master mode, the clock is generated by prescaling
the system clock. Data is transmitted as soon as
SPIBUF is written to. The interrupt is generated at the
middle of the transfe r of the last bit.
In Slave mode, data is transmitted and received as
external clock pulses appear on SCK. Again, the inter-
rupt is generated when the last bit is latched in. If SSx
control i s enabled , then tran smission and recepti on are
enabled only when SSx = low. The SDOx outpu t will be
disabled in SSx mode with SSx high.
The clock provided to the module is (FOSC/4). This
clock is then prescaled by the primary (PPRE<1:0>)
and the secondary (SPRE<2:0>) prescale factors. The
CKE bit determines whether transmit occurs on transi-
tion from active clock state to IDLE clock state, or vice
versa. Th e CKP b it s ele cts the IDLE st a te (h ig h or l ow )
for the clock.
16.1.1 WORD AND BYTE
COMMUNICATION
A control bit, MODE16 (SPIxCON<10>), allows the
module to communicate in either 16-bit or 8-bit mode.
16-bit operation is identical to 8-bit operation, except
that the number of bits transmitted is 16 instead of 8.
The user software must disable the module prior to
changing the MODE16 bit. The SPI module always
gets reset to start a new communication when the
MODE16 bit is changed by the user.
A basic dif ference betwee n 8-bit and 16-bit operat ion is
that the data is transmitted out of bit 7 of the SPIxSR for
8-bit operation, and data is transmitted out of bit15 of
the SPIxSR for 16-bit opera tion. In both mode s, dat a is
shifted into bit 0 of the SPIxSR.
16.1.2 SDOx DISABLE
A control bit , DISSDO, is provided to the SPIxCON reg-
ister to allow the SDOx output to be disabled. This will
allow the SPI module to be connected in an input only
configuration. SDO can also be used for general
purpose I/O.
16.2 Framed SPI Support
The module supports a basic framed SPI protocol in
Master or Sla ve mode. The co ntrol bit FRMEN enables
framed SPI s upport and c auses the SSx pin to pe rform
the frame synchronization pulse (FSYNC) function.
The control bit SPIFSD determines whether the SSx
pin is an input or an output, i.e., whether the module
receive s or gene rates the frame sync hronizati on puls e.
The frame pu lse is an activ e high pulse for a single SPI
clock cycle. When frame synchronization is enabled,
the data starts transmitting only on the subsequent
transmit edge of the SPI clock.
Note: The transmit and receive buffers are
mapped to the same register address,
SPIxBUF.
dsPIC30F
DS70082A-page 108 Advance Information 2002 Microchip Technology Inc.
FIGURE 16-1: SPI BLOCK DIAGRAM
FIGURE 16-2: SPI MASTER/SLAVE CONNECTION
Note: x = 1 or 2.
Read Write
Internal
Data Bus
SDIx
SDOx
SSx
SCKx
SPIxSR
SPIxBUF
bit0
Shift
clock Edge
Select
FOSC
Primary
1, 4, 16, 64
Enable Master Clock
Prescaler
Secondary
Prescaler
1,2,4,6,8
SS & FSYN C
Control
Clock
Control
Transmit
SPIxBUF
Receive
Serial Input Buffer
(SPIxBUF)
Shift Register
(SPIxSR)
MSb LSb
SDOx
SDIx
PROCESSOR 1
SCKx
SPI Ma ster
Serial Input Buffer
(SPIyBUF)
Shift Register
(SPIySR)
LSb
MSb
SDIy
SDOy
PROCESSOR 2
SCKy
SPI Slav e
Serial Clock
Note: x = 1 or 2, y = 1 or 2.
2002 Microchip Technology Inc. Advance Information DS70082A-page 109
dsPIC30F
16.3 Slave Select Synchronization
The SSx pin allows a Synchronous Slave mode. The
SPI must be configured in SPI Slave mode, with SSx
pin control enabled (SSEN = 1). When the SSx pin is
low, transmission and reception are enabled, and the
SDOx pin is driven. When SSx pin goes high, the SDOx
pin is no longer driven. Also, the SPI module is re-
synchronized, all counters and control circuitry are
reset; therefore, when the SSx pin is asserted low
again, transmission/reception will begin at the Most
Signific ant bi t, even i f SSx had been d e-asserte d in th e
middle of a transmit/receive.
16.4 SPI Operation During CPU SLEEP
Mode
During SLEEP mode, the SPI module is shut-down. If
the CPU enters SLEEP mod e whi le a n SPI t rans actio n
is in progress, then the transmission and reception is
aborted.
The transmitter and receiver will stop in SLEEP mode.
However, register contents are not affected by
entering or exiting SLEEP mode.
16.5 SPI Operation During CPU IDLE
Mode
When the device enters IDLE mode, all clock sources
remain functional. The SPISIDL bit (SPIxSTAT<13>)
selects if the SPI module will stop on IDLE or continue
on IDLE. If SPISIDL = 0, the module will continue
operation when the CPU enters IDLE mode. If
SPISIDL = 1, the module will stop when the CPU
enters IDLE mode.
dsPIC30F
DS70082A-page 110 Advance Information
2002 Microchip Technology Inc.
TABLE 16-1: SPI1 REGISTER MAP
TABLE 16-2: SPI2 REGISTER MAP
SFR
Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RESET State
SPI1STAT 0220 SPIEN SPISIDL SPIROV SPITBF SPIRBF 0000 0000 0000 0000
SPI1CON 0222 FRMEN SPIFSD DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE2 SPRE1 SPRE0 PPRE1 PPRE0 0000 0000 0000 0000
SPI1BUF 0224 Transmit and Receive Buffer 0000 0000 0000 0000
Legend: u = uninitialized bit
SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RESET State
SPI2STAT 0226 SPIEN SPISIDL SPIROV SPITBF SPIRBF 0000 0000 0000 0000
SPI2CON 0228 FRMEN SPIFSD DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE2 SPRE1 SPRE0 PPRE1 PPRE0 0000 0000 0000 0000
SPI2BUF 022A Transmit and Receive Buffer 0000 0000 0000 0000
Legend: u = uninitialized bit
2002 Microchip Technology Inc. Advance Information DS70082A-page 111
dsPIC30F
17.0 I2C MODULE
The Inter-Integrated CircuitTM (I2CTM) module provides
complete hardware support for both Slave and Multi-
Master modes of the I2C serial communication
standard, with a 16-bit interface.
This module offers the following key features:
Inter-Integrated Circuit (I2C) interface
I2C interface support s both M aster and Slav e
operation.
I2C Slave mode supports 7 and 10-bit address.
I2C Master mode supports 7 and 10-bit address.
I2C port allows bi-direct ional transfe rs bet ween
master and slav es.
Serial clock synchronization for I2C port can be
used as a ha ndshake mechanis m to suspen d and
resume serial transfer (SCLREL control).
I2C supports Multi-Master operation; detects bus
collision and will arbitrate accordingly.
17.1 Operating Function Description
The hardw are fully im plements all the maste r and slave
function s of the I2C S t a ndard a nd Fas t mode s peci fica-
tions, as well as 7 and 10-bit addressing.
Thus, the I2C module can operate either as a slave or
a master on an I2C bus.
17.1.1 VARIOUS I2C MODES
The following types of I2C operation are supported:
I2C Slave operation with 7-bit address
I2C Slave operation with 10-bit address
I2C Master operation with 7 or 10-bit address
See the I2C programmers model in Figure 17-1.
FIGURE 17-1: PROGRAM MERS MODEL
17.1.2 PIN CONFIGURATION IN I2C MODE
I2C has a 2-pi n inte rface: pin SCL is cl ock a nd pin SDA
is data.
17.1.3 I2C REGISTERS
I2CCON and I2 CSTAT are control and sta tus re gisters ,
respect ively . The I2CCO N register is readable an d writ-
able. The lower 6 bits of I2CSTAT are read only. The
remaining bits of the I2CSTAT are read/write.
I2CRSR is the shift register used for shifting data,
whereas I2CRCV is the buffer register to which data
bytes are written to or read from. This register is the
receive buffer, as shown in Figure 16-1. I2C TRN is the
transmit register to which bytes are written during a
transmit oper ation, as show n in Figure 16-2 .
The I2CADD regis ter hol ds the s lave a ddress. A status
bit, ADD10, indicates 10-bit Address mode. The
I2CBR G acts as the baud rate genera tor relo ad value .
In receive operations, I2CRSR and I2CRCV together
form a double buffered receiver. When I2CRSR
receives a complete byte, it is transferred to I2CRCV
and the I2CIF interrupt pulse is generated. During
transmission, the I2CTRN is not double buffered.
bit 7 bit 0 I2CRCV (8-bits)
bit 7 bit 0 I2CTRN (8-bits)
bit 8 bit 0 I2CBRG (9-bits)
bit 15 bit 0 I2CCON (16-bits)
bit 15 bit 0 I2CSTAT (16-bits)
bit 9 bit 0 I2CADD (10-bits)
Note: Following a RESTART condition in 10-bit
mode, the user only needs to match the
first 7-bit addre ss.
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DS70082A-page 112 Advance Information 2002 Microchip Technology Inc.
FIGURE 17-2: I2C BLOCK DIAGRAM
I2CRSR
I2CRCV
Internal
Data Bus
SCL
SDA
Shift
Mat ch Detect
I2CADD
START and
STOP bi t D e te ct
Clock
Addr_Match
Clock
Stretching
I2CTRN LSB
Shift
Clock
Write
Read
BRG Down I2CBRG
Reload
Control
FOSC
START, RES TART,
STOP bit Generate
Write
Read
Acknowledge
Generation
Collision
Detect
Write
Read
Write
Read
I2CCON
Write
Read
I2CSTAT
Control Logic
Read
LSB
Counter
2002 Microchip Technology Inc. Advance Information DS70082A-page 113
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17.2 I2C Module Addresses
The I2CADD register contains the Slave mode
addresses. The register is a 10-bit register.
If the A10M bit (I2CCON<10>) is 0, the address is
assumed to be a 7-bit address. When an address is
received, it is compared to the Least Significant 7 bits
of the I2CADD register.
If the A10M bit is 1, the address is assumed to be a
10-bit address. When an address is received, it will be
compared with the binary value 1 1 1 1 0 A9 A8
(where A9, A8 are two Most Significant bits of
I2CADD). If that value matches, the next address will
be compared with the Least Significant 8-bits of
I2CADD, as specified in the 10-bit addressing
protocol.
17.3 I2C 7-bit Slave Mode Operation
Once enabled (I2CEN = 1), the slave module will wait
for a START bit to occur (i .e., th e I2C module is IDLE).
Following the detection of a START bit, 8 bits are
shifted into I2CRSR and the address is compared
against I2CADD. In 7-bit mode (A10M = 0), bits
I2CADD<6:0> are compared against I2CRSR<7:1>
and I2CRSR<0> is the R_W bit. All incoming bits are
sampled on the rising edge of SCL.
If an address match occurs, an Acknowledge will be
sent, and on the falling edge of the ninth bit (ACK bit),
the I2CIF interrupt pulse is generated. The address
match does not affect the contents of the I2CRCV
buffer or t he RBF bit.
17.3.1 SLAVE TRANSMISSION
If the R_W bit received is a '1', then the serial port will
go into Transmi t mode. It wil l send AC K on the ninth b it
and then hol d SCL to '0' until the CPU responds by writ-
ing to I2C TRN. SCL is rele ased by settin g the SCLREL
bit, and 8 bits of data are shifted out. Data bits are
shifted out on the fa lling edge of SCL, s uch that SDA i s
valid during SCL high (see timing diagram). The inter-
rupt pulse is sent on the falling edge of the ninth clock
pulse, regardless of the status of the ACK received
from the master.
17.3.2 SLAVE RECEPTION
If the R_W bit received is a '0' during an address match,
then Receive mode is initiated. Incoming bits are sam-
pled on the rising edge of SCL. After 8 bits are
received, if I2CRCV is not full or I2COV is not set,
I2CRSR is transferred to I2CRCV. ACK is sent on the
ninth clock.
If the RBF flag is set, indicating that I2CRCV is still
holding data fro m a previo us operat ion (RBF = 1), then
ACK is not sent; however, the interrupt pulse is gener-
ated. In the case of an overflow, the contents of the
I2CRSR are not loaded into the I2CRCV.
17.4 I2C 10-bit Slave Mode Operation
In 10-bit mode, the basic receive and transmit opera-
tions are the same as in the 7-bit mode. However, the
criteria for address match is more complex.
The I2C specification dictates that a slave must be
address ed for a write ope ration, with tw o address byte s
following a START bit.
The A10M bit is a control bit that signifies that the
address in I2CADD is a 10-bit address rather than a
7-bit address. The address detection protocol for the
first byte of a message address is identical for 7-bit
and 10-bit messages, but the bits being compared are
different.
I2CADD holds the entire 10-bit address. Upon receiv-
ing an addres s following a ST AR T bit, I2CRSR <7:3> is
compared against a literal 11110 (the default 10-bit
address) and I2CRSR<2:1> are compared against
I2CADD<9:8>. If a match occurs and only if R_W = 0,
the interrupt pulse is sent. The ADD10 bit will be
cleared to indicate a partial address match. If a match
fails or R_W = 1, the ADD10 bit is cleared and the
module returns to the IDLE state.
Then, the low b yte of the add ress i s rece ived a nd com-
pared against I2CADD<7:0>. If an address match
occurs , the interru pt pulse is genera ted and the ADD10
bit is set , indicatin g a comple te 10-bit addre ss match . If
an address match did not occur, the ADD10 bit is
cleared and the module returns to the IDLE state.
17.4.1 10-BIT MODE SLAVE
TRANSMISSION
Once a slave is addressed in this fashion, with the full
10-bit address (we will refer to this state as
"PRIOR_ADDR_MATCH"), the master can begin
sending data bytes for a slave reception operation.
17.4.2 10-BIT MODE SLAVE RECEPTION
Once add res sed, the master can, with out generatin g a
STOP bit, generate a Repeated START bit and reset
the high byte of the address and R_W = 1, thus
initiating a slave transmit operation.
Note: The I2CRCV will be loaded if the I2COV bit
= 1 and the RBF flag = 0. In this case, a
read of the I2CRCV was performed, but
the user did not clear the state of the
I2COV bit before the next receive
occurred. The Acknowledge is not sent
(ACK = 1) and the I2CRCV is updated.
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17.5 Automatic Clock Stretch
In the Slave modes, the module can synchronize
buffer reads and write to the master device by clock
stretching.
17.5.1 TRANSMI T CLOCK STRE TCHING
Both 10-bit and 7-bit Transmit modes implement clock
stretching by asserting the SCLREL bit after the falling
edge of th e ninth c lock if th e TBF bit i s clea red, ind icat-
ing the buffer is empty. This occurs regardless of the
state of the STREN bit.
In Slave Transmit modes, clock stretching is always
performed, irrespective of the STREN bit.
Clock synchronization takes place following the ninth
clock of the transmit sequence. If the device samples
an ACK on the fa lling edge o f the ni nth cl ock, a nd if th e
TBF bit is still clear, then the SCLREL bit is automati-
cally cleared. The SCLREL being cleared to 0 will
assert the SCL line low. The user s ISR must set the
SCLREL bit before transmission is allowed to con-
tinue. By ho ldi ng the SC L l ine lo w, the user has tim e to
service the ISR and load the contents of the I2CTRN
before the master device can initiate another transmit
sequence.
17.5.2 RECEIVE CLOCK STRETCHING
The STREN bit in the I2CCON register can be used to
enable clock stretching in Slave Receive mode. When
the STREN bit is set, the SCL pin will be held low at
the end of each data receive sequence.
17.5.3 CLOCK STRETCHING DURING
7-BIT AD DRESSING (ST REN = 1)
When the STREN bit is set in Slave Receive mode,
the SCL line is held low when the buffer register is full.
The method for stretching the SCL output is the same
for both 7 and 10-bit Addressing modes.
Clock stretching takes place following the ninth clock of
the receive sequence. On the falling edge of the ninth
clock at the end of the ACK sequence, if the RBF bit is
set, the SCLREL bit is automatically cleared, forcing the
SCL output to be held low. The user s ISR must set the
SCLREL bit before reception is allowed to continue. By
holding the SCL line low, the user has time to service
the ISR and read the contents of the I2CRCV before the
master device can initiate another receive sequence.
This will prevent buffer overruns from occurring.
17.5.4 CLOCK STRETCHING DURING
10-BIT ADDRESSING (STREN = 1)
Clock stretching takes place automatically during the
addressing sequence. Because this module has a
register for the entire address, it is not necessary for
the protocol to wait for the address to be updated.
After the address phase is complete, clock stretching
will occur on each data receive or transmit sequence
as is described earlier.
17.6 Software Controlled Clock
Stretching (STREN = 1)
When the STREN bit is 1, the SCLREL bit may be
cleared by software to allow software to control the
clock stretching. The logic will synchronize writes to
the SCLREL bit with the SCL clock. Clearing the
SCLREL bit will not assert the SCL output until the
module detects a falling edge on the SCL output and
SCL is sampled low. If the SCLREL bit is cleared by
the use r whi le t he SCL line is al rea dy sa mp led low, the
SCL output will be asserted. The SCL output will
remain low until the SCLREL bit is set, and all other
devices on the I2C bus have de-asserted SCL. This
ens ures that a write to t he SCLR EL bit will not viol ate
the minimum high time requirement for SCL.
If the STREN bit is 0, a software write to the SCLREL
bit will be disregarded and have no effect on the
SCLREL bit.
17.7 Interrupts
The I2C module generates two interrupt flags, I2CIF
(I2C Transfer Complete Interrupt Flag) and BCLIF (I2C
Bus Collis ion Interru pt Flag). The I2CIF int errupt flag is
pulsed high for one TCY on the falling edge of the 9th
clock pulse. The BCLIF interrupt flag is pulsed high for
one TCY when a bus collision event is detected.
Note 1: If the user loads the contents of I2CTRN,
setting the TBF bit before the falling edge
of the ninth clock, the SCLREL bit wi ll not
be cleared and clock stretching will not
occur.
2: The SCLREL bit can be set in software,
regardless of the state of the TBF bit.
Note 1: If the user reads the contents of the
I2CRCV, clearing the RBF bit before the
falling edge of the ninth clock, the
SCL REL bit wil l not be clea red and clo ck
stretching will not occur.
2: The SCLREL bit can be set in software,
regardles s of th e st ate of th e RBF bit. Th e
user sho uld be ca reful to c lear the RBF b it
in the ISR before the next receive
sequence in order to prevent an overflow
condition.
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17.8 Slope Control
The I2C standard requires slope control on the SDA
and SCL signals for Fast Mode (400 kHz). The control
bit, DISSLW , enab les the user to disable slew rate co n-
trol, if desired. It is necessary to disable the slew rate
control for 1 MHz mode.
17.9 IPMI Support
The control bit IPMIEN enables the module to support
Intelligent Peripheral Management Interface (IPMI).
When this bit is s et, t he m od ule ac ce pts and ac t s upon
all addres ses .
17.10 General Call Address Support
The general call address can address all devices.
When this address is used, all devices should, in the-
ory, respond with an Acknowl edg e.
The general call address is one of eight addresses
reserved for specific purposes by the I2C protocol. It
consists of all 0s with R_W = 0.
The general call address is recognized when the Gen-
eral Call Enable bit (GCEN) is set (I2CCON<15> = 1).
Following a START bit detect, 8 bits are shifted into
I2CRSR and the address is compared against
I2CADD, and is also compared to the general call
address, which is fixed in hardware.
If a gen eral cal l addre ss matc h occurs, the I2CRS R is
transferred to the I2CRCV after the eighth clock, the
RBF flag is set, and on the falling edge of the ninth bit
(ACK bit), the I2CIF interrupt is set.
When the i nte rrupt is serviced, the source for the int er-
rupt can be checked by reading the contents of the
I2CRCV to determine if the address was device
specific, or a general call address.
17.11 I2C Master Support
As a Master device, six operations are supported.
Assert a START condition on SDA and SCL.
Assert a RESTART condition on SDA and SCL.
Write to the I2CTRN register initiating
transmission of data/address.
Generate a STOP condition on SDA and SCL.
Configu re the I2C port to receive data.
Generat e an Ackno wled ge conditi on at the end of
a received byte of data.
17.12 I2C Master Operation
The master device generates all the serial clock pulses
and the START and STOP conditions. A transfer is
ended with a STOP condition or with a Repeated
START condition. Since the Repeated START condi-
tion is al so the beginni ng of the next s eri al transfer, the
I2C bus will not be released.
In Master Transmitter mode, serial data is output
through SDA, while SCL outputs the serial clock. The
first byte transmitted contains the slave address of the
receiving device (7 bits) and the data direction bit. In
this case, the data direction bit (R_W) is logic 0. Serial
data is transmitted 8 bits at a time. After each byte is
transmitted, an Acknowledge bit is received. START
and STOP conditions are output to indicate the
beginning and the end of a serial transfer.
In Master Rec eive mode, the firs t byte transmitte d con-
tains the slave address of the transmitting device (7
bits) and the data direction bit. In this case, the data
directio n bit (R_W) is logi c 1. Thu s, the first by te trans -
mitted i s a 7-b it sla ve add res s, fol lowe d by a 1 to indi-
cate re ceive bi t. Serial data is rece ived via SD A while
SCL outputs the serial clock. Serial data is received 8
bits at a time. After each byte is received, an Acknowl-
edge bit is transmitted. START and STOP conditions
indicate the beginning and end of transmission.
17.12.1 I2C MASTER TRANSMISSION
T ransmis sion of a dat a byte, a 7 bit addres s, or the sec -
ond half of a 10 bit address is accomplished by simply
writing a value to I2CTRN register. The user should
only write to I2CTRN when the module is in a WAIT
state. This action will set the buffer full flag (TBF) and
allow the baud rate generator to begin counting and
start the next transmission. Each bit of address/data
will be shifted out onto the SDA pin after the falling
edge of SCL is asserted. The Transmit Status Flag,
TRSTAT (I2CSTAT<14>), indicates that a master
transmit is in progress.
17.12.2 I2C MASTER RECEPTION
Master mode recepti on is enabl ed by progra mmin g the
receive enable (RCEN) bit (I2CCON<11>). The I2C
module must be IDLE before the RCEN bit is set, oth-
erwise the RCEN bit will b e disrega rded. The baud rate
generator begins counting, and on each rollover, the
state of the SCL pin changes (high to low/low to high),
and data is shifte d in to the I2C RSR on the ris in g edg e
of each clock.
17.12.3 BAUD RATE GENERATOR
In I2C Master mode, the reload value for the BRG is
located in the I2CBRG register. When the BRG is
loaded with this value, the BRG counts down to 0 and
stop s until anothe r reload has taken pla ce. If clock arbi-
tration i s taking place, for inst ance, the BRG is reloade d
when the SCL pin is sampled high.
As per the I2C standard, FSCK may be 100 kHz,
400 kHz. However, the user can specify any baud rate
up to 1 MHz. I2CBRG values of 0 or 1 are illegal.
EQUATION 17-1: SERIAL CLOCK RATE
FSCK = FCY / I2CBRG
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DS70082A-page 116 Advance Information 2002 Microchip Technology Inc.
17.12.4 CLOCK ARBITRATION
Clock arbitration occurs when the master de-asserts
the SCL pin (SCL allowed to float high) during any
receive , tran sm it, or RESTART /ST O P co ndi tion. When
the SCL pin is allo w ed to flo at hig h, the ba ud rate gen-
erator (BRG) is suspended from counting until the SCL
pin is ac tually sam pled high. When the SCL pin is sam -
pled high, the baud rate generator is reloaded with the
content s of I2CB RG and begin s counting. Th is ensures
that t he S CL high time w i ll a lway s be at l eas t o ne BRG
rollove r count, in the ev en t tha t th e c loc k is he ld l ow by
an external device.
17.12.5 MULTI-MASTER COMMUNICATION,
BUS COLLISION, AND BUS
ARBITRATION
Multi-M aster operation support is achiev ed by bus arbi-
tration. When the master outputs address/data bits
onto the SDA pin, arbitration takes place when the
master outputs a 1 on SDA, by letting SDA float high
and another master asserts a 0. When the SCL pin
floats high, data should be stable. If the expected data
on SDA is a 1 and the data sampled on the SDA
pin = 0, then a b us c ol li sion has taken place. The ma s-
ter will set the Bus Collision Interrupt (BCLI F) pulse and
reset th e master po rtion of the I 2C port to its IDLE s tate.
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the TBF flag is
cleared, the SDA and SCL lines are de-asserted, and
the I2CTRN can now be written to. When the user ser-
vices the bus collision Interrupt Service Routine, and if
the I2C bus is free (i.e., the P bit is set), the user can
resume communication by asserting a START
condition.
If a START, RESTART, STOP, or Acknowledge condi-
tion was in progress when the bus collision occurred,
the con dition is aborte d, the SDA and SC L lines are d e-
asserte d, and the respe ctive control bi ts in the I2 CCON
register are cleared to 0. When the user services the
bus collision Interrupt Service Routine, and if the I2C
bus is free, the user can resume communication by
asserti ng a START conditio n.
The Master will continue to monitor the SDA and SCL
pins, and if a STOP condition occurs, the I2CIF bit will
be set.
A write to the I2CTR N will start the transm ission of dat a
at the fi rst data bit, regardless of where the transmitter
left off when bus collision occurred.
In a Multi-Master environment, the interrupt generation on
the detection of S TART and S TOP conditi ons a llows t he
determination of w hen the bus i s free. Contro l of the I2C
bus can be taken when the P bit is set in the I2CSTAT
register, or the bus is IDLE and the S and P bits are
cleared.
17.13 I2C Module Operation During CPU
SLEEP and IDLE Modes
17.13.1 I2C OPERATION DURING CPU
SLEE P MOD E
When the device enters SLEEP mode, all clock
sources to the module are shutdown and stay at logic
0. If SLEEP occurs in the middle of a transmission,
and the st ate mac hine is p artially into a transmission a s
the clocks stop, then the transmission is aborted. Sim-
ilarly, if SLEEP occurs in the middle of a reception, the n
the reception is aborted.
17.13.2 I2C OPERATION DURING CPU IDLE
MODE
For the I2C, the I2CSIDL bit selects if the module will
stop on IDLE or continue on IDLE. If I2CSIDL = 0, the
module will continue operation on assertion of the IDLE
mode. If I2CSIDL = 1, the module will stop on IDL E.
2002 Microchip Technology Inc.
Advance Inf ormat ion
DS70082A-page 117
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TABLE 17-1: I2C REGISTER MAP
SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RESET State
I2CRCV 0200 Receive Register 0000 0000 0000 0000
I2CTRN 0202 Tra nsmit Register 0000 0000 1111 1111
I2CBRG 0204 Baud Rate Generator 0000 0000 0000 0000
I2CCON 0206 I2CEN I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 0001 0000 0000 0000
I2CSTAT 0208 ACKSTAT TRSTAT BCL GCSTAT ADD10 IWCOL I2COV D_A P S R_W RBF TBF 0000 0000 0000 0000
I2CADD 020A Address Regist er 0000 0000 0000 0000
Legend: u = uninitialized bit
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NOTES:
2002 Microchip Technology Inc. Advance Information DS70082A-page 119
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18.0 UNIVERSAL ASYNCHRONOUS
RECEIVER TRANSMITTER
(UART) MODULE
This section describes the Universal Asynchronous
Receiver/Transmitter Communications module.
18.1 UART Module Overview
The key features of the UART module are:
Full-duplex, 8 or 9-bit data communication
Even, Odd or No Parity options (for 8 -bit data)
One or two STOP bits
Fully integ rate d Baud R ate Ge nera tor with 16-b it
prescaler
Baud rates range from 38 bps to 1.875 Mbps at a
30 MHz instruction rate
4-word deep transmit data buffer
4-word deep receive data buffer
Parity, Framing and B uff er Overrun error de tection
Support for Interrupt only on Address Detect
(9th bit = 1)
Separate Transmit and Receive Interrupts
Loopback mode for diagnostic support
FIGURE 18-1: UART TRANSMITTER BLOCK DIAGRAM
Write Write
UTX8 UxTXREG Low Byte
Load TSR
Transmit Control
Control TSR
Control Buffer
Generate Flags
Generate Interrupt
Control and Status bits
UxTXIF
Data
0 (START)
1 (STOP)
Parity Parity
Generator
Transmit Shift Register (UxTSR)
16 Divider
Control
Signals
16X Baud Clock
from Baud Rate
Generator
Internal Data Bus
UTXBRK
Note: x = 1 or 2.
UxTX
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DS70082A-page 120 Advance Information 2002 Microchip Technology Inc.
FIGURE 18-2: UART RECEIVER BLOCK DIAGRAM
Read
URX8 UxRXREG Low Byte
Load RSR
UxMODE
Receive Buffer Control
Generate Flags
Generate Interrupt
UxRXIF
UxRX
· START bit Detect
Receive Shift Register
16 Divider
Control
Signals
UxSTA
Shift Data Characters
Read Read
Write Write
to Buffer
8-9
(UxRSR)
PERR
FERR
· Parity Check
· STOP bit Detect
· Shift Clock Generation
· Wake Logic
16
Internal Data Bus
1
0
LPBACK
From UxTX
16X Baud Clock from
Baud Rate Generato r
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18.2 Enabling and Setting Up UART
18.2.1 ENABLING THE UAR T
The UART module is enabled by setting the UARTEN
bit in the UxMODE register (where x = 1 or 2). Once
enabled , the UxTX and UxRX pins are configu red as an
output and an input respectively, overriding the TRIS
and LATCH register bit settings for the corresponding
I/O port pin. The UxTX pin is at logic 1 when no
transmission is taking place.
18.2.2 DISABLING THE UART
The UART module is disabled by clearing the
UARTEN bit in the UxMODE register. This is the
default s t a te a fter any RESET. If the UAR T is di sable d,
all I/O pins operate as port pins, under the control of
the latch and TRIS bits of the corresponding port pins.
Disabling the UART module resets the buffers to
empty states. Any data characters in the buffers are
lost, and the baud rate counter is reset.
All error and status flags associated with the UART
module are reset when the module is disabled. The
URXDA, OERR, FERR, PERR, UTXEN, UTXBRK and
UTXBF bits are cleared, whereas RIDLE and TRMT
are set. Other control bits, including ADDEN,
URXISEL<1:0>, UTXISEL, as well as the UxMODE
and UxBRG registers, are not affected.
Clearing the UARTEN bit while the UART is active will
abort all pending transmissions and receptions and
reset the module as defined above. Re-enabling the
UART will restart the UART in the same configuration.
18.2.3 ALT ERNAT E I/O
The alternate I/O function is enabled by setting the
ALTIO bit (UxMODE<10>). If ALTIO = 1, the UxATX
and UxARX pins (alternate transmit and alternate
receive pins, respectively) are used by the UART mod-
ule, instead of the UxTX and UxRX pins. If ALTIO = 0,
the UxTX and UxRX pins are used by the UART
module.
18.2.4 SETTING UP DATA, PARITY AND
STOP BIT SELECTIONS
Control bits PDSEL<1:0> in the UxSTA register are
used to select the data length and parity used in the
transmi ssion. The dat a length may eit her be 8-bi ts wi th
even, odd or no parity, or 9-bits with no parity.
The STSEL bit determines whether one or two STOP
bits will be used during data transmission.
The defau lt (Power-on) se tting of the UAR T is 8 bit s, no
parity, 1 STOP bit (typically represented as 8, N, 1).
18.3 Transmitting Data
18.3.1 TRANSMITTING IN 8-BIT DATA
MODE
The following steps must be performed in order to
transmit 8-bit data:
1. Set up the UART:
First, the data length, parity and number of
STOP bits must be selected, and then, the
Transmit and Receive Interrupt enable and pri-
ority bits are setup in the UxMODE and UxSTA
registers. Also, the appropriate baud rate value
must be written to the UxBRG register.
2. Enable the UART by setting the UARTEN bit
(UxMODE<15>).
3. Set the UTXEN bit (UxSTA<10>), thereby
enabling a transmission.
4. Write the data byte to be transmitted, to the
lower byte of UxTXREG. The value will be trans -
ferred to Transmit Shift register (UxTSR) imme-
diately and the seria l bit stream will sta rt shiftin g
out during the next rising edge of the baud clo ck.
5. A Transmit interrupt will be generated depend-
ing on the value of the interrupt control bit
UTXISEL (UxSTA<15>).
Alternatively, the data byte may be written while
UTXEN = 0, fo llow ing whi ch, the user may set UTXEN .
This will cause the serial bit stream to begin immedi-
ately because the baud clock will start from a cleared
state.
18.3.2 TRANSMITTING IN 9-BIT DATA
MODE
The sequence of steps involved in the transmission of
9-bit data is similar to 8-bit transmission, except that a
16-bit data word (of which the upper 7 bits are always
clear) must be written to the UxTXREG register.
18.3.3 TRANSMIT BUFFER (UXTXB)
The transmit buffer is 9-bits wide and 4 characters
deep. Including the Transmit Shift Register (UxTSR),
the user effectively has a 5-deep FIFO (First In First
Out) buffer. The UTXBF status bit (UxSTA<9>)
indicates whether the transmit buffer is full.
If a user attempts to write to a full buffer, the new data
will not be accepted into the FIFO, and no data shift
will occur within the buffer. This enables recovery from
a buffer overrun condition.
The FIFO is reset during any device RESET, but is not
affected when the device enters a Power Saving mode,
or wakes up from a Power Saving mode.
dsPIC30F
DS70082A-page 122 Advance Information 2002 Microchip Technology Inc.
18.3.4 TRANSMIT INTERRUPT
The transmit interrupt flag (U1TXIF or U2TXIF) is
located in the corresponding interrupt flag register.
The transmitter generates an edge to set the UxTXIF
bit. The condition of generating the interrupt depends
on UTXISEL control bit.
a) If UTXISEL = 0, an interrupt is generated when
a word is tra ns ferre d fro m the Transmit buffer to
Transmit Shift register (UxTSR). This implies
that the transmit buffer has at least one empty
word.
b) If UTXISEL = 1, an interrupt is generated when
a word is tra ns ferre d fro m the Transmit buffer to
Transmit Shift register (UxTSR) and the
Transmit buffer is empty.
Switching between the two interrupt modes during
operation is possible and sometimes offers more
flexibility.
18.3.5 TRANSMIT BREAK
Setting the UTXBRK bit (UxSTA<11>) will cause the
UxTX line to be driven to logic 0. The UTXBRK bit
overrides all transmission activity. Therefore, the user
should generally wait for the transmitter to be IDLE
before setting UTXBRK.
To send a break character, the UTXBRK bit must be
set by software and must remain set for a minimum of
13 baud cl oc k cy cl es . The UTX BR K b it is then cle a red
by softwa re to genera te ST OP bit s. The use r must wa it
for a duration of at least one or two baud clock cycles
in or der to en sure a valid ST OP bit(s ), befo re reloadin g
the UxTXB or starting other transmitter activity. Trans-
mission of a break character does not generate a
transmit interrupt.
18.4 Receiving Data
18.4.1 RECEIVING IN 8-BIT OR 9-BIT DATA
MODE
The following steps must be performed while receiving
8-bit or 9-bit data:
1. Set up the UART (see Section 18.3.1).
2. Enable the UART (see Section 18.3.1).
3. A receive interrupt will be generated when one
or more data bytes have been received,
depending on the receive interrupt settings
specified by the URXISEL bits (UxSTA<7:6>).
4. Read the OERR bit to determine if an overrun
error has occ urred. The OERR bit must be reset
in software.
5. Read the received dat a from UxRXREG. The act
of reading UxRXREG will move the next word to
the top of the receive FIFO, and the PERR and
FER R values will be update d.
18.4.2 RECEIVE BUFFER (UXRXB)
The receive buffer is 4-deep. Including the Receive
Shift register (UxRSR), the user effectively has a
5-deep FIFO (First In First Out) buffer.
URXDA (UxSTA<0>) = 1 indicates that the receive
buffer has data available. URXDA = 0 implies that the
buffer is empty. If a user attempts to read an empty
buffer, the old values in the buffer will be read, and no
data shift will occur within the FIFO.
The FIFO is reset during any device RESET. It is not
affected when the device enters a Power Saving mode
or wakes up from a Power Saving mode.
18.4.3 RECEIVE INTERRUPT
The receive interrupt flag (U1RXIF or U2RXIF) can be
read from the c orresp onding interru pt fla g register. The
interrupt flag is set by an edge generated by the
rece iver. The cond iti on f or se tti ng t he re ceiv e int err upt
flag depends on the settings specified by the
URXISEL<1:0> (UxSTA<7:6>) control bits.
a) If URXISEL<1:0> = 00 or 01, an interrupt is
generated every time a data word is transferred
from the Receive Shift Register (UxRSR) to the
Receive Buffer. There may be one or more
charact ers in the receive buffer.
b) If URXISEL<1:0> = 10, an interrupt is generated
when a word is transferred from the Receive
Shift Register (UxRSR) to the Receive Buffer
and as a result of the transfer, the Receive
Buffer contains 3 characters.
c) If URXISEL<1:0> = 11, an interrupt is set when
a word is transferred from the Receive Shift
Register (UxRSR) to the Receive Buffer and as
a result of the transfer, the Receive Buffer
contains 4 characters (i.e., becomes full).
Switching between the Interrupt modes during opera-
tion is possible, though generally not advisable during
normal operation.
18.5 Reception Error Handling
18.5.1 RECEIVE BUFFER OVERRUN
ERROR (OERR BIT)
The OERR bit (UxSTA<1>) is set if all of the following
conditions occur:
a) The receive buffer is full.
b) The receive shift register is full, but unable to
transfer the character to the receive buffer.
c) The STOP bit of the character in the UxRSR is
detected, indicating that the UxRSR needs to
transfer the character to the buffer.
Once OERR is set, no further data is shifted in UxRSR
(until the OERR bit is cleared in software or a RESET
occurs). The data held in UxRSR and UxRXREG
remains val id.
2002 Microchip Technology Inc. Advance Information DS70082A-page 123
dsPIC30F
18.5.2 FRAMING ERROR (FERR)
The FERR bit (UxSTA<2>) is set if a 0 is detected
instead of a STOP bit. If two STOP bits are selected,
both STOP bits must be 1, otherwise FERR will be set.
The read only FERR bit is buffered along with the
received data. It i s cle ared on any RESET.
18.5.3 PARITY ERROR (PERR)
The PERR bit (UxSTA<3>) is set if the parity of the
received word is incorrect. This error bit is applicable
only if a Parity mode (odd or even) is selected. The
read only PERR bit is buffered along with the received
data bytes. It is cleared on any RESET.
18.5.4 IDLE STATUS
When the receiver is active, i.e., between the initial
detection of the START bit and the completion of the
STOP bit, the RIDLE bit (UxSTA<4>) is 0. Between
the completion of the STOP bit and detection of the
next START bit, the RIDLE bit is 1, indicating that the
UART is IDLE.
18.5.5 REC EIV E BRE AK
The receiver will count and expect a certain number of
bit times based on the values programmed in the
PDSEL (UxMODE<2:1>) and STSEL (UxMODE<0>)
bits.
If the break is much longer than 13 bit times, the
reception is considered complete after the number of
bit times specified by PDSEL and STSEL. The
URXDA bit is set, FERR is set, zeros are loaded into
the receive FIFO, interrupts are generated, if
appropr iate and the RIDLE bit is set.
When the module receives a lo ng b r ea k s ign al a nd th e
receiver has detected the START bit, the data bits and
the invalid STOP bit (which sets the FERR), the
receiver must wait for a valid STOP bit before looking
for the next START bit. It cannot assume that the
break condition on the line is the next START bit.
Break is regarded as a character containing all 0s,
with the FERR bit set. The break character is loaded
into the buffer. No further reception can occur until a
STO P bit is rece ived. Note that R IDLE goes hi gh whe n
the STOP bit has not been received yet.
18.6 Address Detect Mode
Setting the ADDEN bit (UxSTA<5>) enables this spe-
cial mode, in which a 9th bit (URX8) value of 1 identi-
fies the received word as an address rather than data.
This m ode is o nly a pplicable for 9-bit dat a co mm un ic a-
tion. The URXISEL control bit does not have any
impact on interrupt generation in this mode, since an
interrupt (if enabled) will be generated every time the
received word has the 9th bit set.
18.7 Loopback Mode
Setting the LPBACK bit enables this special mode, in
which the UxT X pin is int ernally conne cted to the UxRX
pin. Whe n configured f or the loop back mode, the UxRX
pin is disconnected from the internal UART receive
logic. However, the UxTX pin still functions as in a
normal operation.
To select this mode:
a) Configure UART for desired mode of operation.
a) Set LPBACK = 1 to enable Loopback mode.
b) Enable transmis si on as def ined in Section 18.3.
18.8 Baud Rate Generator
The UART has a 16-bit baud rate generator to allow
maximum flexibility in baud rate generation. The baud
rate generator register (UxBRG) is readable and
writable. The baud rate is computed as follows:
BRG = 16-bit value held in UxBRG register
(0 through 65535)
FCY = Instruction Clock Rate (1/TCY)
The equation for the Baud Rate is given below.
EQUATION 18-1: BAUD RATE
Therefore, maximum baud rate possible is = FCY /16
(if BRG = 0),
and minimum baud ra te possible is = FCY / (16* 65 536).
With a full 16-bit baud rate generator, at 30 MIPs
operation, the minimum baud rate achievable is
28.5 bps.
18.9 Auto Baud Support
To allow the system to determine baud rates of
received characters, the input can be optionally linked
to a selected capture input. To enable this mode, the
user must program the input capture module to detect
the falling and rising edges of the START bit.
Baud Rate = FCY / (16*(BRG+1))
dsPIC30F
DS70082A-page 124 Advance Information 2002 Microchip Technology Inc.
18.10 UART Operation During CPU
SLEEP and IDLE Modes
18.10.1 UART OPERATION DURING CPU
SLEEP MODE
When the device enters SLEEP mode, all clock
sources to the module are shutdown and stay at logic
0. If entry into SLEEP mode occurs while a transmis-
sion is in progress, then the transmission is aborted.
The UxTX pin is driven to logic 1. Similarly, if entry
into SLEEP mode occurs while a reception is in
progress, then the reception is aborted. The UxSTA,
UxMODE, transmit and receive registers and buffers,
and the UxBRG register are not affected by SLEEP
mode.
If the WAKE bit (UxSTA<7>) is set before the device
enters SLEEP mode, then a falling edge on the UxRX
pin will generate a receive interrupt. The Receive
Interrupt Select mode bit (URXISEL) has no effect for
this function. If the receive interrupt is enabled, then
this will wake-up the device from SLEEP. The
UARTEN bit must be set in order to generate a
wake-up interrupt.
18.10.2 UART OPERATION DURING CPU
IDLE MODE
For the UART, the USIDL bit selects if the module will
stop operation when the device enters IDLE mode, or
whether the module will continue on IDLE. If
USIDL = 0, the module will continue operation during
IDLE mode. If USIDL = 1, the module will stop on
IDLE.
2002 Microchip Technology Inc.
Advance Inf ormat ion
DS70082A-page 125
dsPIC30F
TABLE 18-1: UART1 REGISTER MAP
TABLE 18-2: UART2 REGISTER MAP
SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RESET State
U1MODE 020C UARTEN USIDL ALTIO WAKE LPBACK ABAUD PDSEL1 PDSEL0 STSEL 0000 0000 0000 0000
U1STA 020E UTXISEL UTXBRK UTXEN UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA 0000 0001 0001 0000
U1TXREG 0210 UTX8 Transmit Register 0000 000u uuuu uuuu
U1RXREG 0212 URX8 Receive Register 0000 0000 0000 0000
U1BRG 0214 Baud Rate Generator Prescaler 0000 0000 0000 0000
Legend: u = uninitialized bit
SFR
Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RESET State
U2MODE 0216 UARTEN USIDL WAKE LPBACK ABAUD PDSEL1 PDSEL0 STSEL 0000 0000 0000 0000
U2STA 0218 UTXISEL UTXBRK UTXEN UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA 0000 0001 0001 0000
U2TXREG 021A UTX8 Transmit Register 0000 000u uuuu uuuu
U2RXREG 021C URX8 Receive Register 0000 0000 0000 0000
U2BRG 021E Baud Rate Generator Prescaler 0000 0000 0000 0000
Legend: u = uninitialized bit
dsPIC30F
DS70082A-page 126 Advance Information 2002 Microchip Technology Inc.
NOTES:
2002 Microchip Technology Inc. Advance Information DS70032D-page 127
dsPIC30F
19.0 CAN MODULE
19.1 Overview
The Controller Area Network (CAN) module is a serial
interfac e, useful for communicating with other peripher-
als or microcontroller devices. This interface/protocol
was designed to allow communications within noisy
environments.
The C AN mo du le i s a co mm un i ca tio n co ntr o ll er i mp le -
menting the CAN 2.0 A/B protocol, as defined in the
BOSCH specification. The module will support CAN
1.2, CAN 2.0A, CAN2.0B Passive, and CAN 2.0B
Active v ersio ns of th e protocol. Th e m od ule im ple me n-
tation is a Full CAN system. The CAN specific ation is
not covered within this data sheet. The reader may
refer to the BOSCH CAN specification for further
details.
The module features are as follows:
Implementation of the CAN protocol CAN1.2,
CAN2.0A and CAN2.0B
Standard and extended data frames
0 - 8 byte s data length
Programmable bit rate up to 1 Mbit/sec
Support for remote frames
Double buffered receiver with two prioritized
received message storage buffers (each buffer
may contain up to 8 bytes of data)
6 full (s t an dard/extended id entifier) accepta nc e fi l-
ters, 2 associated with the high priority receive
buffer, and 4 associated with the low priority
rece ive buffer
2 full acceptance filter masks, one each associ-
ated wit h the high and l ow priority r eceive buffers
Three transmit buffers with application specified
priori tization and abort c apabilit y (each buf fer may
contain up to 8 bytes of data)
Programmable wake-up functionality with
integrated low pass filter
Programm abl e L oop ba ck m ode su pports s elf-test
operation
Signaling via interrupt capabilities for all CAN
receiver and transmitter error states
Programmable clock source
Programmable link to timer module for time-
stamping and network synchronization
Low power SLEEP mode
19.1.1 OVERVIEW OF THE MODULE
The CAN bus module consists of a Protocol Engine
and message buffering and control. The CAN protocol
engine ha ndles all func tions fo r receiv ing and trans mit-
ting messages on the CAN bus. Messages are trans-
mitted by first loading the appropriate data registers.
Status and errors can be checked by reading the
appropriate registers. Any message detected on the
CAN bus is checked for errors and then matched
against filters to see if i t sh oul d be r ece iv ed a nd s tore d
in one of the 2 receive registers.
The CAN Module supports the following Frame types:
Standard Data Frame
Extended Data Frame
Remote Frame
Error Frame
Overload Frame Reception
Interframe Space
19.1.2 TRANSMIT/RECEIVE BUFFERS
The dsPIC30F has three transmit an d two receive buff-
ers, two acceptance masks (one for each receive
buffer), and a total of six acceptance filters. Figure 19-1
is a blo ck diagram of the se buffers and their connec tion
to the protocol engine.
dsPIC30F
DS70032D-page 128 Advance Information 2002 Microchip Technology Inc.
FIGURE 19-1: CAN BUFFERS AND PROTOCOL ENGINE BLOCK DIAGRAM
Acceptance Filter
RXF2
R
X
B
1
A
c
c
e
p
t
A
c
c
e
p
t
Identifier
Data Field Data Field
Identifier
Acceptance Mask
RXM1
Acceptance Filter
RXF3
Acceptance Filter
RXF4
Acceptance Filter
RXF5
M
A
B
Acceptance Mask
RXM0
Acceptance Filter
RXF0
Acceptance Filter
RXF1
R
X
B
0
MSGREQ
TXB2
TXABT
TXLARB
TXERR
MTXBUFF
MESSAGE
Message
Queue
Control T ransmit Byte Sequencer
MSGREQ
TXB1
TXABT
TXLARB
TXERR
MTXBUFF
MESSAGE
MSGREQ
TXB0
TXABT
TXLARB
TXERR
MTXBUFF
MESSAGE
Receive ShiftTransmit Shift
Receive
Error
Transmit
Error
Protocol
RERRCNT
TERRCNT
ErrPas
BusOff
Finite
State
Machine
Counter
Counter
Transmit
Logic
Bit
Timing
Logic
CxTX CxRX
Bit Timing
Generator
PROTOCOL
ENGINE
BUFFERS
CRC Check
CRC Generator
Note: x = 1 or 2.
2002 Microchip Technology Inc.
Advance Inf ormat ion
DS70032D-page 129
dsPIC30F
TABLE 19-1: CAN1 REGISTER MAP
SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RESET State
C1RXF0SID 0300 Receive Acceptance Filter 0 Standard Identifier Filter EXIDEN EID17 EID16 uuuu uuuu uuu0 u0uu
C1RXF0EID 0302 Receive Acceptance Filter 0 Extended Identifier uuuu uuuu uuuu uuuu
C1RXF1SID 0304 Receive Acceptance Filter 1 Standard Identifier Filter EXIDEN EDI17 EID16 uuuu uuuu uuu0 u0uu
C1RXF1EID 0306 Receive Acceptance Filter 1 Extended Identifier uuuu uuuu uuuu uuuu
C1RXF2SID 0308 Receive Acceptance Filter 2 Standard Identifier Filter EXIDEN EID17 EID16 uuuu uuuu uuu0 u0uu
C1RXF2EID 030A Receive Acceptance Filter 2 Extended Identifier uuuu uuuu uuuu uuuu
C1RXF3SID 030C Receive Acceptance Filter 3 Standard Identifier Filter EXIDEN EID17 EID16 uuuu uuuu uuu0 u0uu
C1RXF3EID 030E Receive Acceptance Filter 3 Extended Identifier uuuu uuuu uuuu uuuu
C1RXF4SID 0310 Receive Acceptance Filter 4 Standard Identifier Filter EXIDEN EID17 EID16 uuuu uuuu uuu0 u0uu
C1RXF4EID 0312 Receive Acceptance Filter 4 Extended Identifier uuuu uuuu uuuu uuuu
C1RXF5SID 0314 Receive Acceptance Filter 5 Standard Identifier Filter EXIDEN EID17 EID16 uuuu uuuu uuu0 u0uu
C1RXF5EID 0316 Receive Acceptance Filter 5 Extended Identifier uuuu uuuu uuuu uuuu
C1RXM0SID 0318 Receive Acceptance Mask 0 Standard Identifier Mask EID17 EID16 uuuu uuuu uuu0 00uu
C1RXM0EID 031A Receive Acceptance Mask 0 Extended Identifier Mask uuuu uuuu uuuu uuuu
C1RXM1SID 031C Receive Acceptance Mask 1 Standard Identifier Mask EID17 EID16 uuuu uuuu uuu0 00uu
C1RXM1EID 031E Receive Acceptance Mask 1 Extended Identifier Mask uuuu uuuu uuuu uuuu
C1TX2CON 0320 TXRTR DLC<3:0> TXABT TXLARB TXERR TXREQ TXPRI<1:0> 0000 0000 0000 0000
C1TX2SID 0322 Transmit Buffer 2 Standard Identifier EXIDE EID17 EID16 uuuu uuuu uuu0 u0uu
C1TX2EID 0324 Transmit Buffer 2 Extended Identifier uuuu uuuu uuuu uuuu
C1TX2B1 0326 Transmit Buffer 2 Byte 1 Transmit Buffer 2 Byte 0 uuuu uuuu uuuu uuuu
C1TX2B2 0328 Transmit Buffer 2 Byte 3 Transmit Buffer 2 Byte 2 uuuu uuuu uuuu uuuu
C1TX2B3 032A Transmit Buffer 2 Byte 5 Transmit Buffer 2 Byte 4 uuuu uuuu uuuu uuuu
C1TX2B4 032C Transmit Buffer 2 Byte 7 Transmit Buffer 2 Byte 6 uuuu uuuu uuuu uuuu
C1TX1CON 0330 TXRTR DLC<3:0> TXABT TXLARB TXERR TXREQ TXPRI<1:0> 0000 0000 0000 0000
C1TX1SID 0332 Transmit Buffer12 Standard Identifier EXIDE EID17 EID16 uuuu uuuu uuu0 u0uu
C1TX1EID 0334 Transmit Buffer 1 Extended Identifier uuuu uuuu uuuu uuuu
C1TX1B1 0336 Transmit Buffer 1 Byte 1 Transmit Buffer 1 Byte 0 uuuu uuuu uuuu uuuu
C1TX1B2 0338 Transmit Buffer 1 Byte 3 Transmit Buffer 1 Byte 2 uuuu uuuu uuuu uuuu
C1TX1B3 033A Transmit Buffer 1 Byte 5 Transmit Buffer 1 Byte 4 uuuu uuuu uuuu uuuu
C1TX1B4 033C Transmit Buffer 1 Byte 7 Transmit Buffer 1 Byte 6 uuuu uuuu uuuu uuuu
C1TX0CON 0340 TXRTR DLC<3:0> TXABT TXLARB TXERR TXREQ TXPRI<1:0> 0000 0000 0000 0000
C1TX0SID 0342 Transmit Buffer STARTD Identifer EXIDE EID17 EID16 uuuu uuuu uuu0 u0uu
C1TX0EID 0344 Transmit Buffer Extended Identifier uuuu uuuu uuuu uuuu
C1TX0B1 0346 Transmit Buffer 0 Byte 1 Transmit Buffer 0 Byte 0 uuuu uuuu uuuu uuuu
C1TX0B2 0348 Transmit Buffer 0 Byte 3 Transmit Buffer 0 Byte 2 uuuu uuuu uuuu uuuu
C1TX0B3 034A Transmit Buffer 0 Byte 5 Transmit Buffer 0 Byte 4 uuuu uuuu uuuu uuuu
Legend: u = uninitialized bit
dsPIC30F
DS70032D-page 130 Advance Information
2002 Microchip Technology Inc.
C1TX0B4 034C Transmit Buffer 0 Byte 7 Transmit Buffer 0 Byte 6 uuuu uuuu uuuu uuuu
C1RX1CON 0350 RXRTR RB1 RB0 DLC<3:0> RXFUL RXM<1:0> RXRTRO FILHIT<2:0> 0000 0000 0000 0000
C1RX1SID 0352 Receive Buffer 1 Standard Identi fier SRR EXID EID17 EDI16 uuuu uuuu uuuu u0uu
C1RX1EID 0354 Receive Buffer 1 Extended Identifer uuuu uuuu uuuu uuuu
C1RX1B1 0356 Receive Buffer 1 Byte 1 Receive Buffer 1 Byte 0 uuuu uuuu uuuu uuuu
C1RX1B2 0358 Receive Buffer 1 Byte 3 Receive Buffer 1 Byte 2 uuuu uuuu uuuu uuuu
C1RX1B3 035A Receive Buffer 1 Byte 5 Receive Buffer 1 Byte 4 uuuu uuuu uuuu uuuu
C1RX1B4 035C Receive Buffer 1 Byte 7 Receive Buffer 1 Byte 6 uuuu uuuu uuuu uuuu
C1RX0CON 0360 RXRTR RB1 RB0 DLC<3:0> RXFUL RXM<1:0> RXRTRO DBEN JTOFF FILHIT0 0000 0000 0000 0000
C1RX0SID 0362 Receive Buffer 0 Standard Identi fier SRR EXID EID17 EID16 uuuu uuuu uuuu u0uu
C1RX0EID 0364 Receive Buffer 0 Extended Identifer uuuu uuuu uuuu uuuu
C1RX0B1 0366 Receive Buffer 0 Byte 1 Receive Buffer 0 Byte 0 uuuu uuuu uuuu uuuu
C1RX0B2 0368 Receive Buffer 0 Byte 3 Receive Buffer 0 Byte 2 uuuu uuuu uuuu uuuu
C1RX0B3 036A Receive Buffer 0 Byte 5 Receive Buffer 0 Byte 4 uuuu uuuu uuuu uuuu
C1RX0B4 036C Receive Buffer 0 Byte 7 Receive Buffer 0 Byte 6 uuuu uuuu uuuu uuuu
C1CTRL 036E CSIDLE ABAT REQOP<2:0> OPMODE<2:0> ICODE<2:0> 0000 0100 1000 0000
C1CFG1 0370 SJWS<1:0> BRP<5:0> 0000 0000 0000 0000
C1CFG2 0372 CANCAP WAKFIL SEG2PH<2:0> BTLMODE SAM SEG1PH<2:0> PRSEG<2:0> uu00 0uuu uuuu uuuu
C1INTF 0374 RX0OVR RX1OVR TXBO TXEP RXEP TXWAR RXWAR EWARN IVRIF WAKIF ERRIF TX2IF TX1IF TX0IF RX1IF RX0IF 0000 0000 0000 0000
C1INTE 0376 IVRIE WAKIE ERRIE TX2IE TX1IE TX0IE RX1E RX0IE 0000 0000 0000 0000
C1EC 0378 Transmit Error Count Register Receive Error Count Register 0000 0000 0000 0000
TABLE 19-1: CAN1 REGISTER MAP (CONTINUED)
SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RESET State
Legend: u = uninitialized bit
2002 Microchip Technology Inc.
Advance Inf ormat ion
DS70032D-page 131
dsPIC30F
TABLE 19-2: CAN2 REGISTER MAP
SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RESET State
C2RXF0SID 0380 Receiv e Acceptance Filter 0 Standard Identifier Filter EXIDEN EID17 EID16 uuuu uuuu uuu0 u0uu
C2RXF0EID 0382 Receive Acceptance Filter 0 Extended Identifier uuuu uuuu uuuu uuuu
C2RXF1SID 0384 Receiv e Acceptance Filter 1 Standard Identifier Filter EXIDEN EDI17 EID16 uuuu uuuu uuu0 u0uu
C2RXF1EID 0386 Receive Acceptance Filter 1 Extended Identifier uuuu uuuu uuuu uuuu
C2RXF2SID 0388 Receiv e Acceptance Filter 2 Standard Identifier Filter EXIDEN EID17 EID16 uuuu uuuu uuu0 u0uu
C2RXF2EID 038A Receive Acceptance Filter 2 Extended Identifier uuuu uuuu uuuu uuuu
C2RXF3SID 038C Receiv e Acceptance Filter 3 Standard Identifier Filter EXIDEN EID17 EID16 uuuu uuuu uuu0 u0uu
C2RXF3EID 038E Receive Acceptance Filter 3 Extended Identifier uuuu uuuu uuuu uuuu
C2RXF4SID 0390 Receiv e Acceptance Filter 4 Standard Identifier Filter EXIDEN EID17 EID16 uuuu uuuu uuu0 u0uu
C2RXF4EID 0392 Receive Acceptance Filter 4 Extended Identifier uuuu uuuu uuuu uuuu
C2RXF5SID 0394 Receiv e Acceptance Filter 5 Standard Identifier Filter EXIDEN EID17 EID16 uuuu uuuu uuu0 u0uu
C2RXF5EID 0396 Receive Acceptance Filter 5 Extended Identifier uuuu uuuu uuuu uuuu
C2RXM0SID 0398 Receive Acceptance Mask 0 St andard Identifier Mask EID17 EID16 uuuu uuuu uuu0 00uu
C2RXM0EID 039A Receive Acceptance Mask 0 Extended Identifier Mask uuuu uuuu uuuu uuuu
C2RXM1SID 039C Receive Acceptance Mask 1 St andard Identifier Mask EID17 EID16 uuuu uuuu uuu0 00uu
C2RXM1EID 039E Receive Acceptance Mask 1 Extended Identifier Mask uuuu uuuu uuuu uuuu
C2TX2CON 03A0 TXRTR DLC<3:0> TXABT TXLARB TXERR TXREQ TXPRI<1:0> 0000 0000 0000 0000
C2TX2SID 03A2 Transmit Buffer 2 Standard Identifier EXIDE EID17 EID16 uuuu uuuu uuu0 u0uu
C2TX2EID 03A4 Transmit Buffer 2 Extended Identifier uuuu uuuu uuuu uuuu
C2TX2B1 03A6 Transmit Buffer 2 Byte 1 Transmit Buffer 2 Byte 0 uuuu uuuu uuuu uuuu
C2TX2B2 03A8 Transmit Buffer 2 Byte 3 Transmit Buffer 2 Byte 2 uuuu uuuu uuuu uuuu
C2TX2B3 03AA Transmit Buffer 2 B yte 5 Transmit Buffer 2 Byte 4 uuuu uuuu uuuu uuuu
C2TX2B4 03AC Transmit Buffer 2 Byte 7 Transmit Buffer 2 Byte 6 uuuu uuuu uuuu uuuu
C2TX1CON 03B0 TXRTR DLC<3:0> TXABT TXLARB TXERR TXREQ TXPRI<1:0> 0000 0000 0000 0000
C2TX1SID 03B2 Transmit Buffer12 Standard Identifier EXIDE EID17 EID16 uuuu uuuu uuu0 u0uu
C2TX1EID 03B4 Transmit Buffer 1 Extended Identifier uuuu uuuu uuuu uuuu
C2TX1B1 03B6 Transmit Buffer 1 Byte 1 Transmit Buffer 1 Byte 0 uuuu uuuu uuuu uuuu
C2TX1B2 03B8 Transmit Buffer 1 Byte 3 Transmit Buffer 1 Byte 2 uuuu uuuu uuuu uuuu
C2TX1B3 03BA Transmit Buffer 1 B yte 5 Transmit Buffer 1 Byte 4 uuuu uuuu uuuu uuuu
C2TX1B4 03BC Transmit Buffer 1 Byte 7 Transmit Buffer 1 Byte 6 uuuu uuuu uuuu uuuu
C2TX0CON 03C0 TXRTR DLC<3:0> TXABT TXLARB TXERR TXREQ TXPRI<1:0> 0000 0000 0000 0000
C2TX0SID 03C2 Transmit Buffer STARTD Identifer EXIDE EID17 EID16 uuuu uuuu uuu0 u0uu
C2TX0EID 03C4 Transmit Buffer Extended Identifier uuuu uuuu uuuu uuuu
C2TX0B1 03C6 Transmit Buffer 0 By te 1 Transmit Buffer 0 Byte 0 uuuu uuuu uuuu uuuu
C2TX0B2 03C8 Transmit Buffer 0 By te 3 Transmit Buffer 0 Byte 2 uuuu uuuu uuuu uuuu
Legend: u = uninitialized bit
dsPIC30F
DS70032D-page 132 Advance Information
2002 Microchip Technology Inc.
C2TX0B3 03CA Transmit Buffer 0 By te 5 Transmit Buffer 0 Byte 4 uuuu uuuu uuuu uuuu
C2TX0B4 03CC Transmit Buffer 0 Byte 7 Transmit Buffer 0 Byte 6 uuuu uuuu uuuu uuuu
C2RX1CON 03D0 RXRTR RB1 RB0 DLC<3:0> RXFUL RXM<1:0> -RXRTRO FILHIT<2:0> 0000 0000 0000 0000
C2RX1SID 03D2 Receive Buffer 1 S tandard Identifier SRR EXID EID17 EDI16 uuuu uuuu uuuu u0uu
C2RX1EID 03D4 Receive Buffer 1 Extended Identifer uuuu uuuu uuuu uuuu
C2RX1B1 03D6 Receive Buffer 1 B yte 1 Receive Buffer 1 Byte 0 uuuu uuuu uuuu uuuu
C2RX1B2 03D8 Receive Buffer 1 B yte 3 Receive Buffer 1 Byte 2 uuuu uuuu uuuu uuuu
C2RX1B3 03DA Receiv e Buffer 1 Byte 5 Receive Buffer 1 Byte 4 uuuu uuuu uuuu uuuu
C2RX1B4 03DC Receive Buffer 1 Byte 7 Receive Buffer 1 Byte 6 uuuu uuuu uuuu uuuu
C2RX0CON 03E0 RXRTR RB1 RB0 DLC<3:0> RXFUL RXM<1:0> RXRTRO DBEN JTOFF FILHIT0 0000 0000 0000 0000
C2RX0SID 03E2 EXID EID17 EID16 uuuu uuuu uuuu u0uu
C2RX0EID 03E4 Receive Buffer 0 Extended Identifer uuuu uuuu uuuu uuuu
C2RX0B1 03E6 Receive Buffer 0 Byte 1 Receive Buffer 0 Byte 0 uuuu uuuu uuuu uuuu
C2RX0B2 03E8 Receive Buffer 0 Byte 3 Receive Buffer 0 Byte 2 uuuu uuuu uuuu uuuu
C2RX0B3 03EA Receive Buffer 0 Byte 5 Receive Buffer 0 Byte 4 uuuu uuuu uuuu uuuu
C2RX0B4 03EC Receive Buffer 0 Byte 7 Receive Buffer 0 Byte 6 uuuu uuuu uuuu uuuu
C2CTRL 03EE CSIDLE ABAT REQOP<2:0> OPMODE<2:0> ICODE<2:0> 0000 0100 1000 0000
C2CFG1 03F0 SJWS<1:0> BRP<5:0> 0000 0000 0000 0000
C2CFG2 03F2 CANCAP WAKFIL SEG2PH<2:0> BTLMODE SAM SEG1PH<2:0> PRSEG<2:0> uu00 0uuu uuuu uuuu
C2INTF 03F4 RX0OVR RX1OVR TXBO TXEP RXEP TXWAR RXWAR EWARN IVRIF WAKIF ERRIF TX2IF TX1IF TX0IF RX1IF RX0IF 0000 0000 0000 0000
C2INTE 03F6 IVRIE WAKIE ERRIE TX2IE TX1IE TX0IE RX1E RX0IE 0000 0000 0000 0000
C2EC 03F8 Transmit Error Count Register Receive Error Count Register 0000 0000 0000 0000
TABLE 19-2: CAN2 REGISTER MAP (CONTINUED)
SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RESET State
Legend: u = uninitialized bit
2002 Microchip Technology Inc. Advance Information DS70082A-page 133
dsPIC30F
20.0 10-BIT HIGH SPEED ANALOG-
TO-DIGITAL CONVERTER (A/D)
MODULE
The10-bit high-speed analog-to-digital converter (A/D)
allows conversion of an analog input signal to a corre-
sponding 10-bit digital number. This module is based
on a Successive Approximation Register (SAR) archi-
tectur e, a nd prov id es a maximum sampling rate of 50 0
ksps. The A/D module has up to 16 analog inputs,
which are mul t ip le xed into four sample and hold ampli-
fiers. Th e output of th e sample an d hold is the in put into
the converter, which generates the result. The analog
reference volt ages are s oftware select able to e ither the
devi ce sup ply vol tag e (AVDD/AVSS) or the voltage level
on the (VREF+/VREF-) pin. The A/D converter has a
unique fe ature of being able to operate while the device
is in SLEEP mode.
The A/D module has six 16-bit registers.
A/D Control Register1 (ADCON1)
A/D Control Register2 (ADCON2)
A/D Control Register3 (ADCON3)
A/D Input Select Register (ADCHS)
A/D Port Configuration Register (ADPCFG)
A/D Input Scan Selection Register (ADCSSL)
The ADCON1, ADCON2 and ADCON3 registers con-
trol the operation of the A/D module. The ADCHS reg-
ister selects the input channels to be converted. The
ADPCFG register configures the port pins as analog
inputs or as digital I/O. The ADCSSL register selects
input s for sca nni ng .
The block diagram of the A/D module is shown in
Figure 20-1.
Note: The SSRC<2:0>, ASAM, SMPI<3:0>,
BUFM and ALTS bits, as well as the
ADCON3 and ADCSSL registers, must not
be written to while ADON = 1. This would
lead to indeterminate results.
dsPIC30F
DS70082A-page 134 Advance Information 2002 Microchip Technology Inc.
FIGURE 20-1: 10-BIT HIGH SPEED A/D FUNCTIONAL BLOCK DIAGRAM
S/H
+
-
10-bit Resu lt Conversion Logic
VREF+
AVSS
AVDD
ADC
Data
16-wor d, 10- bit
Dual Port
RAM
Bus Interface
AN12
AN0
AN5
AN7
AN9
AN13
AN14
AN15
AN12
AN1
AN2
AN3
AN4
AN6
AN8
AN10
AN11
AN13
AN14
AN15
AN8
AN9
AN10
AN11
AN4
AN5
AN6
AN7
AN0
AN1
AN2
AN3
CH1
CH2
CH3
CH0
AN5
AN2
AN11
AN8
AN4
AN1
AN10
AN7
AN3
AN0
AN9
AN6
AN1
VREF-
Sample/Sequence
Control
sample
CH1,CH2,
CH3,CH0
Input Mux
Control
input
switches
S/H
+
-
S/H
+
-
S/H
+
-
Format
2002 Microchip Technology Inc. Advance Information DS70082A-page 135
dsPIC30F
20.1 A/D Result Buffer
The module contains a 16-word dual port RAM, called
ADRES<15:0>, to buffer the A/D results. The RAM is
10-bits wide, but is read into different format 16-bit words.
Only word wr ites ar e all owed to the re sult b uf fer. If by te
writes are attempted, the results are indeterminate.
20.2 Conversion Operation
After the A/D module has been configured as desired, the
sampling is started by setting the SAMP bit. Various
sources, such as a programmable bit, timer time-outs and
external events, will terminate sampling and start a con-
version. When the A/D conversion is completed, the result
is loaded into ADRES<15:0>, the CONV bit is cleared,
and if, at t he correct number of samples as specified by
the SMPI bit, the A/D interrupt flag ADIF is set.
The following steps should be followed for doing an
A/D conversion:
1. Configure the A/D module:
Configure analog pins/voltage reference/and
digital I/O
Select A/D input channels
Selec t A/D conversi on cl ock
Select A/D con ver si on trig ger
Turn on A/D module
2. Configu re A/ D interrupt (if required):
Clear ADIF bit
Select A/D interrupt priority
3. Start sampling.
4. Wait the required sampling time.
5. Trigger sample end, start conversion:
Module sets CONV bit
6. Wait for A/D conversion to complete, by either:
Polling for the CONV bit to be cleared
Waiting for the A/D interrupt
7. Read A/D result buffer, clear ADIF if required.
20.3 Selecting the Conversion
Sequence
Several groups of control bits select the sequence that
the A/D connects inputs to the sample/hold channels,
converts channels, writes the buffer memory, and gen-
erates interrupts. The sequence is controlled by the
sampling clocks.
The SIMSAM bit controls the sample/convert sequ ence
for multi ple ch annels . If the SIM SAM bit is 0, the two or
four selected channels are sampled and converted
sequentially, with two or four sample clocks. If the
SIMSAM bit is 1, two or four selected channels are
sampled simultaneously, with one sample clock. The
channe ls are then converted sequ entially. Obviously, if
there is on ly 1 c ha nne l s el ec ted , th e SIM SAM bi t is n ot
applicable.
The CHPS bits selects how many channels are sam-
pled. This can vary from 1, 2 or 4 channels. If CHPS
selects 1 channel, the CH0 channel will be sampled
and at the sample clock, CH0 will be converted. The
result is stored in the buffer. If CHPS selects 2 chan-
nels, the CH0 and CH1 channels will be sampled and
convert ed. If CHPS s el ec t s 4 cha nne ls , the CH0, C H1,
CH2 and CH3 channels will be sampled and converted.
The SMPI bits will select the number of values loaded
into the buf fer before a n inte rrupt oc curs. T his c an var y
from 1 sample per interrupt, to 16 samples per
interrupt.
The user cannot program a combination of CHPS and
SMPI bits that specifies more than 16 conversions per
interrupt, or 8 conversions per interrupt, depending on
the BUFM bit. The BUFM bit, when set, will split the
16-word results buffer (ADRES) into two 8-word
groups. Writing to the 8-word buffers will be alternated
on each interrupt event. Use of the BUFM bit will
depend on how m uc h tim e is available for mov in g data
out of the buffers after the interrupt, as determined by
the application.
If the processor can quickly unload a full buffer within
the time it takes to sample and convert one channel,
the BUFM bit can be 0 and up to 16 conversions may
be done per interrupt. The processor will have one
sample and conversion time to move the sixteen
conversions.
If the processor cannot unload the buffer within the
sample and conversion time, the BUFM bit should be 1.
For example, if SMPI<3:0> (ADCON2<5:2>) = 0111,
then eight conversions will be loaded into 1/2 of the
buffer, following which, an interrupt occurs. The next
eight co nversions will b e loaded into the o ther 1/2 of the
buff er. The pro cessor w ill have the entir e time b etwee n
interrupts to move the eight conversions.
The ALTS bit can be used to alternate the inputs
select ed durin g the samp ling sequ ence. The i nput mu l-
tiplexer has two sets of sample inputs: SAMPLE A and
SAMPLE B. If the ALTS bit is 0, only the SAMPLE A
input s are selected for sa mpling. If the ALTS bit is 1 and
SMPI<3:0> = 0000, on the first sample/convert
sequence, the SAMPLE A inputs are selected, and on
the next sample/convert sequence, the SAMPLE B
inputs are selected .
The CSCNA bit (ADCON2<10>) will allow the CH0
channel inputs to be alternately scanned across a
selected number of analog inputs for the SAMPLE A
group. The inputs are selected by the ADCSSL regis-
ter. If a particular bit in the ADCSSL register is 1, the
corresponding input is selected. The inputs are always
scanne d from low er to higher numbered in puts, st arting
after each interrupt occurs. If the number of inputs
selec ted is greater than th e number of samp les taken
per interrupt, the higher numbered inputs are unused.
dsPIC30F
DS70082A-page 136 Advance Information 2002 Microchip Technology Inc.
20.4 Programming the Start of
Conversion Trigger
The sample trigger will terminate sampling and start the
requested convers ions.
The SSRC<2:0> bits select the source of the sample
trigger.
When SSRC<2:0> = 000, the sample trigger is under
software control. Clearing the SAMP bit will cause the
sample trigger.
When SSRC<2:0> = 111 (Auto Start mode) , the sam-
ple trigger is under A/D clock control. The SAMC bits
select the number of A/D clocks between the start of
sampli ng and the st art of c onvers ion. Th is prov ides the
fastest conversion rates on multiple channels. SAMC
must always be at least 1 clock cycle.
Other trigger sources can come from timer modules,
Motor Control PWM module, or external interrupts.
The SSRC bits provide for up to 5 alternate sources of
sample trigger.
20.5 Aborting a Conversion
Clearing the CONV bit during a conversion will abort
the cu rrent conv ersion a nd stop the sam pling sequ enc-
ing until the next sampling trigger. The ADRES will not
be updated with the partially completed A/D conversion
sample. Tha t is, the ADRES will continue to cont ain the
value of the last completed conversion (or the last
value written to the ADRES register).
If the clearing of the CONV bit coincides with an auto
start, the clearing has a higher priority.
After the A/D conversion is aborted, a 2 TAD wait is
required before the next sampling may be started by
setting the SAMP bit.
If sequent ial sampling is specified, the A/D will continue
at the next sample pulse which corresponds with the
next channel converted. If simultaneous sampling is
specified, the A/D will continue with the next
multi-channel group conversion sequence.
20.6 Selecting the A/D Conversion Clock
The A/D co nversi on requi res 11 TAD. The source of the
A/D conversion clock is software selected using a six
bit counter. There are 64 possible options for TAD.
EQUATION 20-1: A/D CONVERSION CLOCK
The internal RC oscillator is selected by setting the
ADRC bit.
For correct A/D conversions, the A/D conversion clock
(TAD) must be selected to ensure a minimum TAD time
of 150 nsec. Table 20-1 shows the resultant TAD times
derived from the device operating frequencies and the
A/D clock source se lected.
TABLE 20-1: TYPICAL TAD VS. DEVICE OPERATING FREQUENCIES
TAD = TCY * (0. 5*(ADCS <5:0> +1))
A/D Clock Period (TAD Values)
A/D Clock Source Select Device FCY
A/D
Clock ADRC ADCS<5:0> 30 MHz 25 MHz 12.5 MHz 6.25 MHz 1 MHz
TCY/2 0 000000 16.67 ns(2) 20 ns(2) 40 ns(2) 80 ns(2) 500 ns
TCY 0 000001 33.33 ns(2) 40 ns (2) 80 ns(2) 160 ns 1.0 µs
2 TCY 0 000011 66.66 ns(2) 80 ns(2) 160 ns 320 ns 2.0 µs(3)
4 TCY 0 000111 133.32 ns(2) 160 ns 320 ns 6 40 ns(3) 4.0 µs(3)
8 TCY 0 001111 266.64 ns 320 ns 640 ns(3) 1.28 µs(3) 8.0 µs(3)
16 TCY 0 011111 533.28 ns(3) 640 ns(3) 1.28 µs(3) 2.56 µs(3) 16.0 µs(3)
32 TCY 0 111111 1066.56 ns(3) 1280 ns(3) 2.56 µs(3) 5.12 µs(3) 32.0 µs(3)
RC 1 xxxxxx 200 - 400 n s(1,4) 200 - 40 0 ns(1,4) 200 - 400 ns(1,4) 200 - 400 ns(1,4) 200 - 400 ns(1)
Note 1: The RC source has a typical TAD time of 300 ns for VDD > 3.0V.
2: These values violate the minimum required TAD time.
3: For faster conversion times, the selection of another clock source is recommended.
4: A/D cannot meet full accuracy with RC clock source and FOSC > 20 MHz
2002 Microchip Technology Inc. Advance Information DS70082A-page 137
dsPIC30F
20.7 A/D Sampling Requirements
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 20-2. The
source impedance (RS) and the internal sampling
switch (RSS) impedance directly affect the time
required to charge the capa citor CHOLD. The sampling
switch (RSS) impedance va ries ov er the dev ice vol tag e
(VDD), see Figure 20-2. The impedance for analog
sources must be small enough to meet accuracy
requirem ents a t the given speed. After the anal og input
channel is selected (changed), this sampling must be
done before the conversion can be started.
To calculate the minimum sampling time, Equation 20-2
may be used. This equation assumes that the input is
stepped some multiple (n) of the LSB step size and the
output must be captured to within 1/2 LSb error (2096
steps for 10-bit A/D).
The CHOLD is assu med to be 5 pF for the A/D converter .
EQUATION 20-2: A/D SAMPLING TIME
EQUATIONS
FIGURE 20-2: ANALOG INPUT MODEL
VO=VI (1 e (-TC/CHOLD (RIC+RSS+RS)))
1 (VO / VI) = e
(-TC/CHOLD (RIC+RSS+RS))
VI=VIN VREF-
VO=n LSB 1/2 LSB
VO / VI= (n LSB 1/2 LSB) / n LSB
1 (VO / VI)= 1 / 2n
1 / 2n = e (-TC/CHOLD (RIC+RSS+RS))
TC= CHOLD (RIC+RSS+RS) -In(1/ 2 n)
TSMP = Amplifier Settling Time
+ Holding Capacitor Charging Time (TC)
+ Temperature Coefficie n t
The te mp erature coe ffici ent is only re qui red for
temperatures > 2 5°C.
TSMP = 0.5 ms
+ CHOLD (RIC+RSS+RS) -In(1/2 n)
+ [(Temp 25°C)(0.05 ms/°C)]
CPIN
VA
Rs ANx
5 pF
VT = 0.6V
VT = 0.6V I leakage
RIC 250
Sampling
Switch
SS RSS
CHOLD
= DAC capacitance
VSS
VDD
= 5 pF
± 500 nA
Legend: CPIN
VT
I leakage
RIC
SS
CHOLD
= input capacitance
= threshold voltage
= leakage current at the pin due to
= interconnec t resistance
= sampling switch
= sample/hold capacitance (from DAC)
various junctions
VDD (V)
3.5
2.5
2.0
1.5
1.0
234 5
(Rss k)
Sampling
3.0
0.5
06
Switch
Note: Values shown here are untested typical values, for reference only. Exact electrical specifications are to be determined.
dsPIC30F
DS70082A-page 138 Advance Information 2002 Microchip Technology Inc.
20.8 Module Power-down Modes
The module has 3 internal Power modes.
When the ADON bit is 1, the module is in Active mode
and is fully powered and functional.
When ADON is 0 and ADSTBY is 1, the module is in
Standb y mode . In Standby mode, th e digit al p ortions of
the module are active; however, the analog portions
are powered down, including the bias generators.
When ADON is 0 and ADSTBY is 0, the module is in Of f
mode. The dig ital and analog port ion s of the c irc uit are
disabled for maximum current savings.
In order to return to the Active mode from Standby or
Off mo de, the user must wai t fo r the bias generat ors to
stabilize.
20.9 A/D Oper ation During CPU SLEEP
and IDLE Modes
20.9.1 A/D OPERATION DURING CPU
SLEEP MODE
When the device enters SLEEP mode, all clock
sources to the module are shutdown and stay at logic
0.
If SLEEP occurs in the middle of a conversion, the
conversion is aborted. The converter will not continue
with a partially completed conversion on exiting from
SLEEP mode.
Register contents are not affected by the device
entering or leaving SLEEP mode.
The A/D module can operate during SLEEP mode, if
the A/D clock source is set to RC (ADRC = 1). When
the RC clock source is selected, the A/D module waits
for one i nstruc tion c ycle before s tar ting th e conv ersio n.
This allows the SLEEP instruction to be executed,
which eliminates all digital switching noise from the
conversion. When the conversion is completed, the
CONV bit will be cleared and the result loaded into the
ADRES register.
If the A/D interrupt is enabled, the device will wake-up
from SLEEP. If the A/D interrupt is not enabled, the
A/D module w ill then be tu rned of f , althoug h the ADON
bit will remain set.
20.9.2 A/D OPERATION DURING CPU IDLE
MODE
For the A/D, the ADSIDL bit selects if the module will
stop on IDLE or continue on IDLE. If ADSIDL = 0, the
module will continue operation on assertion of IDLE
mode. If ADSIDL = 1, the module will stop on IDLE.
20.10 Effects of a RESET
A device RESET forces all registers to their RESET
state. This forces the A/D module to be turned off, and
any conversion and sampling sequence are aborted.
The values that are in the ADRES registers are not
modified. The A/D result register will contain unknown
data after a Power-on Reset.
2002 Microchip Technology Inc. Advance Information DS70082A-page 139
dsPIC30F
20.11 Output Formats
The A/D result is 10-bits wide. The data buffer RAM is
also 1 0-bit s wid e. The 10-bi t dat a c an be read in on e of
four different formats. The FORM<1:0> bits select the
format. Eac h of the output formats translates to a 16-bit
result on the data bus.
Write data will always be in right justified (integer)
format.
FIGURE 20-3: A/D OUTPUT DATA FORMATS
20.12 Configuring Anal og Port Pins
The use of the ADPC FG and TRIS registers control the
operation of the A/D port pins. The port pins that are
desired as analog inputs must have their correspond-
ing TRIS bit set (input). If the TRIS bit is cleared (out-
put), the digital output level (VOH or VOL) will be
converted.
The A/D operation is independent of the state of the
CH0SA<3:0>/CH0SB<3:0> bits and the TRIS bits.
When read ing the POR T register, all pins confi gured as
analog in put channel w ill read as cleare d (a low lev el).
Pins configured as digital inputs, will not convert an
analog i nput. Analog leve ls on any pin that is defined as
a digital input (including the ANx pins), may cause the
input buffer to consume current that exceeds the
device specifications.
20.13 Connection Considerations
Since the analog inputs employ ESD protection, they
have diodes to VDD and VSS. This requires that the
analog input mus t be bet ween VDD and VSS. If the input
volt age exce eds this range by greater th an 0.3V (eith er
direction), one of the diodes becomes forward biased
and it may damage the device if the input current
specification is exceeded.
An external RC filter is sometimes added for anti-
aliasi ng of the input signal. The R compo nent should be
select ed to ens ure that th e sampl ing time requirem ents
are satisfied. Any external components connected (via
high impedance) to an analog input pin (capacitor,
zener diode, etc.) should have very little leakage
current at the pin.
RAM Contents: d09 d08 d07 d06 d05 d04 d03 d02 d01 d00
Read to Bus:
Signed Fractional (1.15) d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 0 0 0 0 0 0
Fractional (1.15) d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 0 0 0 0 0 0
Signed Integer d09 d09 d09 d09 d09 d09 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00
Integer 000000d09 d08 d07 d06 d05 d04 d03 d02 d01 d00
dsPIC30F
DS70082A-page 140 Advance Information
2002 Microchip Technology Inc.
TABLE 20-2: ADC REGISTER MAP
SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RE SET State
ADCBUF0 0280 ADC Data Buffer 0 uuuu uuuu uuuu uuuu
ADCBUF1 0282 ADC Data Buffer 1 uuuu uuuu uuuu uuuu
ADCBUF2 0284 ADC Data Buffer 2 uuuu uuuu uuuu uuuu
ADCBUF3 0286 ADC Data Buffer 3 uuuu uuuu uuuu uuuu
ADCBUF4 0288 ADC Data Buffer 4 uuuu uuuu uuuu uuuu
ADCBUF5 028A ADC Data Buffer 5 uuuu uuuu uuuu uuuu
ADCBUF6 028C ADC Data Buffer 6 uuuu uuuu uuuu uuuu
ADCBUF7 028E ADC Data Buffer 7 uuuu uuuu uuuu uuuu
ADCBUF8 0290 ADC Data Buffer 8 uuuu uuuu uuuu uuuu
ADCBUF9 0292 ADC Data Buffer 9 uuuu uuuu uuuu uuuu
ADCBUFA 0294 ADC Data Buffer 10 uuuu uuuu uuuu uuuu
ADCBUFB 0296 ADC Data Buffer 11 uuuu uuuu uuuu uuuu
ADCBUFC 0298 ADC Data Buffer 12 uuuu uuuu uuuu uuuu
ADCBUFD 029A ADC Data Buffer 13 uuuu uuuu uuuu uuuu
ADCBUFE 029C ADC Data Buffer 14 uuuu uuuu uuuu uuuu
ADCBUFF 029E ADC Data Buffer 15 uuuu uuuu uuuu uuuu
ADCON1 02A0 ADON ADSIDL ADSTBY FORM<1:0> SSRC<2:0> SIMSAM ASAM SAMP CONV 0000 0000 0000 0000
ADCON2 02A2 VCFG<2:0> OFFCAL CSCNA CHPS<1:0> BUFS SMPI<3:0> BUFM ALTS 0000 0000 0000 0000
ADCON3 02A4 SAMC<4:0> ADRC ADCS<5:0> 0000 0000 0000 0000
ADCHS 02A6 CH123NB<1:0> CH123SB CH0NB CH0SB<3:0> CH123NA<1:0> CH123SA CH0NA CH0SA<3:0> 0000 0000 0000 0000
ADPCFG 02A8 PCFG15 PCFG14 PCFG13 PCFG12 PCFG11 PCFG10 PCFG9 PCFG8 PCFG7 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 0000 0000 0000 0000
ADCSSL 02AA CSSL15 CSSL14 CSSL13 CSSL12 CSSL11 CSSL10 CSSL9 CSSL8 CSSL7 CSSL6 CSSL5 CSSL4 CSSL3 CSSL2 CSSL1 CSSL0 0000 0000 0000 0000
Legend: u = uninitialized bit
2002 Microchip Technology Inc. Advance Information DS70082A-page 141
dsPIC30F
21.0 SYSTEM INTEGRATION
There are several features intended to maximize sys-
tem reliability, minimize cost through elimination of
external compone nts, pro vide Power Sav ing Oper ating
modes and of fer code protection:
Oscillato r Selection
RESET
- Power-on Reset (P OR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Programmable Brown-out Reset (BOR)
Watchdog Timer (WDT)
Power Saving modes (SLEEP and IDLE)
Code Protection
Unit ID Locations
In-Circuit Serial Programming (ICSP)
dsPIC30F devices have a Watchdog Timer, which is
permanently enabled via the configuration bit s, or it can
be software controlled. It runs off its own RC oscillator
for added re liability. There are two timers that off er nec-
essary de la ys on p ow er-u p. On e is the O s cil la tor Start-
up Timer (OST), intended to keep the chip in RESET
until the crystal oscillator is stable. The other is the
Power-up Timer (PWRT), which provides a delay on
power-up only, designed to keep the part in RESET
while the power supply stabilizes. With these two tim-
ers on-chip, most applications need no external
RESET circuitry.
SLEEP mode is designed to offer a very low current
Power-down mode. The user can wake-up from
SLEEP through external RESET, Watchdog Timer
Wake-up or through an interrupt. Several oscillator
options are also made available to allow the part to fit
the application. In the IDLE mode, the clock sources
are still active, but the CPU is shut-off. The RC oscilla-
tor option saves system cost, while the LP crystal
option s aves power . A s et of configura tion bits are used
to select various options
21.1 Overview
The dsPIC30F oscillator system has the following
modules and features:
Various external and internal oscillator options as
clock sources
An on-chip PLL to boost internal operating
frequency
A clock switching mechanism between various
clock sources
Programm abl e c loc k pos t s ca ler f or s ys tem po wer
savings
A Fail-Safe Clock Monitor (FSCM) that detects
clock failure and takes fail-safe measures
Clock Control Register OSCCON
Configuration bits for main oscillator selection
Table 21-1 provides a summary of the dsPIC30F
Oscillat or Operating modes. A simplified diagram of the
oscillator system is shown in Figure 21-1.
TABLE 21-1: OSCILLATOR OPERATING MODES
Oscillator Mode Description
XTL 200 kHz - 4 MHz crystal on OSC1:OSC2.
XT 4 MHz - 10 MHz crystal on OSC1:OSC2.
XT w/ PLL 4x 4 MHz - 10 MHz crystal on OSC1:OSC2. 4x PLL enabled.
XT w/ PLL 8x 4 MHz - 10 MHz crystal on OSC1:OSC2. 8x PLL enabled.
XT w/ PLL 16x 4 MHz - 10 MHz crystal on OSC1:OSC2. 16x PLL enabled(1).
LP 32 kHz crystal on SOSC1:SOSC2(2).
HS 10 MH z - 25 MHz crystal.
EC External clock input (0 - 40 MHz).
ECIO External clock input (0 - 40 MHz). OSC2 pin is I/O.
EC w/ PLL 4x External clock input (0 - 40 MHz). OSC2 pin is I/O. 4x PLL enabled(1).
EC w/ PLL 8x External clock input (0 - 40 MHz). OSC2 pin is I/O. 8x PLL enabled(1).
EC w/ PLL 16x External clock input (0 - 40 MHz). OSC2 pin is I/O. 16x PLL enabled(1).
ERC External RC oscillator. OSC2 pin is FOSC/4 output(3).
ERCIO External RC oscillator. OSC2 pin is I/O(3).
FRC 8 MHz internal RC Oscillator.
LPRC 32 kHz internal RC Oscillator.
Note 1: dsPIC30F maximum operating frequency of 120 MHz must be met.
2: LP oscillator can be conveniently shared as system clock, as well as real-time clock for Timer1.
3: Requires external R and C. Frequency operation up to 4 MHz.
dsPIC30F
DS70082A-page 142 Advance Information 2002 Microchip Technology Inc.
Configuration bits determine the clock source upon
Power-on Reset (POR) and Brown-out Reset (BOR).
Thereafte r, cloc k source ca n be change d between per-
missible clock sources. The OSCCON register con-
trols the clock switching and reflects system clock
related status bits.
FIGURE 21-1: OSCILLATOR SYSTEM BLOCK DIAGRAM
Primary
OSC1
OSC2
SOSC1
SOSC2
Oscillator
32 kHz LP
Clock
and Control
Block
Switching
Oscillator
x4, x8, x16
PLL
Primary
Oscillator
Stability Detector
Stability Detector
Secondary
Oscillator
Programmable
Clock Divider
Oscillator
Start-up
Timer
Fail-Safe Clock
Monitor (FSCM)
Internal Fast RC
Oscillator (FRC)
Internal Low
Power RC
Oscillator (LPRC)
PWRSAV Instruction
Wake-up Request
Oscillator Configuration bits
System
Clock
Oscillator Trap
to Timer1
LPRC
FRC
Secondary Osc
POR Done
Primary Os c
FPLL
POST<1:0>
2
FCKSM<1:0> 2
PLL
Lock COSC<1:0>
NOSC<1:0>
OSWEN
CF
2002 Microchip Technology Inc. Advance Information DS70082A-page 143
dsPIC30F
21.2 Oscillator Configurations
21.2.1 INITIAL CLOCK SOURCE
SELECTION
While coming out of Power-on Reset or Brown-out
Reset, the device selects its clock s ource based on:
a) FOS<1:0> configuration bits that select one of
four oscillator groups .
b) AND FPR<3:0> configuration bits that select
one of 13 oscillator choices within the primary
group.
The selection is as shown in Table 21-2.
TABLE 21-2: CONFIGURATION BIT VALUES FOR CLOCK SELECTION
Oscillator Mode Oscillator
Source FOS1 FOS0 FPR3 FPR2 FPR1 FPR0 OSC2
Function
EC Primary 1 1 1 0 1 1 CLKO
ECIO Primary 1 1 1 1 0 0 I/O
EC w/ PLL 4x Primary 1 1 1 1 0 1 I/O
EC w/ PLL 8x Primary 1 1 1 1 1 0 I/O
EC w/ PLL 16x Primary 1 1 1 1 1 1 I/O
ERC Primary 1 1 1 0 0 1 CLKO
ERCIO Primary 1 1 1 0 0 0 I/O
XT Primary 1 1 0 1 0 0 OSC2
XT w/ PLL 4x Primary 1 1 0 1 0 1 OSC2
XT w/ PLL 8x Primary 1 1 0 1 1 0 OSC2
XT w/ PLL 16x Primary 1 1 0 1 1 1 OSC2
XTL Primary 1 1 0 0 0 X OSC2
HS Primary 1 1 0 0 1 X OSC2
LP Secondary 0 0 - - - - (Notes 1, 2)
FRC Internal FRC 0 1 - - - - (Notes 1, 2)
LPRC Internal
LPRC 1 0 - - - - (Notes 1, 2)
Note 1: OSC2 pin function is determined by the Primary Oscillator mode selection (FPR<3:0>).
2: Note that OSC1 pin cannot be used as an I/O pin, even if the secondary oscillator or an internal clock
source is selected at all times.
dsPIC30F
DS70082A-page 144 Advance Information 2002 Microchip Technology Inc.
21.2.2 OSCIL LA TOR START-UP TIMER
(OST)
In order to ensure that a crystal oscillator (or ceramic
resonator) has started and stabilized, an oscillator
start-up timer is included. It is a simple 10-bit counter
that counts 1024 TOSC cycles before releasing the
oscil lator clock t o th e rest of the syste m. The t ime-ou t
period is designated as TOST. The TOST time is
involv ed eve ry ti me th e os ci ll ator has to res t art, i.e., on
POR, BOR and wake-up from SLEEP. The oscillator
start-up timer is applied to the LP Oscillator, XT, XTL,
and HS modes (upon wake-up from SLEEP, POR and
BOR) for the primary oscillator.
21.2.3 LP OSCILLATOR CONTROL
Enabling the LP oscillator is controlled by two
elements:
1. The current oscillator group bits COSC<1:0>.
2. The LPOS CEN bit (OSCON register ).
In normal Operating mode, the LP oscillator is ON if:
COSC<1:0> = 00 (LP selected as main oscillator)
or
LPOSCEN = 1
In SLEEP mode, the LP oscillator is ON if
LPOSCEN = 1.
In IDLE mode, the LP oscillator is ON if:
COSC<1:0> = 00 (LP s elec ted as main o scillat or)
or
LPOSCEN = 1
Keeping the LP oscillator ON at all times allows for a
fast swit ch to the 3 2 kHz syst em cl oc k f or lowe r powe r
operation. Returning to the faster main oscillator will
still require a start-up time
21.2.4 PHASE LOCKED LOOP (PLL)
The PLL multi plies the clock whic h is gen era ted by the
primary oscillator. The PLL is selectable to have either
gains of x4, x8, and x16. Input and output frequency
ranges are summarized in the table below.
TABLE 21-3: PLL FREQUENCY RANGE
The PLL fe atures a loc k output, which i s asserted when
the PLL enters a phase locked state. Should the loop
fall out of lock (e.g ., due to nois e), the lock signal will b e
rescinded. The state of this signal is reflected in the
read only LOCK bit in the OSCC ON regis ter.
21.2.5 FAST RC OSCILLATOR (FRC)
The FRC oscillator is a fast (8 MHz nominal) internal
RC osci ll ator. This oscill ato r is int ended to pro vide rea-
sonable device operating speeds without the u se of a n
external crystal, ceramic resonator, or RC network.
The dsP IC30F operates from the FRC Osci llator when-
ever the C urre nt Osc il la tor Sel ec tio n Control bits in th e
OSCCON register (OSCCON<13:12>) are set to 01.
21.2.6 LOW POWER RC OSCILLATOR
(LPRC)
The LPRC oscillator is a component of the Watchdog
Timer (WDT) and oscillates at a nominal frequency of
512 kHz. The LPRC oscillator is the clock source for
the Power-up Timer (PWRT) circuit, WDT, and clock
monitor circuits. It may also be used to provide a low
frequency clock source option for applications where
power consumption is critical, and timing accuracy is
not required
The LPRC oscillator is always enabled at a Power-on
Reset, because it is the clock source for the PWRT.
After the PWRT expires, the LPRC oscillator will
remain ON if one of the following is TRUE:
The Fail-Safe Clock Monitor is enabled
The WDT is enabled
The LPRC oscillator is selected as the system
clock via the COSC<1:0> control bits in the
OSCCON register
If one of the above condi tions i s not tru e, the LPRC wil l
shut-off after the PWRT expires.
FIN PLL
Multiplier FOUT
4 MHz - 10 MHz x4 16 MHz - 40 MHz
4 MHz - 10 MHz x8 32 MHz - 80 MHz
4 MHz - 7.5 MHz x16 64 MHz - 160 MHz
Note 1: OSC2 pin function is determined by the
Primary Oscillator mode selection
(FPR<3:0>).
2: Note tha t OSC 1 pi n ca nn ot be u sed as an
I/O pin, even if the secondary oscillator or
an internal clock source is selected at all
times.
2002 Microchip Technology Inc. Advance Information DS70082A-page 145
dsPIC30F
21.2.7 FAIL-SAFE CLOCK MONITOR
The Fail-Saf e Cl oc k Mo nit or (FSC M) al lows the dev ic e
to conti nue to ope rate even i n the e vent o f an os cilla tor
failure. The FSCM functi on i s e nab le d by ap propriately
programming the FCKSM configuration bits (Clock
Switch and Monitor Selection bits) in the FOSC device
configu r ati on reg is ter. If the FSC M fun ction is ena ble d,
the LP RC In tern al os cil la tor w i ll run at all t ime s (ex ce pt
during SLEEP mode) and will not be subject to control
by the SWDTEN bit.
In the event of an oscillator failure, the FSCM will gen-
erate a Clock Failu re Trap event and will switch the sys-
tem cloc k ove r to the FRC oscil lator. The user will the n
have the op tion to either att empt to restart the os cillator
or execu te a controlled shutdown. The us er may decide
to treat the Trap as a warm RESET by simply loading
the RESET addres s into the osci llator fail trap v ector . In
this event, the CF (Clock Fail) status bit (OSCCON<3>)
is also set whenever a clock failure is recognized.
In the event of a clock failure, the WDT is unaffected
and continues to run on the LPRC clock.
If the oscillator has a very slow start-up time coming
out of POR, BOR or SLEEP, it is possible that the
PWRT timer will expire before the oscillator has
started. In such cases, the FSCM will be activated and
the FSCM will initiate a Clock Failure Trap, and the
COSC<1:0> bits are loaded with FRC oscillator selec-
tion. This will effectively shut-off the original oscillator
that was trying to start.
The user may detect this situation and restart the
osci llator in the Clock Fail Trap ISR.
Upon a clock failure detection the FSCM module will
initiate a clock switch to the FRC Oscillator as follows:
1. The COSC bits (OSCCON<13:12>) are loaded
with the FRC Oscillator selection value.
2. CF bit is set (OSCCON<3>).
3. OSWEN control bit (OSCCON<0>) is cleared.
For the purpose of clock switching, the clock sources
are sectioned into four groups:
1. Primary
2. Secondary
3. Internal FRC
4. Internal LPRC
The user can switch between these functional groups,
but canno t switch between opt ions within a group. If the
primary group is selected, then the choice within the
group is always determined by the FPR<3:0>
configuration bits.
The OSCCON register holds the CONTROL and STA-
TUS bits related to clock switching.
COSC<1: 0>: Re ad only st a tus bit s alw a ys reflect
the current oscillator group in effect.
NOSC<1:0>: Control bits which are written to
indicate the new oscillator group of choice.
- On POR and BOR, COSC<1:0> and
NOSC<1:0> are both l oaded wi th the
Configuration bit values FOS<1:0>.
LOCK: The LOCK status bit indicates a PLL lock.
CF: Read only status bit indicating if a clock fail
detect has occurred.
OSWEN: Control bit changes from a 0 to a 1
when a clock transition sequence is initiated.
Clearing the OSWEN control bit will abort a clock
transition in progress (used for hang-up
situations).
If co nfi gura tio n bi ts FCK SM< 1: 0> = 1x, then the clock
switching function and the fail-safe clock monitor func-
tion are disabled. This is the default configuration bit
setting.
If clock switching is disabled, then the FOS<1:0> and
FPR<3:0> bits directly control the oscillator selection
and the COSC<1:0> bits do not control the clock
selection. However, these bits will reflect the clock
source selection.
21.2.8 PROTECTION AGAINST
ACCIDENTAL WRITES TO OSCCON
A write to the OSCCON register is intentionally made
difficult, because it controls clock switching and clock
scaling.
To write to the OSCCON low byte, the following code
sequence must be executed without any other
instructions in between:
Byte Write 0x46 to OSCCON low
Byte Write 0x57 to OSCCON low
Byte Write is allowed for one instruction cycle. Write
desired value or use bit manipulation instruction.
To write to the OSCCON high byte, the following
instructions must be executed without any other
instructions in between:
Byte Write 0x78 to OSCCON high
Byte Write 0x9A to OSCCON high
Byte Write is allowed for one instruction cycle. Write
Desired Value or use bit manipulation instruction.
dsPIC30F
DS70082A-page 146 Advance Information 2002 Microchip Technology Inc.
21.3 RESET
The dsPIC30F differentiates between various kinds of
RESET:
a) Power-on Reset (POR)
b) MCLR Reset during normal operation
c) MCLR Reset during SLEEP
d) Watchdog Timer (WDT) Reset (during normal
operation)
e) Programmable Brown-out Reset (BOR)
f) RESET Inst ruction
g) Reset cause by trap lockup (TRAPR)
h) Reset caused by illegal opcode, or by using an
uninitialized W register as an address pointer
(IOPUWR)
Dif fer ent regi sters a re a ffe cted in dif fe rent w ays by var-
ious RESE T condition s. Most registe rs are not affecte d
by a WD T wake-up, since this is viewed as the resump-
tion of normal operation. Status bits from the RCON
register are set or cleared differently in different RESET
situations, as indicated in Table 21-4. These bits are
used in software to determine the nature of the RESET.
A block di ag ram of the on-ch ip RESET circ ui t i s show n
in Figure 21-2.
A MCLR noise filter is provided in the MCLR Reset
path. The filter detects and ignores small pulses.
Internally generated RESETS do not drive MCLR pin
low.
FIGURE 21-2: RESE T SYSTEM BLOCK DIAGRAM
21.3.1 POR: PO W ER-O N RESET
A power-on event will generate an internal POR pulse
when a VDD rise is detected. The Reset pulse w ill occur
at the POR circuit threshold voltage (VPOR), which is
nominally 1.85V. The device supply voltage character-
istics mus t meet spec ified sta rting v olt ag e and rise ra te
requirem ents. For mo re informati on, please refer to the
Electric al Specif ications s ection (TBD). The POR p ulse
will reset a POR timer and place the device in the
RESET state. The POR also selects the device clock
source identified by the oscillator configuration fuses.
The POR circuit inserts a small delay, TPOR, which is
nominally 10 µs and ensures that the device bias cir-
cuits are stable. Furthermore, a user selected power-
up time-out (TPWRT) is applied. The TPWRT pa ram e te r
is based on device configuration bits and can be 0 ms
(no delay ), 4 ms, 16 ms , or 64 ms . The tot al del ay is at
device power-up TPOR + TPWRT. When these delays
have expired, SYSRST will be negated on the next
leading edge of the Q1 clock, and the PC will jump to
the RESET vector.
The timing for the SYSRST signal is shown in
Figure 21-3 through Figure 21-5.
S
RQ
MCLR
VDD
VDD Rise
Detect POR
SYSRST
SLEE P or IDLE
Brown-out
Reset BOREN
RESET
Instruction
WDT
Module
Digital
Glitch Filter
BOR
TRAP Conflict
Illegal Opcode/
Uninitialized W Register
2002 Microchip Technology Inc. Advance Information DS70082A-page 147
dsPIC30F
FIGURE 21-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)
FIGURE 21-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
FIGURE 21-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
TPWRT
TOST
VDD
INTERNAL POR
PWRT TI ME-OUT
OST TIME-OUT
INTERNAL RESET
MCLR
TPWRT
TOST
VDD
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
MCLR
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
TPWRT
TOST
dsPIC30F
DS70082A-page 148 Advance Information 2002 Microchip Technology Inc.
21.3.1.1 POR with Long Crystal Start-up Time
(with FSCM Enabled)
The osci ll ator s tart-up circ uitry is not linked t o the POR
circuitry. Some crystal circuits (especially low fre-
quency crystals) will have a relatively long start-up
time. Th erefore, one or more of the foll owing condit ions
is possible after the POR timer and the PWRT have
expired:
The oscillator circuit has not begun to oscillate.
The osc il lat or s t art-up tim er h as NO T expired (if a
crystal oscillator is used).
The PLL has not achieved a LOCK (if PLL is
used).
If th e FSCM is enabled and one of th e above c onditions
is true, the n a Clock Failure T rap w ill oc cur. The dev ice
will automatically switch to the FRC oscillator and the
user can switch to the desired crystal oscillator in the
trap ISR.
21.3.1.2 Operating without FSCM and PWRT
If the FSCM is disabled and the Power-up Timer
(PWRT) is also disabled, then on a power-up, the
device will exit from RESET rapidly. If the clock source
is FRC, LPRC, EXTRC or EC, it will be active
immediately.
If the FSCM is disabled and the system clock has not
started, the device will be in a frozen state at the
RESET vector, until the system clock starts. From the
users perspective, the device will appear to be in
RESET until a system clock is available.
21.3.2 BOR : PROG RA MMA BL E
BROWN-OUT RESET
The BOR (Brown-out Reset) module is based on an
internal voltage reference circuit. The main purpose of
the BOR module is to generate a device RESET when
a brown-out condition oc curs. Brown-out conditions are
generally caused by glitches on the AC mains, i.e.,
missing w aveform porti ons of the AC cycle s due to bad
power tr ansmission lines, or vo ltage sags du e to exces-
sive c urren t dra w wh en a larg e in duc ti ve l oad is turne d
on.
The BOR module allows selection of one of the follow-
ing voltage trip points:
2.0V
2.7V
4.2V
4.5V
A BOR will generate a RESET pulse which will reset
the device. The BOR will se lect the clock source, based
on the device configuration bit values (FOS<1:0> and
FPR<3:0>). Furthermore, if an Oscillator mode is
selected, the BOR will activate the Oscillator Start-up
Timer (OST). The system clock is held until OST
expires. If the PLL is used, then the clock will be held
until the LOCK bit (OSCCON<5>) is 1.
Concurrently, the POR time-out (T POR) and the PWRT
time-out (TPWRT) will be applied before the internal
RESET is released. If TPWRT = 0 and a crystal oscillator
is being used , the n a nom in al de lay of TFSCM = 100 µs
is applied. The total delay in this case is (TPOR +
TFSCM).
The B OR status bit (RCON <1>) wi ll be set to indic ate
that a BOR has occurred. The BOR circuit, if enabled,
will con tinue to oper ate while i n SLEEP o r IDLE mo des
and wi ll reset the de vice shoul d VDD fall below the BOR
threshold voltage.
FIGURE 21-6: EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW VDD POWER-UP)
Table 21-4 shows the RESET cond itions for the RCON
Register. Since the control bits within the RCON regis-
ter are R/W, the information in the table implies that all
the bits are negated prior to the action specified in the
conditi on col um n.
Note: The BO R voltag e trip points indicated here
are nominal values provided for design
guidance only. Refer to the Electrical
Specifications in the specific device data
sheet for BOR voltage limit specifications.
Note: Dedicated supervisory devices, such as the
MCP1XX and MCP8XX, may also be used
as an external Power-on Reset circuit.
Note 1: External Power-on Reset circuit is
required only if the VDD powe r-up slop e is
too slow . The dio de D help s disch arge the
capacitor quickly when VDD powers
down.
2: R should be suitably chosen so as to
make s ure that the voltag e drop ac ross R
does not violate the devices electrical
specification.
3: R1 should be suitably chosen so as to
limit any current flowing into MCLR from
external capac itor C, in the even t of
MCLR/VPP pin breakdown due to Electro-
static Discharge (ESD), or El ectrical
Overstress (EOS).
C
R1
R
D
VDD
dsPIC30F
MCLR
2002 Microchip Technology Inc. Advance Information DS70082A-page 149
dsPIC30F
TABLE 21-4: INITIALIZATION CONDITION FOR RCON REGISTER CASE 1
Table 21-5 shows a second example of the bit
conditi ons for th e R CO N Re gis ter. In this case, it is n ot
assu med th e use r has s et/ cle ared s peci fic bits pr ior to
action specified in the condition column.
TABLE 21-5: INITIALIZATION CONDITION FOR RCON REGISTER CASE 2
Condition Program
Counter TRAPR IOPUWR EXTR SWR WDTO IDLE SLEEP POR BOR
Power-on Reset 0x000000 0 0 0 0 0 0 0 1 1
Brown-out Reset 0x000000 0 0 0 0 0 0 0 0 1
MCLR Reset during normal
operation 0x000000 0 0 1 0 0 0 0 0 0
Software Reset during
normal ope rati on 0x000000 0 0 0 1 0 0 0 0 0
MCLR Reset during SLEEP 0x000000 0 0 1 0 0 0 1 0 0
MCLR Reset during IDLE 0x000000 0 0 1 0 0 1 0 0 0
WDT Time- out R eset 0x000000 0 0 0 0 1 0 0 0 0
WDT Wake-up PC + 2 0 0 0 0 1 0 1 0 0
Interrupt Wake-up from
SLEEP PC + 2(1) 0 0 0 0 0 0 1 0 0
Clock Failure Trap 0x000004 0 0 0 0 0 0 0 0 0
Trap Reset 0x000000 1 0 0 0 0 0 0 0 0
Illegal Operation Trap 0x000000 0 1 0 0 0 0 0 0 0
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as 0
Note 1: When the wake-up is due to an enabl ed in terru pt, the PC is loade d with the corre sp ond ing interrupt vect or.
Condition Program
Counter TRAPR IOPUWR EXTR SWR WDTO IDLE SLEEP POR BOR
Power-on Reset 0x000000 0 0 0 0 0 0 0 1 1
Brown-out Reset 0x000000 u u u u u u u 0 1
MCLR Reset during normal
operation 0x000000 u u 1 0 0 0 0 u u
Software Reset during
normal ope rati on 0x000000 u u 0 1 0 0 0 u u
MCLR Reset during SLEEP 0x000000 u u 1 u 0 0 1 u u
MCLR Reset during IDLE 0x000000 u u 1 u 0 1 0 u u
WDT Time- out R eset 0x000000 u u 0 0 1 0 0 u u
WDT Wake-up PC + 2 u u u u 1 u 1 u u
Interrupt Wake-up from
SLEEP PC + 2(1) u u u u u u 1 u u
Clock Failure Trap 0x000004 u u u u u u u u u
Trap Reset 0x000000 1 u u u u u u u u
Illegal Operation Reset 0x000000 u 1 u u u u u u u
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as 0
Note 1: When the wake-up is due to an enabled interrupt, the PC is loaded with the corresponding interrupt vector.
dsPIC30F
DS70082A-page 150 Advance Information 2002 Microchip Technology Inc.
21.4 Watchdog Timer (WDT)
21.4.1 WATCHDOG TIMER OPERATION
The primary function of the Watchdog Timer (WDT) is
to reset the processor in the event of a software mal-
function. The WDT is a free running timer, which runs
off an on-chip RC osc il lat or, requi ring no e xte rnal com -
ponent. Th erefore, the WDT timer w ill continue to oper-
ate even if the main processor clock (e.g., the crystal
oscillator) fails.
21.4.2 ENABLING AND DISABLING THE
WDT
The Watchdog Timer can be Enabled or Disabled
only through a configuration bit (FWDTEN) in the
configu r ati on regi ste r FWD T.
Setting F WDTEN = 1 enables the W atchdog T imer . The
enabling is done when programming the device. By
default, after chip-erase, FWDTEN bit = 1. Any device
programmer capable of programming dsPIC30F
devices allows programming of this and other
configuration bits to the desired state.
If enabled, the WDT will increment until it overflows or
times out . A WDT ti me-ou t wil l f orce a de vi ce RESET
(except during SLEEP). To prevent a WDT time-out,
the user must clear the Watchdog Timer using a
CLRWDT instruction.
If a WD T times out d uring SLEEP, the de vice will wake-
up. The WDT O bit in the RCO N register wil l be cleare d
to indicate a wake-up resulting from a WDT time-out.
Setting FWDTEN = 0 allows user software to enable/
disabl e W atc hdog Timer via the SWDTEN (RC ON<5>)
control bit.
21.5 Power Saving Modes
There are tw o pow e r s avi ng states that ca n b e en tere d
through the execution o f a spe ci al ins tru cti on, PWRSAV.
These are: SLEEP and IDLE.
The format of the PWRSAV inst ruc ti on is as fol lows :
PWRSAV <parameter>, where parameter defines
IDLE or SLEEP mode.
21.5.1 SLEEP MODE
In SLEEP mode, the clock to the CPU and the periph-
erals is shutdown. If an on-chip oscillator is being
used, it is shutdown.
The fail-safe clock monitor is not functional during
SLEEP, since there is no clock to monitor. However,
LPRC clock remains active if WDT is operational
during SLEEP.
The Brown-out protection circuit and the Low Voltage
Detect circuit, if enabled, will remain functional during
SLEEP.
The processor wakes up from SLEEP if at least one of
the following conditions is true:
on occurrence of any interrupt that is individually
enabled and meets the required priority level
on any Reset (POR, BOR and MCLR)
on WDT time-out
On waking up from SLEEP mode, the processor will
restart the same clock that was active prior to entry
into SLEEP mode. When clock switching is enabled,
bits COSC<1:0> will determine the oscillator source
that will be used on wake-up. If clock switch is
disabled, then there is only one sy ste m cl ock .
If the clock source is an oscillator, the clock to the
device will be held off until OST times out (indicating a
stable oscillator). If PLL is used, the system clock is
held off until LOCK = 1 (indicating that the PLL is sta-
ble). In either case, TPOR, TLOCK and TPWRT delays
are applied.
If EC, FRC, LPRC or EXTRC oscillators are used,
then a delay of TPOR (~ 10 µs) is applied. This is the
smallest delay possible on wake-up from SLEEP.
Moreover, if LP oscillator was active during SLEEP,
and LP is the oscillator used on wake-up, then the
start-up delay will be equal to TPOR. PWRT delay and
OST timer delay are not applied. In order to have the
smallest possible start-up delay when waking up from
SLEEP, then one of these faster wake-up options
should be sel ec ted before ent erin g SLEEP.
Any interrupt that is individually enabled (using the
corresponding IE bit) and meets the prevailing priority
level will be able to wake-up the processor. The pro-
cessor will process the interrupt and branch to the
ISR. The SLEEP status bit in RCON register is set
upon wake-up.
All RESETS will wake-up the processor from SLEEP
mode. Any RESET, other than POR, will set the
SLEEP status bit. In a POR, the SLEEP bit is cleared.
Note: If a PO R or BOR oc curred, the sele ction of
the oscillator is based on the FOS<1:0>
and FPR<3:0> configuration bits.
Note: In spite of various delays applied (TPOR,
TLOCK and TPWRT), the crystal oscillator
(and PLL) may not be active at the end of
the time-out, e.g., for low frequency crys-
tals. In such cases, if FSCM is enabled,
then the device will detect this as a clock
failure and process the Clock Failure Trap,
the FRC oscillator will be enabled, and the
user will have to re-enable the crystal oscil-
lator. If FSCM is not enabled, then the
device will simply suspend execution of
code until the clock is stable, and will
remain in SLEEP until the oscillator clock
has st a rted.
2002 Microchip Technology Inc. Advance Information DS70082A-page 151
dsPIC30F
If Watchdog Timer is enabled, then upon WDT time-
out, the processor will wake-up from SLEEP mode.
SLEEP and WDTO status bits are both set.
21.5.2 IDLE MODE
In IDLE mode, the clock to the CPU is shutdown while
peripherals keep running. Unlike SLEEP mode, the
clock source remains active .
Several peripherals have a control bit in each module,
that allows them to operate during IDLE.
LPRC fail-safe clock remains active if clock failure
detect is enabled.
The processor wakes up from IDLE if at least one of
the following conditions is true:
on any interrupt that is individually enabled (IE bit
is 1) and meets the required priority level
on any Reset (POR, BOR, MCLR)
on WDT time-out
Upon wa ke-up fro m ID LE mode , the cl ock is re-app lied
to the CPU and instruction execution begins immedi-
ately, starti ng w ith the in stru cti on fol low i ng the PWRSAV
instruction.
Any interrupt that is individually enabled (using IE bit)
and meets the prevailing priority level, will be able to
wake-u p th e p roc es sor. The process or wi ll p r oc es s th e
interrupt and branch to the ISR. The IDLE status bit in
RCON register is set upon wake-up.
Any RESET, other than POR, will set the IDLE status
bit. On a POR, the IDLE bit is cleared.
If Watchdog Timer is enabled, then upon WDT time-
out, the processor will wake-up from IDLE mode. IDLE
and WDTO status bits are both set.
Unlike wake-up from SLEEP, there are no time delays
involv ed in wake -up from IDLE.
21.6 Device Configuration Registers
The confi guratio n bits in each devi ce configu ration reg-
ister specify some of the Device modes and are pro-
grammed by a device programmer, or by using the In-
Circuit Serial Programming (ICSP) feature of the
device. Each device configuration register is a 24-bit
register, but only the lower 16 bits of each register are
used to hold configuration data. There are four device
configuration registers available to the user:
1. FOSC (0xF80000): Oscillator Configuration
Register
2. FWDT (0xF80002): Watchdog Timer
Configu ration Register
3. FBORPOR (0xF80004): BOR and POR
Configu ration Register
4. FGS (0xF8000A): General Code Segment
Configu ration Register
The place ment of the configu ration bits is automati cally
hand led when you s elect the device in your devi ce pro-
grammer. The desired state of the configuration bits
may be sp ecified i n the source code (depen dent on the
languag e tool used ), or through th e programming inter-
face. After the device has been programmed, the appli-
cation software may read the configuration bit values
through th e table read instructions . For additio nal infor-
mation, please refer to the Programming Speci fications
of the device.
21.7 Peripheral Module Disable (PMD)
Registers
The peri pheral mo dule d isable ( PMD) regi sters prov ide
a metho d to disable a peripheral m odule by st opping all
clock sources supplied to that modu le. When a periph-
eral is disab led v ia the approp riate PM D con trol bi t, the
peripheral is in a minimum power consumption state.
The control and status registers associated with the
peripheral will also be disabled, so writes to those reg-
isters will have no ef fect and read values will be invalid.
A peripheral module will only be enabled if both the
associated bit in the the PMD register is cleared, and
the peripheral is supported by the specific dsPIC vari-
ant. If the peripheral is present in the device, it is
enabled in the PMD register by default.
dsPIC30F
DS70082A-page 152 Advance Information
2002 Microchip Technology Inc.
TABLE 21-6: SYSTEM INTEGRATION REGISTER MAP
TABLE 21-7: DEVICE CONFIGURATION REGISTER MAP
SFR
Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RESET State
RCON 0740 TRAPR IOPUWR BGST LVDEN LVDL<3:0> EXTR SWR SWDTEN WDTO SLEEP IDLE BOR POR Depends on type of
RESET.
OSCCON 0742 COSC<1:0> NOSC<1:0> POST<1:0> LOCK CF LPOSCEN OSWEN Depends on configuration
bits.
PMD1 0770 T5MD T4MD T3MD T2MD T1MD QEIMD PWMMD I2CMD U2MD U1MD SPI2MD SPI1MD C2MD C1MD 0000 0000 0000 0000
PMD2 0772 IC8MD IC7MD IC6MD IC5MD IC4MD IC3MD IC2MD IC1MD OC8MD OC7MD OC6MD OC5MD OC4MD OC3MD OC2MD OC1MD 0000 0000 0000 0000
Legend: u = uninitialized bit
File Name Addr. Bits 23-16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
FOSC F80000 FSCKM<1:0> FGS<1:0> FG1<3:0>
FWDT F80002 FWDTEN FWPSA<1:0> FWPSB<3:0>
FBORPOR F80004 MCLREN PWMPIN HPOL LPOL BOREN BORV<1:0> FPWRT<1:0>
FGS F8000A GCP GWRP
2002 Microchip Technology Inc. Advance Information DS70082A-page 153
dsPIC30F
22.0 INSTRUCTION SET SUMMARY
The dsPIC30F instruction set adds many
enhancements to the previous PICmicro® instruction
sets, while maintaining an easy migration from
PICmicro instruction sets.
Most instructions are a single program memory word
(24-bits), but there are three instructions that require
two program memory loc atio ns.
Each single-word instruction is a 24-bit word divided
into an 8-bit opcode, which specifies the instruction
type and one or more operands, which further specify
the operation of the instruction.
The instruction set is highly orthogonal and is grouped
into five bas ic ca tego ries:
Word or byte-oriented operations
Bit-oriented operations
Literal operation s
DSP operations
Control operations
Table 22-1 show s the gen eral sym bols used in descri b-
ing the instructions.
The dsPIC30F instruction set summary in Table 22-2
lists all the instructions along with the status flags
affected by each instruction.
Most word or byte-oriented W register instructions
(including barrel shift instructions) have three
operands:
The first source operand, which is typically a
register Wb without any address modifier
The second source operand, which is typically a
register Ws with or without an address modifier
The destination of the result, which is typically a
register Wd with or without an address modifier
However , word or byte-ori ented file register instructions
have two operands:
The file register specified by the value f
The destination, which could either be the file
register f or the W 0 reg is ter, which is de not ed a s
WREG
The destination designator d specifies where the
result of the operation is to be placed. If 'd' is zero, the
result is placed in WREG. If 'd' is one, the result is
placed in the file register specified in the instruction.
Most bit oriented instructions (including simple rotate/
shift instructions) have two operands:
The W register (with or without an address modi-
fier) or file register (specified by the value of Ws
or f)
The bit in the W register or file register
(specified by a literal value, or indirectly by the
contents of register Wb)
The litera l instruct ions that invo lve data m ovement ma y
use some of the following operands:
A literal v alue to be lo aded i nto a W regist er or file
register (specified by the value of k)
The desired W register or file register to load the
literal value into (specified by Wb or f)
However, literal instructions that involve arithmetic or
logical operations use some of the following operands:
The first source operand, which is a register Wb
without any addre s s modifier
The second source operand, which is a literal
value
The desti nation of the result (only if not th e same
as the first source operand), which is typically a
register Wd with or without an address modifier
The MAC class of DSP instructions may use some of the
following operands:
The accumulator (A or B) to be used
The W registers to be used as the two operands
The X and Y address space pre-fetch operations
The X and Y addres s sp ace pre- fetch desti nation s
The accum ula tor wr ite back des tin ation
The other DSP instructions do not involve any
multipl ic ati on, and may include:
The accumulator to be used
The so urce or destin ation ope rand (des ignated as
Wso or Wdo, respectively) with or without an
address modifier
The amount of shift (in the case of accumulator
shift instructions), specified by a W register Wn
or a literal value
The control instructions may use some of the following
operands:
A program memory address
The mode of the Table Read and Table Write
instructions
No operand requir ed
All instructions are a single word, except for certain
double-word instructions, which were made double-
word instructions so that all the required information is
available in these 48-bits. In the second word, the
8MSbs are 0s. If this second word is executed as an
instruction (by itself), it will execute as a NOP.
dsPIC30F
DS70082A-page 154 Advance Information 2002 Microchip Technology Inc.
Most single word instructions are executed in a single
instruc tion cycle , u nle ss a conditional test is tru e or the
program counter is changed as a result of the instruc-
tion. In these cases, the executio n takes tw o instructio n
cycles with the additional instruction cycle(s) executed
as a NOP. Notable exceptions are the BRA (uncondi-
tional/computed branch), indirect CALL/GOTO, all
Table Reads and Wri tes an d RETURN/RETFIE ins truc-
tions, which are single word instructions, but take two
cycles. Certain instructions that involve skipping over
the su bsequen t instruc tion, re quire ei ther two o r three
cycles if the skip is performed, depending on whether
the instruction being skipped is a single word or two-
word instruction. Moreover, double-word moves
require two cycles.
The doub le-word inst ructions exe cute in two ins truction
cycles.
One in struction cycle consist s of f our oscil lator peri ods.
Thus, for an oscillator frequency of 120 MHz, the nor-
mal instruction execution time is 0.033 µs. If a condi-
tional test is tru e or the pr ogra m cou nte r is c han ge d a s
a result of an instru ction, the ins t ruct io n ex ec uti on tim e
is 0.066 µs.
Note: For more details on the instruction s et, refer
to the Programmers Reference Manual.
TABLE 22-1: SYMBOLS USED IN ROADRUNNER OPCODE DESCRIPTIONS
Field Description
#text Me ans literal defined by text
(text) Means content of text
.b Byte mode selection
.d Double-word mode selection
.S Shadow register select
.w Word mode selection (default)
[text] Means the location addressed by text
{ } Optional field or operation
<n:m> Register bit field
Acc One of two accumulators {A, B}
AWB Accumula tor writ e back des tin ation address regis te r {W13, [W13]+=2}
bit3 3-bit bit selection field (used in byte addressed instructions) {0...7}
bit4 4-bit bit selection field (used in word addressed instructions) {0...15}
C, DC, N, OV, Z MCU status bits: Carry, Digit Carry, Negative, Overflow, Sticky-Zero
dFile register destination d {WREG, none}
Expr Absolute address, label or expression (resolved by the linker)
fFile register address {0x0000...0x1FFF}
lit1 1-bit unsigned literal {0,1}
lit14 14-bit unsigned literal {0...16384}
lit16 16-bit unsigned literal {0...65535}
lit23 23-bit unsigned literal {0...8388608}; LSB must be 0
lit4 4-bit unsigned literal {0...15}
lit5 5-bit unsigned literal {0...31}
lit8 8-bit unsigned literal {0...255}
lit10 10-bit unsigned literal {0...255} for Byte mode, {0:1023} for Word mode
None Field does not require an entry, may be blank
OA, OB, SA, SB DSP status bits: AccA Overflow, AccB Overflow, AccA Saturate, AccB Saturate
PC Program Counter
Slit10 10-bit signed literal {-512...511}
Slit16 16-bit signed literal {-32768...32767}
Slit5 5-bit signed literal {-16...15}
Wb Base W register {W0..W15}
Wd Destination W register { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] }
2002 Microchip Technology Inc. Advance Information DS70082A-page 155
dsPIC30F
Wdo Destination W register
{ Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] }
Wm,Wn Dividend, Divisor working register pair (direct addressing)
Wm*Wm Multiplicand and Multiplier working register pair for Square instructions
{W4*W4,W5*W5,W6*W6,W7*W7}
Wm*Wn Multiplicand and Multiplier working register pair for DSP instructions
{W4*W5,W4*W6,W4*W7,W5*W6,W5*W7,W6*W7}
Wn One of 16 working registers {W0..W15}
Wnd One of 16 destination working registers {W0..W15}
Wns One of 16 source working registers {W0..W15}
WREG W0 (working register used in file register instructions)
Ws Source W register { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] }
Wso Source W register
{ Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] }
Wx X data space pre-fetch address register for DSP instructions
{[W8]+=6, [W8]+=4, [W8]+=2, [W8], [W8]-=6, [W8]-=4, [W8]-=2,
[W9]+=6, [W9]+=4, [W9]+=2, [W9], [W9]-=6, [W9]-=4, [W9]-=2,
[W9+W12],none}
Wxd X data space pre-fetch destination register for DSP instructions {W4..W7}
Wy Y data space pre-fetch address register for DSP instructions
{[W10]+=6, [W10]+=4, [W10]+=2, [W10], [W10]-=6, [W10]-=4, [W10]-=2,
[W11]+=6, [W11]+=4, [W11]+=2, [W11], [W11]-=6, [W11]-=4, [W11]-=2,
[W11+W12], none}
Wyd Y data space pre-fetch destination register for DSP instructions {W4..W7}
TABLE 22-1: SYMBOLS USED IN ROADRUNNER OPCODE DESCRIPTIONS (CONTINUED)
Field Description
dsPIC30F
DS70082A-page 156 Advance Information 2002 Microchip Technology Inc.
TABLE 22-2: INSTRUCTION SET OVERVIEW
Base
Instr
#
Assembly
Mnemonic Assembly Syntax Description # of
words # of
cycles Status Flags
Affected
1ADD ADD Acc Add Accumulators 1 1 OA,OB,SA,SB
ADD ff = f + WREG 1 1 C,DC,N,OV,Z
ADD f,WREG WREG = f + WREG 1 1 C,DC,N,OV,Z
ADD #lit10,Wn Wd = lit10 + Wd 1 1 C,DC,N,OV,Z
ADD Wb,Ws,Wd Wd = Wb + Ws 1 1 C,DC,N,OV,Z
ADD Wb,#lit5,Wd Wd = Wb + lit5 1 1 C,DC,N,OV,Z
ADD Wso,#Slit4,Acc 16-bit Signed Add to Accumulator 1 1 OA,OB,SA,SB
2ADDC ADDC ff = f + WREG + (C) 1 1 C,DC,N,OV,Z
ADDC f,WREG WREG = f + WREG + (C) 1 1 C,DC,N,OV,Z
ADDC #lit10,Wn Wd = lit10 + Wd + (C) 1 1 C,DC,N,OV,Z
ADDC Wb,Ws,Wd Wd = Wb + Ws + (C) 1 1 C,DC,N,OV,Z
ADDC Wb,#lit5,Wd Wd = Wb + lit5 + (C) 1 1 C,DC,N,OV,Z
3AND AND ff = f .AND. WREG 1 1 N,Z
AND f,WREG WREG = f .AND. WREG 1 1 N,Z
AND #lit10,Wn Wd = lit10 .AND. Wd 1 1 N,Z
AND Wb,Ws,Wd Wd = Wb .AND. Ws 1 1 N,Z
AND Wb,#lit5,Wd Wd = Wb .AND. lit5 1 1 N,Z
4ASR ASR ff = Arithmetic Right Shift f 1 1 C,N,OV,Z
ASR f,WREG WREG = Arithmetic Right Shift f 1 1 C,N,OV,Z
ASR Ws,Wd Wd = Arithmetic Right Shift Ws 1 1 C,N,OV,Z
ASR Wb,Wns,Wnd Wnd = Arithmetic Right Shift Wb by Wns 1 1 N,Z
ASR Wb,#lit5,Wnd Wnd = Arithmetic Right Shift Wb by lit5 1 1 N,Z
5BCLR BCLR f,#bit4 Bit Clear f 1 1 None
BCLR Ws,#bit4 Bit Clear Ws 1 1 None
6BRA BRA C,Expr Branch if Carry 11 (2) None
BRA GE,Expr Branch if greater than or equal 11 (2) None
BRA GEU,Expr Branch if unsigned greater than or equal 11 (2) None
BRA GT,Expr Branch if greater than 11 (2) None
BRA GTU,Expr Branch if unsigned greater than 11 (2) None
BRA LE,Expr Branch if less than or equal 11 (2) None
BRA LEU,Expr Branch if unsigned less than or equal 11 (2) None
BRA LT,Expr Branch if less than 11 (2) None
BRA LTU,Expr Branch if unsigned less than 11 (2) None
BRA N,Expr Branch if Negative 11 (2) None
BRA NC,Expr Branch if Not Carry 11 (2) None
BRA NN,Expr Branch if Not Negative 11 (2) None
BRA NOV,Expr Branch if Not Overflow 11 (2) None
BRA NZ,Expr Branch if Not Zero 11 (2) None
BRA OA,Expr Branch if accumulator A overflow 11 (2) None
BRA OB,Expr Branch if accumulator B overflow 11 (2) None
BRA OV,Expr Branch if Overflow 11 (2) None
BRA SA,Expr Branch if accumulator A saturated 11 (2) None
BRA SB,Expr Branch if accumulator B saturated 11 (2) None
BRA Expr Branch Unconditionally 1 2 None
BRA Z,Expr Branch if Zero 11 (2) None
BRA Wn Computed Branch 1 2 None
7BSET BSET f,#bit4 Bit Set f 1 1 None
BSET Ws,#bit4 Bit Set Ws 1 1 None
8BSW BSW.C Ws,Wb Write C bit to Ws<Wb> 1 1 None
BSW.Z Ws,Wb Write Z bit to Ws<Wb> 1 1 None
9BTG BTG f,#bit4 Bit Toggle f 1 1 None
BTG Ws,#bit4 Bit Toggle Ws 1 1 None
10 BTSC BTSC f,#bit4 Bit Test f, Skip if Clear 11
(2 or 3) None
BTSC Ws,#bit4 Bit Test Ws, Skip if Clear 11
(2 or 3) None
2002 Microchip Technology Inc. Advance Information DS70082A-page 157
dsPIC30F
11 BTSS BTSS f,#bit4 Bit Test f, Skip if Set 11
(2 or 3) None
BTSS Ws,#bit4 Bit Test Ws, Skip if Set 11
(2 or 3) None
12 BTST BTST f,#bit4 Bit Test f 1 1 Z
BTST.C Ws,#bit4 Bit Test Ws to C 1 1 C
BTST.Z Ws,#bit4 Bit Test Ws to Z 1 1 Z
BTST.C Ws,Wb Bit Test Ws<Wb> to C 1 1 C
BTST.Z Ws,Wb Bit Test Ws<Wb> to Z 1 1 Z
13 BTSTS BTSTS f,#bit4 Bit Test then Set f 1 1 Z
BTSTS.C Ws,#bit4 Bit Test Ws to C, then Set 1 1 C
BTSTS.Z Ws,#bit4 Bit Test Ws to Z, then Set 1 1 Z
14 CALL CALL lit23 Call subroutine 2 2 None
CALL Wn Call indirect subroutine 1 2 None
15 CLR CLR ff = 0x0000 1 1 None
CLR WREG WREG = 0x0000 1 1 None
CLR Ws Ws = 0x0000 1 1 None
CLR Acc,Wx,Wxd,Wy,Wyd,AWB Clear Accumulator 1 1 OA,OB,SA,SB
16 CLRWDT CLRWDT Clear Watchdog Timer 1 1 WDTO,SLEEP
17 COM COM ff = f 1 1 N,Z
COM f,WREG WREG = f 1 1 N,Z
COM Ws,Wd Wd = Ws 1 1 N,Z
18 CP CP fCompare f with WREG 1 1 C,DC,N,OV,Z
CP Wb,#lit5 Compare Wb with lit5 1 1 C,DC,N,OV,Z
CP Wb,Ws Compare Wb with Ws (Wb - Ws) 1 1 C,DC,N,OV,Z
19 CP0 CP0 fCompare f with 0x0000 1 1 C,DC,N,OV,Z
CP0 Ws Compare Ws with 0x0000 1 1 C,DC,N,OV,Z
20 CP1 CP1 fCompare f with 0xFFFF 1 1 C,DC,N,OV,Z
CP1 Ws Compare Ws with 0xFFFF 1 1 C,DC,N,OV,Z
21 CPB CPB fCompare f with WREG, with Borrow 1 1 C,DC,N,OV,Z
CPB Wb,#lit5 Compare Wb with lit5, with Borrow 1 1 C,DC,N,OV,Z
CPB Wb,Ws Compare Wb with Ws, with Borrow
(Wb - Ws - C)1 1 C,DC,N,OV,Z
22 CPSEQ CPSEQ fCompare f with WREG, skip if = 11
(2 or 3) None
23 CPSGT CPSGT fCompare f with WREG, skip if > 11
(2 or 3) None
24 CPSLT CPSLT fCompare f with WREG, skip if < 11
(2 or 3) None
25 CPSNE CPSNE fCompare f with WREG, skip if 11
(2 or 3) None
26 DAW DAW Wn Wn = decimal adjust Wn 1 1 C
27 DEC DEC ff = f -1 1 1 C,DC,N,OV,Z
DEC f,WREG WREG = f -1 1 1 C,DC,N,OV,Z
DEC Ws,Wd Wd = Ws - 1 1 1 C,DC,N,OV,Z
28 DEC2 DEC2 ff = f -2 1 1 C,DC,N,OV,Z
DEC2 f,WREG WREG = f -2 1 1 C,DC,N,OV,Z
DEC2 Ws,Wd Wd = Ws - 2 1 1 C,DC,N,OV,Z
29 DECSNZ DECSNZ ff = f-1, Skip if Not 0 11
(2 or 3) None
DECSNZ f,WREG WREG = f-1, Skip if Not 0 11
(2 or 3) None
30 DECSZ DECSZ ff = f-1, Skip if 0 11
(2 or 3) None
DECSZ f,WREG WREG = f-1, Skip if 0 11
(2 or 3) None
31 DISI DISI #lit14 Disable Interrupts for k instruction cycles 1 1 None
TABLE 22-2: INSTRUCTION SET OVERV IEW (CONTINUED)
Base
Instr
#
Assembly
Mnemonic Assembly Syntax Description # of
words # of
cycles Status Flags
Affected
dsPIC30F
DS70082A-page 158 Advance Information 2002 Microchip Technology Inc.
32 DIV DIV.S Wm,Wn Signed 16/16-bit Integer Divide 118 N,Z,C
DIV.SD Wm,Wn Signed 32/16-bit Integer Divide 118 N,Z,C
DIV.U Wm,Wn Unsigned 16/16-bit Integer Divide 118 N,Z,C
DIV.UD Wm,Wn Unsigned 32/16-bit Integer Divide 118 N,Z,C
33 DIVF DIVF Wm,Wn Signed 16/16-bit Fractional Divide 118 N,Z,C
34 DO DO #lit14,Expr Do code to PC+Expr, lit14+1 times 2 2 None
DO Wn,Expr Do code to PC+Expr, (Wn)+1 times 2 2 None
35 ED ED Wm*Wm,Acc,Wx,Wy,Wxd Euclidean Distance 1 1 OA,OB,OAB,
SA,SB,SAB
36 EDAC EDAC Wm*Wm,Acc,Wx,Wy,Wxd Euclidean Distance Accumulate 1 1 OA,OB,OAB,
SA,SB,SAB
37 EXCH EXCH Wns,Wnd Swap Wns with Wnd 1 1 None
38 FBCL FBCL Ws,Wnd Find Bit Change from Left (MSb) Side 1 1 C
39 FF1L FF1L Ws,Wnd Find First One from Left (MSb) Side 1 1 C
40 FF1R FF1R Ws,Wnd Find First One from Right (LSb) Side 1 1 C
41 GOTO GOTO Expr Go to address 2 2 None
GOTO Wn Go to indirect 1 2 None
42 INC INC ff = f + 1 1 1 C,DC,N,OV,Z
INC f,WREG WREG = f + 1 1 1 C,DC,N,OV,Z
INC Ws,Wd Wd = Ws + 1 1 1 C,DC,N,OV,Z
43 INC2 INC2 ff = f + 2 1 1 C,DC,N,OV,Z
INC2 f,WREG WREG = f + 2 1 1 C,DC,N,OV,Z
INC2 Ws,Wd Wd = Ws + 2 1 1 C,DC,N,OV,Z
44 INCSNZ INCSNZ ff = f+1, Skip if Not 0 11
(2 or 3) None
INCSNZ f,WREG WREG = f+1, Skip if Not 0 11
(2 or 3) None
45 INCSZ INCSZ ff = f+1, Skip if 0 11
(2 or 3) None
INCSZ f,WREG WREG = f+1, Skip if 0 11
(2 or 3) None
46 IOR IOR ff = f .IOR. WREG 1 1 N,Z
IOR f,WREG WREG = f .IOR. WREG 1 1 N,Z
IOR #lit10,Wn Wd = lit10 .IOR. Wd 1 1 N,Z
IOR Wb,Ws,Wd Wd = Wb .IOR. Ws 1 1 N,Z
IOR Wb,#lit5,Wd Wd = Wb .IOR. lit5 1 1 N,Z
47 LAC LAC Wso,#Slit4,Acc Load Accumulator 1 1 OA,OB,OAB,
SA,SB,SAB
48 LNK LNK #lit14 Link fram e poi n ter 1 1 None
49 LSR LSR ff = Logical Right Shift f 1 1 C,N,OV,Z
LSR f,WREG WREG = Logical Right Shift f 1 1 C,N,OV,Z
LSR Ws,Wd Wd = Logical Right Shift Ws 1 1 C,N,OV,Z
LSR Wb,Wns,Wnd Wnd = Logical Right Shift Wb by Wns 1 1 N,Z
LSR Wb,#lit5,Wnd Wnd = Logical Right Shift Wb by lit5 1 1 N,Z
50 MAC MAC Wm*Wn,Acc,Wx,Wxd,Wy,Wyd,
AWB Multiply and Accumulate 1 1 OA,OB,OAB,
SA,SB,SAB
MAC Wm*Wm,Acc,Wx,Wxd,Wy,Wyd S quare and Accumu late 1 1 OA,OB,OAB,
SA,SB,SAB
TABLE 22-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Base
Instr
#
Assembly
Mnemonic Assembly Syntax Description # of
words # of
cycles Status Flags
Affected
2002 Microchip Technology Inc. Advance Information DS70082A-page 159
dsPIC30F
51 MOV MOV f,Wn Move f to Wn 1 1 None
MOV fMove f to f 1 1 N,Z
MOV f,WREG Move f to WREG 1 1 N,Z
MOV #lit16,Wn Move 16-bit literal to Wn 1 1 None
MOV.b #lit8,Wn Move 8-bit literal to Wn 1 1 None
MOV Wn,f Move Wn to f 1 1 None
MOV Wso,Wdo Move Ws to Wd 1 1 None
MOV WREG,f Move WREG to f 1 1 N,Z
MOV.D Wns,Wd Mo ve Double from W(ns):W(ns+1) to Wd 1 2 None
MOV.D Ws,Wnd Move Double from Ws to W(nd+1):W(nd) 1 2 None
52 MOVSAC MOVSAC Acc,Wx,Wxd,Wy,Wyd,AWB Move Special 1 1 None
53 MPY MPY Wm*Wn,Acc,Wx,Wxd,Wy,Wyd Multiply Wm by Wn to Accumulator 1 1 OA,OB,OAB,
SA,SB,SAB
MPY Wm*Wm,Acc,Wx,Wxd,Wy,Wyd Square Wm to Accumulator 1 1 OA,OB,OAB,
SA,SB,SAB
54 MPY.N MPY.N Wm*Wn,Acc,Wx,Wxd,Wy,Wyd -(Multiply Wm by Wn) to Accumulator 1 1 None
55 MSC MSC Wm*Wm,Acc,Wx,Wxd,Wy,Wyd,
AWB Multiply and Subtract from Accumulator 1 1 OA,OB,OAB,
SA,SB,SAB
56 MUL MUL.SS Wb,Ws,Wnd {Wnd+1, Wnd} = signed(Wb) * signed(Ws) 1 1 None
MUL.SU Wb,Ws,Wnd {Wnd+1, Wnd} = signed(Wb) * unsigned(Ws) 1 1 None
MUL.US Wb,Ws,Wnd {Wnd+1, Wnd} = unsigned(Wb) * signed(Ws) 1 1 None
MUL.UU Wb,Ws,Wnd {Wnd+1, Wnd} = unsigned(Wb) *
unsigned(Ws) 1 1 None
MUL.SU Wb,#lit5,Wnd {Wnd+1, Wnd} = signed(Wb) * unsigned(lit5) 1 1 None
MUL.UU Wb,#lit5,Wnd {Wnd+1, Wnd} = unsigned(Wb) *
unsigned(lit5) 1 1 None
MUL fW3:W2 = f * WREG 1 1 None
57 NEG NEG Acc Negate Accumulator 1 1 OA,OB,OAB,
SA,SB,SAB
NEG ff = f + 1 1 1 C,DC,N,OV,Z
NEG f,WREG WREG = f + 1 1 1 C,DC,N,OV,Z
NEG Ws,Wd Wd = Ws + 1 1 1 C,DC,N,OV,Z
58 NOP NOP No Operation 1 1 None
NOPR No Operation 1 1 None
59 POP POP fPop f from top-of-stack (TOS) 1 1 None
POP Wdo Pop from top-of-stack (TOS) to Wdo 1 1 None
POP.D Wnd Pop from top-of-stack (TOS) to
W(nd):W(nd+1) 1 2 None
POP.S Pop Shadow Registers 1 1 All
60 PUSH PUSH fPush f to top-of-stack (TOS) 1 1 None
PUSH Wso Push Wso to top-of-stack (TOS) 1 1 None
PUSH.D Wns Push W(ns):W(ns+1) to top-of-stack (TOS) 1 2 None
PUSH.S Push Shadow Registers 1 1 None
61 PWRSAV PWRSAV #lit1 Go into Standby mode 1 1 WDTO,SLEEP
62 RCALL RCALL Expr Relative Call 1 2 None
RCALL Wn Computed Call 1 2 None
63 REPEAT REPEAT #lit14 Repeat Next Instruction lit14+1 times 1 2 None
REPEAT Wn Repeat Next Instruction (Wn)+1 times 12 None
64 RESET RESET Software device RESET 11 None
65 RETFIE RETFIE Return from interrupt enable 13 (2) None
66 RETLW RETLW #lit10,Wn Return with literal in Wn 13 (2) None
67 RETURN RETURN Return from Subroutine 13 (2) None
68 RLC RLC ff = Rotate Left through Carry f 1 1 C,N,Z
RLC f,WREG WREG = Rotate Left through Carry f 1 1 C,N,Z
RLC Ws,Wd W d = Rotate Left through Carry Ws 1 1 C,N,Z
TABLE 22-2: INSTRUCTION SET OVERV IEW (CONTINUED)
Base
Instr
#
Assembly
Mnemonic Assembly Syntax Description # of
words # of
cycles Status Flags
Affected
dsPIC30F
DS70082A-page 160 Advance Information 2002 Microchip Technology Inc.
69 RLNC RLNC ff = Rotate Left (No Carry) f 1 1 N,Z
RLNC f,WREG WREG = Rotate Left (No Carry) f 1 1 N,Z
RLNC Ws,Wd Wd = Rotate Left (No Carry) Ws 1 1 N,Z
70 RRC RRC ff = Rotate Right through Carry f 1 1 C,N,Z
RRC f,WREG WREG = Rotate Right through Carry f 1 1 C,N,Z
RRC Ws,Wd Wd = Rotate Right through Carry Ws 1 1 C,N,Z
71 RRNC RRNC ff = Rotate Right (No Carry) f 1 1 N,Z
RRNC f,WREG WREG = Rotate Right (No Carry) f 1 1 N,Z
RRNC Ws,Wd Wd = Rotate Right (No Carry) Ws 1 1 N,Z
72 SAC SAC Acc,#Slit4,Wdo Store Accumulator 1 1 None
SAC.R Acc,#Slit4,Wdo Store Rounded Accumulator 1 1 None
73 SE SE Ws,Wnd Wnd = sign extended Ws 1 1 C,N,Z
74 SETM SETM ff = 0xFFFF 1 1 None
SETM WREG WREG = 0xFFFF 1 1 None
SETM Ws Ws = 0xFFFF 1 1 None
75 SFTAC SFTAC Acc,Wn Arithmetic Shift Accumulator by (Wn) 1 1 OA,OB,OAB,
SA,SB,SAB
SFTAC Acc,#Slit5 Arithmetic Shift Accumulator by Slit5 1 1 OA,OB,OAB,
SA,SB,SAB
76 SL SL ff = Left Shift f 1 1 C,N,OV,Z
SL f,WREG WREG = Left Shift f 1 1 C,N,OV,Z
SL Ws,Wd Wd = Left Shift Ws 1 1 C,N,OV,Z
SL Wb,Wns,Wnd Wnd = Left Shift Wb by Wns 1 1 N,Z
SL Wb,#lit5,Wnd Wnd = Left Shift Wb by lit5 1 1 N,Z
77 SUB SUB Acc Subtr a ct Accu m u l at o r s 1 1 OA,OB,OAB,
SA,SB,SAB
SUB ff = f - WREG 1 1 C,DC,N,OV,Z
SUB f,WREG WREG = f - WREG 1 1 C,DC,N,OV,Z
SUB #lit10,Wn Wn = Wn - lit10 1 1 C,DC,N,OV,Z
SUB Wb,Ws,Wd Wd = Wb - Ws 1 1 C,DC,N,OV,Z
SUB Wb,#lit5,Wd Wd = Wb - lit5 1 1 C,DC,N,OV,Z
78 SUBB SUBB ff = f - WREG - (C) 1 1 C,DC,N,OV,Z
SUBB f,WREG WREG = f - WREG - (C) 1 1 C,DC,N,OV,Z
SUBB #lit10,Wn Wn = Wn - lit10 - (C) 1 1 C,DC,N,OV,Z
SUBB Wb,Ws,Wd Wd = Wb - Ws - (C) 1 1 C,DC,N,OV,Z
SUBB Wb,#lit5,Wd Wd = Wb - lit5 - (C) 1 1 C,DC,N,OV,Z
79 SUBR SUBR ff = WREG - f 1 1 C,DC,N,OV,Z
SUBR f,WREG WREG = WREG - f 1 1 C,DC,N,OV,Z
SUBR Wb,Ws,Wd Wd = Ws - Wb 1 1 C,DC,N,OV,Z
SUBR Wb,#lit5,Wd Wd = lit5 - Wb 1 1 C,DC,N,OV,Z
80 SUBBR SUBBR ff = WREG - f - (C) 1 1 C,DC,N,OV,Z
SUBBR f,WREG WREG = WREG -f - (C) 1 1 C,DC,N,OV,Z
SUBBR Wb,Ws,Wd Wd = Ws - Wb - (C) 1 1 C,DC,N,OV,Z
SUBBR Wb,#lit5,Wd Wd = lit5 - Wb - (C) 1 1 C,DC,N,OV,Z
81 SWAP SWAP.b Wn Wn = nibbl e swap Wn 1 1 None
SWAP Wn Wn = byte swap Wn 1 1 None
82 TBLRDH TBLRDH Ws,Wd Read Prog<23:16> to Wd<7:0> 1 2 None
83 TBLRDL TBLRDL Ws,Wd Read Prog<15:0> to Wd 1 2 None
84 TBLWTH TBLWTH Ws,Wd Write Ws <7:0 > to Prog <23:16> 1 2 None
85 TBLWTL TBLWTL Ws,Wd Writ e Ws to Prog <15: 0> 1 2 None
86 ULNK ULNK Unlink frame pointer 1 1 None
87 XOR XOR ff = f .XOR. WREG 1 1 N,Z
XOR f,WREG WREG = f .XOR. WREG 1 1 N,Z
XOR #lit10,Wn Wd = lit10 .XOR. Wd 1 1 N,Z
XOR Wb,Ws,Wd Wd = Wb .XOR. Ws 1 1 N,Z
XOR Wb,#lit5,Wd Wd = Wb .XOR. lit5 1 1 N,Z
88 ZE ZE Ws,Wnd Wnd = Zero-Extend Ws 1 1 None
TABLE 22-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Base
Instr
#
Assembly
Mnemonic Assembly Syntax Description # of
words # of
cycles Status Flags
Affected
2002 Microchip Technology Inc. Advance Information DS70082A-page 161
dsPIC30F
23.0 DEVELOPMENT SUPPORT
Microc hip offers a comp rehens ive p ac kage of dev elop-
ment tools and libraries to support the dsPIC architec-
ture. In addition, the company is partnering with many
third party tools manufacturers for additional dsPIC
device support. The Microchip tools will include:
MPLAB 6.00 Integrat ed De ve lop me nt
Environment (IDE)
dsPIC La nguage Suite, including MPLAB C30
C Compiler, Assembler, Linker and Librarian
MPLAB SIM Software Simulator
MPLAB ICE 4000 In-Circuit Emulator
MPLAB ICD 2 In-Circuit Debugger
PRO MATE® II Universal Device Programmer
PICSTART® Plus Development Programmer
23.1 MPLAB V6.00 Integrated
Development Environment
Software
The MPLAB Integrated Development Environment is
available at no cost. The MPLAB IDE gives users the
flexibi li t y to edi t, co mp il e and emulate, all f rom a si ngl e
user int erface. Engi neers can de sign and dev elop code
for the dsP IC d evic es in th e same de si g n envi r onm en t
that they have used for PICmicro® microcontrollers.
The MPLAB IDE is a 32-bit Windows® based applica-
tion. It pr ovi des many adva nced f eatur es for t he criti cal
engineer in a modern, easy to use interface. MPLAB
IDE integrates :
Full featured, color coded text editor
Easy to use project manager with visual display
Source level debugging
Enhanced source level debugging for C
(structures, automatic variables, etc.)
Customizable toolbar and key mapping
Dynamic status bar displays processor condition
at a glance
Context sensitive, interactive on-line help
Integrated MPLAB SIM instruction simulator
User interface for PRO MATE II and PICSTART
Plus device programmers (sold separately)
User interface for MPLAB ICE 4000 In-Circuit
Emulator (sold separately)
User interface for MPLAB ICD 2 In-Circuit
Debugger
The MPLAB IDE allows the engineer to:
Edit your source files in either assembly or C
One-touch compile and download to dsPIC
program memory on emulator or simulator.
Updates all project information.
Debug us ing :
- Source f iles
- Machine code
- Mixed mode source and machine code
The ability to use the MPLAB IDE with multiple devel-
opment and debugging targets allows users to easily
switch from the cost effective simulator to a full-
featured emulator with minimal retraining.
23.2 dsPIC Language Suite
The Mi cro chip Tech nology MPLAB C30 C comp iler i s a
fully ANSI compliant product with standard libraries for
the dsPI C archi tecture. It is h ighly optimiz ing and t ake s
advantage of many dsPIC architecture specific fea-
tures to provide efficient software code generation.
MPLAB C30 also provides extensions that allow for
excellent support of the hardware, such as interrupts
and peripherals. It is fully integrated with the MPLAB
IDE for high level, source debugging.
16-bit native data types
Efficient use of register-based, 3-operand
instructions
Complex addressing modes
Efficient multi-bit shift operations
Efficient signed/unsigned comparisons
MPLAB C30 comes complete wi th its ow n assembl er,
linker a nd librari an. These allow t he user to write Mi xed
mode C and assembly programs and link the resulting
object files into a s ingle exe cut able file. The c ompi ler i s
sold se para tely. The asse mbler, linker and librari an are
availa ble for free with MPLAB C30.
23.3 MPLAB SIM Software Simulator
The MPLAB SIM sof tware simulat or allows code deve l-
opment in a PC-ho ste d env iro nm ent , by si mu lat ing the
dsPIC device on an instruction level. On any given
instruction, the data areas can be examined or modi-
fied and stimuli can be applied from a file, or user
defined key press, to any of the pins.
The execution can be performed in Single Step, Exe-
cute Until Break, or Trace mode.
The MPLAB SIM simulator fully supports symbolic
debuggi ng using the MPL AB C30 c ompiler and ass em-
bler. The software simulator offers the flexibility to
develop and debug c ode out side o f the la boratory e nvi-
ronment, making it an excellent multi-project software
development tool.
dsPIC30F
DS70082A-page 162 Advance Information 2002 Microchip Technology Inc.
23.4 MPLAB ICE 4000 In-Circuit
Emulator
The MPLAB ICE 4000 In-Circuit Emulator is intended
to provide the product development engineer with a
complete hardware design tool for the dsPIC devices.
Software control of the emula tor is provide d by MPLAB
ICE, allowing editing, building, downloading and
source debugging from a single environment.
The MPLAB ICE 4000 is a full-featured emulator sys-
tem with enhanced trace, trigger and data monitoring
featur es. Interchangea ble processo r modules al low the
system to be easi ly reconfi gured for em ulation of d iffer-
ent processors. The MPLAB ICE 4000 supports the
extended, high end PICmicro microcontrollers, the
PIC18CXXX and PIC18FXXX devices, as well as the
dsPIC30F family of digital signal controllers. The mod-
ular architecture of the MPLAB ICE in-circuit emulator
allows expansion to support new devices.
The MPLAB ICE in-circuit emulator system has been
designed as a real-time emulation system, with
advanced features that are generally found on more
expensive development tools.
Full-speed emula tion, up to 50MHz b us spe ed , or
200MHz external clock speed
Low-voltage emulation down to 1.8 volts
Config ured with 2 Mb progra m emulati on memory,
additional modular memory up to 16Mb
64K x 136-bit wide Trace Memory
Unlimited software breakpoints
Complex break, trace and trigger logic
Multi-level trigger up to 4 levels
Filter trigger func tions to trace specific event
16-bit Pass counter for triggering on sequential
events
16-bit Delay counter
48-bit time stamp
Stopwatch feature
Time between events
Statis tic al perf orm anc e anal ys is
Code coverage analysis
USB and parallel printer port PC connection
23.5 MPLAB ICD 2 In-Circuit Debugger
Microchips In-Circuit Debugger, MPLAB IC D, is a pow-
erful, low cost, run-time development tool. This tool is
based on the PICmicro and dsPIC30F FLASH devices.
The MPLAB ICD utilizes the in-circuit debugging capa-
bility built into the various devices. This feature, along
with Microchips In-C ircuit Serial Pr ogrammingTM proto-
col, offers cost-effective in-circuit debugging from the
graphical user interface of MPLAB. This enables a
designer to develop and debug source code by watching
variables, single-stepping and setting b reak point s. Run-
ning at full speed enables tes ting hardw are in real-time.
Full speed operation to the range of the device
Serial or USB PC connector
Serial interface externally powered
USB powered from PC interface
Low-noise power (VPP and VDD) for use with ana-
log and other noise sensitive applications
Operation down to 2.0v
Can be used as an ICD or in-expensive serial pro-
grammer
Modular application connector as MPLAB-ICD
Limited number of breakpoints
•“Smart watch variable windows
Some chip resources required (RAM, program
memory and 2 pins)
23.6 PRO MATE II Universal Device
Programmer
The PRO MATE II universal device programmer is a
full-featured programmer, capable of operating in
stand-alone mode, as well as PC-hosted mode. The
PRO MATE II device programmer is CE co mpliant.
The PRO MATE II device programmer has programma-
ble VDD and VPP supplies, which allow it to verify pro-
grammed memory at VDDMIN and VDDMAX for
maximum reliability when programming requiring this
capability. It has an LCD display for instructions and
error messages, keys to enter commands. Inter-
changeable socket modules all package types.
In Stand Alone mode, the PRO MATE II device pro-
grammer can read, verify, or program PICmicro and
dsPIC30F devices. It can also set code protection in
this mode. PRO MATE II features include:
Runs under MPLAB IDE
Field upgradable firmware
DOS Command Line interface for production
Host, Safe, and Stand Alone operation
Automatic downloading of object file
SQTPSM serialization adds unique serial number
to each device programmed
In-Circuit Serial Programming Kit (sold sep arately)
Interchangeable socket modules supports all
package op tions (sold separately)
2002 Microchip Technology Inc. Advance Information DS70082A-page 163
dsPIC30F
24.0 ELECTRICAL
CHARACTERISTICS
Electrical characteristics are not available at this time.
dsPIC30F
DS70082A-page 164 Advance Information 2002 Microchip Technology Inc.
NOTES:
2002 Microchip Technology Inc. Advance Information DS70082A-page 165
dsPIC30F
25.0 DC AND AC
CHARACTERISTICS GRAPHS
AND TABLES
DC and AC Characteristics Graphs and Tables are not
available at this time.
dsPIC30F
DS70082A-page 166 Advance Information 2002 Microchip Technology Inc.
NOTES:
2002 Microchip Technology Inc. Advance Information DS70082A-page 167
dsPIC30F
26.0 PACKAGING INFORMATION
26.1 Package Marking Information
XXXXXXXXXXXXXXXXX
YYWWNNN
28-Lead PDIP (Skinny DIP) Example
XXXXXXXXXXXXXXXXX
0248017
dsPIC30F3010-I/SP
28-Lead SOIC
YYWWNNN
Example
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX 0248017
dsPIC30F4011-I/SO
Legend: XX...X Customer specific information*
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week 01)
NNN Alphanumeric traceability code
Note: In the event the full Mic rochi p pa rt numbe r cannot b e marke d on one li ne, it will
be carried ov er to th e ne xt li ne th us limiti ng th e num be r of av ail ab le c hara cte rs
for customer specific information.
*Standard PICmicro device marking consists of Microchip part number, year code, week code, and
traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check
with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP
price.
XXXXXXXXXXXXXXXXXX
YYWWNNN
40-Lead PDIP Example
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
dsPIC30F4011-I/P
0248017
dsPIC30F
DS70082A-page 168 Advance Information 2002 Microchip Technology Inc.
26.2 Package Marking Information (Continue d)
44-Lead TQFP Example
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
dsPIC30F
4011-I/PT
0248017
80-Lead TQFP
XXXXXXXXXXXX
YYWWNNN
XXXXXXXXXXXX
Example
dsPIC30F5013
0236017
-I/PT
2002 Microchip Technology Inc. Advance Information DS70082A-page 169
dsPIC30F
28-Lead Skinny Plasti c Dual In-line (SP) 300 mil (PDIP)
1510515105
β
Mold Draft Angle Bottom 1510515105
α
Mold Draft Angle Top 10.928.898.13.430.350.320
eB
Overall Row Spacing §0.560.480.41.022.019.016BLower Lead Width 1.651.331.02.065.053.040B1Upper Lead Width 0.380.290.20.015.012.008
c
Lead Thickness 3.433.303.18.135.130.125LTip to Seating Plane 35.1834.6734.161.3851.3651.345DOverall Length 7.497.246.99.295.285.275E1Molded Package Width 8.267.877.62.325.310.300EShoulder to Shoulder Width 0.38.015A1Base to Seating Plane 3.433.303.18.135.130.125A2Mold ed Package Thickness 4.063.813.56.160.150.140ATop to Seating Plane 2.54.100
p
Pitch 2828
n
Number of Pins MAXNOMMINMAXNOMMINDimen sion Li mits MILLIMETERSINCHES*Units
2
1
D
n
E1
c
eB
β
E
α
p
L
A2
B
B1
A
A1
Notes:
JEDEC Equivalent: MO-095
Drawing No. C04-070
* Controlling Parameter
Dimension D and E1 do not in clude mold flash or pro trusions. Mold flash or protru sions shall not exceed
.010 (0.254 mm ) per s ide.
§ Significant Characteristic
dsPIC30F
DS70082A-page 170 Advance Information 2002 Microchip Technology Inc.
28-Lead Plastic Small Outline (SO) Wide, 300 mil (SOIC)
Foot Angle Top φ048048
1512015120
β
Mold Draft Angle Bottom 1512015120
α
Mold Draft Angle Top 0.510.420.36.020.017.014BLead Width 0.330.280.23.013.011.009
c
Lead Thickness
1.270.840.41.050.033.016LFoot Length 0.740.500.25.029.020.010hChamfer Distance 18.0817.8717.65.712.704.695DOverall Length 7.597.497.32.299.295.288E1Molded Package Width 10.6710.3410.01.420.407.394EOverall Width 0.300.200.10.012.008.004A1Standoff §2.392.312.24.094.091.088A2Molded Package Thickness 2.642.502.36.104.099.093AOverall Height 1.27.050
p
Pitch 2828
n
Number of Pins MAXNOMMINMAXNOMMINDimension Limi ts MILLIMETERSINCHES*Units
2
1
D
p
n
B
E
E1
L
c
β
45°
h
φ
A2
α
A
A1
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010 (0.254mm) per side.
JEDEC Equivalent: MS-013
Drawing No. C04-052
§ Significant Characteristic
2002 Microchip Technology Inc. Advance Information DS70082A-page 171
dsPIC30F
40-Lead Plastic Dual In-line (P) 600 mil (PDIP)
1510515105
β
Mold Draft Angle Bottom 1510515105
α
Mold Draft Angle Top 17.2716.5115.75.680.650.620eBOverall Row Spacing §0.560.460.36.022.018.014BLower Lea d Width 1.781.270.76.070.050.030B1Upper Lea d Width 0.380.290.20.015.012.008
c
Lead Thic kness 3.433.303.05.135.130.120LTip to Seating Plane 52.4552.2651.942.0652.0582.045DOverall Length 14.2213.8413.46.560.545.530E1Molded Package Width 15.8815.2415.11.625.600.595EShoulder to Shoulder Width 0.38.015
A1
Base to Seating Plane 4.063.813.56.160.150.140A2Molded Package Thickness 4.834.454.06.190.175.160ATop to Seating Plane 2.54.100
p
Pitch 4040
n
Number of Pins MAXNOMMINMAXNOMMINDimension Limits MILLIMETERSINCHES*Units
A2
1
2
D
n
E1
c
β
eB
E
α
p
L
B
B1
A
A1
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010 (0.254mm) per side.
JEDEC Equivalent: MO-011
Drawing No. C04-016
§ Significant Characteristic
dsPIC30F
DS70082A-page 172 Advance Information 2002 Microchip Technology Inc.
44-Lead Plastic Thin Quad Flatp ack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)
* Controlling Parameter
Notes:
Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010 (0.254mm) per side.
JEDEC Equivalent: MS-026
Drawing No. C04-076
1.140.890.64.045.035.025CHPin 1 Corner Chamfer
1.00.039
(F)
Footprint (Reference)
(F)
A
A1 A2
α
E
E1
#leads=n1
p
B
D1 D
n
1
2
φ
c
βL
Units INCHES MILLIMETERS*
Dim ension Limits MIN NOM MAX MIN N OM MAX
Numb er of Pin s n44 44
Pitch p.031 0.80
Overall Height A .039 .043 .047 1.00 1.10 1.20
Molded Package Thickness A2 .037 .039 .041 0.95 1.00 1.05
Standoff §A1 .002 .004 .006 0.05 0.10 0.15
Foot Length L .018 .024 .030 0.45 0.60 0.75
Foot A ngle φ03.5 7 03.5 7
Overall Width E .463 .472 .482 11.75 12.00 12.25
Overall Length D .463 .472 .482 11.75 12.00 12.25
Molded Package Width E1 .390 .394 .398 9.90 10.00 10.10
Molded Package Length D1 .390 .394 .398 9.90 10.00 10.10
Pins per Side n1 11 11
Lead Thickness c.004 .006 .008 0.09 0.15 0.20
Lead Width B .012 . 015 .017 0.30 0.38 0.44
Mold Draft Angle Top α51015 51015
Mold Draft Angle Bottom β51015 51015
CH x 45°
§ Significant Characteristic
2002 Microchip Technology Inc. Advance Information DS70082A-page 173
dsPIC30F
80-Lead Plastic Thin Quad Flatpack (PT) 12x12x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)
* Controlling Parameter
Notes:
Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010 (0.254mm) per side.
JEDEC Equivalent: MS-026
Drawing No. C04-092
1.101.00.043.039
1.140.890.64.045.035.025CHPin 1 Corner Chamfer
1.00.039
(F)
Footprint (Reference)
(F)
E
E1
#leads=n1
p
B
D1 D
n
1
2
φ
c
βL
A
A1 A2
α
Units INCHES MILLIMETERS*
Dimen sion Li mits MIN N O M MAX MIN N OM MAX
Number of Pins n80 80
Pitch p.020 0.50
Overall Height A .047 1.20
Molded Package Thickness A2 .037 .039 .041 0.95 1.00 1.05
Standoff §A1 .002 .004 .006 0.05 0.10 0.15
Foot Length L .018 .024 .030 0.45 0.60 0.75
Foot Angle φ03.5 7 03.5 7
Overall Width E .541 .551 .561 13.75 14.00 14.25
Overal l Length D . 541 .5 51 .561 13.75 14.00 1 4.2 5
Molded Package Width E1 .463 .472 .482 11.75 12.00 12.25
Molded Package Length D1 .463 .472 .482 11.75 12.00 12.25
Pins per Side n1 20 20
Lead Thickness c.004 .006 .008 0.09 0.15 0.20
Lead Width B .007 .009 .011 0.17 0.22 0.27
Mold Draft Angle Top α5 10 15 5 10 15
Mold Draft Angle Bottom β5 10 15 5 10 15
CH x 45°
§ Significant Characteristic
dsPIC30F
DS70082A-page 174 Advance Information 2002 Microchip Technology Inc.
NOTES:
2002 Microchip Technology Inc. Advance Information DS70082A-page 175
dsPIC30F
INDEX
A
Address Generator Units ....................................................37
Alternate Vector Table .......................................................49
Alternate 16-bit Timer/Counter ...........................................91
Automatic Clock St retc h ...................................................114
During 10-bit Addressing (STREN = 1) ....................114
During 7-bit Addressing (STREN = 1) ......................114
Receive Mode ..........................................................114
Transmit Mode .........................................................114
A/D ...................................................................................133
B
Barrel Shifter ......................................................................23
Bit-Reversed Addressing ...................................................43
Example .....................................................................43
Implementation ..........................................................43
Modifier Values (table) ...............................................44
Sequence Table (16-Entry) ........................................44
Block Diagrams
CAN Buffers and Protocol Engine ............................128
Dedicated Port Structure ............................................61
DSP Engine ...............................................................20
dsPIC30F6010 ...........................................................10
External Power-on Reset Circuit .............................. 148
Input Capture Mode ...................................................81
I2C ............................................................................112
Oscillator System .....................................................142
Output Compare Mode ..............................................85
Quadrature Encoder Interface ...................................89
RESE T System ........................................................146
Shared Port Structure ................................................63
SPI ...........................................................................108
SPI Master/Slave Connection ..................................108
UART Receiver ........................................................120
UART Transmitter ....................................................119
10-bit High Speed A/D Functional ............................134
16-bit Timer1 Module .................................................67
16-bit Timer4 ..............................................................78
16-bit Timer5 ..............................................................78
32-bit Timer4/5 ...........................................................77
8-Output PWM Module ..............................................96
BOR. See Brown-out Reset
Brown-out Reset (BOR) ...................................................141
C
CAN Module .....................................................................127
CAN1 Register Map .................................................129
CAN2 Register Map .................................................131
Overview ..................................................................127
Overview of the Module ...........................................127
Transmit/Receive Buffers .........................................127
Center Aligned PWM ........................................................100
Code Examples
Data EEPROM Block Erase .......................................58
Data EEPROM Block Write ........................................60
Data EEPROM Read .................................................57
Data EEPROM Word Erase .......................................58
Data EEPROM Word Write ........................................59
Erasing a Row of Program Memory ...........................53
Initiating a Programming Sequence ...........................55
Loading Write Latches ...............................................54
Program Space Data Read Through Data
Space Within a REPEAT Loop ..........................28
Code Protection ............................................................... 141
Complementary PW M Operat io n ..................................... 100
Configuring Analog Port Pins ............................................. 63
Control Registers ............................................................... 52
NVMADR ................................................................... 52
NVMADRU ................................................................. 52
NVMCON ................................................................... 52
NVMKEY ................................................................... 52
Core Architecture
Overview .................................................................... 13
Core Register Map ............................................................. 34
D
Data Accumulators and Adder/Subtractor ....................22, 23
Data Address Space .......................................................... 29
Access RAM .............................................................. 31
Alignment ................................................................... 30
Alignment (Figure) ..................................................... 30
Effect of Invalid Memory Acces ses ............................ 30
MCU and DSP (MAC Class) Instructions
Example ............................................................. 33
Memory M ap .............................................................. 30
Memory Map Example ............................................... 32
Spaces ....................................................................... 29
Width ......................................................................... 30
Data EEPROM Memory ..................................................... 57
Erasing ...................................................................... 58
Erasing, Block ............................................................ 58
Erasing, Word ............................................................ 58
Protection Against Spurious Write ............................. 60
Reading ..................................................................... 57
Write Verify ................................................................ 60
Writing ....................................................................... 59
Writing, Block ............................................................. 60
Writi ng, Word ............................................................. 59
Data Space Organization ................................................... 37
DC and AC Characteristics Graphs and Tables .............. 165
Dead-Time Generators .................................................... 101
Assignment .............................................................. 101
Ranges .................................................................... 101
Selection Bits ........................................................... 101
Device Configuration
Register Map ........................................................... 152
Device Configuration Registers ....................................... 151
FBORPOR ............................................................... 151
FGS ......................................................................... 151
FOSC ....................................................................... 151
FWDT ...................................................................... 151
Device Overview .................................................................. 9
Divide Support ................................................................... 18
DSP Engine ....................................................................... 19
Multiplier .................................................................... 21
Dual Output Compare Match Mode ................................... 86
Continuous Pulse Mode ............................................. 86
Single Pulse Mode ..................................................... 86
DSPIC30F
DS70082A-page 176 Advance Information 2002 Microchip Technology Inc.
E
Edge Aligned PWM ............................................................99
Electrical Characteristics ..................................................163
Equations
A/D Conversion Clock ..............................................136
A/D Sampling Time ..................................................137
Baud Rate ................................................................123
PWM Period ...............................................................99
PWM Resolution ........................................................99
Serial Clock Rate .....................................................115
Errata ...................................................................................7
Exception Processing .........................................................45
Interrupt Priority ..........................................................45
Natural Order Priority (table) ......................................46
Exception Sequence
Trap Sources ..............................................................47
External Interrupt Requests ...............................................49
F
Fast Context Saving ...........................................................49
Firmware Instructions .......................................................153
FLASH Program Memory ...................................................51
In-Circuit Serial Programming (ICSP) ........................51
Run Time Self-Programming (RTSP) .........................51
Table Instruction Operation Summary .......................51
I
In-Circuit Serial Programming (ICSP) ..............................141
Independent PWM Output ................................................102
Initializ ation Condition for RCON Register,
Case 1 ......................................................................149
Initializ ation Condition for RCON Register,
Case 2 ......................................................................149
Input Capture Interrupts .....................................................82
Register Map ..............................................................83
Input Capture Module .........................................................81
In CPU SLEEP Mode .................................................82
Simple Capture Event Mode ......................................81
Input Change Notification Module ......................................66
Register Map (bit 15-8) ..............................................66
Register Map (bits 15-8) .............................................66
Register Map (bits 7-0) ...............................................66
Instruction Addressing Modes ............................................37
File Register Instruct i ons ............................................38
Fundamental Modes Supported .................................37
MAC Instructions ........................................................38
MCU Instructions ........................................................38
Move and Accumulator Instruc tions ...........................38
Other Instructions .......................................................38
Instruction Flow ..................................................................16
Pipeline - 1-Word, 1-Cycle (Figure) ............................16
Pipeline - 1-Word, 2-Cycle MOV.D
Operations (Figure) ............................................16
Pipeline - 1-Word, 2-Cycle Table
Operations (Figure) ............................................17
Pipeline - 1-Word, 2-Cycle with Instruction
Stall (Figure) ......................................................18
Pipeline - 1-Word, 2-Cycle (Figure) ............................16
Pipeline - 2-Word, 2-Cycle
DO, DOW (Figure) .............................................17
Pipeline - 2-Word, 2-Cycle GOTO,
CALL (Figure) ....................................................17
Instruction Set ..................................................................153
Instruction Set Overview .................................................. 156
Instruction Stalls ................................................................ 39
Introduction ................................................................ 39
Raw Dependency Detection ...................................... 39
Inter-Integrated Circuit. See I2C
Interrupt Controller
Register Map ............................................................. 50
Interrupt Priority
Traps .......................................................................... 47
Interrupt Sequence ............................................................ 48
Interrupt Stack Fr ame ................................................ 48
I2C .................................................................................... 111
I2C Master Mode
Baud Rate Generator ............................................... 115
Clock Arbitration ...................................................... 116
Multi-Master Communication, Bus Collision,
and Bus Arbitration .......................................... 116
Reception ................................................................. 115
Transmission ........................................................... 115
I2C Module ....................................................................... 111
Addresses ................................................................ 113
General Call Address Support ................................. 115
Interrupts .................................................................. 114
IPMI Support ............................................................ 115
Master Operation ..................................................... 115
Master Support ........................................................ 115
Operating Function Description ............................... 111
Operation During CPU SLEEP and
IDLE Modes ..................................................... 116
Pin Configuration ..................................................... 111
Register Map ........................................................... 117
Registers .................................................................. 111
Slope Control ........................................................... 115
Software Controlled Clock Stretching
(STREN = 1) .................................................... 114
Various Modes ......................................................... 111
I2C Module
Programmers Model ............................................... 111
I2C 10-bit Slave Mode Operation ..................................... 113
Reception ................................................................. 113
Transmission ........................................................... 113
I2C 7-bit Slave Mode Operation ....................................... 113
I2C 7-bit Slave Mode Operation
Reception ................................................................. 113
Transmission ........................................................... 113
I/O Por ts ............................................................................. 61
Para ll e l I/O (P IO) ....................................................... 61
M
Memory Organization ......................................................... 25
Modulo Addressing ............................................................ 40
Applicability ................................................................ 42
Decrementing Buffer Operation Example .................. 42
Incrementing Buffer Operation Example .................... 41
Restrictions ................................................................ 43
Start and End Address ............................................... 40
W Address Register Selection ................................... 40
Motor Control PWM Module ............................................... 95
2002 Microchip Technology Inc. Advance Information DS70082A-page 177
dsPIC30F
O
Oscillator Configurations ..................................................143
Fail-Safe Clock Monitor ............................................145
Fast RC (FRC) .........................................................144
Initial Clock Source Selection ..................................143
Low Power RC (LPRC) ............................................144
LP Oscillator Control ................................................144
Phase Locked Loop (PLL) .......................................144
Start-up Timer (OST) ...............................................144
Oscillator Operating Modes Table ....................................141
Oscillator Selection ..........................................................141
Output Compare Interrupts ................................................87
Output Compare Mode
Register Map ..............................................................88
Output Compare Module ....................................................85
Output Compare Operation During
CPU IDLE Mode ........................................................87
Output Compare SLEEP Mode Operation .........................87
P
Packaging Information .....................................................167
Marking ....................................................................167
Peripheral Module Display (PMD) Registers ....................151
Pinout Descriptions ............................................................11
PORTA
Register Map ..............................................................62
PORTB
Register Map ..............................................................64
PORTC
Register Map ..............................................................64
PORTD
Register Map ..............................................................64
PORTE
Register Map ..............................................................64
PORTF
Register Map ..............................................................65
PORTG
Register Map ..............................................................65
POR. See Power-on Reset
Position Measurement Mode .............................................90
Power Saving Modes .......................................................150
IDLE .........................................................................151
SLEEP .....................................................................150
Power Saving Modes (SLEEP and IDLE) ........................141
Power-on Reset (POR) ....................................................141
Oscillator Start-up Timer (OST) ...............................141
Pow e r-up Timer (PWRT ) .........................................141
Prod u ct Id enti fi catio n System ...........................................183
Program Addre ss Spac e ....................................................25
Alignment and Data Access Using
Table Instructions ...............................................26
Construction ...............................................................25
Data Access from, Address Generation .....................25
Memory Map ..............................................................29
Table Instructions
TBLRDH .............................................................26
TBLRDL .............................................................26
TBLWTH ............................................................26
TBLWTL .............................................................26
Program Counter ................................................................14
Program Data Table Access ..............................................27
Program Space Visibility
Window into Program Space Operation .....................28
Program Space Visibility from Data Space ........................ 27
Data Pre-fetch from Program Space Within a
REPEAT Loop ................................................... 27
Programmable ................................................................. 141
Programmable Digital Noise Filters ................................... 91
Programmers Model ......................................................... 14
Diagram ..................................................................... 15
Programming Operations ................................................... 52
Algorithm for Program FLASH ................................... 53
Erasing a Row of Program Memory ........................... 53
Initiating the Programming Sequence ........................ 55
Loading Write Latches ............................................... 54
Programm ing, Device Ins tr uctions ................................... 153
Protection Against Accidental Writes
to OSCCON ............................................................. 145
PWM Duty Cycle Comparison Units ................................ 100
Duty Cycle Register Buffers ..................................... 100
PWM FAULT Pins ............................................................ 103
Enable Bits .............................................................. 103
FAULT Sta t e s .......................................................... 103
Modes ...................................................................... 103
Cycle-by-Cycle ................................................ 103
Latched ............................................................ 103
Priority ..................................................................... 103
PWM Operation During CPU IDLE Mode ........................ 104
PWM Operation During CPU SLEEP Mode .................... 104
PWM Output and Polarity Control .................................... 103
Output Pin Control ................................................... 103
PWM Output Override ..................................................... 102
Complementary Output Mode .................................. 102
Synchronization ....................................................... 102
PWM Period ....................................................................... 99
PWM Special Event Trigger ............................................. 104
Postscaler ................................................................ 104
PWM Time-Base ................................................................ 98
Continuous Up/Down Counting Modes ...................... 98
Double Update Mode ................................................. 99
Free Running Mode ................................................... 98
Postscaler .................................................................. 99
Prescaler ................................................................... 99
Single Shot Mode ...................................................... 98
PWM Update Lockout ...................................................... 104
Q
QEI Module
Operation During CPU IDLE Mode ............................ 91
Operation During CPU SLEEP Mode ........................ 91
Register Map ............................................................. 93
Timer Operation During CPU IDLE Mode .................. 92
Timer Operation During CPU SLEEP Mode .............. 91
Quadrature Encoder Interface Interrupts ........................... 92
Quadrature Encoder Interface Logic .................................. 90
Quadrature Encoder Interface (QEI) Module ..................... 89
R
RESET ......................................................................141, 146
RESET Sequence .............................................................. 47
RESET Source s ......................................................... 47
RESETS
BOR, Programmable ............................................... 148
POR ......................................................................... 146
Operating without FSCM and PWRT ............... 148
POR with Long Crystal Start-up Time ...................... 148
RTSP Operation ................................................................ 52
DSPIC30F
DS70082A-page 178 Advance Information 2002 Microchip Technology Inc.
S
Sales and Support ............................................................183
Serial Peripheral Interface. See SPI
Simple Capture Event Mode
Capture Buffer Operation ...........................................82
Capture Prescaler ......................................................81
Hall Sensor Mode .......................................................82
Input Capture in CPU IDLE Mode ..............................82
Timer2 and Timer3 Selection Mode ...........................82
Simple Output Compare Match Mode ................................86
Simple PWM Mode ............................................................86
Input Pin FAULT Protection .......................................86
Period .........................................................................87
Single Pulse PWM Operation ...........................................102
Software Stack Pointer, Frame Pointer ..............................14
CALL Stack Frame .....................................................31
SPI ...................................................................................107
SPI Mode
Slave Select Synchronization ...................................109
SPI1 Register Map ...................................................110
SPI2 Register Map ...................................................110
SPI Module .......................................................................107
Framed SPI Support ................................................107
Operating Function Description ................................107
SDOx Disable ...........................................................107
Word and Byte Communication ...............................107
SPI Operation During CPU IDLE Mode ...........................109
SPI Operation During CPU SLEEP Mode ........................109
STATUS Register ...............................................................14
Sticky Z (SZ) Status Bit ..............................................14
Subtractor ...........................................................................22
Data Space Write Saturation ......................................23
Overflow and Saturation .............................................22
Round Logic ...............................................................23
Write Back ..................................................................23
Symbols used in Roadrunner
Opcode Descriptions ................................................154
System Integration ...........................................................141
Overview ..................................................................141
Register Map ............................................................152
T
Timer1 Module ...................................................................67
Gate Operation ...........................................................68
Interrupt ......................................................................68
Operation During SLEEP Mode .................................68
Prescaler ....................................................................68
Real-Time Clock .........................................................68
RTC Interrupts ...................................................68
RTC Oscillator Operation ...................................68
Register Map ..............................................................69
16-bit Asynchronous Counter Mode ...........................67
16-bit Synchronous Counter Mode ............................67
16-bit Timer Mode ......................................................67
Timer2 and Timer 3 Selection Mode ..................................86
Timer2/3 Module ................................................................71
ADC Event Trigger .....................................................74
Gate Operation ...........................................................74
Interrupt ......................................................................74
Operation During SLEEP Mode .................................74
Register Map ..............................................................75
Timer Pres cal er ..........................................................74
32-bit Synchronous Counter Mode ............................71
32-bit Timer Mode ......................................................71
Timer4/5 Module ................................................................ 77
Register Map ............................................................. 79
Timing Diagrams
Center Aligned PWM ............................................... 100
Dead-Time ............................................................... 102
Edge Aligned PWM .................................................... 99
PWM Output .............................................................. 87
Time-out Sequence on Power-up (MCLR Not
Tied to VDD), Case 1 ........................................ 147
Time-out Sequence on Power-up (MCLR Not
Tied to VDD), Case 2 ........................................ 147
Time-out Sequence on Power-up (MCLR
Tied to VDD) ..................................................... 147
U
UART
Address Detect Mode .............................................. 123
Auto Baud Support .................................................. 123
Baud Rate Generator ............................................... 123
Enabling and Setting Up UART ............................... 121
Altern a te I/O .................................................... 121
Disabling .......................................................... 121
Enabling ........................................................... 121
Setting Up Data, Parity and STOP
Bit Selections ........................................... 121
Loopback Mode ....................................................... 123
Module Overview ..................................................... 119
Operation During CPU SLEEP and IDLE Modes .... 124
Receiving Data ........................................................ 122
In 8-bit or 9-bit Data Mode ............................... 122
Interrupt ........................................................... 122
Receive Buffer (UxRCB) .................................. 122
Reception Error Handling ........................................ 122
Framing Error (FERR) ..................................... 123
IDLE Status ..................................................... 123
Parity Erro r (PERR) ......................................... 123
Receive Break ................................................. 123
Receive Buffer Overrun Error
(OERR Bit) ............................................... 122
Transmitting Data
In 8-bit Data Mode ........................................... 121
Transmitting Data .................................................... 121
In 9-bit Data Mode ........................................... 121
Interrupt ........................................................... 122
Transmit Buffer (UxTX B) ................................. 121
UART1 Register Map ............................................... 125
UART2 Register Map ............................................... 125
Unit ID Locations ............................................................. 141
Universal Asynchronous Receiver Transmitter. See UART.
W
Wake-up from SLEEP ...................................................... 141
Wake-up from SLEEP and IDLE ........................................ 49
Watchdog Timer (WDT) ............................................141, 150
Enabling and Disabling ............................................ 150
Operation ................................................................. 150
WWW, On-Line Support ...................................................... 7
2002 Microchip Technology Inc. Advance Information DS70082A-page 179
dsPIC30F
Z
10-bit High Speed Analog-to-Digital Converter. See A/D
10-bit High Speed A/D
Aborting a Conversion .............................................136
ADCHS ....................................................................133
ADCON1 ..................................................................133
ADCON2 ..................................................................133
ADCON3 ..................................................................133
ADCSSL ...................................................................133
ADPCFG ..................................................................133
Analog Input Model ..................................................137
Configuring Analog Port Pins ...................................139
Connection Considerations ......................................139
Conversion Operation ..............................................135
Effects of a RESET ..................................................138
Operation During CPU IDLE Mode ..........................138
Operation During CPU SLEEP Mode ......................138
Output Formats ........................................................139
Power-down Modes .................................................138
Programming the Start of Conversion Trigger .........136
Register Map ............................................................140
Result Buffer ............................................................135
Sampling Requirements ...........................................137
Selecting the Conversion Clock ...............................136
Selecting the Conversion Sequence ........................135
TAD vs. Device Operating Frequencies Table ..........136
16-bit Integer and Fractional Modes Example ...................21
16-bit Up/Down Position Counter Mode .............................90
Count Direction Status ...............................................90
Error Checking ...........................................................90
6-Output PWM
Register Map ............................................................105
6-Output PWM vs . 8-Ou tput PWM
Feature Summary ......................................................95
8-Output PWM
Register Map ............................................................105
DSPIC30F
DS70082A-page 180 Advance Information 2002 Microchip Technology Inc.
NOTES:
2002 Microchip Technology Inc. Advance Information DS70082A-page181
dsPIC30F
Systems Information and Upgrade Hot Line
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dsPIC30F
DS70082A-page182 Advance Information 2002 Microchip Technology Inc.
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DS70082A
dsPIC30F
2002 Microchip Technology Inc. Advance Information DS70082A-page 183
dsPIC30F
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
* JW Devices are UV erasable and can be programmed to any device configuration. JW Devices meet the electrical requirement of
each oscillator type.
Sales and Support
Examples:
a) dsPIC30F2011 ATP-E/SO = Extended temp., SOIC package, Rev. A.
b) dsPIC30F6014ATP-I/PT = I ndustri al temp., TQFP package, Rev. A.
c) dsPIC30F3011 ATP-I/P = Industrial temp., PDIP package, Rev. A.
dsPIC30LF1001ATP-I/PT-000
Trademark
Family
Memory
Type
FLASH = F
E = Extended High Temp -40°C to +125°C
I = Industrial -40°C to +85°C
Temperature
Device ID
P = Pilot
Package
PT = TQF P 10x10
PT = TQF P 12x12
PF = TQFP 14x14
SO = SOIC
SP = SDIP
P=DIP
S = Die (Waffle Pack)
W = Die (Wafers)
L = Low Voltage
Memory Size in Bytes
0 = ROMless
1 = 1K to 6K
2 = 7K to 12K
3 = 13K to 24K
4 = 25K to 48K
5 = 49K to 96K
6 = 97K to 192K
7 = 193K to 384K
8 = 385K to 768K
9 = 769K and Up
Custom ID
T = Tape and Reel
A,B,C = Revision
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-
mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office
2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277
3. The Microchip Worldwide Site (www. micr ochip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
New Customer Notification System
Register on our web site (www.microchip.com /cn) to receive the most current information on our products.
DS70082A-page 184 Advance Information 2002 Microchip Technology Inc.
M
AMERICAS
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200 Fax: 480-792-7277
Technical Support: 480-792-7627
Web Address: http://ww w.microchip .com
Rocky Mountain
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Chandler, AZ 85224-6199
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Atlanta
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Westford, MA 01886
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Chicago
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Dallas
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Detroit
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New York
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Hauppauge, NY 11788
Tel : 631 -2 73- 530 5 Fax: 631- 273 -5335
San Jose
Microchip Technology Inc.
2107 North First Street, Suite 590
San Jose, CA 95131
Tel : 408 -4 36- 795 0 Fax: 408- 436 -7955
Toronto
6285 Northam Drive, Suite 108
Mississ aug a, Ontario L4V 1X5, C ana da
Tel: 905-673-0699 Fax: 905-673-6509
ASIA/PACIFIC
Australia
Microchip Technology Australia Pty Ltd
Suite 22, 41 Rawson Street
Epping 212 1, NSW
Australia
Tel: 61-2-9868-6733 Fax: 61-2-9868-6755
China - Beijin g
Microchip Technology Consulting (Shanghai)
Co., Ltd., Beijing Liaison Office
Unit 915
Bei Hai Wa n Tai Bldg.
No. 6 Chaoyangmen Beidajie
Beijing, 100027, No. China
Tel: 86-10-85282100 Fax: 86-10-85282104
China - Chengdu
Microchip Technology Consulting (Shanghai)
Co., Ltd., Chengdu Liaison Office
Rm. 2401, 24th Floor,
Ming Xing Financial Tower
No. 88 TIDU Street
Cheng du 610 016 , Chi na
Tel: 86-28-86766200 Fax: 86-28-86766599
China - Fuzhou
Microchip Technology Consulting (Shanghai)
Co., Ltd., F u zhou Liaison O ffice
Unit 28F, World Trade Plaza
No. 71 Wusi Road
Fuzhou 350001, China
Tel: 86-591-7503506 Fax: 86-591-7503521
China - Shanghai
Microchip Technology Consulting (Shanghai)
Co., Ltd.
Room 701, Bldg. B
Far East International Plaza
No. 317 Xian Xia Road
Shanghai, 200051
Tel: 86-21-6275-5700 Fax: 86-21-6275-5060
China - Shenzhen
Microchip Technology Consulting (Shanghai)
Co., Ltd., Shenzhen Liaison Office
Rm. 1315, 13/F, Shenzhen Kerry Centre,
Renminnan Lu
Shenzhen 518001, China
Tel: 86-755-2350361 Fax: 86-755-2366086
China - Hong Kong SAR
Microchip Technology Hongkong Ltd.
Unit 901-6, Tower 2, Metroplaza
223 Hing Fong Road
Kwai Fong, N.T., Hong Kong
Tel: 852-2401-1200 Fax: 852-2401-3431
India
Microchip Technology Inc.
India Liaiso n Office
Divyasree Chambers
1 Floor, Wing A (A3/A4)
No. 11, OShaugnessey Road
Bangalore, 560 025, India
Tel: 91-80-2290061 Fax: 91-80-2290062
Japan
Microchip Technology Japan K.K.
Benex S-1 6F
3-18-20, Shinyokohama
Kohoku-Ku, Yokohama-shi
Kanagawa, 222-0033, Japan
Tel: 81-45-471- 6166 Fax: 81-45-471-6122
Korea
Microc hip Technolo gy Korea
168-1, You ng bo Bld g. 3 Floor
Samsung-Dong, Kangnam-Ku
Seoul, Ko re a 135- 88 2
Tel: 82-2-554-7200 Fax: 82-2-558-5934
Singapore
Microchip Technology Singapore Pte Ltd.
200 Midd le Ro ad
#07-02 Prime Centre
Singapore, 188980
Tel: 65-6334-8870 Fax: 65-6334-8850
Taiwan
Microchip Technology (Barb ad os) Inc. ,
Taiwan Branch
11F-3, No. 207
Tung Hua North Road
Taipei, 105, Taiwan
Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
EUROPE
Austria
Microchip Technology Austria GmbH
Durisolstrasse 2
A-4600 Wels
Austria
Tel: 43-7242-2244-399
Fax: 43-7242-2244-393
Denmark
Microchip Technology Nordic ApS
Regus Business Centre
Lautrup hoj 1-3
Ballerup DK-2750 Denmark
Tel: 45 4420 9895 Fax: 45 4420 9910
France
Microc hip Technolo gy SARL
Parc dActivite du Moulin de Massy
43 Rue du Sa ule Trapu
Batiment A - ler Et age
91300 Massy, France
Tel: 33-1-69-53-63-20 Fax: 33-1-69- 30-90-79
Germany
Microc hip Technolo gy Gmb H
Gustav-Heinemann Ring 125
D-81739 Munich, Germany
Tel: 49-89-627-144 0 Fax: 49-89-627-144-44
Italy
Microc hip Technolo gy SRL
Centro Direzionale Colleoni
Palazzo Taurus 1 V. Le Colleoni 1
20041 Agrate Brianza
Milan, Italy
Tel: 39-039-65791-1 Fax: 39-039-6899883
United Kingdom
Micro chip Ltd.
505 Eskdale Road
Winnersh Triangle
Wokingham
Berksh ire, E ngla nd RG 41 5TU
Tel: 44 118 921 5869 Fax: 44-118 921-5820
05/16/02
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