dsPIC30F2010ATP-E/SP - Microchip Technology

 2002 Microchip Technology Inc. Advance Information DS70082A

dsPIC30F Data Sheet

Motor Control and

Power Conversion Family

High Performance

Digital Signal Controllers

DS70082A - page ii Advance Information  2002 Microchip Technology Inc.

Information contained in this publication regarding device

applications and the like is intended through sug gestion only

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

No representation or warranty is given and no liability is

assumed by Microc hip Technology Incorporated with respect

to the accuracy or use of such inf orm ation, or inf ringement of

patents or other intellectual property rights arising from such

use or otherwise. Use of Microchip’s products as critical com-

ponents in life support systems is not authorized except with

express written approval by Microchip. No licenses are con-

veyed, implicitly or otherwise, under any intellectual property

rights.

Trademarks

The Microchip name and logo, the Microchip logo, FilterLab,

KEELOQ, microID, MPLAB, PIC, PICmicro, PICMASTER,

PICSTART, PRO MATE, SEEVAL and The Embedded Control

Solutions Company are registered trademarks of Microchip

Technology Incorporated in the U.S.A. and other countries.

dsPIC, ECONOMONITOR, FanSense, FlexRO M, fuzzyLAB,

In-Circuit Serial Programming, ICSP, ICEPIC, microPort,

Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM,

MXDEV, MXLAB, PICC, PICDEM, PICDEM.net, rfPIC, Se lect

Mode and Total Endurance are trademarks of Microchip

Technology Incorporated in the U.S.A.

Serialized Quick Turn Programming (SQTP) is a service mark

of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Microchip received QS-9000 quality system

certification for its worldwide headquarters,

design and wafer fabrication facilities in

Chandler and Tempe, Arizona in July 1999. The

Company’s quality system processes and

procedures are QS-9000 compliant for its

PICmicro® 8-bit MCUs, KEELOQ® code ho pp in g

devices, Serial EEPROMs and microperipheral

products. In addition, Microchip’s quality

system for the design and manufacture of

development systems is ISO 9001 certified.

Note the following details of the code protection feature on PICmicro® MCUs.

•The PICmicro family meets the specifications contained in the Microchip Data Sheet.

•Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today,

when used in the intended manner and under normal conditions.

•There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowl-

edge, require using the PICmicro microcontroller in a manner outside the operating specifications contained in the data sheet.

The person doing so may be engaged in theft of intellectual property.

•Microchip is willing to work with the customer who is concerned about the integrity of their code.

•Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable”.

•Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of

our product.

If you have any further questions about this matter, please contact the local sales office nearest to you.

 2002 Microchip Technology Inc. Advance Information DS70082A-page 1

MdsPIC30F

High Performance Modified RISC CPU:

•Modified Harvard architecture

•C compiler optimized instruction set architecture

•88 base instructions

•24-bit wide instructions, 16-bit wide data path

•Linear pr ogram memory addressing up to 4M

Instruction Words

•Linear data memory addre ssing up to 64 Kbytes

•Up to 144 Kbytes on-chip FLASH program space

- Up to 48K Instr uction Words

•Up to 8 Kbytes of on-chip data RAM

•Up to 4 Kbytes of non-volatile data EEPROM

•16 x 16-bit working register array

•Three Address Generation Units that enable:

- Dual data fetch

- Accumulator write back for DSP operations

•Flexible Addressing modes supporting:

- Indirect, Modulo and Bit-Reversed modes

•Two, 40-bit wide accumulators with optional

saturati on log ic

•17-bit x 17-bit single cycle hardware fractional/

integer multiplier

•Single cycle Multiply-Accumulate (MAC) operation

•40-stage Barrel Shifter

•Up to 30 MIPs operation:

- DC to 40 MHz external clock input

- 4 MHz - 10 MHz oscillator input with

PLL active (4x, 8x, 16x)

•Up to 42 interrupt sources

- 8 user selectable priority levels

•Vector table with up to 62 vectors

- 54 interrupt vectors

- 8 processor exceptions and software traps

Peripheral Feat ures:

•High current sink /source I/O pi ns: 25 mA/25 mA

•Up to 5 external interrupt sources

•Timer module with programmable prescaler:

- Up to five 16-bit timers/counters; optionally

pair up 16-bit timers into 32-bit timer modules

•16-bit Capture input functions

•16-bit Compare /PWM output functions

- Dua l Co mpare mode availabl e

•3-wire SPITM modules (supports 4 Frame modes)

•I2CTM module suppo r t s Mu lti-Master /Sla ve mo de

and 7-bit/10-bit addressing

Peripheral Feat ures (Continued):

•Addressable UART modules supporting:

- Interrupt on address bit

- Wake-up on START bit

- 4 characters deep TX and RX FIFO buffers

•CAN bus modules

Motor Control PWM Module Features:

•Up to 8 PWM output channels

- Complement ary or Indepe ndent Outpu t modes

- Edge and Center Aligned modes

•4 duty cycle generators

•Dedicated time-base with 4 modes

•Programmable output polarity

•Dead-time control for Complementary mode

•Manual output control

•Trigger for A/D conversions

Quadrature Encoder Interface Module

Features:

•Phase A, Phase B and Index Pulse input

•16-bit up/down position counter

•Count di rection s tatus

•Position Measurement (x2 and x4) mode

•Programmable digital noise filters on inputs

•Alternate 16-bit Timer/Counter mode

•Interrupt on position counter rollover/underflow

Input Capture Module Features:

•Captures 16- bit t imer value

- Capture every 1st, 4th or 16th rising edge

- Capture every falling edge

- Capture every rising and falling edge

•Resolution of 33 ns at 30 MIPs

•Timer2 or Timer3 time-base selection

•Input Capt ure duri ng ID LE

•Interrupt on input capture event

Analog Features:

•10-bit Analog-to-Digital Converter (A/D) with:

- 500 Ksps (for 10-bit A/D) co nversion rate

- Up to 16 input channels

- Conversion available during SLEEP and IDLE

•Programmable Low Voltage Detection (PLVD)

•Programmable Brown-out Detection and Reset

generation

dsPIC30F Enhan ced FLASH 16-bit Digital Signal Contr ollers

Motor Contr ol and Power Conversion Family

 2002 Microchip Technology Inc. Advance Information DS70082A-page 2

dsPIC30F

Special Microcontroller Features:

•Enhanced FLASH program memory

- 10,000 erase/write cycle (typical) for

industrial temperature range

•Data EEPROM memory

- 100,000 erase/write cycle (typical)

industrial temperature range

•Self-reprogrammable under software control

•Power-on Reset (POR), Power-up Timer (PWRT)

and Oscillator Start-up Timer (OST)

•Flexible Watchdog Timer (WDT) with on-chip low

power RC oscillator for reliable operation

•Fail-Safe clock monitor operation

- Det ec t s clo ck failu re and sw it ch es to on-c hip

low power RC oscillator

•Programmable code protection

•In-Circuit Serial Programming™ (ICSP™) via 3

pins and power/ground

•Selectable Power Management modes

- SLEEP, IDLE and Alternate Clock modes

CMOS Technology:

•Low power, high speed FLASH technology

•Wide operating voltage range (2.5V to 5.5V)

•Industrial and Extended temperature ranges

•Low power consumption

 2002 Microchip Technology Inc. Advance Information DS70082A-page 3

dsPIC30F

dsPIC30F Motor Control and Powe r Conversion Family

Pin Diagrams

Device Pins Program

Mem. Bytes/

Instructions

SRAM

Bytes EEPROM

Bytes Timer

16-bit Input

Cap

Output

Comp/Std

PWM

Motor

Control

PWM

A/D 10-bit

500 Ksps Quad

Enc

UART

SPITM

I2CTM

CAN

dsPIC30F2010 28 12K/4K 512 1024 3 4 2 6 ch 6 ch Yes 1 1 1 -

dsPIC30F3010 28 24K/8K 1024 1024 5 4 2 6 ch 6 ch Yes 1 1 1 -

dsPIC30F4012 28 48K/16K 2048 1024 5 4 2 6 ch 6 ch Yes 1 1 1 1

dsPIC30F3011 40/44 24K/8K 1024 1024 5 4 4 6 ch 9 ch Yes 2 1 1 -

dsPIC30F4011 40/44 48K/16K 2048 1024 5 4 4 6 ch 9 ch Yes 2 1 1 1

dsPIC30F5015* 64 66K/22K 2048 1024 5 4 4 8 ch 16 ch Yes 1 2 1 1

dsPIC30F6010 80 144K/48K 8192 4096 5 8 8 8 ch 16 ch Yes 2 2 1 2

* Pinout for dsPIC30F5015 will be provided at a later date.

MCLR

PWM1L/RE0

PWM1H/RE1

PWM2L/RE2

PWM2H/RE3

PWM3L/RE4

PWM3H/RE5VSS

VDD

PGD/EMUD/AN0/VREF+/CN2/RB0

PGC/EMUC/AN1/VREF-/CN3/RB1

AVDD

AVSS

AN2/SS1/LVDIN/CN4/RB2

EMUD2/OC2/IC2/INT2/RD1 EMUC2/OC1/IC1/INT1/RD0

EMUC1/SOSC1/T1CK/U1ARX/CN0/RC14

EMUD1/SOSC2/T2CK/U1ATX/CN1/RC13 VSS

OSC2/CLKO/RC15

OSC1/CLKI VDD

EMUC3/FLTA/INT0/SCK1/OCFA/RE8

U1RX/SDI1/SDA/C1RX/RF2

EMUD3/U1TX/SDO1/SCL/C1TX/RF3

AN5/QEB/IC8/CN7/RB5

AN4/QEA/IC7/CN6/RB4

AN3/INDX/CN5/RB3

28-Pin SDIP

Note: Pinout subject to change.

dsPIC30F2010

AN7/RB7

AN6/OCFA/RB6

C1RX/RF0

C1TX/RF1

OC3/RD2

EMUC2/OC1/IC1/INT1/RD0

AN8/RB8

dsPIC30F3011

MCLR

VDD

VSS

PGD/EMUD/AN0/VREF+/CN2/RB0

PGC/EMUC/AN1/VREF-/CN3/RB1

AN2/SS1/LVDIN/CN4/RB2

EMUD2/OC2/IC2/INT2/RD1

EMUC1/SOSC1/T1CK/U1ARX/CN0/RC14

EMUD1/SOSC2/T2CK/U1ATX/CN1/RC13

OSC2/CLKO/RC15

OSC1/CLKI

AN5/QEB/IC8/CN7/RB5

AN4/QEA/IC7/CN6/RB4

AN3/INDX/CN5/RB3

PWM1L/RE0

PWM1H/RE1

PWM2L/RE2

PWM2H/RE3

PWM3H/RE5

AVDD

AVSS

OC4/RD3

VSS

VDD

EMUC3/SCK1/RF6

U1RX/SDI1/SDA/RF2

EMUD3/U1TX/SDO1/SCK/RF3

PWM3L/RE4

VSS VDD

U2RX/RF4

U2TX/RF5

FLTA/INT0/RE8

40-Pin PDIP

Note: Pinout subject to change.

dsPIC30F3010

dsPIC30F4012

dsPIC30F4011

 2002 Microchip Technology Inc. Advance Information DS70082A-page 4

dsPIC30F

Pin Diagrams (Continued)

EMUD3/U1TX/SDO1/SCL/RF3

EMUC3/SCK1/TC1/RF6

EMUC2/OC1/IC1/INT1/RD0

OC3/RD2

VDD

EMUC1/SOSC1/T1CK/U1ARX/CN0/RC14

VSS

OC4/RD3

EMUD2/OC2/IC2/INT2/RD1

FLTA/INT0/RE8

AN3/INDX/CN5/RB3

AN2/SS1/LVDIN/CN4/RB2

PGC/EMUC/AN1/VREF-/CN3/RB1

PGD/EMUD/AN0/VREF+/CN2/RB0

MCLR

AVDD

AVSS

PWM1L/RE0

PWM1H/RE1

PWM2L/RE2

PWM2H/RE3

PWM3L/RE4

PWM3H/RE5

VDD

VSS

C1RX/RF0

C1TX/RF1

U2RXRF4

U2TX/RF5

U1RX/SDI1/SDA/RF2

AN4/QEA/IC7/CN6/RB4

AN5/QEB/IC8/CN7/RB5

AN6/OCFA/RB6

AN7/RB7

AN8/RB8

VDD

VSS

OSC1/CLKI

OSC2/CLKO/RC15

EMUD1/SOSC2/T2CK/U1ATX/CN1/RC13

dsPIC30F3011

44-Pin TQFP

Note: Pinout subject to change.

dsPIC30F4011

 2002 Microchip Technology Inc. Advance Information DS70082A-page 5

dsPIC30F

Pin Diagrams (Continued)

dsPIC30F6010

IC5/RD12

OC4/RD3

OC3/RD2

EMUD2/OC2/RD1

PWM2L/RE2

PWM1H/RE1

PWM1L/RE0

C2RX/RG0

C2TX/RG1

C1TX/RF1

C1RX/RF0

PWM3L/RE4

PWM2H/RE3

OC8/CN16/UPDN/RD7

OC6/CN14/RD5

EMUC2/OC1/RD0

IC4/RD11

IC2/RD9

IC1/RD8

INT4/RA15

IC3/RD10

INT3/RA14

VSS

OSC1/CLKI

VDD

SCL/RG2

U1RX/RF2

U1TX/RF3

EMUC1/SOSC1/

EMUD1/SOSC2/CN1/RC13

VREF+/RA10

VREF-/RA9

AVDD

AVSS

AN8/RB8

AN9/RB9

AN10/RB10

AN11/RB11

VDD

U2RX/CN17/RF4

IC8/CN21/RD15

U2TX/CN18/RF5

AN6/OCFA/RB6

AN7/RB7

PWM4H/RE7

T2CK/RC1

T4CK/RC3

SCK2/CN8/RG6

SDI2/CN9/RG7

SDO2/CN10/RG8

MCLR

SS2/CN11/RG9

AN4/QEA/CN6/RB4

AN3/INDX/CN5/RB3

AN2/SS1/LVDIN/CN4/RB2

PGC/EMUC/AN1/CN3/RB1

PGD/EMUD/AN0/CN2/RB0

VSS

VDD

PWM3H/RE5

PWM4L/RE6

FLTB/INT2/RE9

FLTA/INT1/RE8

AN12/RB12

AN13/RB13

AN14/RB14

AN15/OCFB/CN12/RB15

VDD

VSS

OC5/CN13/RD4

IC6/CN19/RD13

SDA/RG3

SDI1/RF7

EMUD3/SDO1/RF8

AN5/QEB/CN7/RB5

VSS

OSC2/CLKO/RC15

OC7/CN15/RD6

EMUC3/SCK1/INT0/RF6

IC7/CN 20/ RD 14

80-Pin TQFP

Note: Pinout subject to change.

T1CK/CN0/RC14

 2002 Microchip Technology Inc. Advance Information DS70082A-page 6
dsPIC30F
Table of Contents
0 Device Ov e rv i e w.............................................................. ............................................ ............................................................ 9
0 Core Architecture Overview ................................................................................................................................................... 13
0 Memory Organization................................................ ............. .... ...... ........... .... ...... ........... ...................................................... 25
0 Ad dress G enerator U nits........................................................................................................................................................ 37
0 Exception  Processing.... .................................................................................. ....................................................................... 45
0 FLASH Prog ram Memory............................................ ........................................................................................................... 51
0 Data EEPROM  Memory.. ................... .................................................................................................................................... 57
0 I/O Ports................................................................................................................... .............................................................. 61
0 Timer1 Module....................................................................................................................................................................... 67
0 Timer2/3 Module ............................ .. .... .. ....... .... .. .... .. ....... .... .. .... .. .... ....... .. .... .. .... .. ....... .. ........................................................ 71
0 Timer4/5 Module ............................ .. .... .. ....... .... .. .... .. ....... .... .. .... .. .... ....... .. .... .. .... .. ....... .. ........................................................ 77
0 Input Capture Module............................................................................................................................................................. 81
0 Output Compare Module........................................................................................................................................................ 85
0 Quadrature Encoder Interface (QEI) Module ......................................................................................................................... 89
0 Motor Control PWM Module................................................................................................................................................... 95
0 SPI Module........................................................................................................................................................................... 107
0 I2C Module............ .... .. .. .. .. ..... .. .. .. .. .. .. .. .. ..... .. .... .. .. .. .. .. ..... .. .. .. .. .. .. .. .. ..... .... .. .. .. .. .. .. ..... .......................................................... 111
0 Universal Asynchronous Receiv er Transmitter (UAR T) Module.......................................................................................... 119
0 CAN Module................ .. .. .. ....... .. .. .. .. .. .. .. ..... .... .. .. .. .. .. .. ..... .... .. .. .. .. .. .. ..... .. .... .. .. .. .. .. ..... .. ........................................................ 127
0 10-bit High speed Analog-to-Digital Converter (A/D) Module .............................................................................................. 133
0 System Integration............................................................................................................................................................... 141
0 Instruction Set Summary...................................................................................................................................................... 153
0 Development Support ...................... .. .. .. ....... .. .. .... .. .. .. ....... .. .... .. .. .. ....... .. .. .... .. .. .... ..... .. .... .. .................................................. 161
0 Electrical Characteristics...................................................................................................................................................... 163
0 DC and AC Characteristics Graphs and Tables................................................................................................................... 165
0 Packaging Information ......................................................................................................................................................... 167
Index .................................................................................................................................................................................................. 175
On-Line Support.................... .... .. .... ....... .... .... .. .... ......... .. .... .... .. ......... .. .... .... .. ......... .... .. .... ................................................................. 181
Reader Response.............................................................................................................................................................................. 182
Product Identification System ............................................................................................................................................................ 183

 2002 Microchip Technology Inc. Advance Information DS70082A-page 7

dsPIC30F

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip

products. To this end, we will continue to improv e our publications to better suit your needs. Our publications will be refined and

enhanced as new volumes and updates are introduced.

If you have any questions o r co mm ents regarding this publication, please c ontact the M arketing Communications Department via

E-mail at docerrors@mail.microchip.com or fax the R eader Response Form in the back of th is data sheet to (480) 792-4150.

We welcome your feedback.

Most Current Data Sheet

To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:

http://www.microchip.com

You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.

The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current

devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision

of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

•Microchip’s Worldwide Web site; http://www.microc hip.com

•Your local Microc hip sales office (see last page)

•The Microchip Corporate Literature Center; U.S. F AX: (480) 792-7277

When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include

literature number) you are using.

Customer Noti fic atio n Syst em

 2002 Microchip Technology Inc. Advance Information DS70082A-page 8

dsPIC30F

NOTES:

 2002 Microchip Technology Inc. Advance Information DS70082A-page 9

dsPIC30F

1.0 DEVICE OVERVIEW

This document contains device family specific

information for the dsPIC30F family of Digital Signal

Controller (DSC) devices. The dsPIC30F devices

contain extensive Digital Signal Processor (DSP)

functionality within a high performance 16-bit

Microcontroller (MCU) architecture.

Figure 1-1 shows a sample device block diagram.

Note: The device(s) depicted in this block

diagram are representative of the

corresponding device family. Other

devices of the same family may vary in

terms of number of pins and multiplexing of

pin functions. Typically, smaller devices in

the family contain a subset of the

periphera ls pres ent in the dev ice(s ) shown

in this diagram.

dsPIC30F

DS70082A-page 10 Advance Information  2002 Microchip Technology Inc.

FIGURE 1-1: dsPIC30F6010 BLOCK DIAGRAM

AN8/RB8

AN9/RB9

AN10/RB10

AN11/RB11

Power-up

Timer

Oscillator

Start-up Timer

POR/BOR

Reset

Watchdog

Timer

Instruction

Decode &

Control

OSC1/CLKI

MCLR

VDD, VSS

AN4/QEA/CN6/RB4

AN12/RB12

AN13/RB13

AN14/RB14

AN15/OCFB/CN12/RB15

Low Vo l tage

Detect

UART1,

SPI1, Motor Control

PWM

INT4/RA15

INT3/RA14

VREF+/RA10

VREF-/RA9

CAN2

Timing

Generation

CAN1,

AN5/QEB/CN7/RB5

PCH PCL

Program Counter

ALU<16>

Address Latch

Prog ram Memory

(144 Kbytes)

Data Latch

X Data Bus

I2C

QEI

AN6/OCFA/RB6

AN7/RB7

PCU

PWM1L/RE0

PWM1H/RE1

PWM2L/RE2

PWM2H/RE3

PWM3L/RE4

10-bit ADC

Timers

PWM3H/RE5

PWM4L/RE6

PWM4H/RE7

FLTA/INT1/RE8

FLTB/INT2/RE9

SCK2/CN8/RG6

SDI2/CN9/RG7

SDO2/CN10/RG8

SS2/CN11/RG9

U2TX/CN18/RF5

EMUC3/SCK1/INT0/RF6

SDI1/RF7

EMUD3/SDO1/RF8

Input

Capture

Module

Output

Compare

Module

EMUC1/SOSC1/T1CK/CN0/RC14

EMUD1/SOSC2/CN1/RC13

T4CK/RC3

T2CK/RC1

PORTB

C1RX/RF0

C1TX/RF1

U1RX/RF2

U1TX/RF3

C2RX/RG0

C2TX/RG1

SCL/RG2

SDA/RG3

PORTG PORTF

PORTD

16 16

16 x 16

W Reg Array

Divide

Unit

Engine

DSP

Decode

ROM Latch

Y Data Bus

Effective Address

X RAGU

X WAGU

Y AGU

PGD/EMUD/AN0/CN2/RB0

PGC/EMUC/AN1/CN3/RB1

AN2/SS1/LVDIN/CN4/RB2

AN3/INDX/CN5/RB3

OSC2/CLKO/RC15

U2RX/CN17/RF4

AVDD, A VSS

UART2

SPI2

PORTA

PORTC

PORTE

Interrupt

Controller

PSV & Table

Data Access

Control Bl ock

Stack

Control

Logic

Loop

Control

Logic

Data LatchData Latch

Y Data

(4 Kbytes)

RAM X Data

(4 Kbytes)

RAM

Address

Latch

Address

Latch

Control Signals

to Variou s Blocks

EMUC2/OC1/RD0

EMUD2/OC2/RD1

OC3/RD2

OC4/RD3

OC5/CN13/RD4

OC6/CN14/RD5

OC7/CN15/RD6

OC8/CN16/UPDN/RD7

IC1/RD8

IC2/RD9

IC3/RD10

IC4/RD11

IC5/RD12

IC6/CN19/RD13

IC7/CN20/RD14

IC8/CN21/RD15

Data EEP ROM

(4 Kbyt es)

 2002 Microchip Technology Inc. Advance Information DS70082A-page 11

dsPIC30F

Table 1-1 provides a brief description of device I/O

pinouts and the functions that may be multiplexed to a

port pin. Multiple functions may exist on one port pin.

When multiplexing occurs, the peripheral module’s

functional requirements may force an override of the

data dire ction of the port pin.

TABLE 1-1: PINOUT I/O DESCRIPTIONS

Pin Name Pin

Type Buffer

Type Description

AN0 - AN 15 IAnalog Analog input channels.

AN0 and AN1 are also used for device progr amming data and clock inputs, respect ively.

AVDD P P Positive supply for analog module.

AVSS P P Ground referenc e f or anal og module .

CLKI

CLKO I

OST/CMOS

—External cl ock source inpu t. Al ways assoc i at ed wi t h O SC 1 pin function.

Oscillator crystal output. Connects to crystal or resonator in Crystal

Oscillator mode. Optionally functions as CLKO in RC and EC modes. Always

associ at ed with OSC2 pin func tion.

CN0 - CN23 IST Input change notification inputs.

Can be s of twa re programm ed for internal w eak pull-ups on al l in puts.

COFS

CSCK

CSDI

CSDO

I/O

—

Data Co nverter Int er fa ce fr am e synchroni zation pin.

Dat a C onverter Interface serial cl ock inpu t /output pi n.

Data Co nv erter Interfa ce serial dat a in put pin.

Data Converter Interface serial data output pin.

C1RX

C1TX

C2RX

C2TX

—

CAN1 bus receive pi n.

CAN1 bus transm i t pin.

CAN2 bus receive pi n.

CAN2 bus transm i t pin.

EMUD

EMUC

EMUD1

EMUC1

EMUD2

EMUC2

EMUD3

EMUC3

I/O

ICD Primary Comm unication Channel dat a i nput/output pin.

ICD Primary Comm unication Channel cl ock input pin.

ICD Sec on dary Com m uni cation Channel dat a in pu t/output pin.

ICD Sec ondary Co m munication Channel clock input pin.

ICD Te rti ary C om m unication Channel dat a input/out put pin.

ICD Te rti ary C om m unication Chan nel clock input pin.

ICD Quaternar y Com munication Channel data inp ut / output pin.

ICD Quaternar y C om m unication Channel cl ock input p in .

IC1 - IC8 IST Capture inputs 1 through 8.

INDX

QEA

QEB

UPDN

CMOS

Quadrature Encoder Index Pulse input.

Quadrat ur e Encoder Phase A input in QEI m ode.

Auxiliary Timer External Clock/Gate input in Timer mode.

Quadrat ur e Encoder Phase A input in QEI m ode.

Auxiliary Timer External Clock/Gate input in Timer mode.

Positio n Up/ D own Count er Dir ec tion State.

INT0

INT1

INT2

INT3

INT4

Ex tern a l interr u pt 0.

Ex tern a l interr u pt 1.

Ex tern a l interr u pt 2.

Ex tern a l interr u pt 3.

Ex tern a l interr u pt 4.

LVDIN IAnalog Low Voltage Detect Reference Voltage input pin.

FLTA

FLTB

PWM1L

PWM1H

PWM2L

PWM2H

PWM3L

PWM3H

PWM4L

PWM4H

—

PWM Fa ult A inpu t .

PWM Fa ult B inpu t .

PWM 1 Lo w output.

PWM 1 High output.

PWM 2 Lo w output.

PWM 2 High output.

PWM 3 Lo w output.

PWM 3 High output.

PWM 4 Lo w output.

PWM 4 High output.

Legend: CMOS = CMOS compatible input or output Analog = Analog input

ST = Schmitt Tr ig ger input with CMOS levels O = Output

I = Input P = Power

dsPIC30F

DS70082A-page 12 Advance Information  2002 Microchip Technology Inc.

MCLR I/P ST Mast er Clea r ( R es et ) input or prog ra m m in g voltage input. This pin is an act i ve low

RESET t o th e device.

OCFA

OCFB

OC1 - OC8

—

Compare Fault A input (fo r Compare cha nnels 1, 2, 3 and 4).

Compare Fault B input (fo r Compare cha nnels 5, 6, 7 and 8).

Compare output s 1 t hr ough 8.

OSC1

OSC2 I

I/O ST/CMOS

—Oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise.

Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode.

Option al ly fu nctions as CLKO i n R C and EC modes.

PGD

PGC I/O

IST

ST In-Circ uit Se rial Pr ogr am ming data i nput/outpu t pin.

In-Circ uit Se rial Pr ogr am m i ng cl ock input pin.

RA9 - RA10

RA14 - RA15 I/O

I/O ST

ST PORTA is a bi-directional I/O port.

RB0 - RB15 I/O ST PORTB is a bi-directional I/O port.

RC1

RC3

RC13 - R C15

I/O

PORTC is a bi-directional I/O port.

RD0 - RD15 I/O ST PORTD is a bi-directional I/O port.

RE0 - RE9 I/O ST PORTE is a bi-directional I/O port.

RF0 - RF8 I/O ST PORTF is a bi-direc tion al I/O port.

RG0 - RG3

RG6 - RG9 I/O

I/O ST

ST PORTG is a bi-directional I/O port.

SCK1

SDI1

SDO1

SS1

SCK2

SDI2

SDO2

SS2

I/O

—

Synchronous serial clock input/output for SPI1.

SPI1 Data In.

SPI1 Data Out.

SPI1 Slave Synchronization.

Synchronous serial clock input/output for SPI2.

SPI2 Data In.

SPI2 Data Out.

SPI2 Slave Synchronization.

SCL

SDA I/O

I/O ST

ST Synchronous serial clock input/output for I2C.

Synchronous serial data input/output for I2C.

SOSC1

SOSC2 I

OST/CMOS

—32 kHz low power oscillator crystal input; CMOS otherwise.

32 kHz low power osc i llat or crysta l ou t put .

T1CK

T2CK

T3CK

T4CK

T5CK

Timer1 external clock input.

Timer2 external clock input.

Timer3 external clock input.

Timer4 external clock input.

Timer5 external clock input.

U1RX

U1TX

U1ARX

U1ATX

U2RX

U2TX

—

UART1 Receive.

UART1 Transmit.

UART1 Alte r nate Re ceive.

UART1 Alte r nate Transm it.

UART2 Receive.

UART2 Transmit.

VDD P—Positive supply for logic and I/O pins.

VSS P—Ground reference for logic and I/O pins.

VREF+ I Analog Analog Voltage Reference (High) input.

VREF- I Analog Analog Voltage Reference (Low) input.

TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name Pin

Type Buffer

Type Description

Legend: CMOS = CMOS compatible input or output Analog = Analog input

ST = Schmitt Tr ig ger input with CMOS levels O = Output

I = Input P = Power

 2002 Microchip Technology Inc. Advance Information DS70082A-page 13

dsPIC30F

2.0 CORE ARCHITECTURE

OVERVIEW

2.1 Core Overview

The core has a 24-bit instruction word. The Program

Counter (PC) is 23-bits wide with the Least Significant

(LS) bit always clear (see Section 3.1), and the Most

Significant (MS) bit is ignored during normal program

execution, except for certain specialized instructions.

Thus, the PC can address up to 4M instruction words

of user pro gram space. An inst ruc tion pr e- fetc h mech -

anism is used to help maintain throughput. Uncondi-

tional overhead free program loop constructs are

supported using the DO and REPEAT instr uct i ons, bot h

of which are int errup tib le at any point.

The work ing re giste r array c onsist s o f 16 x 16 -bit re gis-

ters, each of which can act as data, address or offset

registers. One working register (W15) operates as a

software stack pointer for interrupts and calls.

The data space is 64 Kbytes (32K words), and is split

into two blocks, referred to as X and Y data memory.

Each block has its own independent Address Genera-

tion Unit (AGU). Most instructions operate solely

through the X memory AGU, which provides the

appearance of a single unified data space. The

Multiply-Accumulate (MAC) class of dual source DSP

instructions operate through both the X and Y AGUs,

splitting the data address space into two parts (see

Section 3.2). The X and Y data space boundary is

device specific and cannot be altered by the user . Each

data word consists of 2 bytes, and most instructions

can address data either as words or bytes.

There are two methods of accessing data stored in

program memory:

•The upper 32 Kbytes of data space memory can

optionally be mapped into the lower half (user

space) of program space at any 16K program

word boundary, defined by the 8-bit Program

Spac e Visibility Page (PSVP AG) register . This let s

any ins truction a ccess p rogram sp ace as if it were

data space, with the sole limitation that the access

requires an additional cycle. Moreover, only the

lower 16 bits of each instruction word can be

accessed using this method.

•Linear indirect access of 32K word pages within

progra m spac e is also possibl e using any w orking

Table read and write instructions can be used to

access all 24 bits of an instruction word.

Overhead-free circular buf fers (modulo addressing) are

supported in both X and Y address spaces. This is pri-

marily intended to remove the loop overhead for DSP

algorithms.

The X AGU also supports bit-reversed addressing on

destination ef fective addresses, to g reatly simplify input

or output data reordering for radix-2 FFT algorithms.

Refer to Section 4.0 for details on modulo and

bit-reversed addressing.

The core s up ports Inherent (no opera nd), Relative, Lit-

eral, Memory Direct, Register Direct, Register Indirect,

Instruct ions ar e associat ed with p redefined Addressin g

modes, depending upon their functional requirements.

For m os t i ns tru c ti o ns , the c or e i s c apa bl e of e xe c ut i ng

a data (or program data) memory read, a working reg-

ister (data) read, a data memory write and a program

(instruction) memory read per instruction cycle. As a

result, 3-operand instructions are supported, allowing

C = A+B operations to be executed in a single cycle.

A DSP engine has been included to significantly

enhance the core arithmetic capab ility and t hroughput.

It features a high speed 17-bit by 17-bit multiplier, a

40-bit ALU, two 40-bit saturating accumulators and a

40-bit bi-directional barrel shifter. Data in the accumu-

lator or any worki ng register can be shi fted up to 15 bit s

right or 16 bits left in a single cycle. The DSP instruc-

tions ope rate sea mles sly with all other in struct ions an d

have be en desi gned for o ptimal re al-time p erforma nce.

The MAC class of instructions can concurrently fetch

two data operands from memory, while multiplying two

W registers. To enable this concurrent fetching of data

operands, the data space is split for these instructions

and linear for all others. This is achieved in a transpar-

ent and flexible manner, through dedicating certain

working registers to each address space for the MAC

class of instructions.

The core does not support a multi-stage instruction

pipeline. However, a single stage instruction pre-fetch

mechanism is used, which accesses and partially

pre-decodes instructions a cycle ahead to maximize

availa ble executio n time. Mos t instructions execute in a

single cycle, with certain exceptions as outlined in

Section 2.3.

The core features a vectored exception processing

structure for traps and interrupts, with 62 independent

vectors. The exceptions consist of up to 8 traps (of

which 4 are res erv ed ) an d 54 interrupts . Eac h in terru pt

is prio ritized based o n a use r assigned priori ty betwee n

1 and 7 (1 being the lowest priority and 7 being the

highest) in conjunction with a predetermined ‘natural

order’. T raps hav e fixed prio rities, rangi ng from 8 to 15.

dsPIC30F

DS70082A-page 14 Advance Information  2002 Microchip Technology Inc.

2.2 Programmer’s Model

The programmer’s model is shown in Figure 2-1 and

consists of 16 x 16-bit working registers (W0 through

W15), 2 x 40-bit accumulators (AccA and AccB),

STATUS register (SR), Data Table Page register

(TBLPAG), Program Space Visibility Page register

(PSVPAG), DO and REPEAT registers (DOSTART,

DOEND, DCOUNT and RCOUNT), and Program

Counter (PC). The working registers can act as data,

address or offset registers. All registers are memory

mapped. W0 acts as the W register for file register

addressing.

Most o f these registers h ave a shadow regi ste r a ss oc i-

ated with each of them, as shown in Figure 2-1. The

shadow register is used as a temporary holding register

and can tr ansfer its con ten t s t o or fro m i t s hos t reg is ter

upon some the occurrence of an event. None of the

shadow registers are accessible directly. The following

rules apply for transfer of registers into and out of

shadows.

•PUSH.S and POP.S

W0...W14, TBLPAG, PSVPAG, SR (DC, N, OV, Z

and C bits only) transferred

•DO instruction

DOSTART, DOEND, DCOUNT shadows push ed

on loop start, popped on loop end

When a byte operation is performed on a working reg-

ister, only th e L eas t S ign ifi can t By te of t he target regi s-

ter is affected. However, a benefit of memory mapped

working registers is that both the Least and Most Sig-

nificant Bytes can be manipulated through byte wide

data m emory space accesses .

2.2.1 SOFTWARE STACK POINTER/

FRAME POINTER

The dsPICTM de vice s contain a softw are sta ck. W1 5 is

the dedicated software stack pointer (SP), and will be

automatically modified by exception processing and

subrouti ne call s and returns. H owever, W15 can b e ref-

erenced by any instruction in the same manner as all

other W registers. This simplifies the reading, writing

and manipulation of the stack pointer (e.g., creating

stac k fram es ).

W15 is initialized to 0x0800 during a RESET. The user

may reprogram the SP during initialization to any

location within data space.

W14 has been dedicated as a stack frame pointer as

defined by the LNK and ULNK instructions. However,

W14 can be referenced by any instruction in the same

manner as all other W registers.

2.2.2 STATUS REGISTER

The dsPIC core has a 16-bit status register (SR), the

LS Byte of which is referred to as the SR Low Byte

(SRL) and the MS Byte as the SR High Byte (SRH).

See Figure 2-1 for SR layout.

SRL contains all the MCU ALU operation status flags

(includ ing the Z bit ), as well as the CPU Inter rupt Prior-

ity Level status bits, IPL<2:0>, and the REPEAT active

status bit, RA. During exception processing, SRL is

concatenated with the MS Byte of the PC to form a

complete word value which is then stacked.

The upper byte of the STATUS register contains the

DSP Adder/Subtractor status bits, the DO Loop Active

bit (DA) and the Digit Carry (DC) status bit.

Most SR bits are read/write. Exceptions are:

1. The DA bit: DA is read and clear only, because

accidentally setting it could cause erroneous

operation.

2. The RA bit: RA is a read only bit, because acci-

dentally setting it could cause erroneous opera-

tion. RA is only set on entry into a repeat loop,

and cannot be directly cleared by software.

3. The OV, OA, OB and OAB bits: These bits are

read only and can only be set by the DSP engine

overflow logic.

4. The SA, SB and SAB bits: These are read and

clear only and can only be set by the DSP

engine saturation logic. Once set, these flags

remain s et until c leared by the user, irrespective

of the results from any subsequent DSP

operations.

2.2.2.1 Z Status Bit

Instructions that use a carry/borrow input (ADDC,

CPB, SUBB and SUBBR) will only be able to clear Z

(for a non-zero result) and can never set it. A multi-

precision sequence of instructions (starting with an

instruction with no carry/borrow input) will thus, auto-

matically logically AND the successive results of the

zero test. All results must be zero for the Z flag to

remain set by the end of the sequence.

All other instructions can set as well as clear the Z bit.

2.2.3 PROGRAM COU NTER

The Program Counter is 23-bits wide. Bit 0 is always

clear. Therefore, the PC can address up to 4M

instruction words.

Note: In o rder to pr otect against misalign ed stac k

accesses, W15<0> is always clear.

Note 1: Clearing the SAB bit will also clear both

the SA and SB bits.

2: When the memory mapped status regis-

ter (S R) i s th e de stina tio n add res s fo r an

operatio n which affects an y of the SR bits,

data writes are disabled to all bits.

 2002 Microchip Technology Inc. Advance Information DS70082A-page 15

dsPIC30F

FIGURE 2-1: PROGRAMME R’S MODEL

TABPAG

PC22 PC0

7 0

D0D15

Program Counter

Data Table Page Address

Status Register

Working Registers

DSP Operand

Registers

W10

W11

W12/DSP Offset

W13/DSP Write Back

W14/Frame Pointer

W15/Stack Pointer

DSP Address

Registers

AD39 AD0AD31

DSP

Accumulators AccA

AccB

PSVPAG

7 0 Program Space Visibility Page Address

OA OB SA SB

RCOUNT

15 0REPEAT Loop Counter

DCOUNT

15 0DO Loop Counter

DOSTART

22 0DO Loop Start Address

IPL2 IPL1

SPLIM Stack Pointer Limit Register

AD15

SRL

PUSH.S Shadow

DO Shadow

OAB SAB

15 0 Core Configuration Register

Legend

CORCON

DA DC RA N

TBLPAG

PSVPAG

IPL0 OV

W0/WREG

SRH

DO Loop End Address

DOEND

dsPIC30F

DS70082A-page 16 Advance Information  2002 Microchip Technology Inc.

2.3 Instruction Flow

There are 8 types of instruction flows:

1. Norma l one-word, one -cycle in struction s. These

instructions take one effective cycle to execute,

as sh own i n Figure 2-2.

FIGURE 2-2: INSTRUCTION PIPELINE FLOW: 1-WORD, 1-CYCLE

2. One-word, two-cycle (or three-cycle) instruc-

tions. These instructions include the relative

branches, relative call, skips and returns. When

an instruction changes the PC (other than to

increment it), the pipelined fetch is discarded.

This causes the instruction to take two effective

cycles to execute as shown in Figure 2-3. Some

program flow change instructions, such as skip

instructions that skip over 2-word instructions,

and the RETURN, RETFIE and RETLW instruc-

tions that are used to return from a subroutine call

or Interrupt Service Routine, require 3 cycles.

FIGURE 2-3: INSTRUCTION PIPELINE FLOW: 1-WORD, 2-CYCLE

3. One-word, two-cycle instructions that are not

flow co ntrol instru ctions. The only instructi ons of this type are the MOV.D (load and store double

word) instructions, as shown in Figure 2-4.

FIGURE 2-4: INSTRUCTION PIPELINE FLOW: 1-WORD, 2-CYCLE MOV.D OPERATIONS

TCY0TCY1TCY2TCY3TCY4TCY5

1. MOV.b #0x55,W0 Fetch 1 Execute 1

2. MOV.b #0x35,W1 Fetch 2 Execute 2

3. ADD.b W0,W1,W2 Fetch 3 Execute 3

TCY0TCY1TCY2TCY3TCY4TCY5

1. MOV #0x55,W0 Fetch 1 Execute 1

2. BTSC W1,#3 Fetch 2 Execute 2

Skip Taken

3. ADD W0,W1,W2 Fetch 3 Flush

4. BRA SUB_1 Fetch 4 Execute 4

5. SUB W0,W1,W3 Fetch 5 Flush

6. Instruction @ address SUB_1 Fetch SUB_1

TCY0TCY1TCY2TCY3TCY4TCY5

1. MOV W0,0x1234 Fetch 1 Execute 1

2. MOV.D [W0++],W1 Fetch 2 Execute 2

R/W Cycle 1

3. MOV W1,0x00AA Fetch 3 Execute 2

R/W Cycle2

3a. Stall Stall Execute 3

4. MOV 0x0CC, W0 Fetch 4 E xecute 4

 2002 Microchip Technology Inc. Advance Information DS70082A-page 17

dsPIC30F

4. Table read/write in str uct ion s. Th es e in stru ctions

will suspe nd the fetching to insert a read or write

cycle to the program memory. The instruction

fetched while executing the table operation is

saved for 1 cycle and executed in the cycle

immediately after the table operation, as shown

in Figure 2-5.

FIGURE 2-5: INSTRUCTION PIPELINE FLOW: 1-WORD, 2-CYCLE TABLE OPERATIONS

5. Two-word instructions for CALL and GOTO. In

these instructions, the fetch after the instruction

provides the remainder of the jump or call desti-

nation address. These instructions require 2

cycles to execute , 1 for fetch ing the 2 i nstruction

words (enabled by a high speed path on the sec-

ond fetch), and 1 for the subsequent pipeline

flush, as shown in Figure 2 -6.

FIGURE 2-6: INSTRUCTION PIPELINE FLOW: 2-WORD, 2-CYCLE GOTO, CALL

6. Two-word instructions for DO. In these instruc-

tions, the fetch after the instruction contains an

address offset. This address offset is added to

the first instruction address to generate the last

loop instruction address. Therefore, these

instructions require two cycles, as shown in

Figure 2-7.

FIGURE 2-7: INSTRUCTION PIPELINE FLOW: 2-WORD, 2-CYCLE DO, DOW

TCY0TCY1TCY2TCY3TCY4TCY5

1. MOV #0x1234,W0 Fetch 1 Execute 1

2. TBLRDL [W0++],W1 Fetch 2 Execute 2

3. MOV #0x00AA,W1 Fetch 3 Execute 2

Read Cycle

3a. Table Operation Bus Read Execute 3

4. MOV #0x0CC,W0 Fetch 4 E xecute 4

TCY0TCY1TCY2TCY3TCY4TCY5

1. MOV #0x1234,W0 Fetch 1 Execute 1

2. GOTO LABEL Fetch 2L Update PC

2a. Second Word Fetch 2H NOP

3. Instruction @ address LABEL Fetch

LABEL Execute

LABEL

4. BSET W1, #BIT3 Fetch 4 E xecute 4

TCY0TCY1TCY2TCY3TCY4

1. PUSH DOEND Fetch 1 Execute 1

2. DO LABEL,#COUNT Fetch 2L NOP

2a. Second Word Fetch 2H Execute 2

3. 1st Instruction of Loop Fetch 3 Execute 3

dsPIC30F

DS70082A-page 18 Advance Information  2002 Microchip Technology Inc.

7. Instr uction s that are subjected to a st all due to a

data dependency between the X RAGU and X

W AGU. An a dditional cy cle is in serted to resolve

the resource conflict, as shown in Figure 2-7.

Instruction stalls caused by data dependencies

are further discussed in Section 4.0.

FIGURE 2-8: INSTRUCTION PIPELINE FLOW: 1-WORD, 2-CYCLE WITH INSTRUCTION ST ALL

8. Interrupt recognition execution. Refer to

Section 5.0 for details on interrupts.

2.4 Divide Support

The ds PIC device s feature a 16 /16-bit s igned fra ctional

divide operation, as well as 32/16-bit and 16/16-bit

signed and unsigned integer divide operations, in the

form of single instruction iterati ve divides. The followin g

instructions and data sizes are supported:

1. DIVF – 16/16 signed fractional divide

2. DIV.sd – 32/16 signed divide

3. DIV.ud – 32/16 unsigned divide

4. DIV.sw – 16/16 signed divide

5. DIV.uw – 16/16 unsigned divide

The 16/16 divides are simila r to the 32/16 (same number

of iterations), but the dividend is eithe r zero-extended or

sign-extended during the first iteration.

The quotient for all divide instructions ends up in W0,

and the remainder in W1. DIV and DIVF can specify any

W register for both the 16-bit dividend and divisor. All

other divides can specify any W register for the 16-bit

divisor, but the 32-bit dividend must be in an aligned W

The non-restoring divide algorithm requires one cycle

for an in itial div idend sh ift (for integer divides only), one

cycle per divisor bit, and a remainder/quotient correc-

tion cycle. The correction cycle is the last cycle of the

iteration loop, but must be performed (even if the

remainder is not required) because it may also adjust

the quotient. A consequence of this is that DIVF will

also pro duce a val id rem ain der (though it is of little use

in fractional arithmetic).

The divide instructions must be executed within a

REPEAT loop. Any other form of execution (e.g. a

series of discrete divide instructions) will not function

correctly because the instruction flow depends on

RCOUNT. The divide ins truction does not automatically

set up the RCOUNT value, and it must, therefore, be

explic itly and correctl y specifi ed in the REPEAT instruc-

tion, as shown in Table 2-1 (REPEAT will execute the

target instruction {operand value+1} times). The

REPEAT loop count must be set up for 18 iterations of

the DIV/DIVF instruction. Thus, a complete divide

operation requires 19 cycles.

TABLE 2-1: DIVIDE INSTRUCTIONS

TCY0TCY1TCY2TCY3TCY4TCY5

1. MOV.b W0,[W1] Fetch 1 Execute 1

2. MOV.b [W1],PORTB Fetch 2 NOP

2a. Stall (NOP) Stall Execute 2

3. MOV.b W0,PORTB Fetch 3 Execute 3

Note: The Divide flow is interruptible. However,

the user needs to save the context as

appropriate.

Instruction Function

DIVF Signed fractional divide: Wm/Wn → W0; Rem → W1

DIV.sd Signed divide: (Wm+1:Wm)/Wn → W0; Rem → W1

DIV.sw Signed divide: Wm/Wn → W0; Rem → W1

DIV.ud Unsigned divide: (Wm+1:Wm)/Wn → W0; Rem → W1

DIV.uw Unsigned divide: Wm/Wn → W0; Rem → W1

 2002 Microchip Technology Inc. Advance Information DS70082A-page 19

dsPIC30F

2.5 DSP Engine

Concurrent operation of the DSP engine with MCU

instruction flow is not possible, though both the MCU

ALU and DSP engine resources may be used concur-

rently by the same instruction (e.g., ED and EDAC

instructions).

The DSP engine consists of a high speed 17-bit x

17-bit multiplier, a barrel shifter and a 40-bit adder/

subtractor with two target accumulators, round and

saturati on log ic .

Dat a input t o the DSP engine i s derived f rom one o f the

following:

1. Directly from the W array (registers W4, W5, W6

or W7 ) via the X and Y da ta buses f or the MAC

class of instructions (MAC, MSC, MPY,

MPY.N, ED, EDAC, CLR and MOVSAC).

2. From the X bus for al l other DSP instructions.

3. From the X bus for all MCU instructions which

use the barrel shifter.

Data output from the DSP engine is written to o ne of the

following:

1. The target accumulator, as defined by the DSP

instruction being executed.

2. The X bus for MAC, MSC, CLR and MOVSAC

accumulator writes, where the EA is derived

from W13 on ly. (MPY, MPY.N, ED and EDAC

do not offer an accumulator write option.)

3. The X bus for all MCU instructions which use the

barrel shifter.

The DSP engine also has the capability to perform inher-

ent accumulator-to-accumulator operations, which

require no additional data. These instructions are ADD,

SUB and NEG.

The DSP engine has various options selected through

various bits in the CPU Core Configuration Register

(CORCON), as listed below:

1. Fractional or integer multiply (IF).

2. Conventional or convergent rounding (RND).

3. Automatic saturation on/off for AccA (SATA).

4. Automatic saturation on/off for AccB (SATB).

5. Automatic saturation on/off for writes to data

memory (SATDW).

6. Accumulator Saturation mode selection

(ACCSAT).

A block diagram of the DSP engine is shown in

Figure 2-9.

Note: For CORCON layout, see Table 4-3.

dsPIC30F

DS70082A-page 20 Advance Information  2002 Microchip Technology Inc.

FIGURE 2-9: DSP ENGINE BLOCK DIAGRAM

Zero Backfill

Sign-Extend

Barrel

Shifter

40-bit Accumula tor A

40-bit Accumula tor B Round

Logic

X Data Bus

To/From W Array

Adder

Saturate

Negate

16 16

40 40

Y Data Bus

Carry/Borrow Out

Carry/Borrow In

Multiplier/Scaler

17-bit

 2002 Microchip Technology Inc. Advance Information DS70082A-page 21

dsPIC30F

2.5.1 MULTIPLIER

The 17x17-bit multiplier is capable of signed or unsigned

operation and can multiplex its output using a scaler to

support either 1.31 fractional (Q31), or 32-bit integer

results. Unsigned operands are zero-extended into the

17th bit of the multiplier input value. Signed operands

are sign-extended into the 17th bit of the multiplier input

value. The output of the 17x17-bit multiplier/scaler is a

33-bit value, which is sign-extended to 40 bits. The

respective number representation formats are shown in

Figure 2-10. Integer data is inherently represented as a

signed two’s complement value, where the MSB is

defined as a sign bit. Generally speaking, the range of

an N-bit two’s complement integer is -2N-1 to 2N-1 – 1.

For a 16-bit integer, the data range is -32768 (0x8000)

to 32767 (0x7FFF), including 0 (see Figure 2-10). For a

32-bit integer, the data range is -2,147,483,648

(0x8000 0000) to 2,147,483,645 (0x7FFF FFFF).

When the multip lier is configured for Frac tional m ultipli-

cation, the data is represented as a two’s complement

fraction , where the MS B is define d as a sig n bit and th e

radix po int is im plied to l ie just after the sign b it (QX for-

mat) . Th e rang e of an N -bit two’s complement fraction

with this implied radix point is -1.0 to (1-21-N). For a

16-bit fraction, the Q15 data range is -1.0 (0x8000) to

0.999969482 (0x7 FFF), including 0 and has a precision

of 3.01518x10-5. In Fractional mode, a 16x16 multiply

operation generates a 1.31 product, which has a

preci si on of 4.65 661 x1 0-10.

FIGURE 2-10: 16-BIT INTEGER AND FRACTIONAL MODES

Certain multiply operations always operate on signed

data. These include the MAC/MSC, MPY[.N] and

ED[AC] instructions. The 40-bit adder/subtractor may

also optionally negate one of its operand inputs to

change the result sign (without changing the oper-

ands). This is used to create a multiply and subtract

(MSC) or multiply and negate (MPY.N) operation.

In the special case when both input operands are 1.15

fractions and equal to 0x8000 (-110), the result of the

multipl icati on is corrected to 0x7FFF FFFF (as th e clo s-

est approx imation to +1) by hardware, be fore it is used.

It sh ou l d be n ot e d th at w i th t h e ex ce pt ion o f DS P mul-

tiplies, the dsPIC30F ALU operates identically on inte-

ger and fractional data. Namely, an addition of two

integers will yield the same result (binary number) as

the ad dit ion of tw o fra cti onal num ber s. The onl y diffe r-

ence is how the result is interpreted by the user. How-

ever, multiplies performed by DSP operations are

different. In these instructions, data format selection is

made by the IF bit (CORCON<0>), and it must be set

accordingly (‘0’ for Fractional mode, ‘1’ for Integer

mode). This is required because of the implied radix

point used by dsPIC30F fractions. In Integer mode,

multiplying two 1 6-bit integers produ ces a 32-bit integer

result. H o wev er, multiplying tw o 1.1 5 v al ues ge ne rates

a 2.30 res ult. Sinc e th e ds PIC 30 F us es 1.3 1 format for

the accumulators, a DSP multiply in Fractional mode

also includes a left shift by one bit to keep the radix

point properly aligned. This feature reduces the resolu-

tion of the DSP multiplier to 2-30, but has no other ef fect

on the computation.

The same multiplier is used to support the MCU multi-

ply instructions, which include integer 16-bit signed,

unsigned and mixed sign multiplies. Additional data

paths are provided to allow these instructions to write

the result bac k into the W array and X dat a bus (via the

W array). These paths are placed prior to the data

scaler. The IF bit in the CORCON register, therefore,

only affects the result of the MAC and MPY instructions.

All other mul tiply op eration s are ass umed to be integ er

operations. If the user executes a MAC or MPY inst ruc-

tion on fractional data, without clearing the IF bit, the

result m ust be ex plicitly s hifted le ft by the use r program

after mul tiplicati on, in orde r to obt ain the co rrect resul t.

The MUL instruction may be directed to use byte or

word si zed op erands. By te opera nds wil l direc t a 16-b it

result, and word operands will direct a 32-bit result to

the specified register(s) in the W array.

Different Representations of 0x4001

Integer:

214 213 212 211 . . . . 20

0x4001 = 214 + 20 = 16385

1.15 Fractional:

2-15

0x4001 = 2-1 + 2-15 = 0.500030518

0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1

2-1 2-2 2-3 . . .

-20

0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1

dsPIC30F

DS70082A-page 22 Advance Information  2002 Microchip Technology Inc.

2.5.2 DATA ACCUMULATORS AND

ADDER/SUBTRACTOR

The data accumulator consists of a 40-bit adder/

subractor with automatic sign extension logic. It can

select one of two accumulators (A or B) as its pre-

accumulation source and post-accumulation destina-

tion. For the ADD and LAC instructions, the data to be

accum ulated or l oaded ca n be optio nally sca led via th e

barrel shifter, prior to accumulation.

2.5.2.1 Adder/Subtractor, Overflow and

Saturation

The adder/subtractor is a 40-bit adder with an optional

zero inpu t into on e side and eith er true, or c omple ment

data into the other input. In the case of addition, the

carry/borrow input is active high and the other input is

true data (not complemented), whereas in the case of

subtrac tion, the carry/borrow inp ut is active low and the

other input is complemented. The adder/subtractor

generates overflow status bits SA/SB and OA/OB,

which are latched and reflected in the status register:

•Overflow from bit 39: th is is a catastrophic

overflow in which the sign of the accumulator is

destroyed.

•Overflow into guard bits 32 through 39: this is a

recoverable overflow. This bit is set whenever al l

the guard bits bits are not identical to each other.

The adder has an additional saturation block which

controls accumulator data saturation, if selected. It

uses the result of the adder, the overflow status bits

described above, and the SATA/B (CORCON<7:6>)

and ACCSAT (CORCON<4>) mode control bits to

determine when to saturate and to what value to

saturate.

Six status register bits have been provided to support

saturation and overflow; they are:

1. OA:

AccA overflo w ed int o guard bit s

2. OB:

AccB overflo w ed int o guard bit s

3. SA:

AccA saturat ed (bit 31 overflow and satu rati on)

AccA overflowed into guard bits and saturated

(bit 39 overflow and saturation)

4. SB:

AccB saturat ed (bit 31 overflow and satu rati on)

AccB overflowed into guard bits and saturated

(bit 39 overflow and saturation)

5. OAB:

Logical OR of OA and OB

6. SAB:

Logical OR of SA and SB

The OA and OB bits are modified each time data

passes through the adder/subtractor. When set, they

indicate that the most recent operation has overflowed

into the accumulator guard bits (bits 32 through 39).

The OA and OB bits can also optionally generate an

arithmetic warning trap when set and the correspond-

ing ove rflow trap flag enable bit (O V A T EN, OVBTEN) in

the INTCON1 re gis ter (refe r to Sec ti on 5.0) is set. Thi s

allows the user to take immediate action, for example,

to correct system gain.

The SA and SB bit s are m odified each tim e data pass es

through the adder/subtractor, but can only be cleared by

the user. When set, they indicate that the accumulator

has overflowed it s max imum range (bit 31 for 32-bi t sat-

uration, or bit 39 for 40-bit saturation) and will be satu-

rated (if saturation is enabled). When saturation is not

enabled, the SA and SB default to bit 39 overflow and

thus, indicate that a catastrop hic overflow has occurred.

If the COVTE bit in the INTCON1 register is set, SA and

SB bits will generate an arithmetic warning trap when

saturation is dis abled.

The overflow and saturation status bits can optionally

be view ed in the S tat us Register (SR) as the logic al OR

of OA and OB (in bit OAB) and the logical OR of SA and

SB (in bit SAB). This all ows programmers to chec k one

bit in the St atus Regist er to determin e if either accum u-

lator has overflowed, or one bit to determine if either

accumulator has saturated. This would be useful for

complex number arithmetic which typically uses both

the accumulators.

The device supports three Saturation and Overflow

modes.

1. Bit 39 Overflow and Saturation:

When bit 39 overflow and saturation occurs, the

saturate logic loads the maximally positive 9.31

(0x7FFFFFFFFF) or maximally negative 9.31

value (0x8000000000) into the target accumula-

tor. The SA or SB bit is set and remains set until

cleared by the user. This is referred to as ‘super

saturation’ and provides protection against erro-

neous data, or unexpected algorithm problems

(e.g., gain calculations).

2. Bit 31 Overflow and Saturation:

When bit 31 overflow and saturation occurs, the

saturate logic then loads the maximally positive

1.31 value (0x007FFFFFFF) or maximally nega-

tive 1.31 value (0x0080000000) into the target

accumulator. The SA or SB bit is set and remains

set until cleared by the user. When this Saturation

mode is in effect, the guard bits are not used (so

the OA, OB or OAB bit s are never se t).

3. Bit 39 Catastrophic Overflow

The bit 39 overflow status bit from the adder is

used to set the SA or SB bit, which remain set

until cleared by the user . No saturation operation

is performed and the accumulator is allowed to

overflow (d estroying its sign). If the COVTE bit in

the INTCON1 register is set, a catastrophic

overflow can initiate a trap exception.

 2002 Microchip Technology Inc. Advance Information DS70082A-page 23

dsPIC30F

2.5.2.2 Accumulator ‘Write Back’

The MAC class of instructions (with the exception of

MPY, MPY.N, ED and EDAC) can optionally write a

roun ded ver sion of t he hig h word ( bits 31 t hrough 16)

of the accumulator, that is not targeted by the instruc-

tion into data space memory. The write is performed

across the X bus into combined X and Y address

spa ce. The following Addressing modes are supported.

1. W13, Regi ste r Direct:

The rounded contents of the non-target accumula-

tor are written into W13 as a 1.15 fraction.

2. [W13]+=2, Register Indirect with Post-Increment:

The round ed contents of the non-target a ccumu-

lator are written into the address pointed to by

W13 as a 1.15 fraction. W13 is then

incremented by 2 (for a word write).

2.5.2.3 Round Logic

The round logic is a combinational block, which per-

forms a conventional (biased) or convergent (unbiased)

round function during an accumulator write (store). The

Round mode is det ermined by the state of the R ND bit

in the CORCON register. It generates a 16-bit, 1.15 data

value which is passed to the data space write saturation

logic. If rounding is not indicated by the instruction, a

truncated 1.1 5 da ta value i s sto red and the LS Word is

simply discarded.

The two Rounding modes are shown in Figure 7-7.

Conve nti ona l ro unding t ak es bit 15 o f the ac cumulator,

zero-ex tend s it and ad ds it to th e AC CxH w ord (b it s 16

through 31 of the accumulator). If the AC CxL word (bits

0 through 15 of the accumulator) is between 0x8000

and 0xFFFF (0x8000 included), ACCxH is incre-

mented. If ACCxL is between 0x0000 and 0x7FFF,

ACCxH is left unchanged. A consequence of this algo-

rithm is that over a succession of random rounding

operations, the value will tend to be biased slightly

positive.

Convergent (or unbiased) rounding operates in the

same manner as conventional rounding, except when

ACCxL equ als 0x8000. If thi s is the case, the LS bit (bit

16 of the ac cumu lator) of ACCxH is examine d. If it is 1,

ACCxH is incremented. If it is 0, ACCxH is not modi-

fied. Assuming that bit 16 is effectively random in

natur e, th is sc hem e wi ll re move any rou nding bias th at

may accumulate .

The SAC and SAC.R instructions store either a trun-

cated (SAC) or rounded (SAC.R) version of the content s

of the t arget accumul ator to data mem ory , via the X bu s

(subject to data saturation, see Section 2.5.2.4). Note

that for the MAC class of instructions, the accumulator

write back operation will function in the same manner,

addressing combined MCU (X and Y) data space

though the X bus. For this class of instructions, the data

is always subje ct to round ing .

2.5.2.4 Data Space Wri te Saturation

In addition to adder/subtractor saturation, writes to data

space may al so be satu rate d, bu t wit hou t affect ing t he

contents of the source accumulator. The data space

write saturation logic block accepts a 16-bit, 1.15 frac-

tional value from the round logic block as its input,

together with overflow status from the original source

(accumulator) and the 16-bit round adder. These are

combin ed and used t o sele ct the a ppropri ate 1.15 frac-

tional value as output to write to data space memory.

If the SATDW bit in the CORCON register is set, data

(after roundi ng or trun ca tio n) is tes ted for overflo w and

adjusted accordingly, For input data greater than

0x007FF F, data writte n to memory i s forced to the m ax-

imum positive 1.15 value, 0x7FFF. For input data less

than 0xF F80 00, dat a w ritten to me mor y is forc ed to th e

maximum negative 1.15 value, 0x8000. The MS bit of

the source (bit 39) is used to determine the sign of the

operand bei ng t es ted.

If the SATDW bit in the CORCON regis ter is not set , the

input data is always passed through unmodified under

all conditions.

2.5.3 BARREL SHIFTER

The barrel shifter is capable of performing up to 15-bit

arithmetic or logic right shifts, or up to 16-bit left shifts

in a single cycle. The source can be either of the two

DSP accumulators, or the X bus (to support multi-bit

shifts of register or memory data).

The sh ifter requires a s ign ed bi nary v al ue to de term in e

both the m agnitude (number of bits) and direct ion of the

shift operation. A positive value will shift the operand

right. A negative value will shift the operand left. A

value of 0 will not modify the operand.

The barrel shifter is 40 bits wide, thereby obtaining a

40-bit res ult for DSP shift ope rations an d a 16-bit resu lt

for MCU shift operations. Data from the X bus is pre-

sented to the barrel shifter between bit positions 16 to

31 for right shift s, and bit positi ons 0 to 15 for l eft shifts .

dsPIC30F

DS70082A-page 24 Advance Information  2002 Microchip Technology Inc.

NOTES:

 2002 Microchip Technology Inc. Advance Information DS70082A-page 25

dsPIC30F

3.0 MEMORY ORGANIZATION

3.1 Program Address Space

The program address space is 4M instruction words. It

is addressable by a 24-bit value from either the PC,

table instruction EA, or data space EA, when program

space is mapped into data space, as defined by

Table 3-1. Note that the program space address is

incremented by two between successive program

words, in orde r to pro vide c omp atibi lity w ith d ata sp ace

addressing.

User program space access is restricted to the lower

4M instruction word address range (0x000000 to

0x7FFFFE), for all access es other than TBLRD/TBLWT,

which use TBLPAG<7> to determin e user or conf igura-

tion space access. In Table 3-1, Read/Write instruc-

tions, b it 23 allo ws access to the Dev ice ID, the Use r ID

and the configuration bits. Otherwise, bit 23 is always

clear.

TABLE 3-1: PROGRAM SPACE ADDRESS CONSTRUCTION

FIGURE 3-1: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION

Note: The address map shown in Figure 3-5 is

concep tual, and the actu al memory co nfig-

uratio n ma y v ary acro ss ind ivi dual devices

depending on available memory.

Access Type Access

Space Program Spac e Addre ss

<23> <22:16> <15> <14:1> <0>

Instruction Access User 0PC<22:1> 0

TBLRD/TBLWT User

(TBLPAG<7> = 0) TBLPAG<7:0> Data EA <15:0>

TBLRD/TBLWT Configuration

(TBLPAG<7> = 1) TBLPAG<7:0> Data EA <15:0>

Program Space Visibility User 0PSVPAG<7:0> Data EA <14:0>

0Program Counter

24-bits

PSVPAG Reg

8-bits

15-bits

Program

Using

Select

TBLPAG Reg

8-bits

16-bits

Using

Byte

24-bit EA

1/0

Select

User/

Configuration

Table

Instruction

Program

Space

Counter

Using

Space

Select

Note: Program Space Visibility cannot be used to access bits <23:16> of a word in program mem ory.

Visibility

dsPIC30F

DS70082A-page 26 Advance Information  2002 Mic rochip Technology Inc.

3.1.1 PROGRAM SPACE ALIGNMENT

AND DATA ACCESS USING TABLE

INSTRUCTIONS

This arc hit ec ture f etc hes 24 -bi t w ide pro gram memo ry.

Consequently, instructions are always aligned. How-

ever, as the architecture is modified Harvard, data can

also be presen t in program space.

There are two methods by which program space can

be accessed: via special table instructions, or through

the rema ppi ng of a 16K word prog ram space page in to

the upper half of data space (see Section 3.1.2). The

TBLRDL and TBLWTL instruc tions of fer a direc t method

of readin g or wri ting the LS W ord o f any ad dress w ithin

progra m spa ce, witho ut g oing thro ugh dat a sp ac e. The

TBLRDH and TBLWTH instructions are the only method

whereb y th e u ppe r 8 bi ts of a program space word can

be accessed as data.

The PC is incremented by two for each successive

24-bit program word. This allows program memory

addresses to directly map to data space addresses.

Program memory can thus be regarded as two 16-bit

word wide address sp ac es , res id ing si de by si de, eac h

with the same address range. TBLRDL and TBLWTL

access the space which contains the LS Data Word,

and TBLRDH and TBLWTH access the space which con-

tains the MS Data Byte.

Figure 3-1 shows h ow th e EA is cre ate d fo r t a ble oper-

ations and data space accesses (PSV = 1). Here,

P<23:0> refers to a program space word, whereas

D<15:0> refers to a data space word.

A set of Table Instruct ions are provided to mo ve byte or

word siz ed data to and from program space.

1. TBLRDL: Table Re ad Low

Word: Read the LS Word of the program

address;

P<15:0> maps to D<15:0>.

Byte: Read one of the LS Bytes of the program

address;

P<7:0> maps to the destination byte when byte

select = 0;

P<15:8> m aps to the d estination byte when byte

select = 1.

2. TBLWTL: Table Write Low (refer to Section 6.0

for details on FLASH Programming).

3. TBLRDH: Table Re ad High

Word: Read the MS Word of the program

address;

P<23:16> maps to D<7:0>; D<15:8> always

be = 0.

Byte: Read one of the MS By tes of the pro gram

address;

P<23:16> maps to the destination byte when

byte select = 0;

The destination byte will always be = 0 when

byte select = 1.

4. TBLWTH: Tabl e Writ e Hi gh (r efe r to S ecti on 6.0

for details on FLASH Programming).

FIGURE 3-2: PROGRAM DATA TABLE ACCESS (LS WORD)

PC Address

0x000000

0x000002

0x000004

0x000006

00000000

Program Memory

‘Phantom’ Byte

(Read as ‘0’).

TBLRDL.W

TBLRDL.B (Wn<0> = 1)

TBLRDL.B (Wn<0> = 0)

 2002 Microchip Technology Inc. Advance Information DS70082A-page 27

dsPIC30F

FIGURE 3-3: PROGRAM DATA TABLE ACCESS (MS BYTE)

3.1. 2 PROGR AM SPACE VISIBILI TY

FROM DATA SPACE

The upper 32 Kbytes of data space may optionally be

mapped into any 16K word program space page. This

provides transparent access of stored constant data

from X data space, without the need to use special

instructions (i.e., TBLRDL/H, TBLWTL/H instructions).

Program space access through the data space occurs

if th e MS bit of the data space EA i s set and program

space visibility is enabled, by setting the PSV bit in the

Core Control register (CORCON). The functions of

CORCON are discussed in Section 6.0, DSP Engine.

Data accesses to this area add an additional cycle to

the instruction being executed, since two program

memory fetch es are requ ire d.

Note that the upper half of addressable data space is

always part of the X data space. Therefore, when a

DSP ope ration uses p rogram sp ace mapp ing to acces s

this m em ory regi on , Y d ata space s ho uld ty pic al ly co n-

tain state (variable) data for DSP operations, whereas

X data space should typically contain coefficient

(constant) da ta.

Although each dat a sp ace address, 0x8000 and higher ,

maps directly into a corresponding program memory

address (see Figure 3-4), only the lower 16-bits of the

24-bit program word are used to contain the data. The

upper 8 bits shoul d be progra mmed to forc e an illeg al

instruction to maintain machine robustness. Refer to

the Programmer’s Reference Manual (DS70030) for

details on instruction encoding.

Note that by incrementing the PC by 2 for each pro-

gram memory word, the LS 15 bits (16 bits for the

TBLRDL/H, TBLWTL/H instructions) of data space

addresses directly map to the LS 15 bits in the corre-

sponding program space addresses. The remaining

bits are provided by the Program Space Visibility Page

3.1.2.1 Data Pre-Fetch from Program Space

Within a REPEAT Loop

Consider the special case of any instruction executed

within the REPEAT loop. When pre-fetching data resi-

dent in prog ram spac e, via the dat a space w indow from

within a REPEAT loop, all iterations of the repeated

instruction will reload the instruction from the Instruc-

tion Latch without re-fetching it, thereby releasing the

program bus for a data pre-fetch. In this example, the

initial 2 data words for the first iteration of the instruction

to be repeated (MAC) are fetched by a prior instruction

(e.g., CLR instruction). The subsequent MAC instruc-

tions, th ere fore , only need to fet ch tw o more data pairs

to comp lete the loop. Th e initial fetch of the MAC instruc-

tion is performed by the REPEAT instruction. As a

result, only the last iteration of the REPEAT loop

requires 2 cycles to execute. Each of the other itera-

tions executes in 1 cycle.

PC Address

0x000000

0x000002

0x000004

0x000006

00000000

Program Memory

‘Phantom’ Byte

(Read as ‘0’)

TBLRDH.W

TBLRDH.B (Wn<0> = 1)

TBLRDH.B (Wn<0> = 0)

Note: PSV access is temporarily disabled during

Table Reads/Writes.

dsPIC30F

DS70082A-page 28 Advance Information  2002 Mic rochip Technology Inc.

EXAMPLE 3-1: PROGRAM SPACE DATA READ THROUGH DATA SPACE WITHIN A

REPEAT LOOP

FIGURE 3-4: DATA SPACE WINDOW INTO PROGRAM SPACE OPERATION

; In this example, data for MAC operations is stored in Program Space.

CLR A, [W8]+=2, W4, [W10]+=2, W5 ; Acc. A cleared, data prefetched (2 cycles)

REPEAT #99 ; Repeat the MAC operation 100 times (1 cycle)

MAC W4*W5, A, [W8]+=2, W4, [W10]+=2, W5

; MAC operation within REPEAT loop (2 cycles for 1st and 100th iterations, 1 cycle for 2nd - 99th

iterations)

23 15 0

PSVPAG(1)

EA<15> = 0

EA<15> = 1

Data

Space

Data Space

Program Space

15 23

0x0000

0x8000

0xFFFF

0x21

0x108000

0x10FFFF

Data Read

Upper Half of Data

Space is Mapped

into Program Space

Note: PSVPAG is an 8-bit register, containing bits <22:15> of the program space address

(i.e., it defines the page in program space to which the upper half of data space is being mapped).

0x108200

Address

Concatenation

BSET CORCON,#2 ; PSV bit set

MOV #0x21, W0 ; Set PSVPAG register

MOV W0, PSVPAG

MOV 0x8200, W0 ; Access program memory location

; using a data space access

 2002 Microchip Technology Inc. Advance Information DS70082A-page 29

dsPIC30F

FIGURE 3-5: SAMPLE PROGRAM

SPACE MEMORY MAP 3.2 Data Address Space

The core ha s two data spa ces. The dat a spaces can be

considered either separate (for some DSP instruc-

tions), or as o ne u nifi ed lin ear a ddre ss rang e (fo r MC U

instructions). The data spaces are accessed using two

Address Generation Units (AGUs) and separate data

paths.

3.2.1 DATA SPACE S

The X data space is used by all instructions and sup-

ports all Addressing modes. There are separate read

and write data buse s. The X read data bus is the return

data path for all instructions that view data space as

combined X and Y address space. It is also the X

address space data path for the dual operand read

instructions (MAC class). The X write data bus is the

only write path to data space for all instructions.

The X data space also supports Modulo Addressing for

all instructions, subject to Addressing mode restric-

tions. Bit-Reversed Addressing is only supported for

writes to X data space.

The Y data space is used in concert with the X data

space by the MAC class of instructions (CLR, ED,

EDAC, MAC, MOVSAC, MPY, MPY.N and MSC) to

provide two concurrent data read paths. No writes

occur ac ros s th e Y bu s. T his cl as s of ins truc tio ns ded i-

cates two W regi ster pointers, W10 and W11, to always

address Y data space, independent of X data space,

whereas W8 and W9 always address X data space.

Note that during accumulator write back, the data

address sp a ce is c onsidered a co mbination of X and Y

data spaces, so the write oc curs across the X bus. Con-

sequently, it can be to any address in the entire data

space.

The Y data space can only be used for the data pre-

fetch operation associated with the MAC class of

instructions. It also supports Modulo Addressing for

automat ed c irc ula r buffers. Of course, a ll o the r ins truc -

tions can access the Y dat a address sp ace through the

X data path, as part of the composite li near space.

The boundary between the X and Y data spaces is

defined as shown in Figure 3-8 and is not user pro-

grammab le. Sh ould a n EA po int to dat a out side its own

assign ed a ddre ss sp a ce , or to a l ocation outside p hys -

ical memory, an all-zero word/ byte will be returne d. For

example, although Y address space is visible by all

non-MAC instructions using any Addressing mode, an

attempt by a MAC instruction to fetch data from that

space, using W8 or W9 (X space pointers), will return

0x0000.

RESET - Target Address

User Memory

Space

000000

00007E

000002

000080

Device Configuration

User FLASH

Program Memory

018000

017FFE

Configuration Memory

Space

Data FLASH

(48K instructions)

(4 Kbytes)

800000

F80000

Registers F8000E

F80010

DEVID (2) FEFFFE

FF0000

FFFFFE

Reserved F7FFFE

Reserved

7FF000

7FEFFE

(Read 0’s)

8005FE

800600

UNITID (32 instr.)

Vector Tables

8005BE

8005C0

RESET - GOTO Instruction

000004

Reserved

7FFFFE

Reserved

000100

0000FE

000084

Alternate Vector Table

Reserved

Interrupt Vector Table

Note: These address boundaries may vary from one device

to another.

dsPIC30F

DS70082A-page 30 Advance Information  2002 Mic rochip Technology Inc.

All effective addresses are 16-bits wide and point to

bytes within the data space. Therefore, the data space

address range is 64 Kbytes or 32K words.

3.2.2 DATA SPACE WIDTH

The core data wid th is 16-b it s . All in tern al reg is ters are

organ ized as 16-bit wide words. Dat a sp ac e mem ory is

organized in byte addressable, 16-bit wide blocks.

3.2.3 DATA ALIGNMENT

To help maintain backward compatibility with

PICmicro® devices and improve data space memory

usage ef ficiency, the dsPIC30F ins truction set sup ports

both word and byte operations. Data is aligned in data

memory a nd regist ers as wo rds, but all dat a sp ace EAs

resolve to bytes. Data byte reads will read the complete

word, which contains the byte, using the LS bit of any

EA to determine which byte to select. The selected byte

is placed onto the LS Byte of the X data path (no byte

acces ses are possible fro m the Y data pa th as the MAC

clas s of inst ruct ion can only fetch words). That is, data

memory and registers are organized as two parallel

byte wide entities with shared (word) address decode,

but sepa rate wri te lines . Data byte w rites o nly write to

the corresponding side of the array or register which

matches the byte address.

As a cons equence of this byte access ibility, all effec tive

address c alc ul ati ons (i ncl ud ing tho se ge nerated by th e

DSP operations, which are restricted to word sized

data ) are internal ly scale d to step th rough word ali gned

memory. For example, the core would recognize that

Post-Modified Register Indirect Addressing mode

[Ws++], will result in a value of Ws+1 for byte opera-

tions and Ws+2 for word operations.

All wo rd accesses must be aligned to an eve n address .

Misaligned word data fetches are not supported, so

care must be taken when mixing byte and word opera-

tions, or translating from 8-bi t MCU code. Should a mis-

aligned read or write be attempted, an Address Error

trap wil l be ge ner ated . I f th e er ror oc curre d o n a read ,

the instruction underway is completed, whereas if it

occurred on a write, the instruction will be inhibited and

the PC will not be incremented. In either case, a trap

will then be executed, allowing the system and/or user

to exa mi ne th e mac hin e stat e pr ior t o ex ecu tio n of the

address fault.

FIGURE 3-6: DATA ALIGNMENT

All byte loads into a ny W register are loaded into the LS

Byte. The MSB is not modified.

A sign-extend (SE) instruction is provided to allow

users to tran slate 8- bit s igned dat a to 16-b it si gned val-

ues. Alternatively, for 16-bit unsigned data, users can

clear the MSB of any W register, by executing a

zero-extend (ZE) instruction on the appropriate

address.

Although m os t i ns truc tio ns are capable of opera t ing o n

word or byte data sizes, it should be noted that some

instructions, including the DSP instructions, operate

only on words.

3.2.4 DATA SPA CE MEMORY MAP

The data space memory is split into two blocks, X and

Y data space. A key element of th is archi tec ture is th at

Y space is a subset of X space, and is fully contained

within X space. In order to provide an apparent linear

addressing space, X and Y spaces have contiguous

addresses.

When executing any instruction other than one of the

MAC class of instructions, the X block consists of the

entire 64 Kbyte data address space (including all Y

addresses). When executing one of the MAC class of

instruc tions, the X block consi st s of the ent ire 64 Kby te

data address space excluding the Y address block (for

data reads only). In other words, all other instructions

regard the entire data memory as one composite

address space. The MAC class instructions extract the

Y address space from data space and addresses it

using EAs sou rce d from W10 and W11. The remai nin g

X data space is addressed using W8 and W9. Both

address spaces are concurrently accessed only by the

MAC class instructions.

An example data space memory map is shown in

Figure 3-8.

TABLE 3-2: EFFECT OF INVALID

MEMORY ACCESSES

Attempted Operation Data Returned

EA = an unimplemented address 0x0000

W8 or W9 used to access Y data

spa ce in a MAC instru ction 0x0000

W10 or W11 used to access X

data space in a MAC instruction 0x0000

15 8 7 0

0001

0003

0005

0000

0002

0004

Byte 1 Byte 0

Byte 3 Byte 2

Byte 5 Byte 4

LS ByteMS Byte

 2002 Microchip Technology Inc. Advance Information DS70082A-page 31

dsPIC30F

3.2.5 NEAR DATA SPACE

An 8 Kbyte ‘near’ data space is reserved in X address

memory space between 0x0000 and 0x1FFF, which is

directly add res sab le via a 13-bit absolute address fiel d

within all memory direct instructions. The remaining X

address space and all of the Y address space is

address able indirec tly. Addi tionally, the whole o f X data

space is addressable using MOV instructions, which

support memory direct addressing with a 16-bit

address field.

The stack pointer always points to the first available

free word and grows from lower addresses towards

higher addresses. It pre-decrements for stack pops

(reads) and post-increments for stack pushes (writes),

as show n i n Fi gu re 3-7. Note that for a PC push durin g

any CALL instruction, the MSB of the PC is zero-

extended before the push, ensuring that the MSB is

always clear.

3.2.6 SOFTWARE STACK

The dsPIC contains a software stack. W15 is used as

the Stack Pointer.

There is a S tack Limit reg ister (SPLI M) assoc iated wi th

the stack pointer. SPLIM is uninitialized at RESET. As

is the case for the stac k point er, SPLIM<0> is forced to

0, because all stack operations must be word aligned.

Wheneve r an effective address (EA) is generate d using

W15 as a source or destination pointer, the address

thus gene rated is compa red with the value in SPLIM. If

the EA is found to be greater than the contents of

SPLIM, then a Stack Pointer Overflow (Stack Error)

trap is generated.

Similarly, a Stack Pointer Underflow (Stack Error) trap

is generated when the stack pointer address is found to

be less than 0x0800, thus preventing the stack from

interfering with the Special Function Register (SFR)

space.

FIGURE 3-7: CALL STACK FRAME

Note: A PC push during exception processing

will concatenate the SRL register to the

MSB of the PC prior to the push.

PC<15:0>

000000000 PC<22:16>

015

W15 (before CALL)

W15 (after CALL)

Stack Grows Towa rd s

Higher Addres s

PUSH : [W15++]

POP : [--W15]

0x0000

dsPIC30F

DS70082A-page 32 Advance Information  2002 Mic rochip Technology Inc.

FIGURE 3-8: SAMPLE DATA SPACE MEMORY MAP

0x0000

0x07FE

SFR Space

0x17FE

0xFFFE

X Data RAM (X)

LS Byte

Address

16-bits

LSBMSB

MS Byte

Address

0x0001

0x07FF

0x17FF

0xFFFF

X Data

0x8001 0x8000

Optionally

Mapped

into Program

Memory

Unimplemented (X)

0x27FF 0x27FE

0x28000x2801

0x0801 0x0800

0x1801

0x1800

Near

Data

0x1FFE 0x1FFF

Y Data RAM (Y)

2 Kbyte

SFR Space

8 Kbyt e

SRAM Space

8 Kbyt e

SRAM boundary

Note: The address map shown in Figure 3-8 is conceptual, and may vary across individual devices

depending on available memory.

Space

 2002 Microchip Technology Inc. Advance Information DS70082A-page 33

dsPIC30F

FIGURE 3-9: DATA SPACE FOR MCU AND DSP (MAC CLASS) INSTRUCTIONS EXAMPLE

SFR SPACE

(Y SPACE)

X SPACE

SFR SPACE

UNUSED

X SPACE

Y SPACE

UNUSED

Non-MAC Class Ops (Read) MAC Class Ops (Read)

Indirect EA from any W Indirect EA from W8, W9 Indirect EA from W10, W11

dsPIC30F

DS70082A-page 34 Advance Information



2002 Microchip Technology Inc.

TABLE 3-3: CORE REGISTER MAP

SFR Name Address

(Home) Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RESET State

W0 0000 W0 / WREG 0000 0000 0000 0000

W1 0002 W1 0000 0000 0000 0000

W2 0004 W2 0000 0000 0000 0000

W3 0006 W3 0000 0000 0000 0000

W4 0008 W4 0000 0000 0000 0000

W5 000A W5 0000 0000 0000 0000

W6 000C W6 0000 0000 0000 0000

W7 000E W7 0000 0000 0000 0000

W8 0010 W8 0000 0000 0000 0000

W9 0012 W9 0000 0000 0000 0000

W10 0014 W10 0000 0000 0000 0000

W11 0016 W11 0000 0000 0000 0000

W12 0018 W12 0000 0000 0000 0000

W13 001A W13 0000 0000 0000 0000

W14 001C W14 0000 0000 0000 0000

W15 001E W15 0000 1000 0000 0000

SPLIM 0020 SPLIM 0000 0000 0000 0000

ACCAL 0022 ACCAL 0000 0000 0000 0000

ACCAH 0024 ACCAH 0000 0000 0000 0000

ACCAU 0026 Sign-Extension (ACCA<39>) ACCAU 0000 0000 0000 0000

ACCBL 0028 ACCBL 0000 0000 0000 0000

ACCBH 002A ACCBH 0000 0000 0000 0000

ACCBU 002C Sign-Extension (ACCB<39>) ACCBU 0000 0000 0000 0000

PCL 002E PCL 0000 0000 0000 0000

PCH 0030 — — — — — — — — — PCH 0000 0000 0000 0000

TBLPAG 0032 — — — — — — — — TBLPAG 0000 0000 0000 0000

PSVPAG 0034 — — — — — — — — PSVPAG 0000 0000 0000 0000

RCOUNT 0036 RCOUNT uuuu uuuu uuuu uuuu

DCOUNT 0038 DCOUNT uuuu uuuu uuuu uuuu

DOSTARTL 003A DOSTARTL 0uuuu uuuu uuuu uuu0

DOSTARTH 003C — — — — — — — — — DOSTARTH 0000 0000 0uuu uuuu

DOENDL 003E DOENDL 0uuuu uuuu uuuu uuu0

DOENDH 0040 — — — — — — — — — DOENDH 0000 0000 0uuu uuuu

SR 0042 OA OB SA SB OAB SAB DA DC IPL2 IPL1 IPL0 RA NOV Z C 0000 0000 0000 0000

CORCON 0044 — — — — EDT DL2 DL1 DL0 SATA SATB SATDW ACCSAT IPL3 PSV RND IF 0000 0000 0000 0000

Legend: u = uninitialized bit

 2002 Microchip Technology Inc.

Advance Inf ormat ion

DS70082A-page 35

dsPIC30F

MODCON 0046 XMODEN YMODEN — — BWM<3:0> YWM<3:0> XWM<3:0> 0000 0000 0000 0000

XMODSRT 0048 XS<15:1> 0uuuu uuuu uuuu uuu0

XMODEND 004A XE<15:1> 1uuuu uuuu uuuu uuu1

YMODSRT 004C YS<15:1> 0uuuu uuuu uuuu uuu0

YMODEND 004E YE<15:1> 1uuuu uuuu uuuu uuu1

XBREV 0050 BREN XB<14:0> uuuu uuuu uuuu uuuu

DISICNT 0052 — — DISICNT<13:0> 0000 0000 0000 0000

TABLE 3-3: CORE REGISTER MAP (CONTINUED)

SFR Name Address

(Home) Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RESET State

Legend: u = uninitialized bit

dsPIC30F

DS70082A-page 36 Advance Information  2002 Mic rochip Technology Inc.

NOTES:

 2002 Microchip Technology Inc. Advance Information DS70082A-page 37

dsPIC30F

4.0 ADDRESS GENERATOR UNITS

The dsPIC core contains two independent address

generat or units: the X AGU and Y AGU. Fu rther, the X

AGU has two parts: X RAGU (Read AGU) and X

WAGU (Write AGU). The X RAGU and X WAGU sup-

port byte and word sized data space reads and writes,

respectively, for both MCU and DSP instructions. The

Y AGU supports word sized data reads for the DSP

MAC class of instructions only. They are each capable

of supporting two types of data addressing:

•Linear Addressing

•Modulo (Circular) Addressing

In addition, the X WAGU can support:

•Bit-Reversed Addre ss ing

Linear and Modulo Data Addressing modes can be

applied to data space or program space. Bit-Reversed

address ing is only applic able t o dat a s pa ce add resses .

4.1 Data Space Organizati on

Although the data sp ace memory is organized as 16-b it

words, all effective addresses (EAs) are byte

addresses. Instructions can thus access individual

bytes as well as properly aligned words. Word

addresses must be aligned at even boundaries. Mis-

aligned word accesses are not supported, and if

attempted, will initiate an address error trap.

When executing instructions which require just one

source operand to be fetched from data space, the X

RAGU a nd X WAGU are used to ca lcula te the ef fectiv e

address . The X RAGU and X W AGU can genera te any

address in the 64 Kbyte data space. They support all

MCU Addressing modes and Modulo Addressing for

low overhead circular buffers. The X WAGU also sup-

ports Bit-Reversed Addressing to facilitate FFT data

reorganization.

When executing instructions which require two source

operands to be concurre ntly fetche d (i.e., the MAC class

of DSP instru ct io ns ), bo th t h e X RA GU an d Y AGU are

used simultaneously and the data space is split into 2

independent address spaces, X and Y. The Y AGU sup-

ports Register Indirect Post-Modified and Modulo

Addressing only. Note that the data write phase of the

MAC class of i ns truc tio n do es not s pl it X a nd Y a dd res s

space. The write EA is calculated using the X WAGU

and the data space is configured for full 64 Kbyte

access.

In the Split Data Space mode, some W register address

pointers are dedicated to X RAGU, and others to Y

AGU. The EAs of each operand must, therefore, be

restricted to be within different address spaces. If they

are not, one of the EAs will be outside the address

space of the corresponding data space (and will fetch

the bus default value, 0x0000).

4.2 Instruction Addressing Modes

The Addressing modes in Table 4-1 form the basis of

the Addressing modes optimized to s upport the specific

features of individual instructions. The Addressing

modes provided in the MAC class of instructions are

somewhat different from those in the other instruction

types.

Some Addressing mode combinations may lead to a

one-cycle stall during instruction execution, or are not

allow ed, as dis c uss ed in Sectio n 4.3.

TABLE 4-1: FUNDAMENTAL ADDRESSING MODES SUPPORTED

Addressing Mode Description

File Register Direct The address of the file register is specified explicitly.

decremented) by a constant value.

to form the EA.

dsPIC30F

DS70082A-page 38 Advance Information  2002 Microchip Technology Inc.

4.2.1 FILE REGISTER INSTRUCTIONS

Most fil e re gis ter i ns truc tio ns us e a 1 3-bi t ad dres s fiel d

(f) to directly address data present in the first 8192

bytes of data memory. These memory locations are

known as File Registers. Most file register instructions

employ a working register W0, which is denoted as

WREG in these instructions. The destin ation is typically

either th e same fil e re gi ste r, or WREG (with the ex ce p-

tion of the MUL instruction), which writes the result to a

16-bit address field.

4.2.2 MCU INSTRUCTIONS

The three-operand MCU instructions are of the form:

Operand 3 = Operand 1 <function> Operand 2

where Ope r and 1 is alwa ys a w orking register (i. e., th e

Addressing mode can only be register direct), which is

referred to as Wb. Operand 2 can be W register,

fetched from data memory, or 5-bit literal. In two-

operand i ns truc tions, the res ult loc ati on is the same as

that of one of the operands. Certain MCU instructions

are one -op eran d ope rati ons . The foll ow in g Add res sin g

modes are s uppor ted by MCU instructions:

•Register Di rec t

•Regist er Indi rect

•Register Indi rec t Post-m od ifi ed

•Regis ter Indi rec t Pre-mo dif ied

•5-bit or 10-bit Literal

4.2.3 MOVE AND ACCUMULATOR

INSTRUCTIONS

Move instructions and the DSP accumulator class of

instructions provide a greater degree of addressing

flexibility than other instructions. In addition to the

Addressing modes supported by most MCU instruc-

tions, Move and Accumulator instructions also support

mode, also referred to as Register Indexed mode.

In summary, the following Addressing modes are

supported by Move and Accumulator instructions:

•Register Direct

•Register Indirect

•Register Indirect Post-modified

•Register Indirect Pre-modified

•Register Indirect with Register Offset (Indexed)

•Register Indirect with Literal Offset

•8-bit Literal

•16-bit Literal

4.2.4 MAC INSTRUCTIONS

The dual so urce op erand D SP instructio ns (CLR, ED,

EDAC, MAC, MPY, MPY.N, MOVSAC and MSC), also

referred to a s MAC instruction s, utilize a si mplified set of

Addressing modes to allow the user to effectively

manipulate the data pointers through register indirect

tables.

The 2 source operand pre-fetch registers must be a

member of the set {W8, W9, W10, W11}. For data

reads, W8 and W9 will always be directed to the X

RAGU and W10 and W11 will alway s be directe d to the

Y AGU. The effective addresses generated (before and

after modification) must, therefore, be valid addresses

within X data space for W8 and W9, and Y data space

for W10 and W11.

In summary, the following Addressing modes are

supported by the MAC class of instructions:

•Register Indirect

•Register Indirect Post-modified by 2

•Register Indirect Post-modified by 4

•Register Indirect Post-modified by 6

•Register Indirect with Register Offset (Indexed)

4.2.5 OTHER INSTRUCTIONS

Besides the various Ad dressing mo des outlined above,

some i nstructio ns use li teral con sta nts of various sizes.

For example, BRA (branch) instructions use 16-bit

signed l iterals to spe cify the branch de stination dire ctly ,

whereas the DISI instruction uses a 14-bit unsigned

literal field. In some instructions, such as ADD Acc, the

source of an operand or result is implied by the opc ode

it self. Cert ain opera tions, such as NOP, do not have any

operands.

Note: Not all instruct ions support all the Addres s-

ing modes given above. Individual instruc-

tions may support different subsets of

these Addressing modes.

Note: For the MOV instructions, the Addressing

mode specifi ed in the instruction can differ

for the source and destination EA. How-

ever, the 4-bit Wb (Register Offset) field is

shared between both source and

destination (but typically only used by

one).

Note: Not all instructi ons support all the Address-

ing modes given above. Individual instruc-

tions may support different subsets of

these Addressing modes.

Note: Register Indirect with Register Offset

Addressing is only available for W9 (in X

spac e) and W11 (in Y spac e).

 2002 Microchip Technology Inc. Advance Information DS70082A-page 39

dsPIC30F

4.3 Instruction Stalls

4.3.1 INTRODUCTION

In order to maximize data space, EA calculation and

operand fetch time, the X data space read and write

accesses are partially pipelined. The latter half of the

read phase overlaps the first half of the write phase of

an instruction, as show n in Section 2.

Address register data dependencies, also known as

‘Read Afte r Write ’ (RA W) dependen cies, may therefore

arise between successive read and write operations

using common registers. They occur across instruction

boundaries and are detected by the hardware.

An exam pl e of a RAW depende nc y is a w rite operation

(in the current instruction) that modifies W5, followed

by a read operation (in the next instruction) that uses

W5 as a source addre ss pointer . W 5 will not be v alid for

the read operation until the earlier write completes.

This p robl em is re solv ed by st allin g t he ins tructi on ex e-

cution for one instruction cycle, thereby allowing the

write to complete before the next read is started.

4.3.2 RAW DEPENDENCY DETECTION

During the inst ruction pre -de code, t he core determi nes

if any address register d epe nde nc y i s i mm in ent ac ros s

an instruction boundary. The stall detection logic com-

pares the W regi ster (if any ) used for t he destination EA

of the instruction currently being executed, with the W

fetched instruction. As t he W registers are also memor y

mapped, the stall detection logic also derives an SFR

address from the W regis ter being us ed by the destin a-

tion EA, and determines whether this address is being

issued during the write phase of the instruction cur-

rently being executed.

When it o bserves a match be tween the de stinat ion and

source registers, a set of rules are applied to decide

whether or not to stall the instruction by one cycle.

Table 4-2 lists out the various RAW conditions which

cause an instruction execution stall.

TABLE 4-2: RAW DEPENDENCY RULES (DETECTION BY HARDWARE)

Destination

Addressing M ode

Using Wn

Source Addressing

Mode Using Wn Status Examples

(Wn = W2)

Direct Direct No Stall ADD.w W0, W1, W2

MOV.w W2, W3

Direct Indirect Stall ADD.w W0, W1, W2

MOV.w [W2], W3

Direct Indirect with Pre- or

Post-Modification Stall ADD.w W0, W1, W2

MOV.w [W2++], W3

Indirect Direct No Stall ADD.w W0, W1, [W2]

MOV.w W2, W3

Indirect Indirect No Stall ADD.w W0, W1, [W2]

MOV.w [W2], W3

Indirect Indirect Stall ADD.w W0, W1, [W2] ; W2=0x0004 (mapped W2)

MOV.w [W2], W3 ; (i.e., if W2 = addr. of W2)

Indirect Indirect with Pre- or

Post-Modification No Stall ADD.w W0, W1, [W2]

MOV.w [W2++], W3

Indirect Indirect with Pre- or

Post-Modification Stall ADD.w W0, W1, [W2] ; W2=0x0004 (mapped W2)

MOV.w [W2++], W3 ; (i.e., if W2 = addr. of W2)

Indirect wi th Pre- or

Post-Modification Direct No Stall ADD.w W0, W1, [W2++]

MOV.w W2, W3

Indirect wi th Pre- or

Post-Modification Indirect Stall ADD.w W0, W1, [W2++]

MOV.w [W2], W3

Indirect wi th Pre- or

Post-Modification Indirect with Pre- or

Post-Modification Stall ADD.w W0, W1, [W2++]

MOV.w [W2++], W3

dsPIC30F

DS70082A-page 40 Advance Information  2002 Microchip Technology Inc.

4.4 Modulo Addressing

Modulo addressing is a method of providing an auto-

mated means to support circular data buffers using

hardwa re. The ob jectiv e is to remo ve t he need for soft-

ware to perform data address boundary checks when

executing tightly looped code, as is typical in many

DSP algorithms.

Modulo Addressing can operate in either data or pro-

gram space (since the dat a pointer mechanism is essen-

tially the same for both). One circular buffer can be

supported in each of the X (which also provides the

pointers into Program space) and Y data spaces. Mod-

ulo Addressing can operate on any W register pointer.

However, it is not advisable to use W14 or W15 fo r Mod-

ulo Addressing, since these two registers are used as

the S tack Frame Pointer and S tack Pointer , respectively .

In general, any particular circular buffer can only be

configu red to operate in one direct ion, as ther e are c er-

tain restrictions on the buffer start address (for incre-

menting buffers) or end address (for decrementing

buffe rs), based upon the direction of the buffer.

The only exception to the usage restrictions is for buff-

ers which have a power-of-2 length. As these buffers

satisfy the start and end address criteria, they may

operate in a Bi-Directional mode, i.e., address bound-

ary checks will be performed on both the lower and

upper address boundaries.

4.4.1 START AND END ADDRESS

The Modulo Addressing scheme requires that a start-

ing and an end address be specified and loaded into

the 16-bi t mod ulo bu f fer ad dress registe rs: XMO DSR T,

XMODEND, YMODSRT, YMODEND (see Table 3-3).

If the length of an inc rementin g buffer is gre ater than M

= 2N-1, but not greater than M = 2N bytes, then the last

’N’ bits of the data buffer start address must be zeros.

There are no such res trictions on the end addres s of an

incrementing buffer. For example, if the buffer size

(modulu s value) is cho sen to be 100 bytes (0x6 4), then

the buf fer st art addres s for an in crementing b uffer m ust

cont ain 7 Le ast Significan t ze ros. Valid sta rt addres ses

may, therefore, be 0xXX00 and 0xXX80, where ‘X’ is

any hexa decimal value. Adding the buff er length to this

value and subtracting 1 will give the end address to be

written into X/YMODEND.

For example, if the start address was chosen to be

0x2000, then the X/YMODEND would be set to

(0x2000 + 0x0064 – 1) = 0x2063.

In the case of a decrementing buffer, the last ‘N’ bits of

the data buffer end address must be ones. There are

no such restrictions on the start address of a decre-

menting buffer . For exam ple, if the buf fer size (modu lus

value) i s chose n to be 10 0 bytes (0x64), the n the buf fer

end address for a decrementing buffer must contain 7

Least Significant ones. Valid end addresses may,

therefore, be 0xXXFF and 0xXX7F, where ‘X’ is any

hexadecimal value. Subtracting the buffer length from

this val ue and a dding 1 wi ll g ive the sta rt addres s to be

written into X/YMODSRT. For example, if the end

address was chosen to be 0x207F, then the start

address would be (0x207F – 0x0064+1) = 0x201C,

which is the first physical address of the buffer.

The leng th of a ci rcular buf fer is not di rectly spec ified. It

is determined by the difference between the corre-

spondin g st art and end addres ses. The maxi mu m pos-

sible length of the circular buffer is 32K words

(64 Kbytes).

4.4.2 W ADDRESS R EGI S TER

SELECTION

The M od u lo an d B i t-R e ve rs ed A dd r es si ng c o ntr o l reg -

ister MODCON<15:0> contains enable flags plus W

XWM and YWM fields select which registers will oper-

ate with Modulo Add ressing. If XWM = 15, X RAGU and

X WAGU Modulo Addressing are disabled. Similarly, if

YWM = 15, Y AGU Modulo Addressing is disabled.

The X address space pointer W register (XWM) to

which Modulo Addressing is to be applied, is stored in

MODCON<3 :0> (see Table 3-3). Modul o Addres sing i s

enabled for X data sp ace when XWM is set to any value

other than 15 and the XMODEN bit is set at

MODCON<15>.

The Y address space pointer W register (YWM) to

which Modulo Addressing is to be applied, is stored in

MODCON<7:4>. Modulo addressing is enabled for Y

data space when YWM is set to any value other than 15

and the YM ODEN bit is set at MODCON<14>.

Note: The start and end addresses are the first

and last byte addresses of the buffer (irre-

spective of whether it is a word or byte

buffer, or an increasing or decreasing

buffer). Moreover, the start address must

be even and the end address must be odd

(for both word and byte buffers).

Note: ‘Start address’ refers to the smallest

address boundary of the circular buffer.

The first access of th e buffer m ay be at any

address within the modulus range (see

Section 4.4.4).

Note: Y-space Modulo Addressing EA calcula-

tions assume word sized data (LS bit of

every EA is always clear).

Note: The XMO DSR T an d XMO DEND registers ,

and the XWM register selection, are

shared between X RAGU and X WAGU.

 2002 Microchip Technology Inc. Advance Information DS70082A-page 41

dsPIC30F

FIGURE 4-1: INCREMENTING BUFFER MODULO ADDRESSING OPERATION EXAMPLE

0x1100

0x1163

Start Addr = 0x1100

End Addr = 0x1163

Length = 0x0032 words

MOV #0x1100,W0

MOV W0,XMODSRT ;set modulo start address

MOV #0x1163,W0

MOV W0,MODEND ;set modulo end address

MOV #0x8001,W0

MOV W0,MODCON ;enable W1, X AGU for modulo

MOV #0x0000,W0 ;W0 holds buffer fill value

MOV #0x1110,W1 ;point W1 to buffer

DO AGAIN,#0x31 ;fill the 50 buffer locations

MOV W0,[W1++] ;fill the next location

AGAIN: INC W0,W0 ;increment the fill value

Byte

Address

dsPIC30F

DS70082A-page 42 Advance Information  2002 Microchip Technology Inc.

FIGURE 4-2: DECREMENTING BUFFER MODULO ADDRESSING OPERATION EXAMPLE

4.4.3 MODULO ADDRESSING

APPLICABILITY

Modulo Addressing can be applied to the effective

address (EA) calculation associated with any W regis-

ter. It is important to realize that the address bound-

aries c he ck fo r ad dre sses le ss th an or greater tha n th e

upper (for incrementing buffers), and lower (for decre-

menting buffers) boundary addresses (not just equal

to). A ddress change s may, therefore, j ump over b ound-

arie s and stil l be adjust ed correc tly (see S ection 4.4. 4

for restrictions)

0x11D0

0x11FF

Start Addr = 0x11 D0

End Addr = 0x11FF

Length = 0x0018 words

MOV #0x11D0,W0

MOV #0,XMODSRT ;set modulo start address

MOV 0x11FF,W0

MOV W0,XMODEND ;set modulo end address

MOV #0x8001,W0

MOV W0,MODCON ;enable W1, X AGU for modulo

MOV #0x000F,W0 ;W0 holds buffer fill value

MOV #0x11E0,W1 ;point W1 to buffer

DO AGAIN,#0x17 ;fill the 24 buffer locations

MOV W0,[W1--] ;fill the next location

AGAIN: DEC W0,W0 ; decrement the fill value

Byte

Address

Note: The modulo corrected effective address is

written back to the register only when Pre-

Modify or Post-Modify Addressing mo de i s

used to compute the Effective Address.

When an address offset (e.g., [W7+W2] ) is

used, modulo address correction is per-

formed, but the contents of the register

remains unchanged.

 2002 Microchip Technology Inc. Advance Information DS70082A-page 43

dsPIC30F

4.4.4 MODULO ADDRESSING

RESTRICTIONS

As stated in Section 4.4.1, for an incrementing buffer,

the circular buffer start address (lower boundary) is

arbitrary, but must be at a ‘zero’ power-of-two bound-

ary. For a decrementing buffer, the circular buffer end

address is arbitrary, but must be at a ‘ones’ boundary.

There are no restrictions regarding how much an EA

calculation can exceed the address boundary being

checked, and still be successfully corrected.

Once configured, the direction of successive

addresses into a buffer should not be changed.

Although all EAs will co ntinue to be gen erated c orrectly

irrespective of offset sign, only one address boundary

is checked for each type of buffer . Thus, if a buf fer is set

up to be an incrementing buffer by choosing an appro-

priate starting address, then correction of the effective

address will be performed by the AGU at the upper

address b oun dary, but no address c orrec ti on will occur

if the EA crosses the lower address boundary. Similarly ,

for a decrementing boundary, address correction will

be performed by the AGU at the lower address bound-

ary, but no address correction will take place if the EA

crosses the upper address boundary. The circular

buf f er poin ter ma y be free ly modified in both directions

without a possibility of out-of-range address access

only when the start address satisfies the condition for

an inc rement ing b uff er (las t ‘N’ bit s are zeroe s) and the

end address satisfies the condition for a decrementing

buffer (last ‘N’ bits are ones). Thus, the Modulo

Addressing capability is truly bi-directional only for

modulo-2 length buffers.

4.5 Bit-Reversed Addressing

Bit-Reversed Addressing is intended to simplify data

re-ordering for radix-2 FFT algorithms. It is supported

by the X WAGU only, i.e., for data writes only.

The modifier , which may be a constant value or register

contents, is regarded as having its bit order reversed.

The addres s sourc e and dest inat ion are ke pt in norma l

order. Thus, the only operand requiring reversal is the

modifier.

4.5.1 BIT-REVERSED ADDRESSING

IMPLEMENTATION

Bit-Reversed Addressing is enabled when:

1. BWM (W register selection) in the MODCON

not be accessed using Bit-Reversed Address-

ing) and

2. the BREN bit is set in the XBREV register and

3. the Addressing mode used is Register Indirect

with Pre-Increment or Post-Increment.

XB<14:0> is the Bit-Reversed Address modifier or

‘pivot po in t’ w hic h is typ ic all y a c ons t a nt. In the case of

an FFT computation, its value is equal to half of the FFT

dat a buffer size.

When enabled, Bit-Reversed Addressing will only be

executed with register indirect with Pre-Increment or

Post-Incre ment Addressing and word sized data writes.

It will no t functio n for any ot her Addres sing m ode or for

byte-sized data, and normal addresses will be gener-

ated instea d. When Bit-R eversed Addr essin g is active,

the W address pointer will always be added to the

address modifier (XB) and the offset associated with

the register Indirect Addressing mode will be ignored.

In addition, as word sized data is a requirement, the LS

bit of the EA is ignored (and a lways clear).

FIGURE 4-3: BIT-REVERSED ADDRESS EXAMPLE

Note: All Bit-Reversed EA calculations assume

word sized data (LS bit of every EA is

always clear). The XB value is scaled

accordingly to generate compatible (byte)

addresses.

Note: Modulo Addressing and Bit-Reversed

Addressing should not be enabled together .

In the event that the user attempts to do

this, bit reversed addressing will assume

priority when active for the X WAGU, and X

W AGU Mo dulo Addressing will be dis abled.

However, Modulo Addressing will continue

to function in the X RAGU.

b3 b2 b1 0

b2 b3 b4 0

Bit Locations Swapped Left-to-Right

Around Center of Binary Value

Bit-Reversed Address

XB = 0x0008 for a 16-word Bit-Reversed Buffer

b7 b6 b5 b1

b7 b6 b5 b4b11 b10 b9 b8

b11 b10 b9 b8

b15 b14 b13 b12

Sequenti al Addre ss

Pivot Point

dsPIC30F

DS70082A-page 44 Advance Information  2002 Microchip Technology Inc.

TABLE 4-3: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY)

TABLE 4-4: BIT-REVERSED ADDRESS MODIFIER VALUES

Normal

Address Bit-Reversed

Address

A3 A2 A1 A0 Decimal A3 A2 A1 A0 Decimal

0 0 0 0 0 0 0 0 0 0

0 0 0 1 1 1 0 0 0 8

0 0 1 0 2 0 1 0 0 4

0 0 1 1 3 1 1 0 0 12

0 1 0 0 4 0 0 1 0 2

0 1 0 1 5 1 0 1 0 10

0 1 1 0 6 0 1 1 0 6

0 1 1 1 7 1 1 1 0 14

1 0 0 0 8 0 0 0 1 1

1 0 0 1 9 1 0 0 1 9

1 0 1 0 10 0 1 0 1 5

1 0 1 1 11 1 1 0 1 13

1 1 0 0 12 0 0 1 1 3

1 1 0 1 13 1 0 1 1 11

1 1 1 0 14 0 1 1 1 7

1 1 1 1 15 1 1 1 1 15

Buffer Size (Words) XB<14:0> Bit-Reversed Address Modifier Value

32768 0x4000

16384 0x2000

8192 0x1000

4096 0x0800

2048 0x0400

1024 0x0200

512 0x0100

256 0x0080

128 0x0040

64 0x0020

32 0x0010

16 0x0008

80x0004

40x0002

20x0001

 2002 Microchip Technology Inc. Advance Information DS70082A-page 45

dsPIC30F

5.0 EXCEPTION PROCESSING

The dsPIC30F Motor Control and Power Conversion

Family has up to 44 interrupt sources and 4 processor

exceptions (traps), which must be arbitrated based on

a priority scheme.

The processor core is responsible for reading the

Interrupt Vector Table (IVT) and transferring the

address contained in the interrupt vector to the pro-

gram counter. The interrupt vector is transferred from

the program data bus into the program counter, via a

24-bit wide multiplexer on the input of the program

counter.

The Interrupt Vector Table (IVT) and Alternate Inter-

rupt Vector Tabl e (AIVT) are pl aced ne ar the begin ning

of program memory (0x000004). The IVT and AIVT

are shown in Table 5-2.

The interrupt controller is responsible for pre-

processing the interrupts and processor exceptions,

prior to their being presented to the processor core.

The peripheral interrupts and traps are enabled, priori-

tized, and controlled using centralized special function

registers:

•IFS0<15:0>, IFS1<15:0>, IFS2<15:0>

All interrupt request flags are maintained in these

three registers. The flags are set by their respec-

tive peripherals or external signals, and they are

cleared via software.

•IEC0<15:0>, IEC1<15:0>, IEC2<15:0>

All interrupt enable control bits are maintained in

these three registers. These control bits are used

to individually enable interrupts from the

peripherals or external signals.

•IPC0<15:0> ... IPC11<7:0>

The user assignable priority level associated with

each of these 44 interrupts is held centrally in

these twelve registers.

•IPL<3:0> The current CPU priority level is explic-

itly stored in the IPL bits. IPL<3> is present in the

CORCON reg ister , whereas IPL<2:0 > are present

in the status register (SR) in the processor core.

•INTCON1< 15:0>, INTCON2<1 5:0>

Global interru pt co ntrol fu nctio ns are deriv ed from

these two registers. INTCON1 contains the con-

trol and status flags for the processor exceptions.

The INTCON2 register controls the external inter-

rupt request signal behavior and the use of the

alternate vector table.

All interrupt sources can be user assigned to one of 7

priority levels, 1 through 7, via the IPCx registers.

Each interrupt source is associated with an interrupt

vector, as shown in Table 5-2. Levels 7 and 1 repre-

sent the highest and lowest maskable priorities,

respe ct ive ly.

If the NSTDIS bit (INTCON1<15>) is set, nesting of

interrupts is prev en ted . Th us , i f a n i nte rrupt is c urrentl y

being serviced, processing of a new interrupt is pre-

vented, even if the new interrupt is of higher priority

than the one currently being serviced.

Certain interrupts have specialized control bits for fea-

tures like edge or level triggered interrupts, interrupt-

on-change, etc. Control of these features remains

within the peripheral module which generates the

interrupt.

The DISI instruction can be used to disable the pro-

cessing of interrupts of priorities 6 and lower for a cer-

tain number of instructions, during which the DISI bit

(INTCON2<14>) remains set.

When an interrupt is serviced, the PC is loaded with the

address stor ed in the vecto r locati on in Program mem-

ory that cor respond s to the interrupt. There are 63 dif-

feren t vectors within the IVT (refer to Table 5-2). These

vectors are contained in locations 0x000004 through

0x0000FE of program memory (refer to Table 5-2).

These locations contain 24-bit addresses, and in order

to preserve robustness, an address error trap will take

place should the PC attempt to fetch any of these

words during normal execution. This prevents execu-

tion of random dat a through acc ide nt a lly decrementin g

a PC into vector space, accidentally mapping a data

spac e addr ess in to vec tor sp ace , or the PC roll ing over

to 0x000000 after reaching the end of implemented

program memory space. Execution of a GOTO instruc-

tion to this vector space will also generate an address

error trap.

5.1 Interrupt Priority

The user a ssig nab le In terru pt Pri ori ty (I P<2:0 >) bi t s for

each individual interrupt source are located in the LS

3-bits of each nibble, within the IPCx register(s). Bit 3

of each nibble is not used and is read as a ‘0’. These

bits define the priority level assigned to a particular

interrupt by the user.

Since more than one interrupt request source may be

assigned to a specific user specified priority level, a

means i s provided to assign priority within a given level.

This method is called “Natural Order Priority”.

Note: Interru pt fla g bit s get set when an in terru pt

conditi on oc curs, rega rdle ss of the state of

its c orresponding enable bit. User s oftware

should ensure the appropriate interrupt

flag bits are clear prior to enabling an

interrupt.

Note: Assigning a priority level of 0 to an interrupt

source is equivalent to disabling that

interrupt.

Note: The u ser sele cta ble priority levels s tart at 0

as the lowest priority and level 7, as the

highest priority.

dsPIC30F

DS70082A-page 46 Advance Information  2002 Microchip Technology Inc.

Table 5-1 lists the interrupt numbers and interrupt

sources for the dsPIC devices, and their associated

vector numbers.

The ability for the user to assign every interrupt to one

of sev en priority lev els i mp lie s that the u ser c an as sig n

a very high overall priority level to an interrupt with a

low natural order priority. For example, the PLVD (Low

Voltage Detect) can be given a priority of 7. The INT0

(external interrupt 0) may be assigned to priority level

1, thus giving it a very low effective priority.

TABLE 5-1: NATURAL ORDER PRIORITY

Note 1: The natural order priority scheme has 0

as the highest priority and 53 as the

lowest priority.

2: The natural order priority number is the

same as the INT number.

INT

Number Vector

Number Interrupt Source

Highest Natural Order Priority

0 8 INT0 - External Interrupt 0

1 9 IC1 - Input Capture 1

210 OC1 - Output Compare 1

311 T1 - Timer 1

412 IC2 - Input Capture 2

513 OC2 - Output Compare 2

614 T2 - Timer 2

715 T3 - Timer 3

816 SPI1

917 U1RX - UART1 Receiver

10 18 U1TX - UART1 Transmitter

11 19 ADC - ADC Convert Done

12 20 NVM - NVM Write Complete

13 21 I2C - I2C Transfer Complete

14 22 BCL - I2C Bus Collision

15 23 Input Change Interrupt

16 24 INT1 - External Interrupt 1

17 25 IC7 - Input Capture 7

18 26 IC8 - Input Capture 8

19 27 OC3 - Output Compare 3

20 28 OC4 - Output Compare 4

21 29 T4 - Timer 4

22 30 T5 - Timer 5

23 31 INT2 - External Interrupt 2

24 32 U2RX - UART2 Receiver

25 33 U2TX - UART2 Transmitter

26 34 SPI2

27 35 C1 - Combin ed IRQ for CAN1

28 36 IC3 - Input Capture 3

29 37 IC4 - Input Capture 4

30 38 IC5 - Input Capture 5

31 39 IC6 - Input Capture 6

32 40 OC5 - Output Compare 5

33 41 OC6 - Output Compare 6

34 42 OC7 - Output Compare 7

35 43 OC8 - Output Compare 8

36 44 INT3 - External Interrupt 3

37 45 INT4 - External Interrupt 4

38 46 C2 - Combin ed IRQ for CAN2

39 47 PWM - PWM Period Match

40 48 Q EI - QEI Interrupt

41 49 Reserved

42 50 LVD - Low Voltage Detect

43 51 FLTA - PWM Fault A

44 52 FLTB - PWM Fault B

45 - 53 53 - 61 Reserved

Lowest Natural Order Priority

 2002 Microchip Technology Inc. Advance Information DS70082A-page 47

dsPIC30F

5.2 RESET Sequence

A RESET is n ot a tr ue exc eption, b ecaus e the interru pt

controller is not involved in the RESET process. The

processor initializes its registers in response to a

RESET, which forces the PC to zero. The processor

then begi ns program execution at location 0x000000. A

GOTO instruction is stored in the first program memory

locatio n, immediately followed by the add ress target for

the GOTO instruction. The processor executes the GOTO

to the specified address and then begins operation at

the specified target (start) address.

5.2.1 RESET SOURCES

In addition to external, Power-on Resets (POR) and

software Reset, there are four sources of error

conditions which ‘trap’ to the RESET vector.

•Watchdog Time-out:

The watchdog has timed out, indicating that the

process or is no longer ex ecu tin g the corre ct flo w

of code.

•Uninitialized W Register Trap:

An attempt to use an uninitialized W register as

an address pointer will cause a RESET.

•Illegal Instruction Trap:

Attempted execution of any unused opcodes will

result in an illegal instruction trap. Note that a

fetch of an illegal instruction does not result in an

illegal instruction trap if that instruction is flushed

prior to execution due to a flow change.

•Brown-out Reset (BOR):

A momentary dip in the power supply to the

device has been detected, which may result in

malfunction.

5.3 Traps

Traps can be considered as non-maskable, non-stable

interrupts, which adhere to a predefined priority as

shown in Table 5-2. They are intended to provide the

user a means to correct erroneous operation during

debug and when operating within the application.

Note that many of these trap conditions can only be

detecte d when th ey occur. Consequentl y, the ques tion-

able instruction is allowed to complete prior to trap

exception processing. If the user chooses to recover

from the error, the result of the erroneous action that

caused the trap may have to be corrected.

There are 8 fixed priority levels for traps: Level 8

through Le ve l 15, whic h impl ies tha t the IPL3 i s alw ays

set during processing of a trap.

If the us er is n ot cur rentl y execu ting a trap, a nd he s et s

the IP L<3:0> bit s to a value of ‘0111’ (Level 7), t hen al l

interr upts are disabled, b ut traps c an still b e processed.

5.3.1 TRAP SOURCES

The following traps are provided with increasing prior-

ity. However, since all traps can be nested, priority has

little effect.

•Math Error Trap:

The Math Error trap executes under the following

three ci rcu ms t ances.

1. Should an attempt be made to divide by

zero, the div ide operation wil l be aborted on

a cycle boundary and the trap taken.

2. If enabled, a Math Error trap will be taken

when an arithmetic operation on either

accumulator A or B, causes an overflow

from bit 31 and the accumulator guard bits

are not utilized.

3. If enabled, a Math Error trap will be taken

when an arithmetic operation on either

accumulator A or B causes a catastrophic

overflow from bit 39 and all saturation is

disabled.

•Address Error Trap:

This trap is initiated when any of the following

circumstances occurs:

1. A misaligned data word fetch is attempted.

2. A data fetch from unused data address

spac e is atte mpted.

3. A program fetch from unimplemented user

program address space is attempted.

4. A program fe tch from vec tor addr ess sp ac e

is attempted.

•Stack Error T ra p

This trap is initiated under the following

conditions:

1. The stack pointer is loaded with a value

which is greater than the (user program-

mable) limit value written into the SPLIM

2. The stack pointer is loaded with a value

which is less than 0x0800 (simple stack

underflow).

•Oscillator Fail Trap:

This trap is initiated if the external oscillator fails

and operation becomes reliant on an internal RC

backup.

Note: If the user does not intend to take correc-

tive action in the event of a trap error con-

dition, these vectors must be loaded with

the RESET vect or address. If, on the oth er

hand, one of the vectors containing an

invalid address is called, an address error

trap is generated.

Note: The IPL3 bit is read only , which implies that

the user can not man ually set th e IPL<3:0>

bits to a value greater than 7.

dsPIC30F

DS70082A-page 48 Advance Information  2002 Microchip Technology Inc.

5.3.2 HARD AND SOFT TRAPS

It is possible that multiple traps can become active

within the same cycle (e.g., a misaligned word stack

write to an overflowed address). In such a case, the

fixed priority shown in Figure 5-2 is implemented,

whic h may requir e the user t o check if oth er traps are

pending, in order to completely correct the fault.

‘Soft’ trap s include ex ceptions of p riority level 8 through

level 11, inclusive. The arithmetic error trap (level 11)

falls into this cat egory of traps. Soft traps can be tr eated

like non-maskable sources of interrupt that adhere to

the priority assigned by their position in the IVT. Soft

traps are pr oce ssed li ke in terrupt s an d requ ire 2 c ycle s

to be sampled and Acknowledged prior to exception

processing. Therefore, additional instructions may be

executed before a soft trap is Acknowledged.

‘Hard’ traps include exceptions of priority level 12

through level 15, inclusive. The address error (level

12), st ack error (leve l 13), and osc illator error (level 14)

traps fall into this category.

Like soft traps, hard traps can also be viewed as non-

maska ble so urc es of i nter r upt . The difference betw ee n

hard traps and soft traps is that hard traps force the

CPU t o s t op c od e ex ec ut i on af te r th e i n st ruc t io n caus -

ing t he t rap h as complet ed. Norm al program ex ec ution

flow will not resume until after the trap has been

acknowl edged and process ed.

If a higher priority trap occurs while any lower priority

trap is in progress, processing of the lower priority trap

will be suspended and the higher priority trap will be

acknowledged and processed. The lower priority trap

will remain pending until processing of the higher

priority trap completes.

Each hard trap that occurs must be acknowledged

before code execution of any type may continue. If a

lower priority hard trap occurs while a higher priority

trap is pending, acknowledged, or is being processed,

a hard trap conflict will occur. The conflict occurs

because the lower priority trap cannot be Acknowl-

edged until processing for the higher priority trap

completes.

The device is automatically RESET in a hard trap con-

flict condition. The TRAPR status bit (RCON<15> ) is

set when th e RESET oc cu rs, s o th at the c ond iti on ma y

be detected in software.

5.4 Interrupt Sequence

All interr upt event flags are sampled in the be ginning of

each instruction cycle by the IFSx registers. A pending

interrupt re quest (I RQ) is in dicate d by the flag bit b eing

equal to a ‘1’ i n an IFS x regis ter. The IRQ will c ause an

interrupt to occur if the corresp onding bit in the interrupt

enable (IECx) register is set. For the remainder of the

instruction cycle, the priorities of all pending interrupt

requests are evaluated.

If there is a pending IRQ with a priority level greater

than the current processor priority level in the IPL bits,

the processor will be interrupted.

The proce ssor then stac ks the current program counter

and the low byte of the pro cessor status register (SRL),

as show n in Figu re 5-1. The low b yte of the status reg-

ister contains the processor priority level at the time,

prior to the beginning of the interrupt cycle. The proces-

sor then load s the priority level for this interrup t into the

status register. This action will disable all lower priority

interrupts until the completion of the Interrupt Service

Routine.

FIGURE 5-1: INTERRUPT STACK

FRAME

The RETFIE (Return from Interrupt) instruction will

unstack the program counter and status registers to

return the processor to its state prior to the interrupt

sequence.

Note 1: The user can always lower the priority

level by writing a new value into SR. The

Interrupt Service Routine must clear the

interrupt flag bits in the IFSx register

before lowering the processor interrupt

priority, in order to avoid recursive

interrupts.

2: The IPL3 bit (CORCON<3>) is always

clear when interrupts are being pro-

cessed. It is set only during execution of

traps.

015

W15 (bef ore CALL)

W15 (after CALL)

Stack Grows Towards

Higher Address

PUSH : [W15++]

POP : [--W15]

0x0000

PC<15:0>

SRL IPL3 PC<22:16>

 2002 Microchip Technology Inc. Advance Information DS70082A-page 49

dsPIC30F

TABLE 5-2: EXCEPTION VECTORS

5.5 Alternate Vector Table

In Program Memory, the Interrupt Vector Table (IVT) is

follow ed b y the A ltern ate I nte rrupt Vector Table (AIVT),

as show n in Table 5- 2. Acce ss to the Al ternate Ve ctor

Table is provided by the ALTIVT bit in the INTCON2

tion processes will use the alternate vectors instead of

the defa ult vectors. The alternate vectors are organized

in the same manner as the default vectors. The AIVT

supports emulation and debugging efforts by providing

a means to switch between an application and a sup-

port environment, without requiring the interrupt vec-

tors to be reprogrammed. This feature also enables

switching between applications for evaluation of

different software algorithms at run time.

If the AIVT is not required, the program memory allo-

cated to the AIVT may be used for other purposes.

AIVT is not a protected section and may be freely

programmed by the user.

5.6 Fast Context Saving

A context saving option is available using shadow reg-

isters. Shadow registers are provided for the DC, N,

OV, Z and C bits in SR, the TBLPAG and PSVPAG reg-

isters, and the registers W0 through W14. The shad-

ows are only on e level deep. Th e shado w regi sters a re

accessible using the PUSH.S and POP.S instructions

only.

When the processor vectors to an interrupt, the

PUSH.S instruction can be used to store the current

value of the aforementioned registers into their

respective shadow registers.

If an ISR of a certain priority uses the PUSH.S and

POP.S instructions for fast context saving, then a

higher priority ISR shou ld no t inc lude the s ame instruc-

tions. Users must save the key registers in software

during a lower priorit y interrupt, if t he higher prio rity ISR

uses fast context saving.

5.7 External Interrupt Requests

The interrupt controller supports up to five external

interrupt re quest signa ls, INT0 - INT4. Th ese input s are

edge se nsitive, i.e., the y require a low-to-high or a high-

to-low transition to generate an interrupt request. The

INTCON2 regis ter ha s fi ve bi t s , INT0EP - INT4EP, that

select the polarity of the edge detection circuitry.

5.8 Wake-up from SLEEP and IDLE

The interrupt controller may be used to wake up the

processor f rom either SLEEP o r IDLE modes, if SLEEP

or IDLE mode is active whe n the inte rrupt is g enerated.

If an enabled interrupt request of sufficient priority is

received by the interrupt controller, then the standard

interrupt request is presented to the processor. At the

same time, the processor will wake-up from SLEEP or

IDLE and begin execution of the Interrupt Service

Routin e (ISR), nee ded to p rocess t he interru pt request.

Address Error Trap Vector

Oscillator Fail Trap Vector

Stack Error Trap Vector

Reserved Vector

Math Error Trap Vector

Reserved

Oscillator Fail Trap Vector

Address Error Trap Vector

Reserved Vector

Interrupt 0 Vector

Interrupt 1 Vector

—

Interrupt 52 Vector

Interrupt 53 Vector

Math Error Trap Vector

Decreasing

Priority

0x000000

0x000014

Reserved

Stack Error Trap Vector

Reser ved Vector

Interrupt 0 Vector

Interrupt 1 Vector

—

Interrupt 52 Vector

Interrupt 53 Vecto r

IVT

AIVT

0x000080

0x00007E

0x0000FE

Reserved

0x000094

RESET - GOTO Instruction

RESET - GOTO Addr ess 0x000002

Reserved 0x000082

0x000084

0x000004

Reser ved Vector

dsPIC30F

DS70082A-page 50 Advance Information



2002 Microchip Technology Inc.

TABLE 5-3: INTERRUPT CONTROLLER REGISTER MAP

SFR

Name ADR Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RESET State

INTCON1 0080 NSTDIS — — — — OVATE OVBTE COVTE — — — MATHERR ADDRERR STKERR OSCFAIL —0000 0000 0000 0000

INTCON2 0082 ALTIVT — — — — — — — — — — INT4EP INT3EP INT2EP INT1EP INT0EP 0000 0000 0000 0000

IFS0 0084 CNIF BCLIF I2CIF NVMIF ADIF U1TXIF U1RXIF SPI1IF T3IF T2IF OC2IF IC2IF T1IF OC1IF IC1IF INT0 0000 0000 0000 0000

IFS1 0086 IC6IF IC5IF IC4IF IC3IF C1IF SPI2IF U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF IC8IF IC7IF INT1IF 0000 0000 0000 0000

IFS2 0088 — — — FLTBIF FLTAIF LVDIF —QEIIF PWMIF C2IF INT4IF INT3IF OC8IF OC7IF OC6IF OC5IF 0000 0000 0000 0000

IEC0 008C CNIE BCLIE I2CIE NVMIE ADIE U1TXIE U1RXIE SPI1IE T3IE T2IE OC2IE IC2IE T1IE OC1IE IC1IE INT0IE 0000 0000 0000 0000

IEC1 008E IC6IE IC5IE IC4IE IC3IE C1IE SPI2IE U2TXIE U2RXIE INT2IE T5IE T4IE OC4IE OC3IE IC8IE IC7IE INT1IE 0000 0000 0000 0000

IEC2 0090 — — — FLTBIE FLTAIE LVDIE —QEIIE PWMIE C2IE INT4IE INT3IE OC8IE OC7IE OC6IE OC5IE 0000 0000 0000 0000

IPC0 0094 —T1IP<2:0> —OC1IP<2:0> —IC1IP<2:0> —INT0IP<2:0> 0100 0100 0100 0100

IPC1 0096 —T31P<2:0> —T2IP<2:0> —OC2IP<2:0> —IC2IP<2:0> 0100 0100 0100 0100

IPC2 0098 —ADIP<2:0> —U1TXIP<2:0> —U1RXIP<2:0> —SPI1IP<2:0> 0100 0100 0100 0100

IPC3 009A —CNIP<2:0> —BCLIP<2:0> —I2CIP<2:0> —NVMIP<2:0> 0100 0100 0100 0100

IPC4 009C —OC3IP<2:0> —IC8IP<2:0> —IC7IP<2:0> —INT1IP<2:0> 0100 0100 0100 0100

IPC5 009E —INT2IP<2:0> —T5IP<2:0> —T4IP<2:0> —OC4IP<2:0> 0100 0100 0100 0100

IPC6 00A0 —C1IP<2:0> —SPI2IP<2:0> —U2TXIP<2:0> —U2RXIP<2:0> 0100 0100 0100 0100

IPC7 00A2 —IC6IP<2:0> —IC5IP<2:0> —IC4IP<2:0> —IC3IP<2:0> 0100 0100 0100 0100

IPC8 00A4 —OC8IP<2:0> —OC7IP<2:0> —OC6IP<2:0> —OC5IP<2:0> 0100 0100 0100 0100

IPC9 00A6 —PWMIP<2:0> —C2IP<2:0> —INT41IP<2:0> —INT3IP<2:0> 0100 0100 0100 0100

IPC10 00A8 —FLTAIP<2:0> —LVDIP<2:0> — — — — — QEIIP<2:0> 0100 0100 0000 0100

IPC11 00AA — — — — — — — — — — — — — FLTBIP<2:0> 0000 0000 0000 0100

Legend: u = uninitialized bit

 2002 Microchip Technology Inc. Advance Information DS70032D-page 51

dsPIC30F

6.0 FLASH PROGRAM MEMORY

The dsPIC30F family of devices contains internal pro-

gram FLASH memory for executing user code. There

are two methods by which the user can program this

memory:

1. Run Time Self-Programming (RTSP)

2. In-Circuit Serial Pr ogrammi ngTM (ICSPTM)

6.1 In-Circui t Serial Programming

(ICSP)

The details of ICSP will be provided at a later date.

6.2 Run Time Self-Programming

(RTSP)

RTSP is accomplished using TBLRD (table read) and

TBLWT (table write) instructions, and the following

control regi sters:

•NVMCON: Non-Vo latile Memory Control Register

•NVMKEY: Non-Volatile Memory Key Register

•NVMADR: Non-Volatile Memory Address

With RTSP, the user may erase program memory, 32

instruc tions (96 bytes ) at a tim e an d c an wr it e pro gram

memory data, 4 instructions (12 bytes) at a time.

6.3 Table Instruction Operation Summary

The TBLRDL and the TBLWTL instructions are used to

read or write to bits <15:0> of program memory.

TBLRDL and TBLWTL can access program memory in

Word or Byte mode.

The TBLRDH and TBLWTH instruc tions are us ed to read

or write to bits<23:16> of program memory. TBLRDH

and TBLWTH can access program memory in Word or

Byte mode.

A 24-bit program memory address is formed using

bits<7:0> of the TBLPAG register and the effective

address (EA) from a W register specified in the table

instruction, as sh own i n Figure 6-1.

FIGURE 6-1: ADDRESSING FOR TABLE AND NVM REGISTERS

0Program Counter

24-bits

TBLPAG Reg

8-bits 16-bits

Program

Using

TBLPA G Reg

8-bits

Working Reg EA

16-bits

Using

Byte

24-b it EA

1/0

Select

Table

Instruction

NVMADR

Addressing

Counter

Using

NVMADR Re g EA

User/Configuration

Space S elect

dsPIC30F

DS70032D-page 52 Advance Information  2002 Mic rochip Technology Inc.

6.4 RTSP Operation

The dsPIC30F FLASH program memory is organized

into rows and panels. Each row consists of 32 instruc-

tions, or 96 bytes. Each panel consists of 128 rows, or

4K x 24 instructions. Run Time Self Programming

(RTSP) allows the user to erase one row (32 instruc-

tions) at a time and to program four instructions at one

time. RTSP may be used to program multiple program

memory p a ne ls, bu t th e table p oin ter must be change d

at each panel boundary.

Each panel of program memory contains write latches

that hold four instructi ons of program ming data. Prio r to

the actual programming operation, the write data must

be loaded into the panel write latches. The data to be

programmed into the panel is loaded in sequential

order into the write latches: instruction 0, instruction 1,

etc. T he i ns truc tio n words loaded m us t a lw ay s be from

a group of four boundary (e.g., loading of instructions 3,

4, 5, 6 is not allowed).

The basi c sequence for R TSP programming is to set up

a table point er, then do a se ries o f TBLWT instructions

to load th e wri te latc hes. Program ming is perfo rmed by

setting the special bits in the NVMCON register. Four

TBLWTL and four TBLWTH instructions are required to

load the four instructions. To fully program a row of

program memory , eight cycles of four TBLWTL and four

TBLWTH are req uired. If multipl e pane l prog rammi ng

is required, the table pointer needs to be changed and

the next set of multiple write latches written.

All of the table write operations are single word writes

(2 instruction cycles), because only the table latches

are writt en. A total of 8 programming p asses, ea ch writ-

ing 4 inst ruction words, are required per row . A 12 8 row

panel requires 1024 programming cycles.

The FLASH Program Memory is readable, writable,

and erasable during normal operation, over the entire

VDD range.

6.5 Control Registers

The three SFRs used to read and write the program

FLASH memory are:

•NVMCON

•NVMADR

•NVMADRU

•NVMKEY

6.5.1 NVMCON REGISTER

The NVMCON register controls which blocks are to be

erased, which memory type is to be programmed, and

start of the programming cycle.

6.5.2 NVMADR REGISTER

The NVMADR register is used to hold the lower two

bytes of the effective address. The NVMADR register

captures the EA<15 :0> of the last table instru ct ion that

has been executed and selects the row to write.

6.5.3 NVMADRU REGISTER

The NVMADRU register is used to hold the upper byte

of the effective address. The NVMADRU register cap-

tures the EA<23:16> of the last table instruction that

has been exec uted.

6.5. 4 NVMKEY REGISTER

NVMKEY is a write only register that is used for write

protection. To start a programming or an erase

sequence, the user must consecutively write 0x55 and

0xAA, to th e NVMKEY register. Refer t o Section 6.6 f or

further details.

6.6 Programming Operations

A complete programming sequence is necessary for

programming or erasing the internal FLASH in RTSP

mode. A progra mming operati on is nominally 2 ms ec in

duration and the processor stalls (waits) until the oper-

ation is finished. Setting the WR bit (NVMCON<15>)

starts the operation, and the WR bit is automatically

cleared when the operation is finished.

 2002 Microchip Technology Inc. Advance Information DS70032D-page 53

dsPIC30F

6.6.1 PROGRAMMING ALGORITHM FOR

PROGRAM FLASH

The user can erase one row of program FLASH mem-

ory at a time. The user can program one block (4

instruction words) of FLASH memory at a time. The

general proc es s is:

1. Read one row of pr ogram FLAS H (32 instruct ion

words) and store into data RAM as a data “image”.

2. Update the data image with the desired new data.

3. Erase program FLASH row.

a. Setup NVMCON register for multi-word,

program FLASH, eras e, and set WREN bit.

b. Write address of row to be erased into

NVMADR.

c. Write ‘55’ to NVMKEY.

d. Write ‘AA’ to NVMKEY.

e. Set the WR bit. This will begin erase cycle.

f. CPU will stall for the duration of the erase cycle.

g. The WR bit is cleared when erase cycle ends.

4. Write four instruction words of data from data

RAM into the program FLASH write latches.

5. Program 4 instruction words into program

FLASH.

a. Setup NVMCON register for multi-word,

program FLASH, program, and set WREN bit.

b. Write ‘55’ to NVMKEY.

c. Write ‘AA’ to NVMKEY.

d. Set the WR bit. This will begin program cycle.

e. CPU will stall for duration of the program cycle.

f. The WR bit is cleared by the hardware when

program cycle ends.

6. Re peat ste ps (4 - 5) seven mor e times to fi nish

programming FLASH row.

7. Repeat steps 1 throu gh 6 as needed to pro gram

desired amount of program FLASH memory.

6.6.2 ERASING A ROW OF PROGRAM

MEMORY

The following is a code sequence that can be used to

erase a row (32 instructions) of program memory.

EXAMPLE 6-1: ERASING A ROW OF PROGRAM MEMORY

; Setup NVMCON for erase operation, multi word write

; program memory selected, and writes enabled

MOV #0x4041,W0 ;

MOV W0,NVMCON ; Init NVMCON SFR

; Init pointer to row to be ERASED

MOV #tblpage(PROG_ADDR),W0 ;

MOV W0,TBLPAG ; Initialize PM Page Boundary SFR

MOV #tbloffset(PROG_ADDR),W0 ; Intialize in-page EA[15:0] pointer

MOV W0, NVMADR ; Intialize NVMADR SFR

MOV #0x55,W0 ;

MOV #0xAA,W1 ;

MOV W0,NVMKEY ; Write the 0x55 key

MOV W1,NVMKEY ; Write the 0xAA key

NOP ;

BSET NVMCON,#WR ; Start the erase sequence

NOP ; Insert two NOPs after the erase

NOP ; command is asserted

dsPIC30F

DS70032D-page 54 Advance Information  2002 Mic rochip Technology Inc.

6.6.3 LOADING WRITE LATCHES

The following is a sequence of instructions that can be

used to load the 96 bits of write latches. Four TBLWTL

and four TBLWTH instructions are needed to load the

write latches selected by the table pointer.

EXAMP L E 6-2: L OA D ING WRIT E LA TCHES

; Set up a pointer to the first program memory location to be written

; program memory selected, and writes enabled

MOV #0x0000,W0 ;

MOV W0,TBLPAG ; Initialize PM Page Boundary SFR

MOV #0x6000,W0 ; An example program memory address

; Perform the TBLWT instructions to write the latches

; 0th_program_word

MOV #LOW_WORD_0,W2 ;

MOV #HIGH_BYTE_0,W3 ;

TBLWTL W2,[W0] ; Write PM low word into program latch

TBLWTH W3,[W0++] ; Write PM high byte into program latch

; 1st_program_word

MOV #LOW_WORD_1,W2 ;

MOV #HIGH_BYTE_1,W3 ;

TBLWTL W2,[W0] ; Write PM low word into program latch

TBLWTH W3,[W0++] ; Write PM high byte into program latch

; 2nd_program_word

MOV #LOW_WORD_2,W2 ;

MOV #HIGH_BYTE_2,W3 ;

TBLWTL W2, [W0] ; Write PM low word into program latch

TBLWTH W3, [W0++] ; Write PM high byte into program latch

; 3rd_program_word

MOV #LOW_WORD_3,W2 ;

MOV #HIGH_BYTE_3,W3 ;

TBLWTL W2, [W0] ; Write PM low word into program latch

TBLWTH W3, [W0++] ; Write PM high byte into program latch

Note: In Example 6-2, the contents of the upper byte of W3 has no effect.

 2002 Microchip Technology Inc. Advance Information DS70032D-page 55

dsPIC30F

6.6.4 INITIATING THE PROGRAMMING

SEQUENCE

For protec tion, the w rite i nitiate sequenc e for N VMKEY

must be used to allow any erase or program operation

to procee d. After the prog ramming comm and has bee n

executed, the user must wait for the programming time

until programming is co mplete. The two instructions fol-

lowing the start of the programming sequence should

be NOPs.

EXAMPLE 6-3: INITIATING A PROGRAMMING SEQUENCE

MOV #0x55,W0 ;

MOV #0xAA,W1 ;

MOV W0,NVMKEY ; Write the 0x55 key

MOV W1,NVMKEY ; Write the 0xAA key

NOP ;

BSET NVMCON,#WR ; Start the erase sequence

NOP ; Insert two NOPs after the erase

NOP ; command is asserted

DSPIC30F

DS70032D-page 56 A dva nce Information



2002 Microchip Technology Inc.

TABLE 6-1: NVM REGISTER MAP

File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All RESETS

NVMCON 0760 WR WREN WRERR — — — — — — PROGOP<6:0> 0000 0000 0000 0000

NVMADR 0762 NVMADR<15:0> uuuu uuuu uuuu uuuu

NVMADRU 0764 — — — — — — — — NVMADR<23:16> 0000 0000 uuuu uuuu

NVMKEY 0766 — — — — — — — — KEY<7:0> 0000 0000 0000 0000

Legend: u = uninitialized bit

 2002 Microchip Technology Inc. Advance Information DS70082A-page 57

dsPIC30F

7.0 DATA EEPROM MEMORY

The Data EEPROM Memory is readable and writable

during no rmal operatio n over the enti re VDD range. The

data EEPROM memory is directly mapped in the

program memory address space.

The four SFRs used to read and write the program

FLASH memory are used to access data EEPROM

memory, as well. As described in Section 4.0, these

registers are:

•NVMCON

•NVMADR

•NVMADRU

•NVMKEY

The EEPROM data memory allows read and write of

single words and 16-word blocks. When interfacing to

data memory, NVMADR in conjunction with the

TBLPAG register, are used to address the EEPROM

locatio n bei ng ac cess ed. TBLRDL and TBLWTL instruc-

tions are used to read and write data EEPROM. The

dsPIC30F devices have up to 8 Kbytes (4K words) of

data EEPROM, with an address range from 0x7FF000

to 0x7FFFFE.

A word wri te operatio n should be prec eded by an e rase

of the corresponding memory location(s). The write typ-

ically requires 2 ms to complete. However, the write

time varies with voltage and temperature.

A program or erase operation on the data EEPROM

does n ot sto p the ins truc tion fl ow. The user is re spon-

sible for waiting for the appropriate duration of time

before initiating another data EEPROM write/erase

operatio n. Attem pting t o read t he dat a EEPROM, while

a programming or erase operation is in progress,

results in unspecified data.

Control bi t WR in itia tes w rite ope rati ons , s im ila r to p ro-

gram FLASH writes. This bit cannot be cleared, only

set, in software. This bit is cleared in hardware at the

completion of the write operation. The inability to clear

the WR bit in software prevents the accidental or

premature termination of a write operation.

The WREN bit, when set, will allow a write operation.

On powe r-up, the WR EN bit is clear. The WRERR bit i s

set when a write operation is interrupted by a MCLR

Reset, or a WDT Time-out Reset, during normal oper-

ation . In these situa tio ns, foll owing Rese t, the us er can

check the WRERR bit and rewrite the location. The

address register NVMADR remains unchanged.

7.1 Reading the Data EEPROM

A TBLRD instruction reads a word at the current pro-

gram word address. This example uses W0 as a

pointer to data EEPROM. The result is placed in

EXAMPLE 7-1: DATA EEPROM READ

Note: Interru pt flag bit NVMI F in the IFS0 regis ter

is set when write is complete. It must be

cleared in software.

MOV #LOW_ADDR_WORD,W0 ; Init Pointer

MOV #HIGH_ADDR_WORD,W1

MOV W1,TBLPAG

TBLRDL [ W0 ], W4 ; read data Flash

dsPIC30F

DS70082A-page 58 Advance Information  2002 Microchip Technology Inc.

7.2 Erasing Data EEPROM

7.2.1 ERASI NG A BLOCK OF DATA

EEPROM

In order to erase a block of data EEPRO M, the TBLP AG

and NVMADR registers must initially point to the block

of memory to be erased. Configure NVMCON for eras-

ing a block of data EEPROM, and set the ERASE and

WREN bits in NVMCON register. Setting the WR bit

initiates the erase, as shown in Exampl e 7-2.

EXAMPLE 7-2: DATA EEPROM BLOCK ERASE

7.2.2 ERASING A WORD OF DATA

EEPROM

The TBLPA G and NVMADR registers must point to the

block. Select erase a block of data FLASH, and set the

ERASE and WREN bits in NVMCON register. Setting

the WR bit initiates the erase, as shown in Example 7-3.

EXAMPLE 7-3: DATA EEPROM WORD ERASE

; Select data EEPROM block, ERASE, WREN bits

MOV #4045,W0

MOV W0,NVMCON ; Initialize NVMCON SFR

; Start erase cycle by setting WR after writing key sequence

MOV #0x55,W0 ;

MOV #0xAA,W1 ;

MOV W0,NVMKEY ; Write the 0x55 key

MOV W1,NVMKEY ; Write the 0xAA key

NOP ;

BSET NVMCON,#WR ; Initiate erase sequence

; Erase cycle will complete in 2mS. CPU is not stalled for the Data Erase Cycle

; User can poll WR bit, use NVMIF or Timer IRQ to determine erasure complete

; Select data EEPROM word, ERASE, WREN bits

MOV #4044,W0

MOV W0,NVMCON

; Start erase cycle by setting WR after writing key sequence

MOV #0x55,W0 ;

MOV #0xAA,W1 ;

MOV W0,NVMKEY ; Write the 0x55 key

MOV W1,NVMKEY ; Write the 0xAA key

NOP ;

BSET NVMCON,#WR ; Initiate erase sequence

; Erase cycle will complete in 2mS. CPU is not stalled for the Data Erase Cycle

; User can poll WR bit, use NVMIF or Timer IRQ to determine erasure complete

 2002 Microchip Technology Inc. Advance Information DS70082A-page 59

dsPIC30F

7.3 Writing to the Data EEPROM

To write an EEPROM data location, the following

sequen ce must be followed:

1. Erase data EEPROM word.

a. Select word, data EEPROM, erase, and set

WREN bit in NVMCO N regis ter.

b. Write address of word to be erased into

NVMADR.

c. Optionally, enable NVM interrupt.

d. Write ‘55’ to NVMKEY.

e. Write ‘AA’ to NVMKEY.

f. Set the WR bit. This will begin erase cycle.

g. Either poll NVMIF bit or wait for NVMIF interrupt.

h. The WR bit is cleared when the erase cycle

ends.

2. Write data word into data EEPROM write

latches.

3. Program 1 data word into data EEPROM.

a. Select word, data EEPROM, program, and set

WREN bit in NVMCO N regis ter.

b. Optionally, enable NVM write done interrupt.

c. Write ‘55’ to NVMKEY.

d. Write ‘AA’ to NVMKEY.

e. Set The WR bit. This will begin program cycle.

f. Either poll NVMIF bit or wait for NVM interrup t.

g. The WR bit is cleared when the write cycle

ends.

The write will not initiate if the above sequence is not

exactly followed (write 0x55 to NVMKEY, write 0xAA to

NVMCON, then set WR bit) for each word. It is strongly

recommended that interrupts be disabled during this

code segment.

Additionally, the WREN bit in NVMCON must be set to

enable writes. This mechanism prevents accidental

writes to data EEPROM, due to unexpected code exe-

cution. The WR EN b it sho ul d be k ept clear at a ll tim es ,

except when updating the EEPROM. The WREN bit is

not cleared by hardware.

After a write sequence has been initiated, clearing the

WREN bit wil l not affect the current write cycle. The WR

bit will be inhibited from being set unless the WREN bit

is set. The WREN bit must be set o n a previous instruc -

tion. Both WR a nd WREN c an not be se t with th e s am e

instruction.

At the completion of the write cycle, the WR bit is

cleared in hardware and the Non-Volatile Memory

Write Complete Interrupt Flag bit (NVMIF) is set. The

user may either enable this interrupt, or poll this bit.

NVMIF must be cleared by software.

7.3.1 WRITING A WORD OF DATA

EEPROM

Assuming the user has erased the word to be pro-

grammed, then, use a table write instruction to write

one write latch, as shown in Example 7-4.

EXAMPLE 7-4: DATA EEPROM WORD WRITE

; Point to data memory

MOV #LOW_ADDR_WORD,W0 ; Init pointer

MOV #HIGH_ADDR_WORD,W1

MOV W1,TBLPAG

MOV #LOW(WORD),W2 ; Get data

TBLWTL W2,[ W0] ; Write data

; The NVMADR captures last table access address

; Select data EEPROM for 1 word op

MOV #0x4004,W0

MOV W0,NVMCON

; Operate key to allow write operation

MOV #0x55,W0

MOV #0xAA,W1

MOV W0,NVMKEY ; Write the 0x55 key

MOV W1,NVMKEY ; Write the 0xAA key

NOP

BSET NVMCON,#WR ; Initiate program sequence

; Write cycle will complete in 2mS. CPU is not stalled for the Data Write Cycle

; User can poll WR bit, use NVMIF or Timer IRQ to determine write complete

dsPIC30F

DS70082A-page 60 Advance Information  2002 Microchip Technology Inc.

7.3.2 WRITING A BLOCK OF DATA

EEPROM

To write a block of data EEPROM, write to all sixteen

latches first, then set the NVMCON register and

progra m the block .

EXAMPLE 7-5: DATA EEPROM BLOCK WRITE

7.4 Write V e rify

Depending on the application, good programming

practice may dictate that the value written to the mem-

ory should be verified against the original value. This

should be used in applications where excessive writes

can stress bits near the specification limit.

7.5 Protection Against Spurious Write

There are conditions when the device may not want to

write to the data EEPROM memory. To protect against

spurious EEPROM writes, various mechanisms have

been built-in. On power-up, the WREN bit is cleared;

also, the Power-up Timer prevents EEPROM write.

The wri te initiate sequenc e and the W REN bit toge ther ,

help prevent an accidental write during brown-out,

power glitch, or software malfunction.

MOV #LOW_ADDR_WORD,W0 ; Init pointer

MOV #HIGH_ADDR_WORD,W1

MOV W1,TBLPAG

MOV #data1,W2 ; Get 1st data